2433 Golf Links Cir Malav Shah malavs.shah@gmail.

com
Santa Clara, CA 95050 408-425-8784 (Cell)

Objective

A passionate engineer with a drive to build the most robust chips in record time by using software to drive chip
development process, looking to join a dynamic place building innovative products using latest technologies. Past
experience includes exposure to different aspects of ASIC design and verification, with successful tape-outs across different
technology nodes and product lines.

Work Experience

Senior Logic Design Engineer (True Circuits Inc., Los Altos, CA) 12/2018 to Present
• Designing highly optimized DDR PHY to provide flexible yet efficient and smoothly integrable IP.
• Building a placement-aware, synthesized design to help get most optimum PPA.
• Working on hardware optimization on algorithms to provide reliable write, read, and Vref training.
• Writing C-based tests for exercising training routine to test memory controller, PHY and memory interfaces.
• Using Git for code management.

Staff Design Engineer (Xilinx Inc., San Jose, CA) 04/2017 to 12/2018
• Designed 7-stage VLIW pipelined processor core array used for AI/ML and AWS applications. Interfaced with NOC,
fabric, PMC units.
• Improved PPA significantly - reduced 11% dynamic and 3% static core power and 0.8% area - and met performance
target.
• Re-designed adders, multipliers and various other units to improve function-based power, which also helped in
reducing logic path and improving performance, while maintaining low power intent.
• Worked closely with back-end team to improve floorplan to achieve target speed.
• Wrote UPF which included level shifters, isolation cells and power switches with multiple power domains.
• Ran Conformal Low Power (CLP) to run static LP check and make sure the UPF was clean and met power intent.
• Wrote low power simulation tests and assertions to catch issues caused by inaccurate isolation and level-shifter.
• Synthesized RTL with UPF using Design Compiler to generate low power PG netlist.
• Carried out clock domain crossing (CDC) and reset domain crossing (RDC) analysis using Questa CDC, debugged and
fixed issues, and added waivers for functionally unrealizable paths to make the design CDC-RDC error-proof.
• Ran SpyGlass Lint to keep design squeaky clean, thereby eliminating late bug-finds and reducing major workload for
verification team. Maintained AWL/SWL waiver and parameter files.
• Wrote SpyGlass DFT constraints (SGDC) for different DFT modes like scan shift, capture and capture-at-speed. Made
sure the design worked under all different operating mission and test modes.
• Ran full block synthesis and optimization, wrote timing/STA constraints.
• Ran PowerArtist to verify power results and used different worst-case simulations to further optimize design.

Design Engineer IV (Apple Inc., Cupertino, CA) 08/2016 to 04/2017

• Ran clock domain crossing (CDC) and reset domain crossing (RDC) analysis, debug, fix and sign-off.
• Created and maintained block UPF for low power and ran all checks (CLP, LEC and simulation).
• Ran SpyGlass Lint and fixed all design issues.
• Ran formal analysis using JasperGold to verify blocks.

Staff VLSI Design Engineer (Audience Inc., Mountain View, CA) 06/2013 to 08/2016
• Designed multi-processor audio DSP SoC for high-end phones.
• Was responsible for block design and verification, full-chip integration, constraints and synthesis, formal verification
and STA of ASIC and FPGA for prototype.
• Cut the design/verification cycle time into half by automating configurable-RTL generation and verification for large
design blocks, and synthesis flows. This greatly improved the team efficiency and reduced human errors significantly.
Number of bugs reduced exponentially because of the streamlined process.
• Developed very efficient and convenient methodologies for synthesis using DC, equivalency checking using Formality
(RTL to gates), and STA using PrimeTime, using make flow.
• Developed a register tool to generate AMBA APB 2.0/3.0- and XLMI-compliant registers automatically.
• The register tool supported different flavors like rw, ro, wo, w1s, w1c, wt (write-trigger), etc. and different views like
RTL, HTML, RAL, HEADER, Verilog case decode, etc.
• Designed a configurable, parameterized memory complex with priorities, dual mapping, interleaving and dynamic
sharing. Automated configuration-based RTL generation for stitching entire design using leaf decoders, arbiters with
 TDM, input/output muxes, and data formatters. Closed timing by doing incremental ECOs through Primetime on very
critical performance paths between processors and memories.
• Designed an automated IO muxing with different functional and test inputs/outputs. Fully parameterized IO
multiplexer with different mission modes like UART, SPI, PCM, PDM, I2C, I2S, and test modes like MBIST, Scan,
Codec, PLL, etc.
• Added assertions for memory switch complex and IO muxing structure; verified the design by generating SV
sequences within UVM framework.
• Designed a Power Control block to manage boot-up, sleep and wake-up sequences for always on and switchable power
domains, including interrupt handling modes, in multi-voltage, multi-frequency design. Designed it to use under 25uW
for very low power-sensor application use-cases.
• Implemented low power design techniques like multi-VT gates, dynamic voltage scaling, power switching and
isolation. Synthesized blocks with different VT options to explore trade-offs between area, power and timing.
• Wrote UPF for different power states of various domains. Used MVRC for rule checking and MVSIM for power-aware
simulations.
• Did DFT insertion, including MBIST, B-scan, scan, TAP controller, etc.
• Implemented different design tweaks and fixes to reduce congestion, increase routability and meet setup. Fixed hold
violations in PrimeTime by fixing constraints, clock skewing, and cell sizing. Used re-routing, re-placing to fix
crosstalk, SI issues.

Design Engineer (Broadcom Corporation, Chandler, AZ) 08/2010 to 05/2013

• Designed CCS Noise characterization system for memories to replace costly third-party tool.
• The tool included accurate models to calculate noise bump calculation, noise propagation, driver weakening, and Vdd
and temperature scaling with strong correlation with spice simulation.
• Wrote spice test benches to characterize for different vectors, to create measurement files and wave form dumps
(FSDB), using LPE netlist.
• Designed EM/IR system for accurately analyzing signal integrity and reliability for memories, standard cells and IOs.
• The tool included power-grid integrity analysis, including static and dynamic IR drop and EM analysis and signal net
EM analysis of memories (RF, SRAM, ROM, and OTP, including power-gated designs), standard cells and IO pads/
segments.
• The tool could detect hotspot early and add design fixes to reduce design cycle time and improve circuit reliability.
• The tool worked on various models like CMM, MMX, Sim2iprof and AVM.
• Designed a memory compiler for different types of memories like ROM, RAM, OTP, RF, etc.
• The compiler used SKILL language to build different memories.
• Gained experience with LVS, DRC, ANT and ERC, verification decks and extraction.
• Carried out timing, power and noise characterization with different file formats.
• Built a memory synthesizer to provide the most efficient memories to chip teams depending on various timing/power/
physical requirements like area, cycle/access time, leakage/read/write power, etc.
• Developed intelligent pad ring review system for chip IO pad segment set up and placement.

Software Engineer (Agama Solutions, Fremont, CA) 01/2010 to 08/2010

• Developed scripts in C language for software quality assurance and testing of system performance. Used MySQL for
database queries.

Intern (ViaBlaze Inc., Santa Clara, CA) 06/2009 to 12/2009

• Built a wireless vehicular on-board unit for deploying Intelligent Transportation Systems (ITS) using various
technologies like DSRC, Wi-Fi, Bluetooth and 3G/4G/LTE. Initial prototype was built on Beagleboard on Google’s
Android platform.
• Carried out activities such as system development in C, prototype testing and documenting results.

Graduate Teaching Assistant (San Jose State University, San Jose, CA) 02/2007 to 05/2009
• Teaching assistant for statistics course.

Engineer (Microlink Solutions Pvt. Ltd., India) 06/2005 to 12/2006

• Integrated systems; developed software applications using C/C++.
• Wrote test suites to verify the system.

Education

MBA, Haas School of Business (U C Berkeley) May-2019

MS, Electrical Engineering, San Jose State University (VLSI ASIC Design) May-2009
BE, Electronics & Communication, North Gujarat University, India Sep-2005
Patents

Multi-core audio processor with flexible memory allocation (pending).

Skills

• Languages and Methodology: Verilog, System Verilog, UPF, UVM, MVSIM, MVRC, SDF, C/C++, OOP, Perl,
Python, UNIX Shell Scripting, Tcl, Awk, Sed, SPICE, MySQL, Emacs Verilog, HTML, PHP, Javascript, jQuery.
• Function knowledge: Low power design techniques, synthesis, DFT, MBIST, MBISR, LBIST, BSCAN, JTAG, TAP
controller, STA, timing closure.
• Protocols: I2C, I2S, UART, PCM, PDM, GPIO, AMBA 2.0/3.0 APB, AMBA 3 AHB, NPI, etc.
• Front-end Tools: SypGlass Lint, SpyGlass DFT DRC, Conformal Low Power (CLP), Questa CDC, Design Compiler
(DC), DFT Compiler, Library Compiler, Formality, Verdi, RealIntent Linter & RDC, Mentor’s CDC.
• Sign-off Tools: PrimeTime
• Back-end Tools: Apache Totem/Redhawk, Cadence VAVO/VAEO, StarRC_XT, IC Compiler, Liberty NCX, Cadence
Virtuoso, Hercules.
• Spice simulators: FineSim, HSPICE, HSIM, Spectre.
• Verilog simulators/viewers: VCS, NC Verilog, Sim Vision, Icarus Verilog.
• CM Tools: Git, Perforce, SVN, RCS.

Academic Projects

MIPS 32-bit processor based on Speculative Tomasulo Algorithm.

8-Bit RISC processor ASIC IP with pre-defined instruction-set.
64-bit Perfect Shuffle Router/Switch Architecture connecting all I/O ports.
4 x 16 DRAM Memory Decoder Design.
64-point FFT on Xilinx FPGA for DSP project.
BGP scalability-route reflection algorithm in C.

References of current/previous managers or co-workers can be made available upon request.