Resume Benazir Mustafa ASIC

BENAZIR MUSTAFA
Eligible to work for any employer in Canada.

Montreal, QC
+15144513505
bmtazin@gmail.com
https://www.linkedin.com/in/benazir-mustafa-7a6370137/
CAREER OBJECTIVE
Strong engineering professional with a demonstrated history of working in the
semiconductor industry as well as in the field of Software development and Automation. My
biggest skill is my analytical ability of solving problems which gives me satisfaction with
what I am doing. Aiming to utilize my skills and knowledge to obtain the objectives of your
company and at the same time expand my professional work experience.
WORK EXPERIENCE
Ulkasemi Private Ltd, Dhaka, Bangladesh
Senior Engineer, Front-End Verification Dec 2017 – Jul 2021
3.5+ years experience in front-end verification of ASIC designs.
• Worked on several automation scripts with python, bash, skill(Cadence) for clients to
automate different tasks, verification process, bug fixing, design testing etc.
• Generate and proposed Ideas for possible solutions.
• Prepare reports and documentation manuals for project deliverables.
• Developed analog behavioral model & self-checking test bench to validate the schematics
in Verilog-AMS and SystemVerilog.
• Train new engineers in Mixed Signal Verification.
• Developed the chip top-level test bench & integrating the validated analog models to chip
top level schematic.
• Developed self-checking test bench environment for the verification of digital design
using SystemVerilog and UVM.
• Deep knowledge of object-oriented programming (OOP).
• Developed test bench for bus protocol like AMBA-AXI, AMBA-AHB, AMBA-APB.
• Developed functional coverage for digital design.
• Developed supply sensitive connect modules in Verilog-AMS to support supply
sensitivity in analog model.
• Developed test planning, testcase, constraints, SVA, & coverage models & debugged the
failures.
Tokai Corporation limited, Dhaka, Bangladesh
Testing and Troubleshooting Engineer Jun 2017 – Nov 2017
• Performed detailed inspections and standardized tests on product samples to assess
compliance with tolerances.
• Performed thorough inspections, tests and diagnostic procedures to assess problems.
• Worked successfully with diverse group of coworkers to accomplish goals and address
issues related to our products and services.
Skills
• Programming Language: C# (basic), Python(Advanced), Bash, TCL, HTML, CSS,
Bootstrap, Javascript, React (Advanced).
• Hardware Description Language: Verilog, VHDL, Verilog AMS (Advanced), System
Verilog, UVM.
• IC Design software: ADE L, Cadence Virtuoso & Cadence IUS.
• Microcontroller: Arduino IDE.
• Version control: Git
• SDLC: Agile Development, Scrum.
• Computer Skills: MATLAB
• Operating Systems: Unix, Linux, Windows.
• Sound Expertise on MS Office (Word, PowerPoint, MS Excel)
EDUCATIONAL QUALIFICATION
• Master of Electrical and Computer Engineering (Jan 2021-Dec 2022)
Concordia University, Montreal, Quebec
• Bachelor of Science in Electrical and Electronics Engineering (April 2013-April 2017)
BRAC University, Dhaka, Bangladesh
PROJECT EXPERIENCE
1. Validation & Verification of Power Management IC
▪ Develop the block-level model & self-checking test bench of the analog schematic in
Verilog-AMS such LDO, Sigma-Delta ADC, PLL, Bias Generator, PGA. Temperature
Sensor Circuit.
2. Validation of Piezoelectric Micromachined Ultrasonic Transducers (pMUT) based MEMS
▪ Develop the block-level model & self-checking test bench of the analog schematic in
Verilog-AMS such as Low Noise Amplifier, ADC, DAC, Level Shifter, Loop Filter.
▪ Develop supply sensitive assertion and connect module.
3. Functional Verification of AMBA APB, AHB & AXI Bus protocol
▪ Develop the test bench components in UVM for functional verification of the APB
bus protocol.
▪ Develop test & code coverage plan for the functionality & the coverage.
▪ Develop test cases for READ/WRITE operation of the slave.
4. Design a JTAG as a self-test built-in system through VHDL, Concordia University.
5. Functional Verification of a Calculator, Concordia University.
▪ Conduct the process of testing the design of a simple calculator written in HDL, using
SystemVerilog as the verification language and QuestaSim as the simulation tool.
6. Formal verification of Direct Digital Synthesizer IP Core, Concordia University
▪ Conduct verification process of a given direct digital synthesizer RTL design step by
step with Synopsys design compiler to synthesize the RTL design and check the
comparison between the RTL and synthesized design.
▪ Used Synopsys formality and cadence conformality tool to conduct equivalence
checking between buggy file and the synthesized file.
7. BRACU BAT GPS Based Taxi Fare Meter -Thesis, BRAC University
Link- goo.gl/5UYWRS
8. Healthcare Smart Pillow -Research Project, BRAC University
Link- goo.gl/kQj6bT

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BENAZIR MUSTAFA

Eligible to work for any employer in Canada.

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