Return To Basics I: Understanding POWER7 Capacity Entitlement and Virtual Processors
Return To Basics I: Understanding POWER7 Capacity Entitlement and Virtual Processors
Return To Basics I: Understanding POWER7 Capacity Entitlement and Virtual Processors
Return to Basics I :
Understanding POWER7
Capacity Entitlement and Virtual Processors
VN211
Rosa Davidson
Advanced Technical Skills - Security and Performance - IBM
5.3
Session Evaluations
ibmtechu.com/vp
Prizes will be
drawn from
Evals
Outline Part 1
PowerVM Concepts: (20 slides)
Terminology : CPU, CPU within AIX.
Two Usages View : PowerVM vs OS
Types of Logical PARtitions (LPARs).
Virtual Processor Definition (VP).
Capacity Entitlement Definition (CE).
Dedicated LPAR Definition.
Dedicated Donating Definition.
VPs vs AIX SMT scheduling VP Folding
Shared LPAR Definition.
Maximum VPs for each LPAR.
Shared: The cake & the Invitees story
Capacity Entitlement: Dispatch wheel.
Limit the VPs, Core Access you receive
The Uncapped: The False Hope story
Bibliography - References
Beyond this presentation, read the White Paper from Mala Anand :
POWER7 Virtualization - Best Practice Guide
http://www.ibm.com/developerworks/wikis/display/WikiPtype/Performance+Monitoring+Documentation
An LPAR Review:
http://www.ibmsystemsmag.com/aix/administrator/lpar/An-LPAR-Review/
Virtualization Tricks:
http://www.ibmsystemsmag.com/aix/trends/whatsnew/Virtualization-Tricks/
http://www.ibm.com/common/ssi/fcgi-bin/ssialias?infotype=SA&subtype=WH&appname=STGE_PO_PO_USEN&htmlfid=POL03027USEN&attachment=POL03027USEN.PDF
https://www.ibm.com/developerworks/wikis/display/WikiPtype/Java+Performance+Advisor
ftp://ftp.software.ibm.com/aix/tools/perftools/JPA/AIX61/
http://www.ibm.com/developerworks/wikis/display/WikiPtype/VIOS+Advisor
http://aixptools.austin.ibm.com/virt/virt_advisor/
Terminology : CPU
The Threads of the core are the: Logical Processor (LP) or Logical CPU (lcpu).
100
POWER5
POWER6
150
POWER7 SMT4
NO BOX SIZING
(VIO ? Which VIO?)
VP
Core
SMT Mode
Nb Log. CPUs
SMT Mode
Nb Log. CPUs
CE
GHz + Memory
SpecInt
Throughput
10
20
No Sizing
on a UNIQUE
NUMBER
(rPerf and CPW)
physc: 3.0
Operating System
Core 0
VP 0
CPU 1
sys
CPU 9
idle
idle
CPU 6
CPU 7
idle
idle
CPU 10
CPU 11
idle
idle
Vision
SMT Threads
VP 2
Core 2
1 VP
Folded
POWER7 chip
7
CPU 5
VP 1
CPU 8
Core 3
CPU 3
usr
CPU 4
Core 1
CPU 2
CPU 12
CPU 13
CPU 14
CPU 15
(VP 1)
(VP 2)
(VP 3)
(VP 4)
Questions / Answers
root@davidson /=>lsdev
proc0 Available 00-00
proc2 Available 00-02
proc4 Available 00-04
proc6 Available 00-06
proc8 Defined
00-08
proc10 Defined
00-10
proc12 Defined
00-12
proc14 Defined
00-14
proc16 Defined
00-16
proc18 Defined
00-18
proc20 Defined
00-20
proc22 Defined
00-22
proc24 Defined
00-24
proc26 Defined
00-26
proc28 Defined
00-28
proc30 Defined
00-30
proc32 Defined
00-32
proc34 Defined
00-34
proc36 Defined
00-36
proc38 Defined
00-38
-Cc processor
Processor
Processor
4
Processor
Processor
Processor
Processor
Processor
Processor
Processor
Processor
Processor
Processor
16
Processor
Processor
Processor
Processor
Processor
Processor
Processor
Processor
VIO Server:
An Appliance Partition used to virtualize physical network adapters, physical storage adapters and CD devices.
A server can have one to many VIO servers.
10
VP
VP
LPAR 2
1 VP
VP
VP
LPAR 3
4 VP
VP
VP
VP
VP
PowerVM Hypervisor
Shared Pool
Dedicated Cores
11
VP 10
VP 11
LPAR 2 - SHARED
1 VP CE: 0.3
VP 12
LPAR 3 - DEDICATED
4 VP CE is implicit: 4
VP 20
VP 30
VP 31
VP 32
VP 33
PowerVM Hypervisor
Shared Pool
CORE 0
CORE 1
Dedicated Cores
CORE 2
CORE 3
CORE 4
CORE 5
CORE 6
0.1
CORE 7
0.1
CORE 0
0.5
1.0
0.1
0.6
1/100th
of a core
Type of LPAR
13
VP 30
used
idle
VP 31
used
idle
VP 32
used
idle
VP 33
used
idle
PowerVM Hypervisor
Share Pool
CORE 0
CORE 1
Dedicated Cores
CORE 2
CORE 3
CORE 4
CORE 5
CORE 6
CORE 7
used
idle
VP 31
used
idle
VP 32
used
idle
VP 33
used
idle
PowerVM Hypervisor
Share Pool
CORE 0
CORE 1
Dedicated Cores
CORE 2
CORE 3
CORE 4
used
SP
CORE 5
used
SP
CORE 6
used
CORE 7
SP
SP
used
LPAR 2 - SHARED
CAPPED
3 VP CE: 0.3
uncapped : 2.7
VP 10
VP 11
1 VP CE: 0.3
VP 12
VP 20
PowerVM Hypervisor
Shared Pool
CORE 0
CORE 1
Dedicated Cores
CORE 2
CORE 3
CORE 4
CORE 5
CORE 6
CORE 7
16
THE VPs
17
VP 31
used
used
VP 32
used
VP 33
used
Current (1H2012)
Core 2
ST (SMT 1)
Core 3
Core 1
Core 2
SMT 2
Core 1
Core N
AIX Folding
AIX SMT Scheduling
SMT4
18
VP 31
used
used
VP 32
used
VP 33
used
ARGH !
OUCH ! OUCH !
Core 2
ST (SMT 1)
Core 3
Core 1
Core 2
SMT 2
Core 1
Core N
SMT4
All cores unfolded -> physc = nb VPs
Tertiaries begin to be loaded.
My Sizing ??!!!!
100 users-4 cores; 200 users-8 cores
and
VP=8 I have 100 users physc 8 !!
19
LPAR 3
We are in 1Q1776 We have 100 users
We configure 8 VPs We expect 4 cores used
used
used
used
used
used
used
VP 30
VP 33
used
VP 31
used
used
used
VP 32
used
VP 33
used
used
used
VP 36
used
used
VP 37
used
used
VP 35
VP 38
used
VP 36
used
used
used
VP 37
used
VP 38
used
Core 1
Core 1
20
Core 2
Core 1
Core 2
rPerf
595
595
595
595
595
GHz
5.00
5.00
5.00
5.00
5.00
cores
64
48
32
16
8
rPerf
553.01
430.53
307.12
164.67
87.10
rPerf/core
8.64
8.97
9.60
10.29
10.89
LPAR 1 8 VP
VP 1
VP 2
VP 3
VP 4
VP 5
VP 6
VP 7
VP 8
VP 1
Core 1
Core 2
Core 3
VP 3
VP 4
Core 4
t3
t2
t1
t0
VP 2
Core 2
Core 3
Core 4
Additional
Context
switches
Configuration A
POOR PERFORMER - 8 VP > 4 CORES
Configuration B
GOOD PERFORMER 4 VP < 4 CORES
For my example it is equal : it should not.
The maximum parallelism degree (nb of VPs) for any LPAR is nb of CORES.
Configuration A does lose performance:
It can generate up to 3 VP Context Switches PLUS a hurting and useless loss of Processor affinity.
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t0
Core 1
Core 2
Core 3
1 second
Core 4
t1
CLEANING
(Save VP Context / Restore VP Context)
Launch/Stop
Core 1
Core 2
Core 3
Core 4
t2
Core 1
Core 2
Core 3
Core 4
CLEANING
(Save VP Context / Restore VP Context)
Launch/Stop
t3
Core 1
Launch/Stop Launch/Stop Launch/Stop
Core 2
Core 3
Core 4
Launch/Stop
CLEANING
(Save VP Context / Restore VP Context)
Launch/Stop
LPAR 1 8 VP 32 CPUs
VP 1
VP 2
VP 3
VP 4
VP 5
VP 6
VP 7
VP 8
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0-3
4-7
8-11
12-15
run
16-19
20-23
24-27
28-31
stop
0-3
4-7
8-11
12-15
stop
16-19
20-23
24-27
28-31
run
0-3
4-7
8-11
12-15
run
16-19
20-23
24-27
28-31
stop
0-3
4-7
8-11
12-15
stop
16-19
20-23
24-27
28-31
run
t0-t1-t2-t3
Core 1
Core 2
Core 3
VP 1
VP 2
VP 3
Core 4
Launch/Stop
VP 4
LPAR 1 4 VP 16 CPUs
CE: 4 due to 4 cores in Share Pool
Ratio CE/VP : 1.0
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0-3
4-7
8-11
12-15
0-3
4-7
8-11
12-15
0-3
4-7
8-11
12-15
0-3
4-7
8-11
12-15
Continuously vs Disruptive
24
.
THE VPs
0.x CE PER VP
(Desired CE)
25
SHARE POOL
SLICES = NB. CORES x 10
2011 IBM Corporation
Its LPAR 1 !
VP 2
VP 3
LPAR 3 4 VP CE 0.4
VP 4
VP 1
LPAR 2 4 VP CE 0.4
VP 1
VP 2
VP 3
VP 2
VP 3
VP 4
LPAR 4 4 VP CE 0.4
VP 4
VP 1
VP 2
VP 3
VP 4
4 VP
2.8
Cores
Core 2
Core 3
Core 4
LPAR1
)* 0.1
Here, you can not eat and you must give : (16 4) * 0.1 = 1.2 cores
VP 2
VP 3
LPAR 3 2 VP
VP 4
VP 1
VP 2
3.4
Cores
LPAR 2 2 VP
VP 1
VP 2
LPAR 4 2 VP
VP 1
VP 2
Core 2
Core 3
Core 4
The total of LPAR 2,3,4 deliver with the minimum each: VPtotal - VP
LPAR1
* 0.1
Here, you can not eat and you must give : (10 4) * 0.1 = 0.6 cores
Reduce the others means theres a ratio between nb of Cores and the nb of VPs
Example 1 : ratio = 4 (16 VPs / 4 cores) LPAR 1: max. physc is 2.8
Example 2 : ratio = 2.5 (10 VPs / 4 cores) LPAR 1: max. physc is 3.4
C
O
R
E
VP
THE CE
31
VP 11
VP 12
Core 0 Core 1 Core 2 Core 3 Core 4 Core 5 Core 6 Core 7 Core 8 Core 9 Core A Core B
Total
Shared Pool VPs :
4 VPshar
LPAR 3 4 VP DEDICATED
VP 30
VP 31
VP 32
VP 41
VP 42
vp10
vp11
vp12
vp20
vp30
vp31
vp32
vp33
vp40
vp41
vp42
vp43
vp20
vp30
vp31
vp32
vp33
vp40
vp41
vp42
vp43
vp20
vp30
vp31
vp32
vp33
vp40
vp42
vp43
vp30
vp31
vp32
vp33
vp40
vp41
vp42
vp43
vp30
vp31
vp32
vp33
vp41
vp42
vp43
vp30
vp31
vp32
vp33
vp41
vp42
vp43
vp30
vp31
vp32
vp33
vp41
vp42
vp43
vp30
vp31
vp32
vp33
vp40
vp41
vp30
vp31
vp32
vp33
vp40
vp41
vp42
vp30
vp31
vp32
vp33
vp40
vp41
vp42
VP 33
vp43
VP 43
LPAR 1, LPAR 2
LPAR 3
Shared Pool
Dedicated Cores
LPAR 4
Dedicated Donating
Cores
Each LPAR will receive its CAPACITY Entitlement (CE) every 10 ms (dispatch wheel).
Major difference between Shared, Dedicated, Dedicated Donating: IDLE CYCLES of Core.
Shared Pool: Processor Affinity is optimum due a fabulous ratio of 4VPSHAR = 4 COSHAR.
Shared Pool: Processor Affinity determined by pHyp based on the CE of each Shared LPAR.
32
LPAR 1
3 VP CE=0.3
Min. Required
VP 10
VP 11
VP 12
LPAR 3
4 VP Dedicated
it means CE=4 - %Entc 100%
VP 20
VP 30
VP 31
VP 32
VP 33
vp20
vp33
vp33
vp33
vp33
vp33
vp33
vp33
vp33
vp33
vp33
vp12
vp32
vp32
vp32
vp32
vp32
vp32
vp32
vp32
vp32
vp32
vp11
vp31
vp31
vp31
vp31
vp31
vp31
vp31
vp31
vp31
vp31
vp10
vp30
vp30
vp30
vp30
vp30
vp30
vp30
vp30
vp30
vp30
vp20
10
Shared Pool
CORE 0
CORE 1
10
Dedicated Cores
CORE 2
CORE 3
CORE 4
CORE 5
CORE 6
CORE 7
Each LPAR will receive its CAPACITY Entitlement every 10 ms (dispatch wheel).
CEVP is a ratio (CE LPAR/ VPLPAR).
The CE
vp20
LPAR 2
1 VP CE=0.3
VP 11
vp20
VP 12
LPAR 3
4 VP Dedicated
it means CE=4 - %Entc 100%
VP 20
VP 30
vp20
vp12
Dispatch interval
vp11
vp10
10
CORE 1
VP 32
VP 33
vp33
vp33
vp33
vp33
vp33
vp33
vp33
vp33
vp33
vp32
vp32
vp32
vp32
vp32
vp32
vp32
vp32
vp32
vp32
vp31
vp31
vp31
vp31
vp31
vp31
vp31
vp31
vp31
vp31
vp30
vp30
vp30
vp30
vp30
vp30
vp30
vp30
vp30
vp30
Shared Pool
CORE 0
VP 31
vp33
10
Dedicated Cores
CORE 2
CORE 3
CORE 4
CORE 5
CORE 6
CORE 7
For the SAME CELPAR , lets compare Performance of LPAR 1 with Performance of LPAR 2:
3 ms of core access (LPAR2) vs 1 ms of core access (LPAR1): 300% more or x 3 times of core access !!
Dispatch Interval:
34
Whos the
Winner ?
2011 IBM Corporation
LPAR 1
3 VP CE=0.3
Min. Required
VP 10
vp20
VP 11
vp20
vp12
vp12
vp11
vp11
vp11
vp10
vp10
vp10
VP 20
VP 30
vp33
Dispatch interval
10
vp33
vp33
CORE 1
vp33
VP 32
VP 33
vp33
vp33
vp33
vp33
vp33
vp33
vp32
vp32
vp32
vp32
vp32
vp32
vp32
vp32
vp32
vp32
vp31
vp31
vp31
vp31
vp31
vp31
vp31
vp31
vp31
vp31
vp30
vp30
vp30
vp30
vp30
vp30
vp30
vp30
vp30
vp30
10
Dedicated Cores
Shared Pool
CORE 0
VP 31
vp20
vp12
VP 12
LPAR 3
4 VP Dedicated
it means CE=4 - %Entc 100%
CORE 2
CORE 3
CORE 4
CORE 5
CORE 6
CORE 7
BUT,
Whos eating
the cake tonight ?
35
vp20
vp12
vp12
vp11
vp11
vp11
vp10
vp10
vp10
vp12
Dispatch interval
vp20
Dispatch interval
CAKE: 10 cores
VPs : 10 VPs
UNCAPPED Exposures
Processor Affinity Loss
Dispatch Delays
Adventures
10
Share Pool
Core 0Core 1Core 2Core 3Core 4Core 5 Core 6Core 7Core 8 Core 9
vp10
vp40
vp40
vp41
vp40
vp41
Share Pool
CAKE: 6 cores
VPs : 10 VPs
9
GOOD
FOR PERF
Shared Pool
A very calm and spaceful Share Pool
36
BAD
FOR PERF
Story of the
Interrupt
at 3ms
vp10
vp11 vp12
vp40
vp41 vp50
vp40
vp41 vp50
vp40
vp41 vp50
vp40
vp41 vp50
vp40
vp41 vp50
vp51 vp20
vp10
vp31
vp40 vp41
vp31
vp10 vp11
vp50
Shared Pool
The Jungle of a crowded subway
vp12
vp12
vp12
vp12
vp12
vp11
vp11
vp11
vp11
vp11
vp11
vp10
vp10
vp10
vp10
vp10
vp10
6ms = (CELPAR/VPLPAR) * 10
Dispatch interval
Potential uncapped
0.6
Or
10
= CELPAR / VPLPAR
(CE/VP)
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
37
Conclusions
We have reviewed :
Part I : Basic Concepts of PowerVM.
Part II : Technical Insights on the balance on CE / VP for shared LPARs.
We hope this will help you to size, configure and implement Power7 Servers.
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39
The IBM benchmarks results shown herein were derived using particular, well configured, development-level and generally-available computer systems. Buyers should
consult other sources of information to evaluate the performance of systems they are considering buying and should consider conducting application oriented testing. For
additional information about the benchmarks, values and systems tested, contact your local IBM office or IBM authorized reseller or access the Web site of the benchmark
consortium or benchmark vendor.
IBM benchmark results can be found in the IBM Power Systems Performance Report at http://www.ibm.com/systems/p/hardware/system_perf.html .
All performance measurements were made with AIX or AIX 5L operating systems unless otherwise indicated to have used Linux. For new and upgraded systems, AIX
Version 4.3, AIX 5L or AIX 6 were used. All other systems used previous versions of AIX. The SPEC CPU2006, SPEC2000, LINPACK, and Technical Computing
benchmarks were compiled using IBM's high performance C, C++, and FORTRAN compilers for AIX 5L and Linux. For new and upgraded systems, the latest versions of
these compilers were used: XL C Enterprise Edition V7.0 for AIX, XL C/C++ Enterprise Edition V7.0 for AIX, XL FORTRAN Enterprise Edition V9.1 for AIX, XL C/C++
Advanced Edition V7.0 for Linux, and XL FORTRAN Advanced Edition V9.1 for Linux. The SPEC CPU95 (retired in 2000) tests used preprocessors, KAP 3.2 for FORTRAN
and KAP/C 1.4.2 from Kuck & Associates and VAST-2 v4.01X8 from Pacific-Sierra Research. The preprocessors were purchased separately from these vendors. Other
software packages like IBM ESSL for AIX, MASS for AIX and Kazushige Gotos BLAS Library for Linux were also used in some benchmarks.
For a definition/explanation of each benchmark and the full list of detailed results, visit the Web site of the benchmark consortium or benchmark vendor.
TPC
http://www.tpc.org
SPEC
http://www.spec.org
LINPACK
http://www.netlib.org/benchmark/performance.pdf
Pro/E
http://www.proe.com
GPC
http://www.spec.org/gpc
VolanoMark
http://www.volano.com
STREAM
http://www.cs.virginia.edu/stream/
SAP
http://www.sap.com/benchmark/
Oracle Applications
http://www.oracle.com/apps_benchmark/
PeopleSoft - To get information on PeopleSoft benchmarks, contact PeopleSoft directly
Siebel
http://www.siebel.com/crm/performance_benchmark/index.shtm
Baan
http://www.ssaglobal.com
Fluent
http://www.fluent.com/software/fluent/index.htm
TOP500 Supercomputers
http://www.top500.org/
Ideas International
http://www.ideasinternational.com/benchmark/bench.html
Storage Performance Council http://www.storageperformance.org/results
40
The IBM benchmarks results shown herein were derived using particular, well configured, development-level and generally-available computer systems. Buyers should
consult other sources of information to evaluate the performance of systems they are considering buying and should consider conducting application oriented testing. For
additional information about the benchmarks, values and systems tested, contact your local IBM office or IBM authorized reseller or access the Web site of the benchmark
consortium or benchmark vendor.
IBM benchmark results can be found in the IBM Power Systems Performance Report at http://www.ibm.com/systems/p/hardware/system_perf.html .
All performance measurements were made with AIX or AIX 5L operating systems unless otherwise indicated to have used Linux. For new and upgraded systems, AIX
Version 4.3 or AIX 5L were used. All other systems used previous versions of AIX. The SPEC CPU2000, LINPACK, and Technical Computing benchmarks were compiled
using IBM's high performance C, C++, and FORTRAN compilers for AIX 5L and Linux. For new and upgraded systems, the latest versions of these compilers were used: XL
C Enterprise Edition V7.0 for AIX, XL C/C++ Enterprise Edition V7.0 for AIX, XL FORTRAN Enterprise Edition V9.1 for AIX, XL C/C++ Advanced Edition V7.0 for Linux, and
XL FORTRAN Advanced Edition V9.1 for Linux. The SPEC CPU95 (retired in 2000) tests used preprocessors, KAP 3.2 for FORTRAN and KAP/C 1.4.2 from Kuck &
Associates and VAST-2 v4.01X8 from Pacific-Sierra Research. The preprocessors were purchased separately from these vendors. Other software packages like IBM ESSL
for AIX, MASS for AIX and Kazushige Gotos BLAS Library for Linux were also used in some benchmarks.
For a definition/explanation of each benchmark and the full list of detailed results, visit the Web site of the benchmark consortium or benchmark vendor.
SPEC
http://www.spec.org
LINPACK
http://www.netlib.org/benchmark/performance.pdf
Pro/E
http://www.proe.com
GPC
http://www.spec.org/gpc
STREAM
http://www.cs.virginia.edu/stream/
Fluent
http://www.fluent.com/software/fluent/index.htm
TOP500 Supercomputers
http://www.top500.org/
AMBER
http://amber.scripps.edu/
FLUENT
http://www.fluent.com/software/fluent/fl5bench/index.htm
GAMESS
http://www.msg.chem.iastate.edu/gamess
GAUSSIAN
http://www.gaussian.com
ANSYS
http://www.ansys.com/services/hardware-support-db.htm
Click on the "Benchmarks" icon on the left hand side frame to expand. Click on "Benchmark Results in a Table" icon for benchmark results.
ABAQUS
http://www.simulia.com/support/v68/v68_performance.php
ECLIPSE
http://www.sis.slb.com/content/software/simulation/index.asp?seg=geoquest&
MM5
http://www.mmm.ucar.edu/mm5/
MSC.NASTRAN
http://www.mscsoftware.com/support/prod%5Fsupport/nastran/performance/v04_sngl.cfm
STAR-CD
www.cd-adapco.com/products/STAR-CD/performance/320/index/html
Revised March 12, 2009
NAMD
http://www.ks.uiuc.edu/Research/namd
HMMER
http://hmmer.janelia.org/
http://powerdev.osuosl.org/project/hmmerAltivecGen2mod
Copyright IBM Corporation 2012
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