Microprocessor 68000

 Introduction-
Today's computers are not the best possible machines designed by the brightest and best
engineers and programmers. They are the products of a development path that has relied as much on
whim and commercial considerations as on good engineering practice. This report puts the
microprocessor 68000 in an academic context and discusses architecture and its other features; also
its instruction set, application and other related topics are discussed here.

The Motorola 68000 is a 16/32-bit CISC microprocessor core designed and marketed by Free scale
Semiconductor (formerly Motorola Semiconductor Products Sector). Introduced in 1979 with HMOS
technology as the first member of the successful 32-bit m68k
family of microprocessors, it is generally software forward
compatible with the rest of the line despite being limited to a 16-
bit wide external bus. After three decades in production, the 68000
architecture is still in use. The 68000 did retain a bus protocol
compatibility mode for existing 6800 peripheral devices, and a version with an 8-bit data bus was
produced. However, the designers mainly focused on the future, or forward compatibility, which
gave the M68K platform a head start against later 32-bit instruction set architectures. For instance,
the CPU registers are 32 bits wide, though few self-contained structures in the processor itself
operate on 32 bits at a time. The original MC68000 was fabricated using an HMOS process with a
3.5-micrometre feature size. The 16.67 MHz "12F" version of the MC68000, the fastest version of
the original HMOS chip, was not produced until the late 1980s. Several other companies were
second-source manufacturers of the HMOS 68000. These included Hitachi (HD68000), Mostek
(MK68000), Rockwell (R68000), Signetics (SCN68000), Thomson/SGS-Thomson (originally
EF68000 and later TS68000), and Toshiba (TMP68000). Toshiba was also a second-source maker of
the CMOS 68HC000 (TMP68HC000).

 68000 Architecture and pin usage-

The 68000 has eight 32-bit data registers (D0-D7), eight 32-bit address registers (A0-A7), a
32-bit program counter, two 32-bit stack pointers, and a 16-bit status register. The processor is
capable of handling data as either 32-bit-long words, 16-bit words, bytes, or bits. The processor has
two modes of operation-Supervisor mode (operating system) and User mode (applications). The
mode of operation is made available to external hardware, thereby allowing the address decoder to
have separate supervisor and user spaces. The processors have an input clock that drives all processor
operation. Memory accesses typically take eight input clock cycles, provided that wait states are not
introduced. Many processors based upon the 68000 incorporate built-in address decoding and
software-configurable wait-state generation, making interfacing much simpler.

 Let us see the pinout of 68000 in detail-

Data bus and address bus-We have D0-D15 as the data bus. The address bus with its 23 lines labeled
A1-A23. A0 is missing here; its function is performed by LDS and UDS.

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68000, 68HC000 microprocessor - DIP 64 package  

Manufacturers: Hitachi, Mostek, Motorola, Rockwell, Signetics

D4 1 64 D5
D3 2 63 D6
D2 3 62 D7
D1 4 61 D8
D0 5 60 D9
AS 6 59 D10
UDS 7 58 D11
LDS 8 57 D12
R/W 9 56 D13
DTACK 10 55 D14
BG 11 54 D15
BGAC
12 53 GND
K
BR 13 52 A23
VCC 14 51 A22
CLK 15 50 A21
GND 16 49 VCC
HALT 17 48 A20
Reset 18 47 A19
VMA 19 46 A18
E 20 45 A17
VPA 21 44 A16
BERR 22 43 A15
IPL2 23 42 A14
IPL1 24 41 A13
IPL0 25 40 A12
FC2 26 39 A11
FC1 27 38 A10
FC0 28 37 A9
A1 29 36 A8
A2 30 35 A7
A3 31 34 A6
A4 32 33 A5

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Control lines- FC0,FC1,FC2 are three active high lines output a function code which can be
externally decoded to indicate what the 68000 is doing internally; it also could be used to increase the
68000's memory upto 64 MB if necessary.

FC0 FC1 FC2 Meaning

0 0 0 Not Used
0 0 1 User Data
0 1 0 User Program
0 1 1 Not Used
1 0 0 Not Used
1 0 1 Supervisor Data
1 1 0 Supervisor Program
1 1 1 Interrupt Acknowledge

E (Enable Clock), VMA (Valid Memory Access), and VPA (valid peripheral address) are useful if
the 68000 is used with older I/O chips, those originally intended for Motorola’s 6800 processor. VPA
is also provides some interrupt information, and that is the only function the SK68K system will use
for it.
IPL0, IPL1, IPL2 are interrupt level inputs. These three inputs tell the 68000 whether an interrupt is
being asked for, and what kind of interrupt it is.
The RESET and HALT inputs come from 555 circuit; but these two pins are also output pins. HALT
is used to suspend processor operation without generating a reset.
BR, BG and BGACK are used when DMA circuitry is used. If DMA were used, the DMA controller
circuit would send a bus request (BR) to the 68000, which would release the buses and return a Bus
Grant (BG) signal. The DMA controller would then send a Bus Grant Acknowledge (BGACK) signal
to confirm that it has control of the buses, and temporarily take over the system while 68000 sits back
and waits.
LDS and UDS replace address line A0 in an interesting way. Since the 68000 has a 16 bit data bus
whereas memory is divided into 8-bit byte, the data bus can access two bytes at a time. The memory
is wired so that half of the memory- all the odd-numbered locations connects to the lower part of the
data bus, while the other half memory is connected to the upper half of the data bus. The 68000
asserts LDS (lower address strobe) when it wants to use upper half of the bus, or asserts UDS (upper
address strobe) when it wants to access the upper half of the bus, or asserts both if it wants to transfer
16- bits on the entire bus. Thus an odd address turns on LDS while an even address turns on UDS;
this is similar to the function of A0 pin.
AS is an address strobe which is generally asserted by the 68000 at the same time as either LDS or
UDS, and simply tells external circuitry (mainly address decoder0 that there is valid address on the

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address bus. This is important, since the address bus often carries data which is not meaningful; there
has to be a way to prevent address decoders from responding to it in error.
We also have R/W which stands for read/write. This is a signal used by the 68000 to tell other
circuitry whether it wants to read data or write data.
BERR is an input to the 68000, used by external circuitry to tell the 68000 that something has gone
wrong on one of the buses. This allows the system to trap out accesses to unused regions of memory
space or, in combination with the status lines, to detect user access to memory space allocated for
supervisor use only. For example, if a program crashes and in the process of crashing attempts to
access a region of memory to which no device is allocated, the address decoder is able to signal that
fault back to the processor. An assertion of BERR causes the processor to execute an interrupt and
take appropriate action.
DTACK (Data Transfer Acknowledge) is used by external devices to indicate to the processor that it
may terminate its current memory cycle. (Some 68000 processors call their Data Transfer
Acknowledge DTACKB.) Whenever the 68000 wants to read or write to memory or I/O device.
When 68000 want to write or read data; it
1. Puts the address on the address bus
2. Puts high or low on R/W
3. Output address strobe and LDS and/or UDS, then sits back and waits. It waits until it either gets
back DTACK, indicating that the transfer is finished or BERR indicating that something went wrong.
When DTACK is received, then the 68000 goes on to next step.
The master 68000 clock is called MPUCLK. In basic SK68K system, this clock could be slow as
8MHz or as fast as 12.5 MHz it is this clock that governs how fast 68000 perform its operations.
The MODE pin, present on only some 68000 processors, determines whether the 68000 uses its data
bus as 16 bits or 8 bits. MODE is sampled as the processor comes out of reset. AVEC, also found in
only some 68000 processors, determines whether the processor uses auto vectoring for its interrupts.
If auto vectoring is enabled, the processor will expect the interrupting peripheral to supply the
appropriate vector. This allows a peripheral to specify what type of action the processor needs to take
when a given interrupt is generated. Other 68000 processors may have other signals as well, but these
are the main ones.

Timings of 68000 microprocessor- The memory cycle of a 68000 is divided into a number of clock
states, S0 through to S7. The cycle begins with state S0. The processor validates R/W for the coming
cycle, sending it low for a write access, driving it high for a read access. The processor also tristates
its address bus from the previous memory access. By S2 the processor has output a valid address and
drives the address strobe (AS) low indicating that a valid address is present. The lower and upper
data strobes (LDS and UDS) go low as appropriate and indicate the width of the memory access
taking place. For a 16-bit transfer, both LDS and UDS assert. For an 8-bit transfer, only one of LDS
or UDS will assert, depending on whether the upper byte or lower byte is being transferred. If the
current memory access is a write cycle, the processor outputs valid data in state S3. At this point, all
outputs from the processor are now valid and the processor waits for the device being accessed to
respond. At the falling edge of the clock in S4, the processor begins checking the state of the Data
Transfer Acknowledge (DTACK) input. If DTACK is high, the processor inserts wait states and

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continues to do so until DTACK is found to be low on the falling edge of the clock. (I'll discuss how
to generate wait states later in the chapter.) When DTACK is low, the processor recognizes this as an
indication that the device being accessed has had sufficient time to respond and prepares to terminate
the cycle. If the cycle is a read cycle, the processor will latch data on the falling edge of the clock in
state S6. If it is a write cycle, the device being accessed will latch data as the data strobes go high in
S7.

Support for synchronous operation is also provided for, using control signals found in the old 6800
series of processors. Since 6800s have long since passed into history and 6800-compatible
peripherals are now exceptionally rare, just ignore the 6800 control signals. Most 68000-based
derivative processors no longer include support for 6800 peripherals.

 Address bus-
The original 68000 has a 23-bit address bus (A1 to A23), giving it access to a memory space
of 16M, and a 16-bit data bus. Most other processors based on the 68000 architecture have address
and data buses of 32 bits and can therefore access up to 4G of memory.

The 68000 had a 23-bit external address bus and two byte-select signals "replaced" A0. These 25-
lines could therefore reach 16 MB of physical memory with byte resolution. Address storage and
computation used 32 bits, however, with the high-order byte ignored due to the physical lack of pins.
This allowed it to run software written for a flat 32-bit address space. By modern definition this
meant that the 68000 was a 32-bit microprocessor. Motorola's intent with the internal 32-bit address
space was forwards compatibility, making it feasible to write 68000 software that would take full
advantage of later 32-bit implementations of the 68000 instruction set.

However, this did not prevent programmers from writing forward incompatible software. "24-bit"
software that discarded the upper address byte, or used it for purposes other than addressing, could
fail on 32-bit 68K implementations. An example of this is Apple's Macintosh computers which did
not have "32-bit clean" ROMs until the release of the 1989 Mac IIci. The 68000 was a clever
compromise. When the 68000 was introduced, 16-bit buses were really the most practical size.
However, the 68000 was designed with 32-bit registers and address spaces, on the assumption that
hardware prices would fall. It is important to note that even though the 68000 had 16-bit ALUs,
addresses were always stored as 32-bit quantities, i.e. it had a flat 32-bit address space. Contrast this
to the 8086, which had 20-bit address space, but could only access 16-bit (64 kilobyte) chunks
without manipulating segment registers. The 68000 achieved this functionality using three 16-bit
ALUs. In normal operation, two 16-bit ALUs are chained together to perform an address operation,
while the third executes the 16-bit arithmetic. For example, a 32-bit address register post increment
on a 16-bit ADD.W (An) +, Dn runs without speed penalty. So even though starting out as "16-bit"
CPU, the 68000 instruction set describes a 32-bit architecture. The importance of architecture cannot
be emphasized enough. Throughout history, addressing pains have not been hardware
implementation problems, but always architectural problems (instruction set problems, i.e. software
compatibility problems). The successor 68020 with 32-bit ALU and 32-bit data bus runs unchanged

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 Microprocessor 68000

68000 software at "32-bit speed", manipulating data up to 4 gigabytes, far beyond what software of
other "16-bit" CPUs (for example, the 8086) could do.

 Internal registers-
The CPU had eight 32-bit general-purpose data registers (D0-D7), and eight address registers
(A0-A7). The last address register was also the standard stack pointer, and could be called either A7
or SP. This was a good number of registers in many ways. It was small enough to allow the 68000 to
respond quickly to interrupts (because only 15 or 16 had to be saved), and yet large enough to make
most calculations fast.

Having two types of registers was mildly annoying at times, but not hard to use in practice.
Reportedly, it allowed the CPU designers to achieve a higher degree of parallelism, by using an
auxiliary execution unit for the address registers. Integer representation in the 68000 family is big-
endian.
 Description of 68000 Registers-
• Program Counter (PC) - points to the next instruction to be executed (24 bits).
• General Purpose Registers - D0 through D7
o Called "general purpose" because registers can each perform the same range of
functions.
o 32 bits wide, but can be divided into 2 words or 4 bytes.
o Bits in the data register have an arbitrary meaning; e.g., two's complement number,
unsigned integer, or ASCII characters.
o Word operations applied to these registers can only use the low order 16 bits (d 15…
d0).
o Byte operations applied to these registers can only use the low order 8 bits (d 7…d0).
o Address Registers - A0 through A7
o Called "address registers" because they are always used to store the address of a
memory location. 32 bits wide, but cannot be subdivided.
o A0 through A6 can be used as you see fit; however, A7 is the stack pointer which is
needed to keep track of subroutine return addresses. Therefore, you should not use A7
explicitly.
• CCR Register contains the following flags:
X- Extend flag (similar to the carry flag)
N- Negative flag - true if first bit 1 (sign bit or MSB of result is = 1)
Z- Zero flag - true if all bits 0 (result is equal to zero).
V- Overflow flag (2’s complement overflow)
C- Carry flag (carry out bit from an arithmetic operation).
Certain operations effect all bits; e.g., arithmetic. Certain operations affect only some of the
bits (e.g., Logical operations do not affect overflow or carry). Certain operations do not affect any
of the bits (e.g., exchange registers).

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Microprocessor 68000

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 Status register-
The 68000 comparison, arithmetic and logic operations set bit flags in a status register to
record their results for use by later conditional jumps. The bit flags were "zero" (Z), "carry" (C),
"overflow" (V), "extend" (X), and "negative" (N). The "extend" (X) flag deserves special mention,
because it was separated from the carry flag. This permitted the extra bit from arithmetic, logic, and
shift operations to be separated for the carry for flow-of-control and linkage.

 The instruction set-

The designers attempted to make the assembly language orthogonal. That is, instructions
were divided into operations and address modes, and almost all address modes were available for
almost all instructions. Many programmers disliked the "near" orthogonality, while others were
grateful for the attempt.

At the bit level, the person writing the assembler would clearly see that these "instructions" could
become any of several different op-codes. It was quite a good compromise because it gave almost the
same convenience as a truly orthogonal machine, and yet also gave the CPU designers freedom to fill
in the op-code table.

With only 56 instructions the minimal instruction size was huge for its day at 16 bits. Furthermore,
many instructions and addressing modes added extra words on the back for addresses, more address-
mode bits, etc.

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 Microprocessor 68000

Many designers believed that the MC68000 architecture had compact code for its cost, especially
when produced by compilers. This belief in more compact code led to many of its design wins, and
much of its longevity as an architecture through updated CPUs. This lasted up until the ARM
architecture introduced the Thumb instruction set that was similarly compact.

 Privilege levels-
The CPU, and later the whole family, implemented exactly two levels of privilege. User
mode gave access to everything except the interrupt level control. Supervisor privilege gave access to
everything. An interrupt always became supervisory. The supervisor bit was stored in the status
register, and visible to user programs.

A real advantage of this system was that the supervisor level had a separate stack pointer. This
permitted a multitasking system to use very small stacks for tasks, because the designers did not have
to allocate the memory required to hold the stack frames of a maximum stack-up of interrupts.

 Interrupts-
The CPU recognized 7 interrupt levels. Levels 1 through 7 were strictly prioritized. That is, a
higher-numbered interrupt could always interrupt a lower-numbered interrupt. In the status register, a
privileged instruction allowed one to set the current minimum interrupt level, blocking lower priority
interrupts. Level 7 was not maskable - in other words, an NMI. Level 1 could be interrupted by any
higher level. Level 0 means no interrupt. The level was stored in the status register, and was visible
to user-level programs.

Hardware interrupts are signaled to the CPU using three inputs that encode the highest pending
interrupt priority. A separate interrupt controller is usually required to encode the interrupts, though
for systems that do not require more than three hardware interrupts it is possible to connect the
interrupt signals directly to the encoded inputs at the cost of additional software complexity. The
interrupt controller can be as simple as a 74LS148 priority encoder, or may be part of a VLSI
peripheral chip such as the MC68901 Multi-Function Peripheral, which also provided a UART,
timer, and parallel I/O.

The "exception table" (interrupt vector addresses) was fixed at addresses 0 through 1023, permitting
256 32-bit vectors. The first vector was the starting stack address, and the second was the starting
code address. Vectors 3 through 15 were used to report various errors: bus error, address error, illegal
instruction, zero division, CHK & CHK2 vector, privilege violation, and some reserved vectors that
became line 1010 emulator, line 1111 emulator, and hardware breakpoint. Vector 24 started the real
interrupts: spurious interrupt (no hardware acknowledgement), and level 1 through level 7
autovectors, then the 15 TRAP vectors, then some more reserved vectors, then the user defined
vectors.

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 Microprocessor 68000

Since at a minimum the starting code address vector must always be valid on reset, systems
commonly included some nonvolatile memory (e.g. ROM) starting at address zero to contain the
vectors and bootstrap code. However, for a general purpose system it is desirable for the operating
system to be able to change the vectors at runtime. This was often accomplished by either pointing
the vectors in ROM to a jump table in RAM, or through use of bank-switching to allow the ROM to
be replaced by RAM at runtime.

The 68000 did not meet the Popek and Goldberg virtualization requirements for full processor
virtualization because it had a single unprivileged instruction "MOVE from SR", which allowed
user-mode software read-only access to a small amount of privileged state.

The 68000 was also unable to easily support virtual memory, which requires the ability to trap and
recover from a failed memory access. The 68000 does provide a bus error exception which can be
used to trap, but it does not save enough processor state to resume the faulted instruction once the
operating system has handled the exception. Several companies did succeed in making 68000 based
UNIX workstations with virtual memory that worked, by using two 68000 chips running in parallel
on different phased clocks. When the "leading" 68000 encountered a bad memory access, extra
hardware would interrupt the "main" 68000 to prevent it from also encountering the bad memory
access. This interrupt routine would handle the virtual memory functions and restart the "leading"
68000 in the correct state to continue properly synchronized operation when the "main" 68000
returned from the interrupt.

These problems were fixed in the next major revision of the 68K architecture, with the release of the
MC68010. The Bus Error and Address Error exceptions pushed a large amount of internal state onto
the supervisor stack in order to facilitate recovery, and the MOVE from SR instruction was made
privileged. A new unprivileged "MOVE from CCR" instruction was provided for use in its place by
user mode software; an operating system could trap and emulate user-mode MOVE from SR
instructions if desired.
 Instruction set details-
The standard addressing modes are:
 Register direct
o data register, e.g. "D0"
o address register, e.g. "A6"
 Register indirect
o Simple address, e.g. (A0)
o Address with post-increment, e.g. (A0)+
o Address with pre-decrement, e.g. -(A0)
o Address with a 16-bit signed offset, e.g. 16(A0)
o Indexed register indirect with 8-bit signed offset e.g. 8(A0, D0) or 8(A0, A1)
Note that with (A0)+ and -(A0), the actual increment or decrement value is dependent on the operand
size: a byte access increments the address register by 1, a word by 2, and a long by 4.

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 Microprocessor 68000

 PC (program counter) relative with displacement

o Relative 16-bit signed offset, e.g. 16(PC). This mode was very useful.
o Relative with 8-bit signed offset with index, e.g. 8(PC, D2)
 Absolute memory location
o Either a number, e.g. "$4000", or a symbolic name translated by the assembler
o Most 68000 assemblers used the "$" symbol for hexadecimal, instead of "0x".
o There were 16 and 32-bit version of this addressing mode
 Immediate mode
o Stored in the instruction, e.g. "#400".
 Quick Immediate mode
o 3 bit unsigned (or 8 bit signed with moveq) with value stored in Opcode.
o In addq and subq, 0 is the equivalent to 8.
o e.g. moveq.l #0,d0 was quicker than clr.l d0 (though both made d0 equal 0)
Plus: access to the status register, and, in later models, other special registers.
Most instructions had dot-letter suffixes, permitting operations to occur on 8-bit bytes (".b"), 16-bit
words (".w"), and 32-bit longs (".l").
Most instructions are dyadic, that is, the operation has a source, and a destination, and the destination
is changed. Notable instructions were:
 Arithmetic: ADD, SUB, MULU (unsigned multiply), MULS (signed multiply), DIVU,
DIVS, NEG (additive negation), and CMP (a sort of subtract that set the status bits, but did not
store the result)
 Binary Coded Decimal Arithmetic: ABCD, and SBCD
 Logic: EOR (exclusive or), AND, NOT (logical not), OR (inclusive or)
 Shifting: (logical, i.e. right shifts put zero in the most significant bit) LSL, LSR, (arithmetic
shifts, i.e. sign-extend the most significant bit) ASR, ASL, (Rotates through extend and not :)
ROXL, ROXR, ROL, ROR
 Bit manipulation in memory: BSET (to 1), BCLR (to 0), and BTST (set the Zero bit)
 Multiprocessing control: TAS, test-and-set, performed an indivisible bus operation,
permitting semaphores to be used to synchronize several processors sharing a single memory
 Flow of control: JMP (jump), JSR (jump to subroutine), BSR (relative address jump to
subroutine), RTS (return from subroutine), RTE (return from exception, i.e. an interrupt), TRAP
(trigger a software exception similar to software interrupt), CHK (a conditional software
exception)
 Branch: Bcc (a branch where the "cc" specified one of 16 tests of the condition codes in the
status register: equal, greater than, less-than, carry, and most combinations and logical
inversions, available from the status register).
 Decrement-and-branch: DBcc (where "cc" was as for the branch instructions) which
decremented a D-register and branched to a destination provided the condition was still true and
the register had not been decremented to -1. This use of -1 instead of 0 as the terminating value
allowed the easy coding of loops which had to do nothing if the count was 0 to begin with,

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 Microprocessor 68000

without the need for an additional check before entering the loop. This also facilitated nesting of
DBcc.

 Basic Characteristics of 68000 Assembly Language-

• An assembly language program line or statement is comprised of the following 4 columns:
• Optional label which must begin in column
• An instruction;
o These are the actual instructions themselves, such as MOVE, ADD, etc.
o Opcode fields: The suffixes `.B', `.W', and `.L' denote a byte, word, and long-
word operation, respectively. If not specified, the default is word size (.W).
o Basic addressing modes
Dn data register
An address register
#n constant or immediate
n contents of memory location
• Its operand or operands.
• An optional comment field.
• A line beginning with an asterisk * in the first column is a comment and is totally ignored by
the assembler.
• Number systems are represented as follows:
o A number without any prefix is decimal.
o A number with a leading ‘$’ is hex.
o A number with a leading ‘%’ is binary.
• Enclosing a string in quotes represents a sequence of ASCII characters.
• At least one space is required to separate the label and comment field from the instruction;
but additional spaces are added for readability.
• The following data sizes apply:
o Byte - 8 bits
o Word - 16 bits (default operand size for most instructions).
o Long word - 32 bits

 Applications-
The 68000 had many high-end design wins early on. It became the dominant CPU for Unix
based workstations including Sun workstations and Apollo/Domain workstations, found its way into
heralded computers such as the Amiga, Atari ST, Apple Lisa and Macintosh, and was used in the
first generation of desktop laser printers including the original Apple Inc. LaserWriter. In 1982, the
68000 received an update to its ISA allowing it to support virtual memory and to conform to the
Popek and Goldberg virtualization requirements. The updated chip was called the 68010. A further
extended version which exposed 31 bits of the address bus was also produced, in small quantities, as
the 68012. At its introduction, the 68000 was first used in high-priced systems, including multiuser

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microcomputers like the WICAT 150 [1], early Alpha Microsystems computers, Tandy TRS-80
Model 16, and Fortune 32:16; single-user workstations such as Hewlett-Packard's HP 9000 Series
200 systems, the first Apollo/Domain systems, Sun Microsystems' Sun-1, and the Corvus Concept;
and graphics terminals like Digital Equipment Corporation's VAXstation 100 and Silicon Graphics'
IRIS 1000 and 1200. UNIX systems rapidly moved to the more capable later generations of the 68k
line, which remained popular in that market throughout the 1980s. By the mid 1980s, falling
production cost made the 68000 viable for use in personal and home computers, starting with the
Apple Lisa and Macintosh, and followed by the Commodore Amiga, Atari ST, and Sharp X68000.

Video game manufacturers used the 68000 as the backbone of many arcade games and home game
consoles: Atari's Food Fight, from 1983, was one of the first 68000-based arcade games. Others
included Sega's System 16, Capcom's CP System and CPS-2, and SNK's Neo Geo. By the late 1980s,
the 68000 was inexpensive enough to power home game consoles, such as Sega's Mega Drive
(Genesis) console. The 1993 multi-processor Atari Jaguar console used a 68000 as a support chip,
although some developers used it as the primary processor due to familiarity.
The 68000 also saw great success as an embedded controller. As early as 1981, laser printers such as
the Imagen Imprint-10 were controller by external boards equipped with the 68000. The first HP
LaserJet, introduced in 1984, came with a built-in 8MHz 68000. Other printer manufacturers adopted
the 68000, including Apple with its introduction of the LaserWriter in 1985, the first PostScript laser
printer. The 68000 continued to be widely used in printers throughout the rest of the 1980s, persisting
well into the 1990s in low-end printers.

The 68000 also saw success in the field of industrial control systems. Among the systems which
benefited from having a 68000 or derivative as their microprocessor were families of Programmable
Logic Controllers (PLCs) manufactured by Allen-Bradley, Texas Instruments and subsequently,
following the acquisition of that division of TI, by Siemens. Users of such systems do not accept
product obsolescence at the same rate as domestic users and it is entirely likely that despite having
been installed over 20 years ago, many 68000-based controllers will continue in reliable service well
into the 21st century. As a microcontroller core- After being succeeded by "true" 32-bit
microprocessors, the 68000 was used as the core of many microcontrollers. In 1989, Motorola
introduced the MC68302 communications processor,

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