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    Xilinx Vivado Webpack Download and Installation Tool Guide For EECS31L Fall 2016

    Uploaded by

    reach.tarunp9510
    The document provides instructions for downloading and installing the Vivado Design Suite tools, which are needed for an EECS course. It explains how to get the free Webpack version from the Xilinx website, install it on your computer, and generate a license. It also gives basic steps for creating a new project in Vivado, adding source files, running a simulation, and synthesizing a design.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    Xilinx Vivado Webpack Download and Installation Tool Guide For EECS31L Fall 2016

    Uploaded by

    reach.tarunp9510
    136 views8 pages
    The document provides instructions for downloading and installing the Vivado Design Suite tools, which are needed for an EECS course. It explains how to get the free Webpack version from the Xilinx website, install it on your computer, and generate a license. It also gives basic steps for creating a new project in Vivado, adding source files, running a simulation, and synthesizing a design.

    Original Description:

    Tutorial to download VIVADO webpack edition and synthesize a System Verilog file.

    Original Title

    Vivado Tutorial

    Copyright

    © © All Rights Reserved

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    The document provides instructions for downloading and installing the Vivado Design Suite tools, which are needed for an EECS course. It explains how to get the free Webpack version from the Xilinx website, install it on your computer, and generate a license. It also gives basic steps for creating a new project in Vivado, adding source files, running a simulation, and synthesizing a design.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    136 views8 pages

    Xilinx Vivado Webpack Download and Installation Tool Guide For EECS31L Fall 2016

    Uploaded by

    reach.tarunp9510
    The document provides instructions for downloading and installing the Vivado Design Suite tools, which are needed for an EECS course. It explains how to get the free Webpack version from the Xilinx website, install it on your computer, and generate a license. It also gives basic steps for creating a new project in Vivado, adding source files, running a simulation, and synthesizing a design.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    You are on page 1of 8

    Xilinx Vivado webpack download and installation

    Tool Guide for EECS31L


    Fall 2016
    This guide explains how to download and install the Vivado Design Suite tools. You will use
    this suite throughout the course. There are multiple versions of this tool. Here we will focus on
    installation of Webpack version which is free and available to all students.

    Downloading the Vivado suite


    All Editions and download options are available on the Xilinx website:
    http://www.xilinx.com/support/download.html
    Select the appropriate version for your laptop operating system. You would need a Xilinx
    account to download the tools. Register with your UCI email and sign in to download the Xilinx
    toolchain. This would be a file less than 100MB which will both download and install the tool for
    you. An example of this would be Xilinx_Vivado_SDK_2016.2_0605_1_Win64.exewhich
    indicates you have downloaded the Vivado SDK installer version 2016.2 for 64-bit Windows
    machine.

    Installing the Vivado Design Suite Tools


    This section explains the installation process for all platforms for the Vivado Design Suite.
    Couple points before extracting and installing the tools. Make sure your machine can support
    this toolchain. You can check this on Xilinx website. Also make sure that you have enough
    space on your system for this tool. It might take up to few Gigabytes. Now lets start the installer
    you have downloaded in the previous step. After you click on your installer it will extract the tool
    and prepare it for installation.

    A window will pop up asking about your installation type and your Xilinx account. You can use
    the account youve made at the beginning on the Xilinx website. Select the download and install
    now option.

    License and edition Selection


    In the next step you would select which edition of the Vivado tool you want to install. For now,
    we can install the webpack installation which doesnt require any license. In the next steps
    follow the prompt and make sure in tools or devices select the 7 series in devices.

    Download and installation


    Final section of the installation promp will start to download the full image of the Vivado tool
    which even with fast internet connection will take long time. Try to do this part before the class.
    After downloding the full image the installation process will take place.

    Licensing
    After installation open License Manager, select Get Free ISE WebPack, ISE/Vivado IP or
    PetaLinux License and click Connect Now.

    This step should take you to a webpage. Over here, generate Node-Locked License by
    selecting the WebPack license.

    After generating a license file, you will receive an email from xilinx.notification@entitlenow.com.
    This may take several minutes/hours depending on Xilinx servers. Follow the instructions in the
    email to activate your license.

    Vivado Project creation, Simulation and Synthesis.


    Open Vivado Design Studio, and select Create New Project
    A new window should appear. Enter the name and the location for the new project.
    For example, enter lab1 in the Project name field. Make sure that the Create Project
    Subdirectory box is checked. Click Next.
    Select RTL Project option in the Project Type form, make sure Do not specify sources at this
    time is selected, and click Next.

    We will be using Basy3 boards in the future, select xc7a35tcpg236-1 part. Click next.

    Click finish to create a Vivado Project.

    A new project navigator and project manager is created. We will be using System Verilog for
    EECS31L. Make sure the target language is set to Verilog. By doing so we can run both System
    Verilog (.sv) and Verilog (.v) files.

    Next, we can either create or add a design files. For this project we will work on Full Adder.
    In the Project Navigator window select Add Sources.
    Make sure your select Add or create design sources. Please select fulladder.sv downloaded
    from the website. This is a source file that contains the description of a full adder. You may
    check Copy sources into project if you wish to copy the source file to the project folder. Click
    Finish to continue.
    You also want to add a testbench to the project. It will let you test your design by simulating
    various inputs and observing the outputs. Select Add Sources and Add or create simulation
    sources this time. Add the fulladder_tb.sv after clicking the green plus icon. Click Finish.

    The Full adder design and test bench files should appear in the Project Manager tab. The files
    can be edited just by double clicking on them.

    Simulation:
    First step is to simulate the design and verify the functionality. Select fulladder_tb.sv file and
    click Run Simulation > Run Behavioral Simulation
    You can check the functionality of your source code by monitoring the behavior of the
    waveforms.

    Synthesis:
    Next step is to make sure your design file is synthesizable. Only a synthesizable design can be
    implemented on an evaluation board.
    All your design files should be synthesizable, test-benches cannot be synthesized. To
    synthesize your design, select your fulladder.sv (design) file and click Run Synthesis. A log file
    is created and you can check the log file to verify if the synthesis is successful or not.

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