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    Logic Design Syllabus

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    naciye karademir
    This document provides information about the Logic Design course offered at Middle East Technical University Northern Cyprus Campus for the Electrical & Electronics and Computer Engineering programs. It lists the instructors, their contact information, course and lab schedules, required textbooks, software, course objectives, outline, grading breakdown, lab schedule, and policies regarding academic integrity. The course introduces students to logic design principles including boolean algebra, combinational and sequential logic circuits, and digital design using hardware description languages and FPGAs. Labs involve designing and implementing logic circuits in a step-by-step process culminating in a final project to design a simple calculator or similar system.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    Logic Design Syllabus

    Uploaded by

    naciye karademir
    163 views2 pages
    This document provides information about the Logic Design course offered at Middle East Technical University Northern Cyprus Campus for the Electrical & Electronics and Computer Engineering programs. It lists the instructors, their contact information, course and lab schedules, required textbooks, software, course objectives, outline, grading breakdown, lab schedule, and policies regarding academic integrity. The course introduces students to logic design principles including boolean algebra, combinational and sequential logic circuits, and digital design using hardware description languages and FPGAs. Labs involve designing and implementing logic circuits in a step-by-step process culminating in a final project to design a simple calculator or similar system.

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    This document provides information about the Logic Design course offered at Middle East Technical University Northern Cyprus Campus for the Electrical & Electronics and Computer Engineering programs. It lists the instructors, their contact information, course and lab schedules, required textbooks, software, course objectives, outline, grading breakdown, lab schedule, and policies regarding academic integrity. The course introduces students to logic design principles including boolean algebra, combinational and sequential logic circuits, and digital design using hardware description languages and FPGAs. Labs involve designing and implementing logic circuits in a step-by-step process culminating in a final project to design a simple calculator or similar system.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    163 views2 pages

    Logic Design Syllabus

    Uploaded by

    naciye karademir
    This document provides information about the Logic Design course offered at Middle East Technical University Northern Cyprus Campus for the Electrical & Electronics and Computer Engineering programs. It lists the instructors, their contact information, course and lab schedules, required textbooks, software, course objectives, outline, grading breakdown, lab schedule, and policies regarding academic integrity. The course introduces students to logic design principles including boolean algebra, combinational and sequential logic circuits, and digital design using hardware description languages and FPGAs. Labs involve designing and implementing logic circuits in a step-by-step process culminating in a final project to design a simple calculator or similar system.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 2

    MIDDLE EAST TECHNICAL UNIVERSITY NORTHERN CYPRUS CAMPUS

    ELECTRICAL & ELECTRONICS / COMPUTER ENGINEERING PROGRAMS


    EEE-248 / CNG-232 (3-2) 4

    LOGIC DESIGN

    Spring-2016

    Instructor

    Office

    Phone

    e-mail

    DERV DENZ

    T-136

    661-3012

    ddeniz@metu.edu.tr

    BURAK BARDAK

    TZ-40

    661-3431

    bbardak@metu.edu.tr

    Course Schedule: CNG232: Friday 12:40-15:30, Room TZ-07


    EEE248: Monday 15:40-17:30, Wed.11:40-12:30 all in room R-102
    Office Hours :
    D. Deniz Wed. 11:40-12:30 and Fri. 11:40-12:30
    B. Bardak Mon. 14:00-15:30 and Thu. 14:30-15:30
    Lab Schedule:

    CNG232: Lab_S2: Tue.15:40-18:30; Lab_S3: Wed.17:40-20:30 in RZ-05;


    EEE248: Lab_S1: Tue.12:40-15:30; Lab_S4: Thu. 13:40-16:30 all in RZ-05

    Lab Assistants:

    Muhammad S. Rashid; e-mail:saleh.rashid@metu.edu.tr;T:2950;Office:RZ-08;OfficeHrs:M.11:00-13:00


    Kathy Kiema, e-mail: kathy.kiema@metu.edu.tr; T:3441; Office:TZ-18; OfficeHrs: M and W.13:30-15:00
    Huriye zdemir,e-mail:e219338@metu.edu.tr;T:N/A;Office:R-115;OfficeHrs:T&F8:40-10:40;W:13:40-15:30

    Main Text:
    Auxiliary Text:

    Mano & Ciletti, Digital Design (4th Ed.), Prentice Hall, 2007.
    Wakerly, Digital Design Principles and Practices (4th Ed.), Prentice Hall, 2006.
    Brown & Vranesic, Fund. of Dig. Logic with VHDL Design (2nd Ed.), McGraw Hill, 2005.
    You will have to download and use Altera Quartus II Web Edition (for Windows) in preparation for the
    labs - in order to minimize installation size please pick Cyclone Components only. Since the results are
    reported in timing waveform, you need a version earlier than v10.0.

    Software:

    Course Objectives: Having successfully completed this course, the student will be able to:
    (1) Use boolean algebra and logic principles to solve problems of digital nature
    (2) Analyze and interpret the functions of logic circuits modeled analytically or through schematic drawings
    (3) Apply combinational and sequential design techniques to solve symbolically and verbally defined problems with
    medium complexity
    (4) Identify and use small and medium size logic building blocks to design small systems to solve digital problems
    (5) Use Computer-Aided-Design (CAD) tools, hardware description languages (e.g. VHDL or Verilog), and FieldProgrammable Gate Arrays (FPGAs) to design, model, simulate, implement, and test partial logic circuits, building up
    to the working demonstration of a simple calculator, or similar system with a controller and a datapath, at the
    Laboratory Final

    Course Outline (Tentative)


    Week
    #
    1

    Week Starts
    22-Feb

    Introduction, Number Systems, Arithmetic Operations, Binary Logic

    29-Feb

    7-Mar

    14-Mar

    21-Mar

    28-Mar

    Boolean Algebra / Theorems, Duality, Positive/Negative Logic


    XOR/XNOR, Translating a Problem to Boolean, Minterm/Maxterm
    Expansions, Karnaugh Maps
    Karnaugh Maps, Multi-Level Gate Networks, Functionally Complete
    Sets of Logic Gates
    Combinational Circuit Design Flow, MSI Functional Blocks
    Latches, Flip-Flops;

    4-Apr

    11-Apr

    State Tables, State Diagrams, Seq. Cct. Design Examples; Midterm 1

    18-Apr

    Synchronous Counters, Registers, Shifters

    10

    25-Apr

    Synchronous Counters, Registers, Shifters; FSMs and Datapaths

    11

    2-May

    FSMs and Datapaths;

    12

    9-May

    Fan-In/Out, Gate Delays, Sequential Circuit Timing; Midterm 2

    13

    16-May

    14

    23-May

    15

    30-May/11-Jun

    Grading:

    HW
    Out
    1

    HW
    Due

    : 20%
    : 35%
    : 10%
    : 15%

    Lab
    Held

    IM

    IM

    2
    4

    3
    4

    4
    5

    Asynchronous Interactions, Hazards, Synchronization and Metastability,


    Design with ROMs and PLAs;
    Memory Basics, RAM, SRAM, DRAM, Summary of Logic Design and
    Applications
    Finals

    Midterm 1 & 2
    Final
    H.W. + Attendance
    Labs

    Lab
    Out

    Sequential Circuit Design & Analysis, State Tables & Diagrams

    7
    9

    LECTURE

    April 16th (10:40) & May 15th (15:40); Room TBA


    Date/Time/Place To Be Determined
    Late assignments penalized 20% per week day
    Instructions on lab procedures will follow

    70% score or above from the laboratory portion is required to pass this course.
    All homeworks and labs should be completed independently. Any copying will result in 0 score, and possible disciplinary action.
    We will use ODTUclass to post HWs, labs, solutions, lecture notes, announcements, etc.

    1 allowed
    Those who collect < 15% overall score before final or attend < 70% of the lectures will not be
    to take the Final Exam (and will receive a NA grade).

    Laboratory Schedule
    Week 4:
    Week 5/7:
    Week 9:
    Week 10:
    Week 12:
    Week 14:

    Introduction to Digital Design Entry, Simulation, and Implementation


    Hierarchical Description of Combinational Logic with Multibit Signals
    Synchronous Building Blocks
    Combinational and Sequential Design Using Standard Components
    FSM Design for Digital Control
    (LAB FINAL) Calculator or Similar System Design, Simulation, and Implementation

    Academic Integity
    Copying, communicating, or using disallowed materials during an exam is cheating. Students caught cheating on
    a midterm or final exam will be reported to the campus disciplinary committee. Students may not leave the
    classroom during exams; any student leaving the classroom is leaving the exam.
    Academic integrity is a more complicated issue for assignments and prelab exercises, but one we take very
    seriously. The following rules will be in force for assignments and prelabs:

    Students are allowed to work together in brainstorming solutions, in interpreting error messages from tools,
    and in discussing strategies for finding coding bugs, but NOT in designing or implementing solutions.

    Students may not share logic diagrams, schematics, equations, or VHDL codes, may not copy these, and
    may not discuss their solutions in detail at any time, i.e. while it is being generated or afterwards.

    Similarly, students may not receive detailed help on their solutions from individuals outside the course. This
    restriction includes tutors, students from prior terms, internet resources, etc.

    Students may not show their solutions to other students as a means of helping them. Sometimes good
    students who feel sorry for struggling students are tempted to provide them with "just a peek" at their
    solution. Such "peeks" often turn into extensive copying, despite prior claims of good intentions. No such
    claim will be accepted as an excuse for ethical violations.

    Students may not leave their solutions (either electronic versions or printed copies) in publicly accessible
    areas. Students may not share computers in any way when there is an assignment pending.

    We use various tools, including automated tools, to help spot assignments that have been submitted in violation
    of these rules. We carefully try to detect violation of academic honesty, and make our own judgment about which
    students violated the rules of academic integrity in assignments. When we believe an incident of academic
    dishonesty has occurred, we contact the students involved. All students caught cheating on an assignment (both
    the copier and the provider) will receive an automatic 0 for that assignment. No excuses, no discussions, no
    exceptions! If cheating persists, disciplinary action will be taken. Remember, it is unethical to copy regardless of if
    you get caught or not.
    If citation is needed, proper and accurate citation for the used information sources must be given. Any sort of
    plagiarism will not tolerated. This means no copying, no rewording, no paraphrasing, or giving false or in accurate
    information sources.
    For more details about plagiarism, please see:
    http://www.plagiarism.org/plag_article_what_is_plagiarism.html.

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