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INDEX

S.NO. NAME OF THE EXPERIMENT PAGE

1. LINEAR WAVE SHAPING. 1

2. NON-LINEAR WAVE SHAPING CLIPPERS. 6

3. NON LINEAR WAVE SHAPING CLAMPERS. 13

4. TRANSISTOR AS A SWITCH. 17

5. STUDY OF LOGIC GATES&SOME APPLICATIONS. 20

6. STUDY OF FLIP-FLOPS& SOME APPLICATIONS. 29

7. ASTABLE MULTIVIBRATOR. 36

8. MONOSTABLE MULTIVIBRATOR. 40

9. BISTABLE MULTIVIBRATOR. 43

10. SCHMITT TRIGGER. 47

11. UJT RELAXATION OSCILLATOR 51

12. BOOT STRAP SWEEP GENERATOR 55

(S. Aruna Kumari) (Dr. Y. Madhavee Latha)

Asst.Prof. Professor

Lab Incharge Head of the Department

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LINEAR WAVE SHAPING

Aim :

Design a RC LPF and HPF at various time constants and verify the responses
for Square wave input (choose C = 0.1f, Vi = 4 VP-P, f = 10 K Hz).

Apparatus:

1. CRO
2. Signal Generator
3. Bread board
4. Capacitor (0.1f)
5. Resistors (100, 1K, 10 K)
6. Connecting wires.

Circuit Diagram:

HPF:

Design / Calculations:

a) RC = T

Given T = 1/10KHz = 0.1 mSec

R = 0.1x 10-3 / 0.1f = 1 Kohms

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V1 = V / (1 + e-T/2RC) = 2.49 V

V
V1| = T
= 1.51V
1+ e 2 RC

V1 V1|
%tilt =
V
2

= (2.49 1.51)/2 = 49%)

T1 = T2 = T/2

b) RC >> T

Choose RC = 10T = 1 mSec

10 3
R= = 10K
0.1x10 6

The O/P waveform will be identical to I/P

T1 = T2 = T/2

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c) RC << T

RC = 0.1 T

0.1x10 4
R= = 100
0.1x10 6

LPF:

a) RC = T

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C = 0.1f, R = 1K

V T 2 RC
e 1
V2 = 2 = 0.49V
e 2 RC + 1
T

V1 = -0.49 V

b) RC >> T

R = 10 K, C = 0.1 f

V T 2 RC
e 1
V2 = 2 = 0.05V V1= 0.05v
e 2 RC + 1
T

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c) RC << T

R = 100,

C = 0.1 f

Note:

Low Pass Filter allows the DC component of I/P signal and High Pass Filter
block the DC component of I/P Signal.

Procedure:

1. Connect the circuit as shown in figure (LPF / HPF)

2. Apply the Square wave input to this circuit (Vi = 4 VP-P, f = 10KHz)

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3. Observe the output waveform for (a) RC = T, (b) RC>>T, (c) RC>>T
4. Verify the values with theoretical calculations

Precautions:

Use two CRO probes and observe I/P & O/P waveforms simultaneously by
putting CRO on DC modes.

Result:

LPF and HPF are designed at various time constants and the responses for
square wave input is observed & hence plotted.

Questions:

1. When HP-RC circuit is used as Differentiator?

2. Draw the responses of HPF to step, pulse, ramp inputs?
3. Draw the responses of LPF to step, pulse, ramp inputs?
4. Define % tilt and rise time?
5. When LP-RC circuit is used as integrator?
6. Why noise immunity is more in integrator than differentiator?
7. Why HPF blocks the DC signal?
8. Define 1db?
9. What is meant by linear wave shaping?
10. Write the formula for rise time tr?

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NON-LINEAR WAVE SHAPING CIRCUITS CLIPPERS

Aim:

a) To study the clipping circuits using diodes.

b) To observe the transfer characteristics of all the clipping circuits in CRO.
Apparatus:

1. Signal Generator.
2. Bread board
3. Connecting patch cards.
4. CRO
5. DC power supply (dual)
6. Resistors (1 K, 10K)
7. Diodes (1N4007)
Theory:

Clipping circuits basically limit the amplitude of the input signal either below
or above certain voltage level. They are referred to as Voltage limiters, Amplitude
selectors or Slicers. A clipping circuit is one, in which a small section of input
waveform is missing or cut or truncated at the out put section.
Clipping circuits are classified based on the position of Diode.
1.Series Diode Clipper
2.Shunt Diode Clipper

Procedure:

1. Connect the circuit as shown in fig.1

2. In each case apply 10 VP-P, 1KHz Sine wave I/P using a signal generator.
3. O/P is taken across the load RL.
4. Observe the O/P waveform on the CRO and compare with I/P waveform.
5. Sketch the I/P as well as O/P waveforms and mark the numerical values.
6. Note the changes in the O/P due to variations in the reference voltage
VR = 2V, 3V..
7. Obtain the transfer characteristics of Fig.1, by keeping CRO in X-Y mode.
8. Repeat the above steps for all the circuit.
Precautions:

1. Set the CRO O/P channel in DC mode always.

2. Observe the waveform simultaneously by keeping common ground.
3. See that there is no DC component in the I/P.
4. To find transfer characteristics apply input to the X-Channel, O/P to Y-
Channel, adjust the dot at the center of the screen when CRO is in X-Y
mode. Both the channels must be in ground, then remove ground and
plot the transfer characteristics.

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Circuit Diagram Input&Output Wave Forms

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Circuit diagram O/P Wave Forms

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Circuit Diagrams Transfer Characteristics

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Result: Different types of clipping circuits have been studied and observed the
responses for various combinations of VR and clipping diodes.

Questions:

1. Define clipping circuit?

2. What are the different types of clippers?
3. What is a break region?
4. Which kind of a clipper is called a slicer circuit?
5. What are the disadvantages of the shunt clipper?
6. What are the disadvantages of the series clipper?
7. What is piecewise linear mode of a diode?

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NON-LINEAR WAVE SHAPING CIRCUITS

CLAMPERS

Aim:

To study the clamping circuits using diodes and capacitors.

Apparatus:

1. Signal Generator.
2. Bread board
3. Connecting patch cards.
4. CRO
5. DC power supply (dual)
6. Resistors ( 100 K )
7. Diodes (1N4007)
8. Capacitor (0.1f)

Theory:

Clamping circuits add a DC level to an AC signal. A clamper is also refer to as

DC restorer or DC re-inserter. The Clampers which clamp the given waveform either

above or below the reference level, which are known as positive or negative

clamping respectively.

Procedure:

1. Connect the circuit as shown in fig.1.

2. Apply a Sine wave of 10VP-P, 1KHz at the input terminals with the help of
Signal Generator.
3. Observe the I/P & O/P waveforms of CRO and plot the waveforms and
mark the values with VR = 2 V, 3V
4. O/P is taken across the load RL.

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5. Repeat the above steps for all clamping circuits as shown.

6. Waveforms are drawn assuming diode is ideal.

Circuit diagram I/P & O/P Wave Forms

Vi =5V

-5V
C1

V0
V1 0.1uF R1
10V D1
7.07V_rms 100kohm 0.5V
1N4007GP -
1000Hz
0Deg

-9.5V

C1
V0
9.5V
V1 0.1uF R1
10V D1
7.07V_rms 100kohm 5V
1000Hz 1N4007GP
0Deg
-0.5V

V0

C1

0.1uF D1
1N4007GP
V1 R1
10V
7.07V_rms 100kohm
1000Hz
0Deg V2
2V

-15V

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-11.5V

Circuit diagram O/P Wave forms

Result:

Different types of clamping circuits are studied and observed the response
for different combinations of VR and diodes.

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Questions:

1.What are the applications of clamping circuits?

2.What is the synchronized clamping?

3.Why is a clamper called a dc inserter?

4.What is clamping circuit theorem. How dose the modified clamping
Circuit theorem differs from this?
5. Differentiate ve clamping circuit from +ve clamping circuits in the
above circuits?
6. Describe the charging and discharging of a capacitor is each circuit?
7. What is the function of capacitor?
8. What are the effects of diode characteristics on the output of the
Clamper?

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TRANSISTOR AS A SWITCH
Aim:
Design Transistor to act as a Switch and verify the operation. Choose VCC =
10V, ICmax = 10 mA, hfe = 50, VCESat = 0.2, Vin = 4Vp-p, VBESat = 0.6 V

Apparatus:

1. Transistor (BC 107).

2. Breadboard.
3. CRO.
4. Resistors (1K, 8.2K).
5. DC power supply.
6. Function Generator.
7. Connecting patch cards.
Theory:

When the I/P voltage Vi is negative or zero, transistor is cut-off and no current
flows through Rc hence V0 VCC when I/P Voltage Vi jumps to positive voltage,
transistor will be driven into saturation. Then

V0 = Vcc ICRC VCESat

Design procedure:

VCC VCESat
When Q is ON RC =
I C max

= (10-0.2) / 10 mA = 1K

IB ICmax / hfe

10mA / 50

IB 0.2 mA

To keep transistor remain in ON, IB should be greater than

Ibmin = 0.2mA

Vin = IBRB + VBE Sat

2V = 0.2 mA RB + 0.6V

RB = 7 K (choose practical values as 8.2 K)

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Circuit diagram:

Procedure:

1. Connect the circuit as shown in figure.

2. Apply the Square wave 4 Vp-p frequency of 1 KHz
3. Observe the waveforms at Collector and Base and plot it.

Precautions:

1. When you are measuring O/P waveform at collector and base, keep the
CRO in DC mode.
2. When you are measuring VBE Sat, VCE Sat keep volts/div switch at either 0.2
or 0.5 position.
3. When you are applying the square wave see that there is no DC voltage in
that. This can be checked by CRO in either AC or DC mode, there should
not be any jumps/distortion in waveform on the screen.

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Expectedwaveforms:

Result:

Transistor as a switch has been designed and O/P waveforms are observed.

Questions:

1. Differentiate between Diode and Transistor as a switch?

2. Mention typical values of VBE Sat, VCE Sat for both Si, Ge Transistors?
3. Define ON time, OFF time of the transistor?
4. In which regions Transistor acts as a switch?
5. Explain phenomenon of latching in a Transistor switch?
6. Define Rise time & fall time of a transistor switch

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LOGIC GATES
Aim: 1) Study of logic gates using ICs & discrete components.

2) Realization of basic gates using NAND & NOR gates (Universal gates).

Apparatus: 1. Logic gates (IC) trainer kit.

2. Trainer kit for discrete circuit of gates

3. Connecting patch chords.

I. Verifying the logic gates using ICs:

S.NO GATE SYMBOL INPUTS OUTPUT

A B C

1. NAND 0 0 1
A C= A B
IC 7400
B 0 1 1

1 0 1

1 1 0

2. NOR 0 0 1
IC 7402 A C= A + B
B 0 1 0

1 0 0

1 1 0

3. AND 0 0 0
IC 7408 A C=AB

B 0 1 0

1 0 0

1 1 1

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4. OR 0 0 0
IC 7432 A C=A+B

B 0 1 1

1 0 1

1 1 1

5. NOT C= A 1 - 0
A
IC 7404
0 - 1

6. EX-OR 0 0 0
A
IC 7486
B 0 1 1

1 0 1

1 1 0

REALIZATION OF ALL GATES USING NOR GATE:

NOT GATE

A C=A

OR GATE

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AND GATE
A
A
AB

B
B

NAND GATE

Fig (2.1)

REALIZATION USING NAND GATE:

NOT GATE:

A A

AND GATE:

AB
A
AB
B

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OR GATE:

A A
A+B

B B

NOR GATE:

A A

A+B A+B
B B

Fig (2.2)

REALIZATION OF BASIC EX-OR GATE USING NAND & NOR GATE:

BASIC CONFIGURATION OF EX-OR GATE:

A
A AB

A C= AB + A B

B B
AB

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EX-OR USING ONLY NAND GATES:

A A A+B

C = AB + A B

B B
A+B

EX-OR
OR USING ONLY NOR GATES:

II.Verifying the logic gates using discrete components:

components AND GATE:

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OR GATE:

NOT GATE:

NAND GATE:

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NOR GATE

Procedure:

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1. Connect the logic gates as shown in the figure1.

2. Feed the logic signals 0 or 1 from the logic input switches at the
inputs A & B.
3. Monitor the output using logic output LED indicators.
4. Repeat step 1 to 3 for NOT, AND, OR & NOR operations.
5. Connect the logic gates as shown in figure 2.1 & 2.2 and repeat
the steps 2 through 3.
6. Connect the logic gates as shown in figure 3 and repeat the steps
2 and 3 Verify the truth table for EX OR gate.
7. Implement the logic gates using discrete components (fig 4) and
verify the truth tables.

Result: Verified the Truth Tables of all Logic Gates. .

Questions:

1. Why NAND & NOR gates are called universal gates?

2. Realize the EX OR gates using minimum number of NAND gates.

3. Give the truth table for EX-NOR (EX-OR+NOT) and realize using NAND gates.

4. Realize the given logic function using NAND and also using
NOR gates.

f = A BC + A B C + AB C

5. Explain the operation of NAND gate when realized using discrete components.

6. In what regions does the transistor is operated such that it behaves like a

Switch.

7. What are the logic low and High levels of TTL ICs and CMOS ICs.

8. Compare TTL logic family with CMOS family.

9. Which logic family is called fastest and which logic family is called low power

dissipated.

10. Explain the operation of OR, NOR gates when realized using discrete

Components

11. Why the transistor operates as NOT gate.

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FLIP FLOPS

Aim: To Construct different types of Flip Flops and verify their truth tables.

Apparatus: 1. Flip Flop experiment kit

2. Connecting Patch chords.

RS FLIP-FLOP BASIC VERSION:

R Q

Q
S

Fig (1.a)

TRUTH TABLE FOR RS FLIP FLOP:

Inputs Outputs

R S Q

0 0 Indeterminate

0 1 1

1 0 0

1 1 Q0

(Previous state)

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RS FLIP-FLOP CLOCKED VERSION:

S
Q

CLK

Fig (1.b)

SYMBOL:

R Q
CLK FF
Q
S

TRUTH TABLE FOR CLOCKED RS FLIP FLOP:

Inputs Outputs

R S CLK Q

0 0 Q0

0 1 1

1 0 0

1 1 Indeterminate
state

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IC 7476 M/S JK FLIP FLOP; - 2

4 J SD
15
1 CP FF
7476 14
16 K CD

9 J SD
11
6 CP FF
7476 10
12 K CD

Fig (1.c) 8

TRUTH TABLE FOR JK-FLIP FLOP (IC 7476); -

OUTPUTS
SD CD
Preset Clear Clock J K Q Q
*Unstable condition.
X X X H L It will not remain
L H after Cn and Pn inputs
X X X L H return to their
H L inactive (high) state
X X X H* H*
L L
L L Q0 Q0
H H
H L H L
H H
L H L H
H H
H H TOGGLE
H H
H X X Q0 Q0
H H

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SYMBOL FOR JK FLIP FLOP:

J Q
CLK FF
Q
K

SYMBOL FOR D-FLIP FLOP:

D Q
CLK FF
Q

D-FLIP FLOP USING J-K M/S FLIP FLOP:

2

J SD
D
Q
FF
CP
7476
Q
CLK K
CD

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TRUTH TABLE FOR D-FLIP FLOP (IC 7476): -

INPUTS OUTPUTS

Preset Clear Clock D Q Q

L H X X H L

H L X X L H

L L X X H H

H H H H L

H H L L H

H H L X Q0 Q0

SYMBOL FOR T-FLIP FLOP: -

T Q
FF
Q

T-FLIP FLOP USING JK FLIP FLOP:

2

J SD
T Q

CLK FF
CP
T-FLIP
FLOP Q
K
USING JK
CD

TRUTH TABLE FOR T-FLIP FLOP: -

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INPUTS OUTPUTS

Preset Clear Clock T Q Q

L H X X H L

H L X X L H

L L X X H H

H H H TOGGLE

H H L H L

H H L X TOGGLE

Procedure:

1. Construct the RS flip flop as shown in figures 1.a & 1.b.

2. Feed the logic signals from the logic input switches observe the logic
outputs on the logic level LED indicators.
3. Verify the corresponding truth tables.
4. Construct JK-flip flop (fig 1.c) and repeat step2 and 3.
5. Construct D Flip flop (fig 1. d) and repeat step 2 and 3.
6. Construct T- Flip flop (fig 1.e) and report step 2 and 3.

Result: Different types of Flip flops (RS, Clocked RS, JK, D, T) are

Constructed using IC 7476 and hence their truth tables are verified.

Questions:

1.Difference between latch and flip-flop.

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2.List the applications of flip-flops.

3.Explain the operation of JK master slave flip-flop.

4.What is the difference between SR-flip flop and clocked SR-FF.

5.What is ment by level triggering and edge triggering in flip-flops.

6. Explain the difference between +ve edge and ve edge triggering.

7. Which type of edge triggering is used in IC 7476 J-K M/S Flip-flop?

8. Explain the preset and clear inputs of a flip-flop and why are these

Called asynchronous inputs.

9. What is ment by toggle and where do the T-FFs are used.

10. Where do the D-FFs are used and why it is called a delay flip flop.

11. Explain the race around problem in JK-FF and how it is eliminated in

master slave JK- FF.

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ASTABLE MULTIVIBRATOR
Aim :-
To desian Astable Multivibrator to generate a Square wave of 1KHz frequency.
Choose C = 1nf, 10nf, 100nf.

Apparatus :

1. Regulated DC Power supply - 1 no

2. CRO, - 1 no
3. Resistors (1K, 72K, 724K, 7.2K) - each 2 nos
4. Capacitors (0.1nf, 10nf ,100nf) - 3 nos
5. Transistors (BC 107) - 2 nos

Circuit diagram :

Theory:

The astable circuit has two quasi-stable states. Without external triggering
signal the astable configuration will make successive transitions from one quasi-
stable state to the other. The astable circuit is an oscillator. It is also called as free
running multivibrator and is used to generate Square Wave. Since it does not
require triggering signal, fast switching is possible.

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Design : The period T is given by

T = T1 + T2 = 0.69 (R1C1 + R2C2)

For symmetrical circuit with R1 = R2 = R & C1 = C2 = C

T = 1.38 RC

10-3 = 1.38 x 10-9 x R

R = 724K (When c=1nf) ;

10 3
R = = 72.4 K (when c=10nf)
1.38 x10 x10 9

R = 7.24K (when c=100nf)

Let VCC = 15V; hfe = 51 (for BC107)

VBESat = 0.7V; VCESat = 0.3V

Choose ICmax = 10mA,

RC = (VCC VCESat) / ICmax

= (15 0.3) / (10 x 10-3) = 1.47K RC 1K

Procedure:

1. Connect the circuit as shown in figure.

2. Observe the Base Voltage and Collector Voltages of Q1 & Q2 on CRO in DC
mode and plot them.
Verify the frequencies theoretically.

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Expected Waveforms:

Result :

An Astable Multivibrator is designed, the waveforms are observed and

verified the results theoretically.

Questions:

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1. Is it possible to change time period of the waveform with out changing R

& C? Support your answer?
2. Collector waveforms are observed with rounded edges. Explain?
3. Explain charging and discharging of capacitors in an Astable
Multivibrator?
4. How can an Astable multivibrator be used as VCO?
5. Why do you get overshoots in the Base waveforms?
6. What are the applications of Astable Multivibrator?
7. How can Astable multivibrator be used as a voltage to frequency
converter?
8. What is the formula for frequency of oscillations?
9. What are the other names of Astable multivibrator?

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MONOSTABLE MULTIVIBRATOR

Aim : To design a monostable multivibrator for the Pulse width of 0.03mSec.

Apparatus:

Resistors(10k,1k,43.2k,100k)-2nos,2nos,1no,1no.
Capacitors(0.047f)-2nos
Diodes(1N4007)-1no.
Transistors(BC107)-2nos.
Function Generator.
CRO.
Regulated Power Supply.
Connecting wires.
Circuit diagram :

Theory:

The monostable circuit has one permanently stable and one quasi-stable
state. In the monostable configuration, a triggering signal is required to induce a
transition from the stable state to the quasi-stable state. The circuit remains in its
quasi-stable for a time equal to RC time constant of the circuit. It returns from the
quasi-stable state to its stable state without any external triggering pulse. It is also
called as one-shot a single-cycle, a single step circuit or a univibrator.

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Design :

To design a monostable multivibrator for the Pulse width of 0.03mSec.

Choose ICmax = 15mA, VCC = 15V, VBB = 15V, R1 = 10K.

T = ln 2

T = 0.69 RC

Choose C = 10nf

0.3 x 10-3Sec = 0.69 x R x 10 x 10-9

R = 43.47 K

VCC VCESat
RC =
I C max

RC = (15 0.2) / 15mA 1K

Minimum requirement of for more margin, given

| VB1| 0.1 VB1 = -1.185

V BBR1 VCESat R2
VB1 = +
R1 + R2 R1 + R2

15 R1 + 0.2 R2
-1.18 = ; given R1 = 10K
R1 + R 2

R2 = 100K

Procedure:

1. Switch ON the trainer kit and observe power indication.

2. Wire the circuit as shown in the circuit diagram.
3. Calculate the pulse width (T) of the Monostable O/P with the selected
values of R & C on the CRO. See that CRO is in DC mode.
4. Select the triggering pulse such that the frequency is less than 1/T
5. Apply the triggering input to the circuit and to the CROs channel 1 .
Connect the CRO channei-2 to the collector and base of the
TransisterQ1&Q2..
6. Adjust the triggering pulse frequency to get stable pulse on the CRO and
now measure the pulse width and verify with the theoretical value.
7. Obtain waveforms at different points like VB1, VB2, VC1 & VC2.

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8. Repeat the experiment for different combinations of R & C (C = 1nf,

100nf). Calculate R for same value of T = 0.3 mSec.
Expected Waveforms:

Result :

A collector coupled Monostable Multivinbrator is designed, the waveforms

are observed and verified the results theoretically.

Questions:-
1. What are applications of Monostable Multivibrator?
2. Why is a Monostable Multivibrator called a gating circuit?
3. Explain the waveform of VB1?
4. Describe the operation of the capacitor C3 in the circuit?
5. Why is the time period T also called Delay time?
6. Justify, Why Monostable Multivibrator is called one-shot circuit?
7. Why is the ve voltage given at the base of Q1 transistor.
8. What is the no of quasi & stable states of Monostable Multivibrator

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BISTABLE MULTIVIBRATOR
Aim:
stable Multivibrator circuit and verify the operation.
a) Design the Bi-stable
b) Obtain the resolving time of Bi-stable Bi stable Multivibrator and verify
theoretically. Choose R1 = 10K, C = 0.3f, VCE Sat = 0.2V, ICmax = 15mA,
VCC = 15V,
VBB = 15V, VB1 = -1.2V
Apparatus:

1. Resistors(1k,10k,100k)-5nos,2nos,2nos.
Resistors(1k,10k,100k)
2. Capacitors(0.001f,0.33f)
Capacitors(0.001f,0.33f)-2nos,3nos.
3. Diodes(1N4007)
Diodes(1N4007)-3nos.
4. Transistors(BC107)
Transistors(BC107)-2nos.
5. Function Generator
6. Regulated Power Supply
7. CRO
8. Connecting wires.

Circuit diagram:

Theory:

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A Bistable circuit is one which can exist indefinitely in either of two stable
states and which can be induced to make an abrupt transition from one state to the
other by means of external excitation. The Bistable circuit is also called as Bistable
multivibrator, Eccles jordon circuit, Trigger circuit, Scale-of-2 toggle circuit, Flip-
Flop & Binary.

A bistable multivibratior is used in a many digital operations such as counting and

the storing of binary information. It is also used in the generation and processing of
pulse-type waveform. They can be used to control digital circuits and as frequency
dividers .
There are two outputs available which are complements of one another. i.e.
when one output is high the other is low and vice versa .

Design :

VCC VCESat
RC =
I C max

RC = (15 0.2) / 15mA 1K

V BBR1 VCESat R2
Choose RC = 1K, VB1 = +
R1 + R2 R1 + R2
15 x10 + 0.2 R2
-1.2 = ; R2 =100K
10 + R 2
R1 + R2 10 + 100K
fmax = = = 55KHz
2CR1 R 2 2x0.3x106 x10Kx100K
Procedure:
1. Switch ON the system and observe for the power LED indication.
2. Apply two Square waves with same frequency or different frequency at
terminals T1 & T2. You may observe symmetrical or Asymmetrical square
waves respectively. Observe both I/P & O/P waveforms on CRO.
3. Set the I/P frequency at 500hz.
4. Until you get a 500Hz at the O/P, increase the trigger I/P amplitude, note
down the I/P amplitude, this is the minimum pulse step required for trigger
the bi-stable Multivibrator with the given circuit parameters.
5. Now slowly increase the frequency and at one particular frequency the
circuit does not respond and the output disappears. Just lesser than this
frequency, the circuit again responds, this is the maximum allowable
frequency.
6 Sketch the O/P waveforms. Sample O/P waveforms are as shown in
figure

Expected waveforms:
Vt Trigger Input

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Result:

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Bistable Multivibrator circuit is designed and output waveforms are

observed.

Questions: -

1. What are the applications of a Bitable multivibrator?

2. Describe the operation of commutating capacitors?
3. Why is a Binary also called a flip-flop?
4. Mention the name of different kinds of triggering used in the circuit shown?
5. What are the disadvantages of direct coupled Binary?
6. How many types of unsymmetrical triggering are there?
7. What are catching diodes?
8. Which triggering is used in binary counting circuits?

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SCHMITT TRIGGER
Aim:-
(a) To design the circuit of Schmitt trigger with UTP = 3V LTP
= 1.5V ,Vcc = 15V ,Rs = 1k,Rc2 = 3k,R1 = 15k R2 = 4.7k
(b) To Obtain the UTP and LTP values Practically and verify it
theoretically
(c) To obtain square wave from the sine wave.

Apparatus:

Bread board
Function Generator
Regulated Power Supply
C.R.O
Connecting wires
Resistors(1k,3.3k,15k,2.2k,4.7k)-2nos,1no.
Capacitors(10f,1f)-1no,1no.
Transistors(BC107)-2nos.

Circuit diagram:

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Procedure:-

(1) Connect the circuit as shown in Fig.

(2) Switch ON the supply.
(3) With Vi = 0V, measure the output voltage.
(4) Slowly increase the input voltage from 0V to maximum and
observe the output for the transition.
(5) Obtain the voltage at which the LOW to HIGH transition is
occurred and this is the UTP and now measure the input
voltage.
(6) Now, slowly decrease the input voltage and observe for the
HIGH to LOW transition at the output, the input voltage at
this point is called the LTP.
(7) Apply a sine wave input to the circuit.
(8) Observe the input and output waveforms on CRO.
(9) Vary the input frequency and comment on the results
obtained.
(10) Repeat the experiment with different R2.
(11) Verify the result theoretically.

Observations:-

With Re = 480ohms

DC AC

UTP = 2.9V UTP = 3V

LTP = 1.8V LTP = 2V
VH = UTP LTP VH = UTP LTP

Theoretical Calculations:-

V1 calculation:

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VBE2 = 0.6V for Si

Vr1 = 0.5V
(=VBE at cut in)

VCC R2 R2 ( RC1 + R1 )
V = ; Rb = VCC = 12V
RC1 + R1 + R2 RC1 + R1 + R2

Re (hFE + 1)
VEN = (V - VBE2) *
Rb + Re (hFE + 1)

V1 = VEN + Vr1 (Accurate value)

V1 = V - 0.1 v (approximate value)

V2 calculation:

R2 RC1 ( R1 + R2 )
a = ; R = ;
R1 + R2 RC1 + R1 + R2
1
Re = Re(1+ );
hFE

Re '+ Rs / hFE VBE = 0.6V

V2 = VBE1 + (V - Vr2)
a R + Re ' Vr = 0.5V

Re
(or) V2 = VBE1 + (V Vr2) (approximately)
aR + Re

Expected Waveforms:

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Result: Schmitt Trigger circuit has designed and the square wave is
observed from the sine wave.

Questions:
1. What are the applications of Schmitt Trigger?
2. Define hysteresis action?
3. Why is Schmitt Trigger called a squaring circuit?
4. What is UTP?
5. What is LTP?
6. What is the difference between a Binary and Schmitt Trigger?

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UJT RELAXATION OSCILLATOR

Aim:-
To study the UJT relaxation oscillator.

Apparatus:-

(1) UJT (2N2646)

(2) Capacitor
(3) Resistors
(4) C.R.O
(5) Regulated Power Supply
(6) Bread board.

Theory:

The unijunction is a 3-terminal,semiconductor device with ve resistance

characteristics.It constitute three terminals base 1 and base 2 and emitter.

A relaxation oscillator shown in fig.The circuit must be relaxation biased

for stable operation that is load line determined by v and r must inserted in the input
characteristics in the ve resistance. The resistors rb1 and rb2 are not essential to the
ckt but are included because the voltage level applied across these resistors may prove
useful and the capacitor C charges to peak voltage Vp the device turns ON and
capacitor discharges to the valley voltage Vv where upper cycle repeats the Vc
appears charging time T.

Circuit Diagram:

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Theoretical Values:
We have
Vb1=iRb1.
Vbb 12
But i= = =0.0082A
Rb1 + Rb 2 470 + 1k
Vbb 12
Vb1= * Rb1 = * 470 =3.84v
Rb1 + Rb 2 470 + 1k
Rb1
= * Vbb
Rb1 + Rb 2
Rb1 470
Intrinsic Standoff Ratio = = =0.32.
Rb1 + Rb 2 470 + 1k
Emitter Voltage Ve= V+Vb1
= 0.7+3.84=4.54v
1
f=
RC log(1 /(1 n))
1
=
33k * 0.1 *10^ 6 log(1 /(1 0.32))

= 1.81kHz.

Procedure:-

(1) Connect the circuit as shown in Fig.

(2) Observe the waveforms emitter,base1,base2 on the CRO.
(3) Calculate the frequency of waveforms.

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(4) Compare theoretical and practical frequencies.

(5) Observe the input and output waveforms on CRO.
(6) Plot the waveforms.

ModelWaveforms:

Observations:-

Vb1 = 3.84v
= 0.32
Ve = 4.54v
f = 1.81kHz.

Result: The UJT Relaxation Oscillator has studied.Theoretical values are compared
with the practical values.

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BOOT STRAP SWEEP GENERATOR

Aim:-
To study the Boot Strap Sweep Generator.

Apparatus:-
(1) Transistors
(2) Capacitors
(3) Resistors
(4) C.R.O
(5) Regulated Power Supply
(6) Bread board.
(7) Connecting Wires
(8) Diode
Theory:

The transistor Q1 acts as ON-OFF switch, and the transistor Q2

is an emitter-follower. The input vi is a pulse voltage, or rectangular
wave. when the input signal vi is positive, transistor Q1 becomes ON,
there exist goes into saturation.
Therefore potential of point A,VA=Vce(sat).If Q1 is silicon
transistor,Vce(sat)=0.3v.
Therefore VA=0.3v. Output Voltage Vo= VA-Vbe(Q2)
(in active region) = 0.3-0.6=-0.3v.
The emitter of Q2 is coupled to the collector of Q1 through
the capacitor Cb.Hence point B becomes ve w.r.t. Vcc.Diode D readily
conducts, with the result that potential Vb=Vcc.When the i/p Vi goes
ve,Q1 becomes OFF.The potential of A rises. This increases of voltage at
A is transmitted to B through Q2 and capacitor Cb.The result is that the
potential of B also rises by the same amount. This is the principle of
bootstrap. Thus Vb rises from Vcc to (Vcc+VA).Let I denote the current
through Rc1.
We have I=(Vb-VA)/Rc1=Vcc/Rc1,since Vb=Vcc+VA.
Since both Vcc and Rc1 are of fixed magnitude, the
ratio(Vcc/Rc1) is constant. Hence current I is of constant magnitude.
From the circuit, we have I=i1,since Q1 is now cut off and its collector
current is zero. But i1=i2+i3.i3 is the base current of Q2.
Since Q2 is an emitter follower, its i/p impedance is very very high and
hence i3 is practically zero.
Therefore i1=i2.But i1=I. i2=I,is a constant current

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Circuit Diagram:

VCC
20V

D1
DIODE_VIRTUAL
C2

R1 R2 0.0F
1k? 1k?

U2
U1
C1

0.001F BD135
BD135
V1
C3
1kHz 0.001F R3
5V 1k?

VEE
-12V

Procedure:-

(1) Connect the circuit as shown in Fig.

(2) Observe the waveforms on the CRO.
(3) Observe the input and output waveforms on CRO.
(4) Plot the waveforms.

ModelWaveforms:

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Observations:-

Ts=
Tr=

Result: The Boot Strap Sweep Generator has studied.

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