Intel MCS-51 Users Manual Jan 81 PDF

inter
MCS51 FAMILY OF
SINGLE CHIP MICROCOMPUTERS
USER'S MANUAL
JANUARY 1981
Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which
may appear in this document nor does it make a commitment to update the information contained herein.
Intel software products are copyrighted by and shall remain the property of Intel Corporation. Use, duplication or
disclosure is subject to restrictions stated in Intel's software license, or as defined in ASPR 7-104.9 (a) (9). Intel Cor-
poration assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No
other circuit patent licenses are implied.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent
of Intel Corporation.
The following trademarks of Intel Corporation and its affiliates may only be used to describe their products:
BXP Intelevision MULTIBUS*
CREDIT Intellec MULTIMODULE
i iSBC PROMPT
ICE iSBX Promware
ICS Library Manager RMX
im MCS UPI
Insite Megachassis /AScope
Intel Micromap
and the combinations of ICE, iCS, iSBC, MCS or RMX and a numerical suffix.
MDS is an ordering code only and is not used as a product name or trademark. MDS is a registered trademark of
Mohawk Data Sciences Corporation.
*MULTIBUS is a patented Intel bus.
Additional copies of this manual or other Intel literature may be obtained from:
Literature Department
Intel Corporation
3065 Bowers Avenue
Santa Clara, CA 95051
INTEL CORPORATION, 1981 AFN01300A1

Table of Contents
CHAPTER 1
Introduction
ManualOrganization .................................... 1-1
Product Overview ....................................... 1-1
CHAPTER 2
Functional Description
8051 CPU Architecture ................................... 2-1
CPU Hardware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-2
On-Chip Peripherals ..................................... 2-5
CHAPTER 3
Memory Organization, Addressing Modes and Instruction Set

Memory Organization .................................... 3-1
Addressing Modes ...................................... 3-2
Instruction Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-5
CHAPTER 4
Expanded 8051 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-1
CHAPTER 5
8051 Software Routines

8051 Programming Techniques ............................. 5-1
Peripheral Interfacing Techniques ......................... 5-9
CHAPTER 6
Device Specifications ................................... 6-1
CHAPTER 7
Component Data Sheets
8048 Family
8021 Single Component 8-Bit Microcomputer ........... 7-1
8021 L Single Component 8-Bit Low Power (10mA)
Microcomputer ................................. 7-4
8022 Single Component 8-Bit Microcomputer with On-chip
AID Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 76
8022H High Performance Single Component 8-Bit Micro-
computer with On-chip AID Converter ............. 7-12
8048H/8048H-1/8035HLl8035HL-1 HMOS Single Component
8-bit Microcomputer ........................... 7-13
8048L Special Low Power Consumption Single Component
8-Bit Microcomputer ........................... 7-20
8049H/8039HL HMOS Single Component 8-Bit
Microcomputer ................................ 7-27
8243 MCS-48 Input/Output Expander ............... 7-34
AFN01739A
iii
~ - ........... , ' ' ' _ _ .& \
'-'MAt" I en I ,\JUIU.,
8085 Peripherals
8155/8156/8155-2/8156-2 2048 Bit Static MaS RAM with 1/0
Ports and Timer ................................ 7-40
8185/8185-2 1024 x 8-Bit Static RAM for MCS-85 ....... 7-47
8355/8355-2 16,384-Bit ROM with 1/0 ............... '" 7-51
8755A/8755A-2 16,384-Bit EPROM with 1/0 ............. 7-56
Standard Peripherals
8041A/8641A/8741A Universal Peripheral Interface 8-Bit
Microcomputer ................................ 7-65
8205 High Speed lout of 8 Binary Decoder ............ 7-74
8251A/S2657 Programmable Communication Interface .. 7-78
825318253-5 Programmable Interval Timer ............. 7-83
8255A/8255A-5 Programmable Peripheral Interface ..... 7-92
8271/8271-6/8271-8 Programmable Floppy Disk
Controller ................................... 7-100
8273/8273-4/8273-8 Programmable HDLCISDLC Protocol
Controller ................................... 7-108
8275 Programmable CRT Controller ................. 7-115
8279/8279-5 Programmable KeyboardlDisplay Interface. 7-139
8282/8283 Octal Latch ............................. 7-148
8286/8287 Octal Bus Transceiver .................... 7-153
8291 GPIB TalkerlListener ......................... 7-158
8292 GPIB Controller ............................. 7-173
8293 GPIB Transceiver .......................... " 7-175
8294 Data Encryption Unit ....................... " 7-188
8295 Dot Matrix Printer Controller ................... 7-189
RAM
2114A 1024 x 4-Bit Static RAM .................... " 7-198
2142 1024 x 4-Bit Static RAM ....................... 7-202
2148 1024 x 4-Bit Static RAM ....................... 7-206
2148H 1024 x 4-Bit Static RAM ...................... 7-210
2118 Family 16,384 x 1-Bit Dynamic RAM ........... " 7-214
2147H High Speed 4096 x 1-Bit Static RAM ........... 7-225
EPROM
2716 16K (2K x 8) UV Erasable PROM ................ 7-229
2732 32K (4K x 8) UV Erasable PROM ................ 7-234
2732A 32K (4K x 8) UV Erasable PROM ............... 7-238
2758 8K (1 K x 8) UV Erasable Low Power PROM 7-239
CHAPTER 8
Development Support Tools

Intellec Series 11/85 Model 225 ........................... 8-2
Intellec SjngleIDouble Density Flexible Disk System ........ 8-7
8051 Software Development Package ..................... 8-11
ICE-51TM 8051 In-Circuit Emulator ......................... 8-14
UPP 103 Universal PROM Programmer ..................... 8-20
SDK-51 MCS-51 System Design Kit ........................ 8-22
AFN01739A
iv
APPENDIX A
PUM-80 Description of 8051 Instruction Set ................. A-1
APPENDIX B
An Introduction to the Intel MCS-51 Single-Chip Microcomputer
Family ............................................ B-1
APPENDIX C
Using the Intel MCS-51 Boolean Processing Capabilities ...... C-1
v AFN01739A
I
CHAPTER 1
INTRODUCTION
MANUAL ORGANIZATION 8051 Family

This publication describes Intel's 8051 family of single The 8051 family has three members: The 8031, 8051,
chip microcomputers. It is written for engineers, techni- and 8751. The 8031 is a CPU-only device, the 8051 has
cians and students who understand basic microcom- 4K bytes of factory-masked ROM and the 8751 has 4K
puter operating principles. The manual provides a com- bytes of EPROM. The generic term "8051" is used to
prehensive reference guide for the 8051 family. refer collectively to the 8031, 8051 and 8751.
The manual organization is by chapters and appendices. Supporting the applications of the '80s is the target of
Chapter 1 provides a brief introduction to the the 8051 family. On a single die the 8051 microcomputer
MCS-51 family, its software tools, and its develop- combines CPU; non-volatile 4K x 8 read-only program
ment support in the most general terms. memory (8051 and 8751); volatile 128 x 8 read/write
data memory; 32 110 Hnes; two 16-bit timer/event
The second chapter provides a functional description of counters; a five-source, two-priority-Ievel, nested inter-
the 8051 family hardware. rupt structure; serial 110 channel for either
multiprocessor communications, I/O expansion, or full
The third chapter describes the 8051's family memory duplex UART; and on-chip oscillator and clock circuits.
organization, addressing modes, data types and its in-
struction set. The CPU is in a 40-pin package and uses a single 5V
power supply. Intel's HMOS process technology is the
The fourth chapter is an expanded 8051 family con- driving force behind the 8051's ability to bring many
figured system using peripherals and external program peripheral functions on-board a single-chip microcom-
and external data memories. puter.
Chapter 5 lists software routines that handle program- Along with 4K program memory on-board, the 8051 can
ming applications such as radix conversions and stack address another 60K of external program memory. If
mani pulations. external data memory is needed the 8051 can also ad-
dress 64K of external RAM. When an 8031 is used, all
The chapter following, the sixth, is the specification sec- program memory execution is external and it, too, can
tion for the 8051 family. A.C. and D.C. characteristics address 64K of both external program and data
of the 8051 family are located here. memory. The 8051 contains many features for ease of
manipulating variables in Internal Data Memory. The
Chapter 7 provides data sheets on Intel products that stack may be located anywhere within the internal RAM
can be used in conjunction with the 8051. space. There are 4 banks of registers (eight registers in
each bank) that facilitate context switching and provide
The next chapter describes the development support byte efficiency. Also within the Internal Data Memory
available for the 8051 family. are the Special Function Registers. These are memory-
mapped locations for the ports, arithmetic registers,
That's the end of the chapters, but there are two appen- control and status registers and the timer/counters.
dices. Appendix A is a PL/M-80 description of the 8051
instruction set. Appendix B is the AP Note section Within the Internal Data Memory are 256 individually
where AP-69 and AP-70 are reproduced in their entire- addressable bits. 128 bits are located in the Internal
ty. AP-69 is titled, "An Introduction to the Intel Data RAM and the second 128 bits are located in the
MCS-51 Single-Chip Microcomputer Family" and Special Function Register. These 256 addressable bits
AP-70 is titled, "Using the Intel MCS-51 Boolean provide a new dimension in controller applications. The
Processing Capabilities." programmer/designer may now manipulate individual
bits with specific bit instructions! This new feature is the
PRODUCT OVERVIEW Boolean Processor, which is actually a bit processor
Introduced in May, 1980, Intel's 8051 family of single- with its own accumulator, 110 and instruction set.
chip microcomputers is the next generation microcom-
puter for the controller marketplace. With an expan- To increase programming ease the 8051 added new ad-
dable and flexible architecture the 8051 family provides dressing modes. Direct Addressing was added to
high performance for the applications of the future. manipulate variables within the 128-byte Data RAM
11
INTRODUCTION
and the Special Function Registers. Base-Register plus 3) A programmable baud rate from 122 to 31,250 bits
Index-Register Indirect Addressing gives the program- per second (12MHz operation) for a 9-bit frame
mer the ability to easily manipulate constants in pro- and asynchronous operation.
gram memory for table look-ups. Table look-ups are
supported over the entire 64K range by using 16-bit Since microcontrollers are real-time oriented, the 8051
registers. has four 8-bit ports for interfacing to the external
world. Three of the four ports, under software control,
A more in-depth explanation of the 8051 's memory can have additional capabilities. Port 0 is a time multi-
spaces, addressing modes and instruction set is provided plexed bus. It outputs the lower 8 bits of the 16-bit ad-
in Chapter 3. dress and also receives data and instruction during an
external RAM read or external program memory opera-
The 8051 hardware and on-chip peripherals have been tion. Port 0 also outputs the data when a write opera-
briefly described a few paragraphs earlier. Let's add a tion is performed. Port 2 emits the upper 8-bits of the
little more detail in the following paragraphs. For com- 16-bit address when external memories are being ac-
plete operational and functional explanation of the cessed. Port 3 contains the special control signals such
following features please read Chapter 2. as the read and write strobes, the two external interrupt
inputs, the two counter inputs and the transmit and
MCS-51 family has two independent, 16-bit timer/ receive pins of the serial channel. Port 1 is strictly an
counters. Under software control, each timer/counter 8-bit quasi-bidirectional port.
may be placed in one of four modes:
0) An 8-bit timer/counter with a divide-by-32 Development Support Tools

prescaler Intel provides the tools needed for efficient, low risk
1) A 16-bit timer/counter development of products using the 8051 family. These
2) An auto-reload 8-bit timer/counter development tools are based on the Intellec Series II
3) A mode which provides the programmer/designer Microcomputer Development System. The Intellec
with two timers and a counter for added flexibility system runs ISIS-II, a disk-based operating system be-
ing used in thousands of customer installations. This
There is a five-source interrupt system. The user has same hardware and operating system can also be used to
software control over enabling/disabling the interrupts develop systems based on other Intel microprocessor
and assigning priority levels to the interrupt sources. families such as the iAPX 86, iAPX 88, 8085 and 8048.
The two external interrupts, under software control, can
be either transition or low-level activated. ASM-51, the 8051 macro assembler provides assembly
language programming for the 8051. Symbolic refer-
Two of the three internal interrupt sources generate an ences (i.e., names) to 8051 hardware features are sup-
interrupt request when the overflow of the timer/ ported.
counters occurs. The third interrupt source generates an
interrupt request from the serial channel when the The Universal PROM Programmer can program any of
receiver register is full or when the transmitter register is Intel's PROM memories. To program and verify the
empty. 8751, an 8751 personality card adapter should be used.
Programming and verification operations are initiated
Serial data communication is accomplished by the from the Intellec development system console and are
8051's serial channel. Operation is flexible by providing controlled by the Universal PROM Mapper program.
user-programmable baud rates, two choices of frame
size and multiprocessor communications. There are The SDK-51, System Design Kit, is an 8031-based pro-
four modes of operation: totyping and evaluation kit. It includes the CPU, RAM,
I/O ports and a breadboard area for interfacing to
0) An 8-bit frame, synchronous mode which allows customer circuits. A ROM-based monitor program,
110 expansion using shift registers. A clock output single-line assembler and disassembler are supplied with
is provided by the 8051. the kit. Monitor commands may be entered from an on-
1) An 8-bit frame, asynchronous mode handling pro- board keypad or from a terminal. Monitor commands
grammable baud rates from 122 to 31,250 bits per allow programs to be entered, run, stopped and single-
second (l2MHz operation). stepped; memory contents can be altered as well as
2) A 9-bit frame, asynchronous mode that has a fixed displayed.
baud rate of 187 .5K bits per second (l2MHz opera-
tion) The ICE-5 FM In-Circuit Emulator provides real-time
1-2 AFN-01739A
INTRODUCTION
symbolic debugging support for the 8051 microcom-

puter. A 40-pin probe replaces the 8051 in the system
under test. This probe is connected to a specifically con-
figured 8051 "bond-out" chip which makes internal 8051
hardware available to ICE-51 circuitry. The ICE-51
module emulates the 8051 in the system under test in
response to commands entered through the Intellec con-
sole. These commands allow the user to debug the
system by setting breakpoints, tracing the flow of execu-
tion, single-stepping, examining and altering memory
and flO, etc.
All references to program variables and labels are sym-

bolic (i.e., their ASM-51 names). Software testing can
also map "system under test" memory into the full speed
ICE-51 memory to permit software testing to begin
before prototype hardware has been developed.
1-3 AFN-01739A
1,1\
i
CHAPTER 2
FUNCTIONAL DESCRIPTION
This chapter explains the functions of the 8051. The Conditional branches are performed relative to the Pro-
first part begins with a brief description of the memory gram Counter. The register-indirect jump permits
spaces and addressing modes. (For more in-depth infor- branching relative to a 16-bit base register with an offset
mation, please see Chapter 3.) The chapter then explains provided by an 8-bit index register. Sixteen-bit jumps
the hardware registers, the ALU, and Boolean Pro- and calls permit branching to any location in the con-
cessor. tiguous 64K Program Memory address space.
The second part of Chapter 2 explains in detail the The 8051 has five methods for addressing source
workings of the on-chip peripherals: the interrupt operands: Register, Direct, Register-Indirect, Im-
system, the I/O pins, the timer/counters and the serial mediate, and Base-Register-plus Index Register-Indirect
channel. Addressing.
The first three methods can be used for addressing

8051 CPU ARCHITECTURE destination operands. Most instructions have a "destina-
The 8051 CPU manipulates operands in four memory tion, source" field that specifies the data type, address-
spaces. These are the 64K-byte Program Memory, ing methods and operands involved. For operations
64K-byte External Data Memory, 384-byte Internal other than moves, the destination operand is also a
Data Memory and 16-bit Program Counter spaces. The source operand.
Internal Data Memory address space is further divided
into the 256-byte Internal Data RAM and 128-byte Registers in the four 8-Register Banks can be accessed
Special Function Register (SFR) address spaces shown through Register, Direct, or Register-Indirect Address-
in Figure 2-1. Four Register Banks (each bank has eight ing; the 128 bytes of Internal Data RAM through Direct
registers), 128 addressable bits, and the stack reside in or Register-Indirect Addressing; and the Special Func-
the Internal Data RAM. The stack depth is limited only tion Registers through Direct Addressing. External Data
by the available Internal Data RAM. Its location is Memory is accessed through Register-Indirect Address-
determined by the 8-bit Stack Pointer. All registers ex- ing. Look-up Tables resident in Program memory can
cept the Program Counter and the four 8-Register be accessed through Base Register-plus Index Register-
Banks reside in the Special Function Register address Indirect Addressing.
space. These memory mapped registers include
arithmetie registers, pointers, I/O ports, and registers The 8051 is classified as an 8-bit machine since the inter-
for the interrupt system, tim~rs and serial channel. 128 nal ROM, RAM, Special Function Registers, Arithmet-
bit locations in the SFR address space are addressable ic/Logie Unit and external data bus are each 8-bits
as bits. The 8051 currently contains 128 bytes of Inter- wide. The 8051 performs operations on bit, nibble, byte
nal Data RAM and 20 Special Function Registers. and double-byte data types.
64K
I
64K
EXTERNAL
OVERLAPPED SPACE
I
INTERNAL
4095
-------
~,----Ar
255 I
I
12~ I
I 255
Il
i I I 0
, ~
128
,
PROGRAM PROGRAM INTERNAL SPECIAL EXTERNAL
COUNTER MEMORY DATA RAM FUNCTION DATA
REGISTERS MEMORY
INTERNAL DATA MEMORY
Figure 21. 8051 Family Memory Organization
2-1 AFN01739A
The 8051 has extensive facilities for byte transfer, logic, Register Banks
and integer arithmetic operations. It excels at bit han-
There are four Register Banks within the Internal Data
dling since data transfer, logic and conditional branch
RAM. Each Register Bank contains registers R7-RO.
operations can be performed directly on Boolean
variables. 128 Addressable Bits
The 8051 's instruction set is an enhancement of the in- There are 128 addressable software flags in the Internal
struction set familiar to MCS-48 users. It is enhanced to Data RAM. They are located in the 16 byte locations start-
allow expansion of on-chip CPU peripherals and to op- ing at byte address 32 and ending with byte location 47 of
timize byte efficiency and execution speed. Op codes the RAM address space.
were reassigned to add new high-power operations and
to permit new addressing modes which make the old Stack
operations more orthogonal. Efficient use of program
memory results from an instruction set consisting of 49 The stack may be located anywhere within the Internal
single-byte, 45 two-byte and 17 three-byte instructions. Data RAM address space. The stack may be as large as 128
When using a 12MHz crystal, 64 instructions execute in bytes on the 8051.
1 ~s and 45 instructions execute in 2 ~s. The remaining SPECIAL FUNCTION REGISTERS
instructions (multiply and divide) require only 4 ~s. The
number of bytes in each instruction and the number of The Special Function Registers include arithmetic
oscillator periods required for execution are listed in the registers (A, B, PSW), pointers (SP, DPH, DPL) and
Instruction Set in Chapter 3 in Table 3-2. registers that provide an interface between the CPU and
the on-chip peripheral functions. There are also 128 ad-
CPU HARDWARE dressable bits within the Special Function Registers. The
memory-mapped locations of these registers and bits are
This section describes the hardware architecture of the discussed in Chapter 3.
8051's CPU in detail. The interrupt system and on-chip
functions peripheral to the CPU are described in subse- A Register
quent sections. A detailed 8051 Functional Block
Diagram is displayed in Figure 2-2. The A register is the accumulator.
Instruction Decoder B Register

Each program instruction is decoded by the instruction The B register is dedicated during multiply and divide and
decoder. This unit generates the internal signals that con- serves as both a source and a destination. During all other
trol the functions of each unit within the CPU section. operations the B register is simply another location of the
These signals control the sources and destination of data, Special Function Register space.
as well as the function of the Arithmetic/Logic Unit
(ALU). Program Status Word Register
Program Counter The carry (CY), auxiliary carry (Aq, user flag 0 (FO),
register bank select (RSO and RSl), overflow (OV) and
The 16-bit Program Counter (Pq controls the sequence in parity (P) flags reside in the Program Status Word (PSW)
which the instructions stored in program memory are ex- Register. These flags are bit-memory-mapped within the
ecuted. It is manipulated with the Control Transfer in- byte-memory-mapped PSW. The PSW flags record pro-
structions listed in Chapter 3. cessor status information and control the operation of
Internal Program Memory the processor.
The 805118751 have 4K bytes of program memory resi- The CY, AC, and OV flags generally reflect the status of
dent on-chip. the latest arithmetic operations. The P flag always reflects
the parity of the A register. The carry flag is also the
Internal Data Memory Boolean accumulator for bit operations. Specific details
on these flags are provided in the Arithmetic Flags section
The 8051 contains a 128-byte Internal Data RAM (which
of Chapter 3. FO is a general purpose flag which is pushed
includes registers R7-RO in each of four Banks), and twen-
onto the stack as part of a PSW save. The two Register
ty memory-mapped Special Function Register.
Bank select bits (RSI and RSO) determine which one of the
INTERNAL DATA RAM four Register Banks is selected.
The Internal Data RAM provides a convenient 128-byte Stack Pointer

scratch pad memory. The 8~bit Stack Pointer (SP) contains the address at which
2-2 AFN-01739A
r---~--r-~------------------'L
r-~-+--r-----------------~U
11 A
A
'I
~ ti PARITY J ~
ffi t-C....Y""'TI-IAC""'TI....FO""'TI.....
0
1~Ir-p..... 4~L..--____....I..-l----..J
IRS'""Illr-"IRS'""I0lrO....,V
0 ACC
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III
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SERIAL
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0 > ROM (8051)/
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(J
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....
c( I----------T-L-O--------~ C~~~~~L
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TCON
DPH ~~----~~--------~
:===~~D_P-L_-_-_-_--f--,-V J I ~ '7
SP ~~,,)r~___~'~~~__~~
ffi 128 x 8
PROGRAM CONTROL I - - rV
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(J
III
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~i -------------
o
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REGISTER BANK 3
REGISTER BANK
REGISTER BANK 1 CONTROL
~
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c(
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REGISTER BANK 0
CONTROL DRIVERS
DRIVERS ENGINE
k:: ~~
INSTRUCTION
DECODER
l}::
J
OSC
&
TIMING
~:(r
CIRCUITRY
L Pl I I P3 J I P2 J I PO J
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X
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T
A
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2
E
A
/
V
D
A
L
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P
P
S
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N
D D
PORT 1 PORT 3
D
PORT2
D
PORTO
R
S
T
/
V
V
C
C
V
S
D R P
o D
G
Figure 22. 8051 Family Functional Block Diagram
2-3 AFN-01739A
Hie last byte was pushed onto the stack. This is also the ad- Serial Data Buffer
dress of the next byte that will be popped. The SP is in-
The Serial Data Buffer (SBUF) register is used to hold
cremented during a push. SP can be read or written to
serial port input or output data depending on whether the
under software control.
serial port is receiving or transmitting data.
Data Pointer (High) and Data Pointer (Low)
The 16-bit Data Pointer (DPTR) register is the concatena- ARITHMETIC SECTION
tion of registers DPH (data pointer's high-order byte) and
The arithmetic section of the processor performs many
DPL (data pointer's low-order byte). The DPTR is used in
data manipulation functions and is comprised of the
Register- Indirect Addressing to move Program Memory
Arithmetic/Logic Unit (ALU), A register, B register and
constants, to move External Data Memory variables, and
PSW register. The ALU accepts 8-bit data words from one
to branch over the 64K Program Memory address space.
or two sources and generates an 8-bit result under the con-
Port 3, Port 2, Port 1, Port 0 trol of the instruction decoder. The ALU performs the
arithmetic operations of add, subtract, multiply, divide,
The four ports provide 32 I/O lines to interface to the ex- increment, decrement, BCD-decimal-add-adjust and
ternal world. All four ports are both byte and bit ad- compare, and the logic operations of and, or, exclusive-
dressable. The 8051 also allows memory expansion using or, complement and rotate (right, left, or nibble swap (left
Port 0 (PO) and Port 2 (P2) while Port 3 (P3) contains four.
special control signals such as the read and write strobes.
Port 1 (PI) is used for 110 only.
PROGRAM CONTROL SECTION
Interrupt Priority Register The program control section controls the sequence in
The Interrupt Priority (lPC) register contains the control which the instructions stored in program memory are ex-
bits to set an interrupt to a desired level. A bit set to a one ecuted. The conditional branch logic enables conditions
gives the particular interrupt a high priority listing. internal and external to the processor to cause a change in
the sequence of program execution.
Interrupt Enable Register
The Interrupt Enable (lEC) register stores the enable bits OSCILLATOR AND TIMING CIRCUITRY
for each of the five interrupt sources. Also included is a Timing generation for the 8051 is completely self-
global enable/disable bit of the interrupt system. contained, except for the frequency reference which can
be a crystal or external clock source. The on-board
Timer/Counter Mode Register
oscillator is a parallel anti-resonant circuit with a frequen-
Within the Timer Mode (TMOD) register are the bits that cy range of 1.2MHz to 12MHz. There is adivide-by-12 in-
select which operations each timer/counter will do. ternal timing which gives the 8051 a minimum instruction
cycle of 1 iJ.sec. with a 12MHz crystal. The XT AL2 pin is
Timer/Counter Control Register the output of a high-gain amplifier, while XT ALl is its in-
The timer/counters are controlled by the Timer/ put. A crystal connected between XT ALl and XT AL2
Counter Control (TCON) register bits. The start/stop bits provides the feedback and phase shift required for oscilla-
tion. U XT ALl is being driven by an external frequency
for the timer/counters along with the overflow and inter-
rupt request flags are mapped in TCON. source, XT AL2 should be a no connect. The 1.2MHz to
12MHz range is also accommodated when an external
Timer/Counter 1 (High), Timer/Counter 1 (Low), clock is applied to XT ALl as the frequency source.
Timer/Counter 0 (High), Timer/Counter 0 (Low)
There are four register locations for the two 16-bit timer/ BOOLEAN PROCESSOR
counters. These registers can be read or written to, to give The Boolean Processor is an integral part of the 8051 's ar-
the programmer easy access to the timer/counters. THI chitecture. It is an independent bit processor with its own
and THO refer to the 8 high-order bits of timer/counter 1 instruction set, its own accumulator (the carry register)
and 0, respectively. TLl and TLO refer to the low-order and its own bit-addressable RAM and 110. The bit
bits of both timer/counter 1 and O. manipulation instructions allow the Direct Addressing of
128 bits within the Internal Data RAM and 128 bits within
Serial Control Register the Special Function Registers as shown in Figures 2-3 and
This control register (SCON) has bits that enable recep- 2-4. The Special Function Registers with an address evenly
tion of the serial port. Selecting the operating mode of the divisable by eight (PO, TCON, PI, SCON, P2, lEe, P3,
serial port is accomplished with bits in this register also. IPC, PSW, A, and B) contain Directly Addressable bits.
2-4 AFN-01739A
a.) RAM Bit Addresses. A resource requests an interrupt by setting its associated
RAM interrupt request flag in the TCON or SCON register, as
BYTE
7FH 1....----------.,1
(MSB) (lSB)
detailed in Table 2-2. The interrupt request will be
acknowledged if its interrupt enable bit in the Interrupt
. Enable register (shown in Table 2-3) is set and if it is the
highest priority level as established by the polarity of a bit
2FH 7F 7E 70 7C 7B 7A 79 78 in the Interrupt Priority register. These bit assignments
2EH 77 76 75 74 73 72 71 70 are shown in Table 2-4. Setting the resource's associated
20H 6F 6E 60 6C 6B 6A 69 68 bit to a one (1) programs it to the higher level. The priority
2CH 67 66 65 64 63 62 61 60
of multiple interrupt requests occurring simultaneously
2BH SF 5E 50 5C 5B SA 59 58
and assigned to the same priority level is also shown in
2AH
Table 2.4.
57 56 55 54 53 52 51 50
29H 4F 4E 40 4C 4B 4A 49 48
b.) Hardware Register Bit Addresses.
28H 47 46 45 44 43 42 41 40
Direct Hardware
Bit Addresses
:~~ress
27H 3F 3E 3D 3C 3B 3A 39 38 Register
(MSB) (lSB)
Symbol
26H 37 36 35 34 33 32 31 30 OFFH
25H 2F 2E 20 2C 2B 2A 29 28 OFOH F7 I F6 I F5 I F4 I F3 I F2 I F1
I FO
24H 27 26 25 24 23 22 21 20
23H 1F 1E 10 1C 1B 1A 19 18 OEOH E7 I E6 I E5 1 1 1 1 1
E4 E3 E2 E1 EO ACC
22H 17 16 15 14 13 12 11 10
21H OF OE 00 OC OB OA 09 08 OOOH 07 I 06 I D5 I 04 I 03 I 02 I 01 I DO PSW
20H 07 06 05 04 03 02 01 00
1FH
Bank 3
18H OB8H - I- I- I BC I BB I BA I B9 I B8 IP
17H
Bank 2
10H OBOH B7 I B6 I B5 I B4 I B3 I B2 I B1 I BO P3
OFH
Bank 1
08H OA8H AF I- I- I AC I AB I AA I A9 I A8 IE
07H
Bank 0
OOH OAOH A7 I A6 I AS I A4 1 I A3 A2 I A1 1 AO P2
Figure 23. Data RAM Bit Address Space

98H 9F I 9E I 90 I 9C I 9B I 9A I 99 I 98 SCON
On any addressable bit, the Boolean processor can per-

form the bit operations of set, clear, complement, jump- 90H 97 I 96 I 95 I 94 I 93 I 92 I 91 I 90 P1
if-set, jump-if-not-set, jump-if-set-then-clear and move

to/from carry. Between any addressable bit (or its com- 88H 8F I 8E I 80 I 8C I 8B I 8A I 89 I 88 TCON
plement) and the carry flag it can perform the bit opera-
tion of logical and/ or logical or with the result returned to
the carry flag.
80H 87 I 86 I 85 I 84 I 83 I 82 1 1 81 80 PO
Figure 24. Special Function Register Bit

ONCHIP PERIPHERALS Address Space
The second section of Chapter 2 describes the on-chip The servicing of a resource's interrupt request occurs at
peripherals and external memory timing. This section the end of the instruction-in-progress. The processor
begins with the interrupt system. transfers control to the starting address of this
resource's interrupt service program and begins execu-
Interrupt System tion.
Interrupts result in a transfer of control to a new program
location. The program servicing the request begins at this Within the Interrupt Enable register (IE) there are six
address. In the 8051 there are five hardware resources that addressable flags. Five flags enable/disable the five
can generate an interrupt request. The starting address of interrupt sources when set/cleared. Setting/clearing the
the interrupt service program for each interrupt source is sixth flag permits a global enable/disable of each en-
shown in Table 2-1. abled interrupt request.
2-5 AFN01739A
Setting/ clearing a bit in the Interrupt Priority (IP) rupt request flags (lEO, lEI, TFO and TFI) are cleared
register establishes its associated interrupt request as a when the processor transfers control to the first instruc-
high/low priority. If a low-priority level interrupt is be- tion of the interrupt service program. The T! and RI in-
ing serviced, a high-priority level interrupt will interrupt terrupt request flags are the exceptions and must be
it. However, an interrupt source cannot interrupt a ser- cleared as part of the serial port's interrupt service pro-
vice program of the same or higher level. gram.
The processor records the active priority level(s) by set-

Table 23. Interrupt Enable Flags
ting internal flip-flop(s). One of these non-addressable
flip-flops is set while a low-level interrupt is being ser- Enable Bit
viced. The other flip-flop is set while the high-level in- Interrupt Source Flag Location
terrupt is being serviced. The appropriate flip-flop is set
when the processor transfers control to the service pro- External Request 0 EXO IE.O
gram. The flip-flop corresponding to the interrupt level Internal Timer / Counter 0 ETO 1E.1
being serviced is reset when the processor executes an External Request 1 EXI IE. 2
RET! Instruction. To summarize, the sequence of Internal Timer/ Counter 1 ETI 1E.3
events for an interrupt is: A resource provokes an inter- Internal Serial Port ES lEA
rupt by setting its associated interrupt request bit to let Reserved None 1E.5
the processor know an interrupt condition has occurred. Reserved None 1E.6
The CPU's internal hardware latches the internal re- All Enabled EA 1E.7
quest near the falling-edge of ALE in the tenth, twenty-
second, thirty-fourth and forty-sixth oscillator period of Table 24. Interrupt Priority Flags
the instruction-in-progress. The interrupt request is con-
ditioned by bits in the interrupt enable and interrupt Priority
priority registers. The processor acknowledges the inter- Priority Within Bit
rupt by setting one of the two internal "priority-level ac- Interrupt Source Flag Level Location
tive" flip-flops and performing a hardware subroutine
call. This call pushes the PC (but not the PSW) onto the External Request 0 PXO .0 (highest) IP.O
stack and, for most sources, clears the interrupt request Internal Timer /
flag. The service program is then executed. Control is Counter 0 PTO .1 IP.l
External Request 1 PXI .2 IP.2
returned to the main program when the RET! instruc-
Internal Timer /
tion is executed. The RETI instruction also clears one of
Counter 1 PTl .3 IP.3
the internal "priority-level active" flip-flops. Most inter-
Internal Serial Port PS .4 (lowest) IPA
Reserved None IP.5
Table 21. Starting Address for Interrupt Service Reserved None IP.6
Programs Reserved None IP.7
Interrupt Source Starting Address

External Request 0 3 (0003 H) The process whereby a high-level interrupt request inter-
Internal Timer/ Counter 0 11 (OOOB H) rupts a low-level interrupt service program is called
External Request I 19 (0013 H) nesting. In this case the address of the next instruction in
Internal Timer/ Counter I 27 (OOIB H) the low-priority service program is pushed onto the stack,
Internal Serial Port 35 (0023 H) the stack pointer is incremented by two (2) and processor
control is transferred to the Program Memory location of
the first instruction of the high-level service program. The
last instruction of the high-priority interrupt service pro-
Table 22. Interrupt Request Flags
gram must be an RET! instruction. This instruction clears
Request Bit the higher "priority-level-active" flip-flop. RET! also
Interrupt Source Flag Location returns processor control to the next instruction of the
low-level interrupt service program. Since the lower
External Request 0 lEO TCON.I "priority-level-active" flip-flop has remained set, high
Internal Timer/ Counter 0 TFO TCON.S priority interrupts are re-enabled while further low-
External Request I lEI TCON.3 priority interrupts remain disabled.
Internal Timer/ Counter I TFI TCON.7
Internal Serial Port (xmit) TI SCON.I The highest-priority interrupt request gets serviced at the
Internal Serial Port (rcvr) RI SCON.O ,end of the instruction-in-progress unless the request is
2-6 AFN01739A
made in the last fourteen oscillator periods of the When ITO and ITI are set to one (1), interrupt requests on
instruction-in-progress. Under this circumstance, the INTO and INTI are transition-activated (high-to-Iow), or
next instruction will also execute before the interrupt's else they are low-level activated. lEO and lEI are the inter-
subroutine caIl is made. The first instruction of the service rupt request flags. These flags are set when their cor-
program will begin execution twenty-four oscillator responding interrupt request inputs at INTO and INTI,
periods (the time required for the hardware subroutine respectively, are low when sampled by the 8051 and the
call) after the completion of the instruction-in-progress transition-activated scheme is selected by ITO and ITI.
or, under the circumstances mentioned earlier, twenty- When ITO and ITI are programmed for level-activated in~
four oscillator periods after the next instruction. terrupts, the lEO and lEI flags are not affected by the in-
puts at INTO and INTI, respectively.
Thus, the greatest delay in response to an interrupt request
is 86 oscillator periods (approximately 7\Jsec @ I2MHz).
TransitionActivated Interrupts
Examples of the best and worst case conditions are il-
lustrated in Table 2-5. The external interrupt request inputs (INTO and INTI)
can be programmed for high-to-Iow transition-activated
operation. For transition-activated operation, the input
Table 25. Best and Worst Case Response to
must remain low for greater than twelve oscillator
Interrupt Request
periods, but need not be synchronous with the oscillator.
Time It is internally latched by the 8051 near the falling-edge of
(Oscillator Periods) ALE during an instruction's tenth, twenty-second, thirty-
fourth and forty-sixth oscillator periods and, if the input is
Instruction Best Worst low, lEO and lEI is set. The upward transition of a
Case Case transition-activated input may occur at any time after the
1) External interrupt request 2+ E 2-E twelve oscillator period latching time, but the input must
generated immediately remain high for twelve oscillator periods before reactiva-
before (best) / after (worst) tion.
the pin is sampled. (Time
until end of bus cycle.) LevelActivated Interrupts
2) Current or next instruction 12 12 The external interrupt request inputs (INTO and INTI)
finishes in 12 oscillator can be programmed for level-activated operation. The in-
periods put is sampled by the 8051 near the falling-edge of ALE
3) Next instruction is MUL don't 48 during the instruction's tenth, twenty-second, thirty-
or DIV care fourth and forty-sixth oscillator periods. If the input is
4) Internal latency for hard- 24 24 low during the sampling that occurs fourteen oscillator
ware subroutine call periods before the end of the instruction in progress, an in-
38 86 terrupt subroutine caIl is made. The level-activated input
need be low only during the sampling that occurs fourteen
oscillator periods before the end of the instruction-in-
EXTERNAL INTERRUPTS progress and may remain low during the entire e.xecution
of the service program. However, the input must be raised
The external interrupt request inputs (INTO and INTI) before the service program completes to avoid possibly en-
can be programmed for either transition-activated or voking a second interrupt.
level-activated operation. Control of the external inter-
rupts is provided by the four low-order bits of TCON as
Ports and 1/0 Pins
shown in Table 2-6.
There are 32 110 pins configured as four 8-bit ports. Each
Table 26. Function of Bits in TCON pin can be individually and independently programmed as
(Lower Nibble) input or output and each can be configured dynamically
(Le., on-the-fly) under software control.
Bit
Function Flag Location An instruction that uses a port's bit/byte as a source
operand reads a value that is the logical arid of the last
External Interrupt Request Flag I lEI TCON.3 value written to the bit/byte and the polarity being ap-
Input INTI Transition-Activated ITI TCON.2 plied to the pin/pins by an external device (this assumes
External Interrupt Request Flag 0 lEO TCON.I
that none of the 8051 's electrical specs are being
Input INTO Transition Activated ITO TCON.O violated). An instruction that reads a bit/byte, operates
2-7 AFN01739A
on the content, and writes the result back to the IRE,6.D (READ-
bit/byte, reads the last value written to the bit/byte in- MODIFY-WRITE)
stead of the logic level at the pin/pins. Pins comprising

a single port can be made a mixed collection of inputs +5V
and outputs by writing a "one" to each pin that is to be
an input. Each time an instruction uses a port as the
destination, the operation must write "ones" to those
a
bits that correspond to the input pins. An input to a port INTERNAL
D
BUS
pin need not be synchronized to the oscillator. Each
D
port pin is sampled near the falling-edge of ALE during FLIP
FLOP
the read instruction's tenth or twenty-second oscillator
period. If an input is in transition when it is sampled
near the falling-edge of ALE it will be read as an in- a
CLK
determinate value.
WRITE PULSE
ZERO TO 1
The instructions that perform a read of, operation on, TRANSITION
and write to a port's bit/byte are INC, DEC, CPL, JBC,

CJNE, DJNZ, ANL, ORL, and XRL. The source read READ
by these operations is the last value that was written to (NON READ-
MODIFY-
the port, without regard to the levels being applied at WRITE)
the pins. This insures that bits written to a one (1) for
Figure 26. "QuasiBidirectional" Port Structure
use as inputs are not inadvertently cleared; see Figure
2-5.
In Ports 1, 2 and 3 the output driver provides source
current for two oscillator periods if, and only if, soft-
READ (READ-
MODIFY-WRITE) --~
ware updates the bit in the output latch from a zero (0)
to a one (1). Sourcing current only on "zero to one"
transition prevents a pin, programmed as an input,
+5V from sourcing current into the external device that is
driving the input pin. The output drivers in Ports 1, 2
and 3 can sink/ source one TTL load.
a
INTERNAL
D
BUS Secondary functions (RD, WR, etc.) can be selected in-
D dividually and independently for the pins of Port 3.
FLIP
1/0
FLOP
PIN
Port 3 generates these secondary control signals
PORT automatically as long as the pin corresponding to the
0
a appropriate signal is programmed as an input.
CLK
WRITE PULSE Accessing External Memory

BUS CYCLE
TIMING When accessing external memory the 8051 emits the up-
per address byte from Port 2 and the lower address byte,
as well as the data, from Port O. It uses ALE, PSEN and
READ
(NON READ- two pins from Port 3 (RD and WR) for memory con-
MODIFY-WRITE) trol. ALE is used for latching the address into the exter-
Figure 25. "Bidirectional" Port Structure nal memory. The PSEN signal enables the external Pro-
gram Memory to Port 0, the RD signal enables External
Data Memory to Port 0 and the WR signal latches the
When used as a port, Port 0 has an open-drain output. data byte emitted by Port 0 into the External Data
When used as a bus, it has a standard three-state driver. Memory. Externally the PSEN and RD signals can be
The Port 0 output driver can sink/source two TTL combined logically if a contiguous external program
loads. and data memory space (similar to a "von Neuman"
machine) is desired. The P3.7 (RD) and P3.6 (WR) out-
Ports 1, 2 and 3 have quasi-bidirectional output drivers put latches must be programmed to a one (1) if External
which incorporate a pull-up resistor of lOK-to-20K Data Memory is to be accessed. When P3.7 and P3.6 are
Ohms as shown in Figure 2-6. programmed as RD and WR, respectively, the remain-
28 AFN-01739A
ing pins of Port 3 may be individually programmed as ACCESSING EXTERNAL MEMORY-OPERATION

desired. The 8051 can address 64K bytes of external OF PORTS
Program Memory when the EA pin is tied low. When
EA is high, the 8051 fetches instructions from internal The Port 0 bus is time-multiplexed to permit transfer of
Program Memory when the address is between 0 and both addresses and data. This bus is used directly by
memory and peripheral devices that incorporate on-chip
4095, and from external Program Memory when the ad-
dressed memory location is between 4096 and 64K. In address latching (MCS-85 memories with peripherals),
either case, Ports 2 and 0 are automatically configured or it can be de-multiplexed with an address latch to
as an external bus, based on the value of the Pc. In- generate a non-multiplexed bus (MCS-80 peripherals
struction execution times are the same for code fetched and memory). During an external access, the low-order
from internal or external Program Memory. byte of the address and the data (for a write) is emitted
by the Port 0 output drivers. Ones (l's) are automatical-
Up to 64K of External Data Memory can be accessed us- ly written to Port 0 at the very end of the bus cycle.
ing the MOVX instructions. These instructions Since the Port 0 output latches will contain ones (l's) at
automatically configure Port 0, and often Port 2, as an the end of the bus cycle, Port 0 will be in its high im-
external bus. The MOVX instructions use the DPTR, pedance state when a bus cycle is not in progress. Port 2
Rl or RO register as a pointer into the External Data emits the upper 8-bits of the address when a MOVX in-
Memory. The 16-bit DPTR register is used when suc- struction using DPTR is executed. Port 2's output
cessive accesses cover a wide range of the 64K space. drivers provide source current for two oscillator periods
The 8-bit Rl and RO registers provide greatest byte effi- when emitting the address. Port 2's internal pull-up
ciency when successive accesses are constrained to a resistors sustain the high level.
256-byte block of the External Data Memory space.
When using Rl and RO, a subsequent block can be ac-
cessed by updating the output latch of Port 2. Port 2 is ACCESSING EXTERNAL MEMORY-BUS CYCLE
not affected by execution of a MOVX instruction that TIMING
uses Rl or RO. If, for example, 32K or less of external
data memory is present, only part of Port 2 needs to be (The following section is a description of the 8051 's tim-
used for selecting the desired block; the remaining pins ings. For design purposes, please refer to the specifica-
of Port 2 can be used for 110. When a MOVX using tion section in Chapter 6 for 8051 timing parameters.)
DPTR is executed, the value in Port 2's output latch is
altered only during the external access and then is Each Program Memory bus cycle consists of six
returned to its prior value. This permits efficient exter- oscillator periods. These are referred to as Tl, T2, T3,
nal block moves by interleaving MOVX instructions T4, T5 and T6 on Figure 2-7. The address is emitted
that use DPTR and Rl and RO. from the processor during T3. Data transfer occurs on
the bus during T5, T6, and the following bus cycle's Tl.
The ALE signal is generated every sixth oscillator period When fetching from external Program Memory, the
during reads from either internal or external Program 8051 will always fetch an even number of bytes. If an
Memory. The PSEN signal is generated every sixth odd number of bytes are executed prior to a branch, or
oscillator period when reading from the external Pro- an External Data Memory access, the non-executed byte
gram Memory. When a read or write from External will be ignored by the 8051. An even number of idle bus
Data Memory is being performed, a single ALE and a cycles (each 6 oscillator periods in duration) can occur
RD or a WR signal is generated during a twelve between external bus cycles when the processor is fetch-
oscillator period interval. The 8051 always fetches an ing from internal Program Memory. The read cycle
even number of bytes from its Program Memory. If an begins during T2, with the assertion of address latch
odd number of bytes are executed prior to a branch or enable signal ALE CD. The falling edge of ALE @ is
to an External Data Memory access, the nonexecuted used to latch the address information, which is present
byte is ignored by the 8051. If an instruction requires on the bus at this time Q), into the 8282 latch if a non-
more oscillator periods for its execution than for its multiplexed bus is required. At T5, the address is
fetch, the first byte of the next instruction is fetched removed from the Port 0 bus and the processor's bus
repeatedly while the first instruction completes execu- drivers go to the high-impedance state . The program
tion. If the CPU does not address External Data memory read control signal (PSEN) ~ is also asserted
Memory, then ALE is generated every sixth oscillator during T5. PSEN causes the addressed device to enable
period and can be used as an external clock. When Ex- its bus drivers to the now-released bus. At some later
ternal Data Memory is present, external logic may be time, valid instruction data will become available on the
used to combine the occurrence of RD, WR, and ALE bus @. When the 8051 subsequently returns PSEN to
to generate an external clock with a period equal to six the high level (J), the addressed device will then float its
oscillator periods. bus drivers, relinquishing the bus again .
29 AFN01739A
OSC
T12 T1 T2 T3 T4 TS T6 T7 T8 T9 no n1 T12 n T2
ALE
Ro,WR
PORT 2
PORTO
Figure 27. Program Memory Read Cycle Timing
ALE 8V \0 II
II
RD
~0 011

PORT 2
rx ADDRESS A1S-AS
8) r&l
PORTO INST I~ IFLOAT A7- A O
1 FLOAT
K DATA IN
I FLOAT
ADD RESS
OR FLOAT
I I I I I I
Figure 28. Data Memory Read Cycle Timing
For the MOVe instruction, the op-code is fetched in the and T6 is the period during which the direction of the
first six-oscillator period, the first byte of the next in- bus is changed for the r(;!ad operation. The read cycle
struction is fetched during the second six-oscillator begins during T2, with the assertion of address latch
period, the table entry is fetched in a third six-oscillator enable signal ALE CD: The falling edge of ALE (2) is
period and the first byte of the next instruction is again used to latch the address information, which is present
fetched in the fourth six-oscillator period. on the bus at this time Q) , into the 8282 latch if a non-
multiplexed bus is required. At T5, the address is
Each External Data Memory bus cycle consists of twelve removed from the Port 0 bus and the processor's bus
oscillator periods. These are shown as Tl through TI2 drivers go to the high-impedance state . The data
on Figure 2-8. The twelve-period External Data memory read control signal RD ~, is asserted during
Memory cycle allows the 8051 to use peripherals that are T7. RD causes the addressed device to enable its bus
relatively slower than its program memories. The ad- drivers to the now-released bus. At some later time,
dress is emitted from the processor during T3. Data valid data will be available on the bus . When the
transfer occurs on the bus during T7 through T12. T5 8051 subsequently returns RD to the high level Q), the
AFN-01739A
2-10
addressed device will then float its bus drivers, relin- Mode 1) Configures counter 1 as a 16-bit timer/
quishing the bus again . counter.
The write cycle, like the read cycle, begins with the Mode 2) Configures counter 1 as an 8-bit auto-
assertion of ALE Q) and the emission of an address ~ reload timer/counter. THI holds the
as shown in Figure 2-9. In T6, the processor emits the reload value. TLl is incremented. The
data to be written into the addressed data memory loca- value in THI is reloaded into TLl when
tion Q). This data remains valid on the bus until the TLl overflows from all ones (l's). An 8048
end of the following bus cycle's T2 @. The write signal compatible counter is achieved by con-
WR goes low at T6 CI> and remains active through T12 figuring to mode 2 after zeroing THI.
@.
Mode 3) When counter 1's mode is reprogrammed
to mode 3 (from mode 0, 1 or 2), it disables
Timer/Counters the incrementing of the counter. This mode
is provided as an alternative to using the
Two independent 16-bit timer/counters are on-board TRI bit (TCON.6) to start and stop
the 8051 for use in measuring time intervals, measuring counter 1.
pulse widths, counting events, and causing periodic
(repetitious) interrupts. The serial port receives a pulse each time that counter 1
overflows. The standard UART modes divide this pulse
rate to generate the transmission rate.
TIMER/COUNTER MODE SELECTION
Counter 1 can be configured in one of four modes: Counter 0 can also be configured in one of four modes:
Mode 0) Provides an 8-bit counter with a divide- Modes 0-2) Modes 0-2 are the same as for counter 1.
by-32 prescaler or an 8-bit timer with a
divide-by-32 prescaler. A read/write of Mode 3) In Mode 3, the configuration of THO is not
THI accesses counter l's bits 12-5. A affected by the bits in TMOD or TCON
read/write of TLI accesses counter l's bits (see next section). It is configured solely as
7-0. TLl bits 4-0 are the prescalar (counter an 8-bit timer that is enabled for incremen-
l's bits 4-0), while bits 7-5 are indeter- ting by TCON's TRI bit. Upon THO's
minate and should be ignored. The pro- overflow, the TFI flag gets set. Thus,
grammer should clear the prescaler neither TRI nor TFI is available to counter
(counter 1's bits 4-0) before setting the run 1 when counter 0 is in Mode 3. The func-
flag. tion of TRI can be done by placing counter
ALE (i{ \ I
V
WR
1\0 V
0
PORT 2
~ ADDRESS A15-AS
CD (3) G)
PORTO INST I~ IFLOAT A7- AO
X DATA OUT
ADD RESS
OR FLOAT
I I I I I
Figure 29. Data Memory Write Cycle Timing
2-11 AFN-01739A
1 in Mode 3, so only the function of TFI is Table 27. Function of Bits in TCON
actually given up by counter 1. In Mode 3, (Upper Nibble)
TLO is configured as an 8-bit timer/counter
Bit
and is controlled, as usual, by the Gate
Function Flag Location
(TMOD.3) clf (TMOD.2), TRO
(TCON.4) and TFO (TCON.5) control bits. Counter interrupt request and TFI TCON.7
overflow Flag
Counter enable/disable bit TRI TCON.6
CONFIGURING THE TIMER/COUNTER INPUT
Counter interrupt request and TFO TCON.5
The use of the timer/counter is determined by two 8-bit overflow Flag
registers, TMOD (timer mode) and TCON (timer con- Counter enable/disable bit TRO TCON.4
trol). The counter input circuitry is shown in Figures
2-10 and 2-11. The input to the counter circuitry is from
an external reference (for use as a counter), or from the The functions of the bits in TMOD are shown in Table
on-chip oscillator (f~ use as a timer), depending on 2-8. Recall that the bits in TMOD are not bit ad-
whether TMOD's CIT bit is set or cleared, respectively. dressable.
When used as a time base, the on-chip oscillator fre-
quency is divided by twelve (12) before being input to
the counter circuitry. When TMOD's Gate bit is set (1),
the external reference input (Tl, TO) or the oscillator in- Table 28. Functions of Bits in TMOD
put is gated to the counter conditional upon a second ex- Bit
ternal input (INTO), (INTI) being high. When the Gate Function Flag Location
bit is zero (0), the external reference, or oscillator input,
is unconditionally enabled. In either case, the normal in- Enable input at TI using INTI Gate TMOD.7
terrupt function of INTO and INTI is not affected by Counter I/Timer I select CjT TMOD.6
C I/T I Mode select MSb MI TMOD.5
the counter's operation. If enabled, an interrupt will oc-
C I/T I Mode select LSb MO TMOD.4
cur when the input at INTO or INTI is low. The
Enable input to TO using INTO Gate TMOD.3
counters are enabled for incrementing when TCON's
TRI and TRO bits are set. When the counters overflow
the TFI and TFO bits in TCON get set, and interrupt re~ Counter 0/ Timer 0 select CIT TMOD.2
C OfT 0 Mode select MSb MI TMOD.I
quests are generated. The functions of the bits in TCON
C OfT 0 Mode select LSb MO TMOD.O
are shown in Table 2-7.
COUNTER 0
MODE 0: 8-BIT TIMER WITH PRESCALER/
8-BIT COUNTER WITH PRESCALER
MODE 1: 16-BIT TIMER/COUNTER
MODE 2: 8-BIT AUTO-RELOAD TIMER/COUNTER
MODE 3: 8-BIT TIMER/COUNTER (TLO)
TO---.....I
XTAL1
Figure 210. Timer/Event Counter 0 Control and Status Flag Circuitry
2-12 AFN01739A
PULSE TO
COUNTER 1 SERIAL PORT
MODE 0: 8-BIT TIMER WITH PRESCALER/
8-BIT COUNTER WITH PRESCALER
MODE 1: 16-BIT TIMER/COUNTER
MODE 2: 8-BIT AUTO-RELOAD T/C
MODE 3: PREVENTS INCREMENTING
OFT/C
COUNTER 0
Figure 211. Timer/Event Counter 1 Control and Status Flag Circuitry
OPERATION the time when a toggled input (transition from high to

low) is sampled to the time when the counter is in-
The counter circuitry counts up to all 1's and then
cremented.
overflows to either O's or the reload value. Upon
overflow, TFI or TFO gets set. When an instruction
changes the timer's mode or alters its control bits, the Serial Channel
actual change occurs at the end of the instruction's ex- The 8051 has a serial channel useful for serially linking
ecution. UART (universal asynchronous receiver/transmitter)
devices and for expanding I/O. This full-duplex serial
The Tl and TO inputs are sampled near the falling-edge I/O port can be programmed to function in one of four
of ALE in the tenth, twenty-second, thirty-fourth and operating modes:
forty-sixth oscillator periods of the instruction-in-
progress. They are also sampled in the twenty-second Mode 0) Synchronous I/O expansion using TTL or
oscillator period of MOVX, despite the absence of CMOS shift registers
ALE. Thus, an external reference's high and low times
must each be a minimum of twelve oscillator periods in Mode 1) UART interface with lO-bit frame and
duration. There is a twelve oscillator period delay from variable transmission rate
TXD RXD
TXD
,
RXD TXD RXD RXD TXD
r TXD RXD
r TXD RXD
! TXD ~ RXD
RXD 14- TXD
PORT PIN f...---...-. CTS
8051 8051 8051 8051 8051 8051 8051 8251
A. MULTI-80S1 INTERCONNECT -HALF DUPLEX B. MULTI-80S1 INTERCONNECT -FULL DUPLEX C. 8051-8251 INTERFACE
Figure 212. UART Interface Technique
2-13 AFN-01739A
Mode 2) UART interface with ll-bit frame and fixed Table 29. Functions of Bits in SCON
transmission rate
Bit
Mode 3) UART interface with II-bit frame and Function Flag Location
variable transmission rate Serial Port Operation SMO SCON.7
Mode (MSb)
Modes 2 and 3 also provide automatic wake-up of slave Serial Port Operation SMI SCON.6
processors through interrupt driven address-frame Mode (LSb)
recognition for multiprocessor communications. Conditional Receiver SM2 SCON.5
Several schemes of UART interfacing are shown in Enable
Figure 2-12, and an I/O expansion technique is shown Receiver Enable REN SCON.4
in Figure 2-13. Transmitter Data Bit 8 TB8 SCON.3
Received Data Bit 8 RB8 SCON.2
Transmission Complete TI SCaN. 1
Interrupt Flag.
8051 Reception Complete RI SCaN. 0
Interrupt Flag
DATA
CLOCK
PORT PIN
Mode control bits SMO and SMI program the serial port
A. 1/0 INPUT
EXPANSION in one of four operating modes. A detailed description
of the modes is provided later in the text. The receiver-
8051
enable bit (REN) resets the receiver's start/stop logic.
When software sets REN to one (1), the receiver's
transmission-rate generator is initialized and reception
DATA OS
CLOCK is enabled. REN must be set as part of the serial
EN
PORT PIN channel's initialization program. When REN is cleared,
reception is disabled.
B. 1/0 OUTPUT
EXPANSION
The CPU is informed that the transmitter portion of
Figure 213. 1/0 Expansion Technique SBUF is empty, or the receiver portion is full, by TI and
RI, respectively. TI and RI must be cleared as part of
the interrupt service program so as not to continuously
SERIAL CHANNEL CONTROL AND interrupt the CPU. Since TI and RI are "or-ed" together
DATA REGISTERS to generate the serial port's interrupt request, they must
Data for transmission and from reception reside in the be polled to determine the source of the interrupt.
serial port buffer register (SBUF). A write to SBUF up-
dates the transmitter register, while a read from SBUF OPERATING MODES
reads a buffer that is updated by the receiver register
if/when flag RI is reset. The receiver is double-buffered Operating Mode 0
to eliminate the overrun that would occur if the CPU The I/O expansion mode, Mode 0, is used to expand the
failed to respond to the receiver's interrupt before the number of input and output pins. In this mode, a clock
beginning of the next frame. In general, double buffer- output is provided for synchronizing the shifting of bits
ing of the transmitter is not needed for the high perfor- into, or from, an external register. Eight bits will be
mance 8051 to maintain the serial link at its maximum shifted out each time a data byte is written to the serial
rate. A minor degradation in data rate can occur in rare channel's data buffer (SBUF), even if TI is set. Each
events, such as when the servicing of the transmitter has time software clears the RI flag, eight bits are shifted in-
to wait for a lengthy interrupt service program to com- to SBUF before the RI flag is again set. The receiver
plete. In asynchronous mode, false start-bit rejection is must be enabled [Le., REN set to (1)] for reception to
provided on received frames. A two-out-of-three vote is occur.
taken on each received bit for noise rejection. The serial
port's control and the monitoring of its status is provid- The synchronizing clock is output on pin P3.1 and tog-
ed by the serial port control register (SCaN). The con- gles from high to low near the falling-edge of ALE in
tents of the 8-bit SCON register are shown in Table 2-9. the fifteenth oscillator period following execution of the
2-14 AFN01739A
instruction that updated SBUF or cleared the RI flag. It In Modes 2 and 3, if SM2 is set, frames are received, but
then toggles near the falling-edge of ALE in each subse- an interrupt request is generated only when the received
quent sixth oscillator period until S-bits are transferred. data bit S (RBS) is a one (1). This feature permits inter-
The eighth rising-edge of clock (P3.1) sets the RI or TI rupt generated wake-up during interprocessor com-
flag. At this point, shifting is complete and the clock is munications when multiple S051's are connected to a
once again high. The first bit is shifted out of P3.0 at the serial bus. Thus, data bit S (RBS) awakens all processors
beginning of the eighteenth oscillator period, following on the serial bus only when the master is changing ad-
the instruction that updated SBUF. The first bit shifted dress to a different processor. Each processor not ad-
in from P3.0 is latched by the clock's rising-edge in the dressed then ignores the subsequent transmission of
twenty- fourth oscillator period, following the instruc- control information and data. A protocol for
tion that cleared the RI flag. One bit is shifted every multi-S051 serial communications is shown in Figure
twelfth oscillator period, until all eight bits have been 2-14. The SM2 bit has no effect in Modes 0 and l.
shifted.
Operating Modes 1 through 3

1. The hardware in each slave's serial port
In the UART Modes (i.e., 1 through 3), the transmis- begins by listening for an address. Receipt of
sion rate is subdivided into 16 "ticks." The value of a an address frame wi" force an interrupt if the
received bit is determined by taking a majority vote slave's 5M2 bit is set to one (1) to enable "in
terrupt on address frame only".
after it has been sampled during the seventh, eighth and 2. The master then transmits a frame containing
ninth "ticks." If two or three ones (1 's) are detected, the the 8bit address of the slave that is to receive
bit will be given a one (1) value; if two or three zeros the subsequent commands and data. A
(O's) are detected, the bit will be given a zero (0) value. transmitted address frame has its ninth data
bit (TB8) set equal to one (1).
3. When the address frame is received, each
Until a start bit arrives, the receiver samples the RXD slave's serial port interrupts its CPU. The CPU
input pin (P3.0) every "tick." Approximately one-half then compares the address sent to its own.
bit time (eight "ticks") after the start bit is detected (i.e., 4. The 8051 slave which has been addressed
a low input level was sampled on "tick" one), the serial then resets its 5M2 bit to zero (0) to receive a"
port checks its validity (majority vote from "ticks" subsequent transmissions. A" other 8051's
leave their 5M2 bits at a one (1) to ignore
seven, eight and nine) and accepts or rejects it. This pro- transmissions until a new address arrives.
vides rejection of false start bits. 5. The master device then sends control informa
tion and data, which in turn is accepted by the
The contents of the receiver's input shift register is mov- previously addressed 8051 [i.e., the one that
ed to SBUF and RBS (Modes 2 and 3), and RI is set had set its 5M2 bit to zero (0)].
when a frame's ninth (Mode 1) or tenth (Modes 2 and 3)
bit is received. Upon reception of a second frame's ninth Figure 214. Protocol for MultiProcessor
or tenth bit, the data bits in the shift register are again Communications
transferred to SBUF and RBS, but only if software has
THE SERIAL FRAME
reset the RI flag. If RI has not been reset, then overrun
will occur, since the shift register will continue to accept A frame is a string of bits. The frame transmitted and
bits. Double buffering the receiver provides the CPU received in Mode 0 is S bits in length. The data bits of
with one frame-time in which to empty the SBUF and the frame are transmitted SBUF.O first and SBUF.7
RBS registers. The RI flag is set and bit RBS is loaded last.
during the ninth "tick" of the received frame's ninth or
tenth bit. The serial port begins looking for the next The frame transmitted and received in Mode 1 is ten bits
start bit approximately one-half bit time after the center in length. The frame transmitted and received in Modes
of a stop bit is received. 2 and 3 is eleven bits in length. These frames consist of
one start bit, eight or nine data bits and a stop bit. Data
Data is transmitted from the TXD output pin (P3.1) bits 0-7 are loaded into SBUF.0-SBUF.7, respectively,
each time a byte is written to SBUF, even if TI is set. and data bit S into RBS (receive) or TBS (transmit).
Transmission of the start bit begins at the end of the in- With nominal software overhead, the last data bit can
struction that updates SBUF. TI is set at the beginning be made a parity bit, as shown in Figure 2-15.
of the transmitted tenth (Mode 1) or eleventh (Mode 2
or 3) bit. After TI becomes set, if SBUF is written-to Figure 2-16 shows some typical frame formats' for dif-
prior to the end of the stop (tenth or eleventh) bit, the ferent applications. The data bits of the frame are
transmission of the next frame's start bit will not begin transmitted least significant bit first (SBUF.O) and TBS
until the end of the stop bit. last.
2-15 AFN01739A
First, the 8051 's serial channel provides no indication

MOV C, P ; Parity moved to carry (byte that a valid stop bit has been received. However, since a
already in A). start bit is detected as a high-level to low-level transi-
MOV TB8, C ; Put carry into Transmitter Bit 8 tion, the UART will not receive additional frames if a
MOV SBUF, A; Load Transmit Register stop bit is not received. Second, the RI flag is set and
SBUF and RB8 are loaded from the receiver's input shift
Figure 215. Generating Parity and Transmitting register when the received last data bit (Le., ninth or
Frame tenth received bit) is sampled. As long as RI is set, the
loading of SBUF, the updating of RB8, and the genera-
tion of further receiver interrupts is inhibited. Thus,
110 BAUD TTY
overrun will occur if the programmer does not reset RI
I I
START DATA.O I 121 .31 .41 .Sl .61
.1 PARITY I STOP I STOP I before reception of the next frame's last data bit, since
TYPICAL ASCII TERMINAL the receiver's input shift register will shift in a third
I START I
DATA .0 I I I I I .S I I
.1 .2 .3 .4 .6 PARITY I STOP I frame.
OR
I I .01 I .21 .31 .41 .Sl .61.71
START DATA .1 PARITY I STOP I Processor Reset and Initialization
Processor initialization is accomplished with activation
of the RST/VPD pin. To reset the processor, this pin
OR
should be held high for at least twenty-four oscillator
I I
START DATA.O I I .21 .31 .4 I .SI .6 17 I I
.1 .8 STOP I periods. Upon powering up, RST/VPD should be held
high for at least 24 oscillator periods, after the power
Figure 216. Typical Frame Formats supply stabilizes, to allow the oscillator to stabilize.
Crystal operation below 6MHz will increase the time
TRANSMISSION RATE GENERATION necessary to hold RST IVPD high. 24 oscillator periods
after receipt of RST, the processor ceases instruction ex-
The proper timing for the serial I/O data is provided by ecution and remains dormant for the duration of the
a transmission-rate generator. On-board the 8051, three pulse. The low-going transition then initiates a sequence
different methods of transmission rate generation are which requires approximately twelve oscillator periods
provided. The transmission-rate achievable is dependent to execute before ALE is generated and normal opera-
upon the operating mode of the serial port. tion commences with the instruction at absolute loca-
tion OOOOH. Program Memory locations OOOOH through
In the I/O expansion mode (Mode 0) the oscillator fre- 0003H are reserved for the initialization routine of the
quency is simply divided by 12 to generate the transmis- microcomputer. This sequence ends with registers in-
sion rate. This produces a transmission rate of 1M bits itialized as shown in Table 2-10.
per second at 12MHz. If Modes 1 or 3 are being used,
the transmission rate can be generated from the
oscillator frequency or from an external reference fre- Table 210. Register Initialization
quency. In these modes, either one-twelfth the oscillator
frequency, or the T1 input frequency, is divided by Register Content
256-minus-the-value-in-THI (counter 1 must be con-
figured in auto-reload mode by software) and then PC OOOOH
divided by 32 to generate the transmission rate. When SP 07H
the oscillator frequency input (rather than Tl) is PSW, DPH, DPL, A, B. OOH
selected, this method produces a transmission rate of IP, IE, SCON, TCON, OOH
122 to 31,250 bits per second (including start and stop TMOD, THI, THO, DOH
bits) at 12MHz. The Tl external input is selected by set- TLl, TLO OOH
ting the CIT bit to one (1). When Mode 2 is used, the IP EOH
oscillator frequency is simply divided by 64 to generate IE 60H
the transmission rate. This produces a transmission rate SBUF Indeterminate
of 187,500 bits per second (including start and stop bits) Port 3-PQrt 0 FFH (configures all I/O
at 12MHz. pins as inputs)
Internal RAM Unchanged if VPD
UART ERROR CONDITIONS applied; else
indeterminate
There are two UART error conditions that should be ac-
counted for when designing systems that use the serial
channel.
2-16 AFN01739A
In addition, certain of the control pins are driven to a supply to RST /VPD pin. Applying power to the
high level during reset. These are ALE/PROG and RST /VPD pin resets the 8051 and retains the internal
PSEN. Thus, no ALE or PSEN signals are generated RAM data valid as the vee power supply falls below
while RST /VPD is high. After the processor is reset, all limit. Normal operation resumes when RST /VPD is
ports are written with one (I's). Outputs are undefined returned low. Figure 2-18 shows the waveforms for the
until the reset period is complete. An external reset cir- power-down sequence.
cuit, such as that in Figure 2-17, can be used to reset the
microcomputer.
vee - - - - - - - -....
,i'--...---/'TI----
,
+5V
INTO - - - - - - - "
(POWER-FAIL)
I '
INL.T=ER-=-R-UP=T-J-,_ _ _ _ ..L...\- - - -
, I
I I
RST/VPD - - - - - - - - - ' I
8051
.... -----~.~I~
NORMAL OPERATION SERVICE PROGRAM NORMAL OPERATION
!
RSTNPD
Figure 218. Power Down Sequence
EPROM Programming
+5V
The 8751 is programmed, and the 8051 and 8751 are
L~
verified, using the UPP-851 programming card. For
8051
programming and verification, address is input on Port
RSTNPD 1 and Port pins 2.0-2.3. Pins P2,4 and P2.5 are held to a
t
Figure 217. External Reset
~
\7
TTL low (VIU. Data is input and output through Port
O. RST /VPD is held at a TTL high level (VIHO and
PSEN is held at TTL low level (VIU during program
and verify. To program, ALE/PROG is held at a TTL
low level (VIU. The programming supply voltage is
held at 21 V. The EA/VDD pin receives this program-
ming supply voltage. ALE/PROG is held at TTL high
Power Down (Standby) Operation of level (VIH) to verify the program. Port pin 2.7 forces
Internal RAM the Port 0 output drivers to the high impedance state
when held at a TTL high level and is held at a TTL low
Data can be maintained valid in the Internal Data RAM
level for verification. Erasure of an 8751 will leave the
while the remainder of the 8051 is powered down. When
EPROM programmed to an all one's (I's) state.
powered down, the 8051 consumes about 10070 of its
normal operating power. During normal operation,
Data is introduced by programming "O's" into the
both the epu and the internal RAM derive their power
desired bit locations. Although only "O's" will be pro-
from vee. However, the internal RAM will derive its
grammed, both "1's" and "O's" can be presented in the
power from RST /VPD when the voltage of vee is
d-ata word. The only way to change a "0" to a "1" is by
zero.
ultra-violet light erasure.
When a power-supply failure is imminent, the user's
system generates a "power-failure" signal to interrupt When EA/VDD is at 21 V, the 8751 is in the program-
the processor via INTO or INTI. This power-failure ming mode. It is necessary to put a capacitor between
signal must be early enough to allow the 8051 to save all EA/VDD and ground to block spurious voltage tran-
data that is relevant for recovery before vee falls sients. ALE/PROG receives the 50 msec, active low TTL
below its operating limit. The program servicing the program pulse when the address and data are stable. A
power-failure interrupt request may save any important program pulse must be applied at each address location
data and machine status into the Internal Data RAM. to be programmed. You can program any location at
The service program must also enable the backup power any time - either sequentially or at random.
2-17 AFN-01739A
A verify may be performed on the programmed bits to

ensure correct programming. Data is output on Port 0
when pin 2.7 is at a TTL low level (VIH). Pull-up
resistors must be provided on Port 0 pins during
verification. This verification mode can also be used to
check the 8051 's ROM pattern.
Table 2-11 describes the levels needed on the pins to pro-

gram and verify the 8751.
Table 211. Voltage Inputs for EPROM ProgrammingNerifying
~
MODE
VPD/RST PSEN PROG/ALE VDD/EA P24-26 P27
PROGRAM VIHI VIL VIH Vpp VIL VIL

VERIFY VIHI VIL VIL Vee VIL VIL (enable)
VIH (disable)
2-18 AFN-01739A
Ii~
II
'II'
II
CHAPTER 3
MEMORY ORGANIZATION, ADDRESSING MODES
AND INSTRUCTION SET
Chapter 3 is divided into these categories:
In the 8051 and 8751, the lower 4K of the 64K Program
Memory address space is filled by internal ROM and
Memory Organization EPROM, respectively. By tying the EA pin high, the
processor can be forced to fetch from the internal
Addressing Modes ROM/EPROM for Program Memory addresses 0
through 4K. Bus expansion for accessing Program
Instruction Set Memory beyond 4K is automatic, since external instruc-
tion fetches occur automatically when the Program
The first part, Memory Organization, describes the Counter increases above 4095. If the EA pin is tied low,
memory spaces of the 8051. The Addressing Modes sec- all Program Memory fetches are from external memory.
tion describes addressing techniques used to reach the The execution speed of the 8051 is the same, regardless
memory spaces. The final section explains the instruction of whether fetches are from internal or external Pro-
set, including functional groupings, opcodes and a soft- gram Memory. If all program storage is on-chip, byte
ware example. location 4095 should be left vacant to prevent an
undesired pre-fetch from external Program Memory ad-
MEMORY ORGANIZATION dress 4096.
In the 8051 family the memory is organized over three
address spaces and the program counter. The memory Certain locations in Program Memory are reserved for
spaces shown in Figure 3-1 are the: specific programs. Locations 0000 through 0002 are
reserved for the initialization program. Following reset,
16-bit Program Counter the CPU always begins execution at location 0000.
Locations 0003 through 0042 are reserved for the five
64K-byte Program Memory address space interrupt-request service programs.
64K-byte External Data Memory address space The 64K-byte External Data Memory address space is
automatically accessed when the MOVX instruction is
384-byte Internal Data Memory address space executed.
The 16-bit Program Counter register provides the 8051 Functionally, the Internal Data Memory is the most
with its 64K addressing capabilities. The Program flexible of the address spaces. The Internal Data
Counter allows the user to execute calls and branches to Memory space is subdivided into a 256-byte Internal
any locations within the Program Memory space. There Data RAM address space and a 128-byte Special Func-
are no instructions that permit program execution to tion Register address space. Within these address spaces
move from the Program Memory space to any of the are 256 individually addressable bits. Figure 3-2 shows
data memory spaces. the locations of the address spaces.
!
64K 64K
EXTE1RNAL OVERLAPPED SPACE
INTERNAL
409S -------Lml,----A--2S-S-----~Il
t I
____L-___ ~~-------~-
'___ 0:.'-_ _ _.... 12:1 12810..-----'
~----~,~-===:==~------_~
I 0
,10..-____--',
PROGRAM PROGRAM INTERNAL SPECIAL EXTERNAL
COUNTER MEMORY DATA RAM FUNCTION DATA
REGISTERS MEMORY
INTERNAL DATA MEMORY
Figure 3-1. 8051 Family Memory Organization
3-1 AFN-01739A
MEMORY, ADDRESSING, INSTRUCTION SET
The Internal Data RA~,,1 address space is 0 to 255. Four thf?m to he accessed as easily as internal RAM. As such,
banks of eight registers occupy locations 0 through 31. they can be operated on by most instructions. In addi-
The stack can be located anywhere in the Internal Data tion, 128 bit locations within the Special Function
RAM address space. In addition, 128 bit locations of Register address space can be accessed using Direct Ad-
the on-chip RAM are accessible through Direct Ad- dressing as shown in Figure 3-4. These bits reside in the
dressing. (See next section, Addressing Modes.) These Special Function Register address space and can be ac-
bits reside in Internal Data RAM at byte locations 32 cessed using Direct Addressing. The addressable bits are
through 47, as shown in Figure 3-3. Currently locations located at byte addresses divisible by eight. An easy way
o through 127 of the Internal Data RAM address space to determine which byte locations are bit addressable
are filled with on-chip RAM. Locations 128 through 255 are those byte locations ending in zero (0) or eight (8)
may be filled on later products without affecting ex- when represented in hexadecimal notation. The twenty
isting software. Special Function Registers are listed in Table 3-1. Their
mapping in the Special Function Register address space
The stack depth is limited only by the available Internal is shown in Figure 3-5.
Data RAM, thanks to an 8-bit reload able Stack Pointer.
The stack is used for storing the Program Counter dur- ADDRESSING MODES
ing subroutine calls, and may be used for passing
parameters. Any byte of Internal Data RAM or Special Since the MCS-51 architecture differentiates between
Data Memory and Program Memory, there are dif-
Function Register'S accessible through Direct Address-
ferent addressing modes for each. These are explained
ing can be pushed/popped.
below.
The Special Function Register address space is 128 to
a,) RAM Bit Addresses,
255. All registers except the Program Counter and the
RAM
four banks of eight working registers reside here. BYTE (MSB) (lSB)
Memory mapping the Special Function Registers allows 7FH l~-------'l
SPECIAL
FUNCTION
-
INTERNAL DATA RAM REGISTERS
( _ _A - - _ V_ _~ 2FH 7F 7E 70 7C 7B 7A 79 78 47
2EH 77 76 75 74 73 72 71 70 46
255 255 248 F8H'
255 FOH 2DH 6F 60 6C 6A 69 68 45
6E 6B
E8H
2CH 67 66 65 64 63 62 61 60 44
EOH
D8H 2BH SF 5E 50 5C 5B SA 59 58 43
DOH
ADDRESS- 2AH 57 56 55 54 53 52 51 50 42
C8H
ABLE
COH 29H 4F 4E 40 4C 4B 4A 49 48 41
BITS IN
B8H SFRs
BOH 28H 47 46 45 44 43 42 41 40 40
(128 BITS)
A8H 27H 3F 3E 3D 3C 3B 3A 39 38 39
AOH
26H 37 36 35 34 33 32 31 30 38
98H
90H 2C 2A 28 37
25H 2F 2E 20 2B 29
88H
128 135 128 80H 24H 27 26 25 24 23 22 21 20 36
128 ...127....:::.- 23H 1F 1E 10 1C 1B 1A 19 18 35
22H 17 16 15 14 13 12 11 10 34
ADORE SS- 48 21H OF DE 00 DC DB OA 09 08 33

ABLE 127 120
BITS IN 20H 07 06 05 04 03 02 01 00 32
RAM 31
7 0
(128BIT S) ;>E. lFH
R7 Bank 3
BANK 3
24 RO 18H 24
R7 17H 23
BANK 2
16 RO Bank 2
REGISTE RS -<
R7 10H 16
BANK 1
.!.. RO OFH 15
R7 Bank 1
BANKO
RO 08H
-'!..
07H
~ Bank 0
INTERNAL SPECIAL FUNCTION DOH
DATA RAM REGISTERS
Figure 32. Internal Data Memory Address Space Figure 33. RAM Bit Addresses
3-2 AFN-01739A ,
There are five general addressing modes operating on is appended to the instruction opcode to provide the
bytes. One of these five addressing modes, however, memory location address. The highest-order bit of this
operates on both bytes and bits. byte selects one of two groups of addresses: values be-
tween 0 and 127 (00H-7FH) access internal RAM loca-
Register Addressing tions, while values between 128 and 255 (80H-OFFH) ac-
Register addressing encodes, in the low-order three bits cess one of the Special Function Registers. In the
of the instruction opcode, the number of a register in assembly language, direct addresses are specified with
the currently enabled register bank. RSI (PSW.4) and the address of the variable or register, or a symbolic
RSO (PSW.3) determine which register bank is enabled. name defined earlier as a direct address. The instruction
In the MCS-51 assembly language, register addressing is set mnemonic for Direct Byte Addressing is "direct".
indicated by the register symbols RO through R7, or by a
symbolic name defined earlier as a register. The instruc- BIT OPERANDS
tion set mnemonic for Register Addressing is "Rn" Direct Bit addressing (bit) lets a number of instructions
where n can be any value from 0 to 7. manipulate or test any of 128 user-defined software
flags in internal data RAM, and manipulate or test 128
bits in the Special Functions Registers address space. An
Direct Addressing additional byte appended to the opcode specifies the
flag or bit to be accessed. Values between 0 and 127
BYTE OPERANDS
(00H-7FH) correspond to software flags in sixteen inter-
Direct Byte addressing specifies an on-chip RAM loca- nal RAM locations, addresses 20H-2FH. Bit addresses
tion or a Special Function Register. An additional byte 00H-07H correspond to bits 0-7 of RAM location 20H,
respectively; addresses 77H-7FH correspond to bits 0-7
of RAM location 2FH. Bit address values between 128
Table 31. Special Function Registers
~pecial Byte
Function ASM51 Location b.) Hardware Register Bit Addresses.
Register in Memory Direct Hardware
Bit Addresses
Symbolic Name !~:ress (MSB) (lSB) Register
Symbol
Accumulator*
Arithmetic B register*
ACC
B
224(EOH)
240(FOH)
240 F7 I F6 I F5 I F4 I F3 I F2 I F1 I FO
Registers Program Status PSW 208(DOH)

Word* 224 E7 I E6 I E5 I E4 I E3 I E2 I E1 I EO ACC
Stack Pointer SP 129(8IH)

Pointers Data Pointer DPH 131(83H)
208 07 I 06 I 05 I 04 I 03 I 02 I 01 I DO PSW
(high)
Data Pointer DPL 130(82H)
(low)
184 - I- I- I BC I BB I BA I B9 I B8 IP
Port 3* P3 I 76(BOH)
Parallel
I/O
Port
Port
2*
1*
P2
PI
160(AOH)
I 44(90H)
176 B7 I B6 I B5 I B4 I B3 I B2 I B1 I BO P3
Ports Port 0* PO 128(80H)
Interrupt Priority IPC 184(B8H)

168 AF I- I- I AC I AB I AA I A9 I A8 IE
Interrupt Control*
System Interrupt Enable IEC 168(A8H) 160 A7 I A6 I A5 I A4 I A3. I A2 I A1 I AO P2
Control*
Timer Mode TMOD 137(89H)

152 9F I 9E I 90 I 9C I 9B I 9A I 99 I 98 SCON
Timer Control* TCON 136(88H)

Timer I (high) THI 141(8DH) 144 97 I 96 I 95 I 94 I 93 I 92 I 91 1 90 P1
Timers Timer I (low) THO 139(8BH)
Timer 0 (high) THO 140(8CH)
Timer 0 (low) TLO 138(8AH) 136 8F I 8E I 80 I 8C I 8B I 8A I 89 I 88 TCON
Serial I/O Serial Control* SCON 152(98H)

Channel Serial Data SBUF 153(99H)
128 87 I 86 I 85 I 84 I 83 I 82 I 81 I 80 PO
Buffer
Figure 34. Special Function Register Bit Address
*Bit addressable byte location
33 AFN01739A
contents of RO or Rl, according to bit 0 of the instruc-

SYMBOLIC BYTE
ADDRESS BIT ADDRESS ADDRESS tion opcode. In the 8051 assembly language, indirect ad-
,-"--,~~ dressing is represented by a commercial "at" sign ("@")
preceding RO, Rl, or a symbol defined by the user to be
BF
B
~l~ (FOH) equal to RO or Rl. The instruction set mnemonic for
Register-Indirect Addressing uses the "at" ("@") also.
I
ACC A 224 (EOH)
231
Immediate Addressing
1
224
I
PSW 208 (DOH)
215
1I
208
IPC 184 (B8H) Immediate Addressing (#data) appends an additional
184 byte to the instruction to hold the source variable. In the
P3 191
183 176 1
176 (BOH)
8051 assembly language and the 8051 instruction set, a
IEC
~
1
1
175
168
1
168
I
1~
(A8H)
(AOH)
number sign (#) precedes the value to be used, which
may refer to a constant, an expression, or a symbolic
SFR's name. Since the value used is fixed at the time of ROM
'BU' !'" '" II'"

CONTAINING
(99H) DIRECT manufacture or EPROM programming, it may not be
ADDRESSABLE
SCON 152 (98H) BITS altered during program execution. (A special case of im-
P1 1159
152 144 (90H)
mediate addressing exists for the instruction MOV
DPTR, #dataI6. Two bytes following the opcode hold
m'~'"
(8DH) the 16 bits of data loaded into the data pointer.)
THO 140 (8CH)
TL1 139 (8BH) Figure 3-6 illustrates how the addressing modes reach
TLO 138 (8AH) different Internal Data Memory.
TMOD 1U (89H)
TCON 136 (88H)
DPH
DPL
SP
~
135 128
131
130
129
1U
(83H)
(82H)
(81H)
(80H)
~r-~
INTERNAL
DATA RAMI
STACK
255 255
SPECIAL
FUNCTION
REGISTERS
248 F8H
255 248 FOH
Figure 35. Special Function Registers Address 240 E8H
232
Space 224
EOH
D8H
216
DOH
208
C8H
200 DIRECT
and 255 (80H-OFFH) select bits in the special function 192
COH
AD~RESS-
registers; the high-order five-bit field of the address byte 184 B8H ING
176 BOH (BITS)
is the same as that of the register used, while the low 168 A8H
or&'r three bits give the bit position within that register. 160 AOH
The assembly language allows three representations for 152 98H

144 90H
a direct bit address: by the bit's sequential number 136 88H
(0-255), by specifying the register or RAM location 128 135 128 80H
which contains the bit, and the bit's position therein .....~
(e.g., 32.6), separated by a period (.) or by a symbol
previously defined as a direct bit address. The instruc- ~
DIRECT 127 120
tion set signifies a bit location by the mnemonic "bit". ADDRESSING
(BITS)
E 7 0
BaseRegisterPlus Index Register > R7
BANK 3
Indirect Addressing ..?! RO
R7
BANK2
Base-Register-plus Index Register-Indirect Addressing REGISTER ~ RO
ADDRESSING R7
simplifies accessing look-up tables (LUT) resident in BANK 1
~ RO
Program Memory. A byte may be accessed from an R7
BANKO
LUT via an indirect move from a location whose ad- ~ RO
dress is the sum of a base register (the DPTR or PC) and ~
~ DIRECT ADDRESSING
the index register (A).
STACK-POINTER REGISTER-INDIRECT AND
REGISTER-INDIRECT ADDRESSING
Registerlndirect Addressing
Figure 36. Internal Data Memory Addressing
Register-Indirect Addressing (@Ri) accesses a RAM
Modes
location whose address is determined by the current
3-4 AFN-01739A
Branch Destination Addressing Modes If both accumulators are accessed as memory locations
using Direct Addressing, different mnemonics are used.
Three program memory addressing modes are used by
"ACC" is the symbol for the byte accumulator and
conditional and unconditional branch operations. "CY" is the symbol for the bit accumulator.
RELATIVE ADDRESSING (rei) Even though there are two different addressing modes
Relative addressing (reI) encodes an 8-bit signed and a set of mnemonics for each accumulator, both ac-
displacement value in the last instruction byte. During cumulators have only one physical space on the chip.
execution, the CPU computes the destination address by
extending the sign-bit of this byte to 16 bits and adding When an I/O port or pin is the destination of a data
this value to the incremented program counter. In the move instruction, data is written into a corresponding
8051 assembly language, the programmer only needs to data latch. When an I/O port or pin is the source for a
specify the address or label assigned to the desired data transfer, or other two operand instructions, the
destination instruction. The assembler will compute the data present at the input pins is read.
signed displacement needed and produce an error
message if the destination is "out of range." Instructions which use the port as both a source and
destination (such as INC PI or ORL PI, #20H) read the
ABSOLUTE ADDRESSING (addr11) internal buffer rather than the input pins, so only the
Absolute Addressing (addr11) encodes the low-order 11 desired output latch bits will be affected.
bits of the destination address in three bits of the opcode
and the second instruction byte. The high-order five bits When an I/O pin is the destination of a SETB, CLR,
CPL, or MOV instruction, the on-chip data latch cor-
of the destination address are taken from the high-order
five bits of the incremented program counter. Note that responding to that pin is affected. When an I/O pin is
this means that an AJMP or ACALL instruction the source operand for a Boolean move or two-operand
located in addresses 07FEH, for example, will reach a instruction, the instruction reads the data present at the
destination between addresses 0800H and OFFFH. input pin. The CPL and JBC instructions read the inter-
nal buffer rather than the input pin state.
LONG ADDRESSING (addr16)
Since the parity flag (pSW.O) is updated after every in-
Long Addressing (addr16) uses the second and third struction cycle, instructions which explicitly alter the
byte of the instruction to hold the high-order and low- PSW or this bit will have no apparent effect on P, as if
order bytes of the 16-bit destination address, respective- PSW.O is a read-only bit. Bits 7, 6, and 5 of register
ly. The destination can be anywhere in the full 64 IPC, and bits 6 and 5 of register IEC are not im-
kilobyte program memory address space. plemented on the 8051 and are reserved.
In the MCS-51 assembly language, only the address or

label of the destination instruction is given in each case. INSTRUCTION SET OVERVIEW
The assembler computes the address encoding needed The MCS-51 instruction set includes 51 fundamental
by the operation mnemonic and produces an error operations broken into five functional groupings. Com-
message if the destination is "out of range."
bining them with various addressing modes for Boolean
(I-bit), nibble (4-bit), byte (8-bit), and address (I6-bit)
Special Addressing Considerations data types produces the III instructions listed in Table
If an indirect on-chip RAM or stack address is greater 3-2.
than the amount of RAM provided (e.g., greater than
127 on the 8051), or if no special function register cor- Each assembly language instruction consists of an
responds to a direct byte or bit address, then the result operation mnemonic and (depending on the operation)
of the instruction is undefined. up to four operands. The mnemonic abbreviates the
basic function or operation to be performed, while the
Note also that the two accumulators, the byte ac- operands, separated by commas, clarify which variables
cumulator and the bit accumulator, (the Boolean Pro- are involved, what data to use, or what instruction to
cessor) can be addressed in two ways using different execute next. Instructions which need two data
ASM-51 mnemonics. operands always specify the destination first, followed
by the source variable, except for the move operation
When using Register Addressing, the byte accumulator between two Directly addressable bytes. In this case the
may be reached using the "A" mnemonic, while the bit source operand is first and the destination operand is
accumulator may be reached using the "c" mnemonic. second.
3-5 AFN01739A
iable 32. 8051 InstiUction Set Summary

Interrupt Response Time: To finish execution of current in- Notes on instruction set and addressing modes:
struction, respond to the interrupt request, push the PC Rn - Register R7-RO of the currently selec.ted
and to vector to the first instruction of the interrupt service Register Bank.
program requires 38 to 81 oscillator periods (3 to 7,.,.s @ 12 data - 8-bit internal data location's address. This
MHz). could be an Internal Data RAM location
(0-127) or a SFR [i.e. 110 port, control
INSTRUCTIONS THAT AFFECT FLAG SETTINGS'
register, status register, etc. (128-255)].
@Ri - 8-bit internal data RAM location (0-255) ad-
INSTRUCTION FLAG INSTRUCTION FLAG
dressed indirectly through register RI or RO.
COY AC COY AC
#data - 8-bit constant included in instruction.
ADD X X X CLR C o #data 16 -16-bit constant included in instruction
ADDC X X X CPL C X
addrl6 -16-bit destination address. Used by LCALL &
SUBB X X X ANL C,bit X
LJMP. A branch can be anywhere within the
MUL o X ANL C,/bit X
64K-byte Program Memory address space.
DIY o X ORL C,bit X
addrll -II-bit destination address. Used by ACALL &
DA X ORL C,bit X
AJMP. The branch will be within the same
RRC X MOY C,bit X
2K-byte page of program memory as the first
RLC X CJNE X
byte of the following instruction.
SETB C I
reI - Signed (two's complement) 8-bit offset byte.
Used by SJMP and all conditional jumps.
Range is -128 to + 127 bytes relative to first
'Note that operations on SFR byte address 208 or bit ad-
byte of the following instruction.
dresses 209-215 (i.e. the PSW or bits in the PSW) will also
bit - Direct Addressed bit in Internal Data RAM or
affect flag settings.
Special Function Register.
- New operation not provided by 8048/8049.
ARITHMETIC OPERATIONS ARITHMETIC OPERATIONS Cont.
Oscillator Oscillator
Mnemonic Description Byte Period Mnemonic Description Byte Period
ADD A,Rn Add register to I 12 SUBB A,direct Subtract direct 2 12
Accumulator byte from Acc
ADD A,direct Add direct 2 12 with borrow
byte to SUBB A,@Ri Subtract 12
Accumulator indirect RAM
ADD A,@Ri Add indirect 12 from Acc with
Ram to borrow
Accumulator SUBB A,#data Subtract 2 12
ADD A,#data Add immediate 2 12 immediate data
data to from Acc with
Accumulator borrow
ADDC A,Rn Add register to 12 INC A Increment 12
Accumulator Accumulator
with Carry INC Rn Increment 12
ADDC A,direct Add direct 2 12 register
byte to INC direct Increment 2 12
Accumulator direct byte
with Carry INC @Ri Increme.nt 12
ADDC A,@Ri Add indirect 12 indirect RAM
RAM to DEC A Decrement 12
with Carry DEC Rn Decrement 12
ADDC A,#data Add immediate 2 12 Register
data to Acc DEC direct Decrement 2 12
with Carry direct byte
SUBB A,Rn Subtract 12 DEC @Ri Decrement 12
register from indirect RAM
Accwith
borrow All mnemonics copyrighted ,< Intel Corporation 1980
3-6 AFN-01739A
Table 32. Instruction Set Summary (continued)
DATA TRANSFER OAT A TRANSFER Cont.
MOV A,Rn Move register 1 12 MOVX @Ri,A Move Acc to 1 24
to External RAM
Accumulator (8-bit addr)
MOV A,direct Move direct 2 12 MOVX @DPTR,A Move Acc to 24
byte to External Ram
Accumulator (l6-bit addr)
MOV A,@Ri Move indirect 12 PUSH direct Push direct 2 24
RAM to byte onto stack
Accumulator POP direct Pop direct byte 2 24
MOV A,#data Move 2 12 from stack
immediate data XCH A,Rn Exchange 12
to register with
MOV Rn,A Move 12 XCH A,direct Exchange 2 12
Accumulator direct byte
to register with
MOV Rn,direct Move direct 2 24 Accumulator
byte to register XCH A,@Ri Exchange 12
MOV Rn,#data Move 2 12 indirect RAM
immediate data with
to register Accumulator
MOV direct,A Move 2 12 XCHD A,@Ri Exchange low- 12
Accumulator order Digit
to direct byte indirect RAM
MOV direct,Rn Move register 2 24 with Acc
to direct byte
MOV direct,direct Move direct 24
byte to direct
MOV direct,@Ri Move indirect 2 24
RAM to direct
byte
MOV direct,#data Move 24
immediate data
to direct byte
MOV @Ri,A Move 12
Accumulator
to indirect
RAM
MOV @Ri,direct Move direct 2 24
byte to indirect
RAM
MOV @Ri,#data Move 2 12
immediate data
to indirect
RAM
MOV DPTR,#dataI6 Load Data 24
Pointer with a
16-bit constant
MOVC A,@A+DPTR Move Code 24
byte relative to
DPTR to Acc
MOVe A,@A+PC Move Code 24
byte relative to
PC and Acc
MOVX A,@Ri Move External 24
RAM (8-bit
addr) to Acc
MOVX A,@DPTR Move External 24
RAM (16-bit
addr) to Acc
All mnemonics copyrighted Intel Corporation 1980
3-8 AFN-01739A
Table 32. Instruction Set Summary (continued)
BOOLEAN VARIABLE MANIPULATION PROGRAM BRANCHING Cont.

CLR C Clear Carry 1 12 JNZ rei Jump if 2 24
CLR bit Clear direct bit 2 12 Accumulator is
SETB C Set Carry 1 12 Not Zero
SETB bit Set direct bit 2 12 CJNE A,direct,rel Compare direct 24
CPL C Complement 1 12 byte to Acc
Carry and Jump if
CPL bit Complement 2 12 Not Equal
direct bit CJNE A,#data,rel Comare 3 24
ANL C,bit AND direct bit 2 24 immediate to
to Carry Acc and Jump
ANL C,/bit AND 2 24 if Not Equal
complement of CJNE RN ,#data,rel Compare 24
direct bit to immediate to
Carry register and
ORL C,bit OR direct bit 2 24 Jump if Not
to Carry Equal
ORL C,/bit OR 2 24 CJNE @Ri,#data,rel Compare 24
complement of immediate to
direct bit to indirect and
Carry Jump if Not
MOY C,bit Move direct bit 2 12 Equal
to Carry DJNZ Rn,rel Decrement 3 24
MOY bit,C Move Carry to 2 24 register and
direct bit Jump if Not
JC rei Jump if Carry 2 Zero
is set DJNZ direct,rel Decrement 3 24
JNC rei Jump if Carry 2 24 direct byte and
not set Jump if Not
JB bit,rel Jump if direct 24 Zero
Bit is set NOP No Operation 12
JNB bit,rel Jump if direct 24
Bit is Not set
JBC bit,rel Jump if direct 3 24
Bit is set &
clear bit
PROGRAMING BRANCHING
Oscillator
Mnemonic Description Byte Period
ACALL addrll Absolute 2 24
Subroutine
Call
LCALL addr16 Long 24
Subroutine
Call
RET Return for 24
Subroutine
RETI Return for 24
interrupt
AJMP addrl1 Absolute Jump 2 24
LJMP addr16 Long Jump 3 24
SJMP rel Short Jump 2 24
(relative addr)
JMP @A+DPTR Jump indirect 24
relative to the
DPTR
JZ rel Jump if 2 24
Accumulator is
Zero
3-9 AFN-01739A
Functional Groupings than the second operand; otherwise it is cleared. A sum-

mary of the two-operand add/subtract operations is
The five functional groupings are as follows:
shown in Figure 3-7.
ARITHMETIC OPERATIONS There are three arithmetic operations that operate ex-
clusively on the A register (the accumulator). These are the
The 8051 implements the arithmetic operations of add, in-
decimal-adjust for BCD addition and the two-test condi-
crement, decrement, compare-to-zero, decrement-and-
tions shown in Figure 3-8. The decimal-adjust operation
compare-to-zero, decimal-add-adjust, subtract-with-
converts the result from a binary addition of two two-digit
borrow, compare, multiply and divide.
BCD values to yield the correct two-digit BCD result. Dur-
ing this operation the auxiliary-carry flag helps effect the
Only unsigned binary integer arithmetic is performed in
proper adjustment. Conditional branches may be taken
the Arithmetic/Logic Unit. In the two-operand opera-
based on the value in the accumulator being zero or not
tions of add, add-with-carry and subtract-with-borrow
zero.
the A register (the accumulator) is the first operand and
receives the result of the operation. The second operand
can be an immediate byte, a register in the selected Register The 8051 simplifies the implementation of software
counters since the increment and decrement operations
Bank, a Register-Indirect Addressed byte or a Direct Ad-
can be performed on the accumulator, a register in the
dressed byte. These instructions affect the overflow (OV),
carry (C), auxiliary-carry (AC), and parity (P) flags in the selected Register Bank, Register-Indirect Addressed byte
in the Internal Data RAM or a byte in the Direct Ad-
Program Status Word (PSW). The carry flag facilitates
nonsigned integer arithmetic and multi-precision rota- dressed Internal Data RAM or Special Function
tions. Handling two's-complement-integer (signed) addi- Register. The 16-bit Data Pointer can be incremented.
tion and subtraction can easily be accommodated with For efficient loop control, the decrement-and-jump-if-
software's monitoring of the PSW's overflow flag. The not-zero operation is provided. This operation can
auxiliary-carry flag simplifies BCD arithmetic. An opera- decrement a register in the selected Register Bank, any
tion that has an arithmetic aspect similar to a subtract is Special Function Register or any byte of Internal Data
the compare-and-jump-if-not-equal operation. This RAM accessible through Direct Addressing, and force a
operation performs a conditional branch if a register in the branch if the result is not zero. The increment/ decre-
selected Register Bank, or a Register-Indirect Addressed ment operations are summarized in Figure 3-9.
byte of Internal Data RAM, does not equal an immediate
value; or ifthe A register does not equal a byte in the Direct The multiply operation multiplies the one-byte A register
Addressable Internal Data RAM, or a Special Function by the one-byte B register and returns a double-byte result
Register. While the destination operand is not updated
and neither source operand is affected by the compare
operation, the carry flag is set if the first operand is less . Declmal-AddAdjust
Jump.If.A.ls.Zero
Jumplf-Als-NotZero
I REG~TER
I
Add
Figure 38. Internal Data Memory Arithmetic
Add-WlthCarry Operations (Register A Specific)
SubtractWlth-Borrow
Compare-And-JumplfNotEqual ( )
DIRECT Increment (INC)

Data Decrement (DEC)
DecrementAndJumplf-NotZero
(DJNZ)
DIRECT REGISTER
Data DPTR
(INC, DEC, DJNZ) (INC)
REGISTER
A
REGISTER INDIRECT (INC, DEC)
@R1,@RO
REGISTER REGISTER-INDIRECT
R7-RO @R1,@RO
Figure 37. Internal Data Memory Arithmetic (INC, DEC, DJNZ) (INC, DEC)
Operations
Operations
3-10 AFN-01739A
(MSB in B, LSB in A). The divide operation divides the

one-byte accumulator by the one-byte B register and And (ANL)
Or (ORL)
returns a byte quotient to the A register and a byte re- Exclusive-or (XRL)
mainder to the B register. These are shown in Figure 3-10.
Divide
Multiply ~ REGISTER
AlB
!I REGISTER I
Operations (Register A with
Register B)
IMMEDIATE
# data
LOGIC OPERATIONS
The 8051 permits the logic operations of and, or, and Figure 311.lnternal Data Memory Logic Operations
exclusive-or to be performed on the A register by a second
operand which can be an immediate value, a register in the
selected Register Bank, a Register-Indirect Addressed

Clear
Complement
Rotate-Left
I REGIASTER J
byte of Internal Data RAM or a Direct Addressed byte of Rotate-Left-Through-Carry
Internal Data RAM or Special Function Register. In addi- Rotate-Right
Rotate-Rlght-Through-Carry
tion, these logic operations can be performed on a Direct Swap-Nibbles (Rotate Lelt Four)
Addressed byte of the Internal Data RAM or Special
Function Register using the A Register as the second Figure 312. Internal Data Memory Logic Operations
operand. Also, use of Immediate Addressing with Direct (Register A Specific)
Addressing permits these logic operations to set, clear or
complement any bit anywhere in the Internal Data RAM
or Special Function Registers without affecting the PSW, REGISTER
Register Bank registers or accumulator. When one takes Set (SETB) C
Clear (CLR) (SETB,
into account that the registers R7-RO and the accumulator Complement (CPL) CLR, CPL)
Jump-II-Blt-Set-Then-Clear-BIt (JBC)
can be Direct Addressed, the two-operand logic opera-
tions allow the destination (first operand) to be a byte in
Figure 313. Internal Data Memory Logic Operations
the Internal Data RAM, a Special Function Register,
(BitSpecific)
Register Bank registers (R7 -RO) or the accumulator, while
the choice of the second operand can be any of the
aforementioned or an immediate value. The 8051 can also
perform a logical or, or a logical and, between the Boolean
accumulator (i.e., the carry register) and any bit, or its DATA TRANSFER OPERATIONS
complement, that can be accessed through Direct Ad- Look-up tables resident in Program Memory can be ac-
dressing. The and, or, and exclusive-or logic operations cessed by indirect moves. A byte constant can be trans-
are summarized in Figure 3-11. ferred to the A register (i.e., accumulator) from the Pro-
gram Memory location whose address is the sum of a base
In addition to the logic operations that are performed on register (the PC or DPTR) and the index register ,A). This
Internal Data Memory as shown in Figure 3-11, there are provides a convenient means for programming transla-
also logic operations that are performed specifically on tion algorithms such as ASCII to seven segment conver-
the accumulator. These are summarized in Figure 3-12. sions. The Program Memory move operations are shown
diagrammatically in Figure 3-14.
In addition to the "and" and "or" bit logicals shown in
Figure 3-11, there are logicals that can operate exclusively A byte location within a 256-byte block of External Data
on a Direct Addressed bit. These operations are listed in Memory can be accessed using Rl or RO in Register-
Figure 3-13. The carry flag is also addressed as a register Indirect Addressing. Any location within the fu1l64K Ex-
and can be set, cleared, or complemented with one-byte ternal Data Memory address space can be accessed
instructions. through Register-Indirect Addressing using a 16-bit base
3-11 AFN-01739A
BOOLEAN VARIABLE OPERAT!ONS
REGISTER
A powerful set of instructions perform data transfer, con-
A ditional and logical operations on Boolean (i-bit)
variables. The 8051 's Boolean Processor can move any of
256 bits to or from the carry register (C) using Direct Ad-
dressing. Individual instructions will set, clear, or comple-
ment these 256 addressable bits or the carry register with
BASE-REGISTER- PLUS
BASE-REGISTER- PLUS
INDEX-REGISTER-INDIRECT INDEX-REGISTER-INDIRECT
Direct Addressing. In conjunction with the bit-test in-
@PC+A @DPTR+A structions described below, these instructions provide
(PROG MEM D-64K) (PROG MEM 0-64K)
direct 8051 code for logic equations and Boolean expres-
sions.
Figure 314. Program Memory Move Operations
The carry register is a "Boolean Accumulator" for logical
"and" or logical "or" operations on Boolean variables.
The carry register acts as a source operand and the
destination for the logical operations. The source
REGISTER operand can be one of the 256 addressable bits or its
A
complement.
The 8051 also provides test operations of jump-if-bit-set,

jump-if-bit-not-set and jump-if-bit-set-then-clear. These
REGISTER-INDIRECT REGISTER-INDIRECT branching instructions are relative to the address of the
@R1,@RO
(EXT DATA 0-255)
@DP
(EXT DATA 0-64K)
next instruction (PC + 127 to PC - 128). Jumps can also
betaken on the status of the Carry register. Ajump can be
taken if the carry is set or not set.
Figure 315. External Data Memory Move

Operations
register (i. e., the Data Pointer). These moves are shown in
CONTROL TRANSFER
Figure 3-15. The 8051 has a non-paged Program Memory to accom-
modate relocatable code. The advantage of a non-paged
The byte in-code-constant (immediate) moves and byte memory is that a minor change to a program that causes a
variable moves within the 8051 are highly orthogonal as shift of the code's position in memory will not cause page
detailed in Figure 3-16. When one considers that the ac- boundary readjustments to be necessary. This also makes
cumulator and the registers in the Register Banks can be relocation possible. Relocation is desirable since it permits
Direct Addressed, the two-operand data transfer opera- several programmers to write relocatable modules in
tions allow a byte to be moved between any two of the various assembly and high-level languages which can later
Register Bank registers, Internal Data RAM, ac- be linked together to form the machine-object code.
cumulator and Special Function Registers. Also, im-
mediate operands can be moved to any ofthese locations. Sixteen-bit jumps and calls are provided to allow branch-
Of particular interest is the Direct Address to Direct Ad- ing to any location in the contiguous 64K Program
dress move which permits the value in a port to be moved Memory address space and pre-empt the need for Pro-
to the Internal Data RAM without using any Register gram Memory bank switching. Eleven-bit jumps and calls
Bank registers or the accumulator. The Data Pointer are also provided to maintain compatibility with the 8048
register can be loaded with a double-byte immediate and to provide an efficient jump within a 2K program
value. module. Unlike the 8048, the 8051 's call operations do not
push the Program Status Word (PSW) to the stack along
The A Register can be exchanged with a register in the with the Program Counter, since many subroutines writ-
selected Register Bank, with a Register-Indirect Addressed ten for the 8051 do not affect the PSW. Hence the 8051
byte in the Internal Data RAM, or with a Direct Addressed return operations pop only the Program Counter. The
byte in the Internal Data RAM, or Special Function 8051 's branch, call and return operations are shown
Register. The least significant nibble of the A register can diagrammatically in Figures 3-18,3-19, and 3-20, respec-
also be exchanged with the least significant nibble of a tively.
Register-Indirect Addressed byte in the Internal Data
RAM. The exchange operation is shown in Figure 3-17. The 8051 also provides a method for performing condi-
3-12 AFN-01739A
REGISTER REGISTER
C DPTR
16
REGISTER
R7-RO
IMMEDIATE
# dete
REGISTER REGISTER-INDIRECT REGISTER-INDIRECT

A @R1.@RO @SP
Figure 316. Internal Data Memory Move Operations
REGISTER DIRECT
R7-RO Dala
SP is pre-incremented.
REGISTER
A
4 LOW
REGISTER-INDIRECT NIBBLE
@R1.@RO
SP is pre-incremented.
Figure 317. Internal Data Memory Exchange Figure 319. Call Operations
Operations
REG~~TER 1..........-"--"'1/<-16----;1 REGIST':~~~DIRECT 1

REGplSCTER ~""""_-I-I,--
_ 7 16 _ _~_IM_M_E_D_IA_TE--,
_ Addr16
SP is post-decremented.
Figure 320. Return Operations
Figure 318. Unconditional Branch Operations
313 AFN-01739A
tional and unconditional hranching, relative to the start- Auxiliary Carry: The auxiliary-carry flag (AC) is set if an
ing address of the next instruction (PC + 127 to PC - arithmetic instruction results in a carry-out of bit 3 (from
128). The accumulator test operations allow a conditional addition) or a borrow into bit 3 (for subtraction); other-
branch based on the accumulator being zero or non-zero. wise it is cleared. This flag is useful for BCD arithmetic.
Also provided are compare-and-jump-if-not-equal and
Overflow: The overflow flag (OV) is set if the addition or
decrement-and-jump-if-not-zero. These are shown in
subtraction of signed variables produces an overflow er-
Figure 3-21. The register-indirect jump in the 8051 permits
ror (i.e., if the magnitude of the sum or difference is too
branching relative to a base register (DPTR) with an offset
great for the seven magnitude bits in two's complement
provided by the non-signed integer value in the index
representation); otherwise it is cleared. The same flag also
register (A). This accommodates N-way branching. The
indicates when the product resulting from multiplication
indirect jump is shown in Figure 3-22.
overflows one byte, and if division by zero was attempted.
parity: The parity flag (P) is updated after every instruc-
Short Jump Jump-II-A-Zero
Jump-II-Bit-Set Jump-II-A-Not-Zero tion cycle to indicate the parity of the accumulator. It is set
Jump-II-Bit-Not-Set Decrement-And-Jump-II-Not-Zero
Jump-II-Bit-Set-Then-Clear-Bit Compare-And-Jump-II-Not-Equal if the number of"1" bits in the accumulator is odd, other-
wise, it is cleared.
The other four PSW bits consist of a general purpose flag,

FO, two bits, RS1 and RSO, which select one offour work-
ing register banks, and a reserved bit location.
Instruction Definitions
The rest of this chapter defines all the instructions and
operations which the MCS-51 CPU can perform. There is
Figure 321. Unconditional Short Branch and a separate section for each of the 51 basic operations,
Conditional Branch Operations ordered alphabetically according to the operation
mnemonic.
When an operation may apply to more than one data type

(generally bit and byte data), the MCS-51 assembly
language uses the same mnemonic for each, reducing the
number of mnemonics the programmer must remember.
The assembler determines which instruction is ap-
propriate from the operands specified. Thus, the
mnemonic "CLR" can operate on the eight-bit ac-
cumulator ("CLR A"), or on one-bit variables ("CLR
FO"). The mnemonics ANL, ORL, CPL, and MOV can
Figure 322. Unconditional Branch (Indirect) relate to more than one data type as well. These operations
Operation present each data type in a separate section.
Each section then describes the action taken by the opera-

Arithmetic Flags tion, the flags and registers affected, and shows a short ex-
The program status word (PSW) contains eight bits. Four ample of how an instruction might be used in a program.
bits are hardware status flags set or cleared by the CPU to Next comes the number of bytes and machine cycles re-
show the result of certain calculations. In general, these quired, the corresponding binary machine-language en-
flags are used for the following purposes: coding, and a symbolic description or restatement of the
function implemented.
Carry: The carry flag (CY) is set by an arithmetic instruc-
tion ifthere is a carry-out of the highest order bit (from ad- Note: Only the carry, auxiliary-carry, and overflow flags
dition) or if a borrow is needed for the highest-order bit are discussed in these instruction descriptions. Since the
(from subtraction or a comparison); otherwise it is parity bit (PSW _0) is recomputed after every instruction
cleared. It is also affected by several rotate operations. cycle any instruction that alters the accumulator - either
The carry flag is also the Boolean accumulator. When inherently or as a special function register - could affect
treated as a Boolean accumulator, the carry mnemonic is the parity flag. Similarly, instructions which alter directly
"C"; otherwise it is CY which denotes an address. addressed registers could affect the other status flags if the
314 AFN-01739A
instruction is applied to the PSW. Status flags can also be are allowed, and gives the assembly language notation,
modified by the generalized bit-manipulation instruc- byte and cycle counts, encoding format, and a symbolic
tions. description for each.
Nineteen operations allow more than one addressing The information in this chapter is directed towards defin-
mode for the source and/or destination operand. The ing the capabilities of the MCS-Sl architecture and hard-
headings for these sections show the instruction format ware. For details on the assembly language or ASMSI
with such operands enclosed in angle brackets (for exam- capabilities refer to the MeS-51 Macro Assembler User's
ple, MOV <dest-byte> , <src-byte. The operation Guide, publication number 9800937.
description tells what modes (or combinations of modes)
ACAll addr11
Function: Absolute Call

Description: ACALL unconditionally calls a subroutine located at the indicated address. Theinstruction increments
the PC twice to obtain the address of the following instruction, then pushes the 16-bit result onto the
stack (low-order byte first) and increments the stack pointer twice. The destination address is obtained
by successively concatenating the five high-order bits of the incremented PC, opcode bits 7-S, and the
second byte of the instruction. The subroutine called must therefore start within the same 2K block of
the program memory as the first byte of the instruction following ACALL. No flags are affected.
Example: Initially SP equals 07H. The label "SUBRTN" is at program memory location 034SH. After executing
the instruction,
ACALL SUBRTN
at location OI23H, SP will contain 09H, internal RAM locations 08H and 09H will contain 2SH and
01 H, respectively, and the PC will contain 034SH.
Bytes: 2
Cycles: 2
Encoding: I alO a9 a8 I I 0 0 0 I I Ia7 a6 as a4 I

a3 a2 al aO
Operation: ACALL
(PC) ~ (PC) + 2
(SP) .-(SP) + I
SP,,-( PC 7-0)
(SP) .--(SP) + I
SP..-(PC IS-8)
(PC I 0-0) ~ page address
315 AFN-Q1739A
A "ft A ... _ .. _ ........ _ ....

KUU K,... ;:'''-uyU......
Function: Add
Description: ADD adds the byte variable indicated to the accumulator, leaving the result in the accumulator. The
carry and auxiliary-carry flags are set, respectively, if there is a carry-out from bit 7 or bit 3, and cleared
otherwise. When adding unsigned integers, the carry flag indicates an overflow occurred.
OV is set if there is a carry-out ofbit6 Qut not out of bit 7, or a carry-out of bit 7 but not bit6; otherwise
OV is cleared. When adding signed integers, OV indicates a negative number produced as the sum of
two positive operands, or a positive sum from two negative operands.
Four source operand addressing modes are allowed: register, direct, register-indirect, or immediate.
Example: The accumulator holds OC3H (l1000011B) and register 0 holds OAAH (10101OIOB). The instruction,
ADD A,RO
will leave 6DH (0110 1101 B) in the accumulator with the AC flag cleared and both the carry flag and OV
set to 1.
ADD A,Rn
Bytes:
Cycles:
Encoding:
1
0 0 01 1 r r r I
Operation: ADD
(A).-(A) + (Rn)
ADD A,direct
Bytes: 2
Cycles: 1
Encoding:
1
0 0 01 0 1 0 11 1 direct address I
Operation: ADD
(A).-(A) + (direct)
ADD A,@Ri
Bytes:
Cycles:
Encoding: 10 0 01 0
Operation: ADD
(A)-+- (A) + Ri
ADD A,#data
Bytes: 2
Cycles: 1
Encoding:
1
0 0 01 0 1 0 01 I immediate data I
Operation: ADD
(A)04- (A) + #data
3-16 AFN-01739A
ADDC A, < srcbyte>
Function: Add with Carry

Description: ADDC simultaneously adds the byte variable indicated, the carry flag and the accumulator contents,
leaving the result in the accumulator. The carry and auxiliary-carry flags are set, respectively, if there is
a carry-out from bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag in-
dicates an overflow occurred.
OV is set if there is a carry-out of bit 6 but not out of bit 7, or acarryout of bit 7 but notoutofbit6; other-
wise OV is cleared. When adding signed integers, OV indicates a negative number produced as the sum
of two positive operands or a positive sum from two negative operands.
Four source operand addressing modes are allowed: register, direct, register-indirect, or immediate.
Example: The accumulator hoidsOC3H (llOOOOllB) and register 0 hoidsOAAH (lOlOlOlOB) with the carry flag
set. The instruction,
ADDC A,RO
will leave6EH (01 1011 lOB) in the accumulator with ACcleared and both the carry flag and OV set to 1.
ADDC A,Rn
Bytes:
Cycles:
Encoding: I0 0 1 111 r r r
Operation: ADDC
(A)~(A) + (C) + (Rn)
ADDC A,direct
Bytes: 2
Cycles:
Encoding: I 0 0 1 1 0I 1 0 1 I direct address I

Operation: ADDC
(A)~(A) + (C) + (direct)
ADDC A,@Ri
Bytes:
Cycles:
Encoding: 1 0 01 110
Operation: AD DC
(A)-+-(A) + (C) + Rm
ADDC A,#data
Bytes: 2
Cycles: 1
Encoding: I0 0 1 I
1 0 1 0 0 I Iimmediate data I
Operation: AD DC
(A)~ (A) + (C) + #data
3-17 AFN-01739A
A ..UID
"",,'W.I .. """".0101
I.
u. ........
Function: Absolute Jump

Description: AJMP transfers program execution to the indicated address, which is formed at run-time by con-
catenating the high-order five bits of the PC (after incrementing the PC twice), opcode bits 7-5, and
the second byte of the instruction. The destination must therefore be within the same 2K block of
program memory as the first byte of the instruction following AJMP.
Example: The label "JMPADR" is at program memory location OI23H. The instruction,
AJMP JMPADR
is at location 0345H and will load the PC with OI23H.
Bytes: 2
Cycles: 2
Encoding: I a10 a9 a8 0 I 0 0 0 Ia7 a6 a5 a41 a3 a2 al aO
Operation: AJMP
(PC)..-(PC) +2
(PC I 0-0) ~ page address
AN L <dest-byte> , <src-byte>
Function: Logical-AND for byte variables

Description: ANL performs the bitwise logical-AND operation between the variables indicated and stores the
results in the destination variable. No flags are affected.
The two operands allow six addressing mode combinations. When the destination is the ac-
cumulator, the source can use register, direct, register-indirect, or immediate addressing; when the
destination is a direct address, the source can be the accumulator or immediate data.
Note: When this instruction is used to modify an output port, the value used as the original port
data will be read from the output data latch, not the input pins.
Example: If the accumulator holds OC3H (l1OOOOIIB) and register 0 holds OAAH (1010101OB) then the in-
struction,
ANL A,RO
will leave 4lH (01OOOOOlB) in the accumulator.
When the destination is a directly addressed byte, this instruction will clear combinations of bits in
any RAM location or hardware register. The mask byte determining the pattern of bits to be cleared
would either be a constant contained in the instruction or a value computed in the accumulator at
run-time. The instruction,
ANL PI ,#01110011 B
will clear bits 7, 3, and 2 of output port 1.
ANL A,Rn
Bytes:
Cycles:
Encoding: 0 r r r
1
Operation: ANL
(A) .... (A) A (Rn)
3-18 AFN-01739A
ANL A,direct
Bytes: 2
Cycles:
Encoding:
Operation:
1
ANL
1 10 1
11
direct address
(A)'--(A) 1\ (direct)
ANL A,@Ri
Bytes:
Cycles:
Encoding:
1 1 10 i I
Operation: ANL
(A) .... (A) 1\ Ri
ANL A,#data
Bytes: 2
Cycles:
Encoding: 1....0 1 .....1_0.......1_0__0....1

_ _ _0__ I immediate data I
Operation: ANL
(A)~ (A) 1\ #data
AN L direct,A
Bytes: 2
Cycles:
Encoding: I-I_o__o__I...I_o_o__I_o.....J
Operation: ANL
(direct) .... (direct) 1\ (A)
AN L direct,#data
Bytes: 3
Cycles: 2
Encoding: 1-10___0__1....1____1 _.....J I immediate data "
Operation: ANL
(direct) .... (direct) 1\ #data
3-19 AFN,01739A
Function: Logical-AND for bit variables

Description:
If the Boolean value of the source bit is a logical then clear the carry flag; otherwise leave the carry
flag in its current state. A slash ("I") preceding the operand in the assembly language indicates that
the logical complement of the addressed bit is used as the source value, but the source bit itself is not
affected. No other flags are affected.
Only direct bit addressing is allowed for the source operand.
Example: Set the carry flag if, and only if, Pl.O = 1, ACe. 7 = 1, and OV = 0:
MOV C,Pl.O ;LOAD CARRY WITH INPUT PIN STATE
ANL C,ACe.7 ;AND CARRY WITH ACCUM. BIT 7
ANL C,/OV ;AND WITH INVERSE OF OVERFLOW FLAG
ANL C,bit
Bytes: 2
Cycles: 2
1 1 I
Encoding: 11
Operation: ANL
(C)~ (C) /\ (bit)
ANL C,/bit
Bytes: 2
Cycles: 2
En~oding: 11-_1_0___
1 ..&.1_0_0_0__
0-, ( bit address I
Operation: ANL
(C).- (C) .., (bit)
3-20 AFN-01739A
CJNE <destbyte>,<srcbyte>,rel
Function: Compare and Jump if Not Equal.

Description: CJNE compares the magnitudes of the first two operands, and branches if their values are not
equal. The branch destination is computed by adding the signed relative-displacement in the last in-
struction byte to the PC, after incrementing the PC to the start of the next instruction. The carry
flag is set if the unsigned integer value of <dest-byte> is less than the unsigned integer value of <src-
byte>; otherwise, the carry is cleared. Neither operand is affected.
The first two operands allow four addressing mode combinations: the accumulator may be com-
pared with any directly addressed byte or immediate data, and any indirect RAM location or work-
ing register can be compared with an immediate constant.
Example: The accumulator contains 34H. Register 7 contains 56H. The first instruction in the sequence,
CJNE R7,#60H, NOT_EQ
R7 = 60H.
NOT_EQ: JC IF R7<60H.
R7>60H.
sets the carry flag and branches to the instruction at label NOT_EQ. By testing the carry flag, this
instruction determines whether R7 is greater or less than 60H.
If the data being presented to port 1 is also 34H, then the instruction,
WAIT: CJNE A,P1,WAIT
clears the carry flag and continues with the next instruction in sequence, since the accumulator does
equal the data read from PI. (If some other value was being input on PI, the program will loop at
this point until the PI data changes to 34H.)
CJ N E A,direct,rel
Bytes: 3
Cycles: 2
Encoding: 1~1_0___1....LI_o__l_0_1--1 Idirect address rel. address I

Operation: CJNE
(PC)~(PC) +3
IF (direct) < (A)
THEN (PC)~(PC) + rei and (C)'-O
OR
IF (direct) > (A)
THEN (PC)~(PC) + reI and (C).-1
CJNE A,#data,rel
Bytes: 3
Cycles: 2
Encoding: 1_1_o
.... ___1.....1_o__
1 _0_0_1 I immediate data I I rel. address
Operation: CJNE
(PC) -+- (PC) + 3
IF #data < (A)
THEN (PC) ~(PC) + reI and (C)~
OR
IF #data > (A)
THEN (PC) '--(PC) + reI and (C)1-1
3-21 AFN-01739A
CJ N E Rn,#data,re!
Bytes: 3
Cycles: 2
Encoding: LI_l_o_ _ _l...1.l_l_r_r__

r--, I immediate data I rei. address I
Operation: CJNE
(PC) "--(PC) + 3
IF #data < (Rn)
THEN (PC) ~(PC) + rei and (C)..-O
OR
IF #data > (Rn)
THEN (PC)~(PC) + rei and (C)..-1
CJNE @Ri,#data,rel
Bytes: 3
Cycles: 2
Encoding: ,-1_1_o__11-10_ _ _1--,'1 Iimmediate data I I rei. address 1
Operation: CJNE
(PC)..-(PC) + 3
IF #data < Ri
THEN (PC~(PC) + rei and (C)..-1
OR
IF #data > Ri
THEN (PC)~(PC) + rei and (C).-O
CLR A
Function: Clear Accumulator

Description: The accumulator is cleared (all bits set to zero). No flags are affected.
Example: The accumulator contains 5CH (01011100B). The instruction,
CLR A
will leave the accumulator set to OOH (OOOOOOOOB).
Bytes: 1
Cycles: 1
Encoding: LI_l_ _ _ _
0...l.1_0_l__
0_0--'
Operation: CLR
(A)~O
3-22 AFN01739A
CLR bit
Function: Clear bit

Description: The indicated bit is cleared (reset to zero). No other flags are affected. CLR can operate on the carry flag
or any directly addressable bit.
Example: Port 1 has previously been written with 5DH (010111OIB). The instruction,
CLR P1.2
will leave the port set to 59H (OlOllOOIB).
CLR C
Bytes:
Cycles:
Encoding: 11 0 01 0 0 1 1 I
Operation: CLR
(C)..-O
CLR bit
Bytes: 2
Cycles:
Encoding: 11 0 01 0 0 1 01
Operation: CLR
(bit)..-O
CPL A
Function: Complement Accumulator

Description: Each bit of the accumulator is logically complemented (one's complement). Bits which previously
contained a one are changed to zero and vice-versa. No flags are affected.
Example: The accumulator contains 5CH (OlOlllOOB). The instruction,
CPL A
will leave the accumulator set to OA3H (lOlOOOllB).
Bytes: 1
Cycles:
Encoding: L-I_l_ _ _1--,-1_o_1_0__

0-,
Operation: CPL
(A)~ -, (A)
3-23
CPL bit
Function: Complement bit

Description: The bit variable specified is complemented. A bit which had been a one is changed to zero and vice-
versa. No other flags are affected. CLR can operate on the carry or any directly addressable bit.
Note: When this instruction is used to modify an output pin, the value used as the original data will
be read from the output data latch, not the input pin.
Example: Port 1 has previously been written with 5BH (01011101B). The instruction sequence,
CPL P1.1
CPL P1.2
will leave the port set to 5BH (0101101IB).
CPL C
Bytes:
Cycles:
Encoding: 11 0 I
1 0 0 1 11
Operation: CPL
(C~ , (C)
CPL bit
Bytes: 2
Cycles: 1
Encoding: 11 0 I
1 0 0 1 01 bit address
Operation: CPL
(bit)..... , (bit)
DA A
Function: Decimal-adjust Accumulator for Addition

Description: DA A adjusts the eight-bit value in the accumulator resulting from the earlier addition of two
variables (each in packed-BCD format), producing two four-bit digits. Any ADD or ADDC instruc-
tion may have been used to perform the addition.
If accumulator bits 3-0 are greater than nine (xxxxlOlO-xxxxl111), or if the AC flag is one, six is
added to the accumulator producing the proper BCD digit in the low-order nibble. This internal ad-
dition would set the carry flag if a carry-out of the low-order four-bit field propagated through all
high-order bits, but it would not clear the carry flag otherwise.
If the carry flag is now set, or if the four high-order bits now exceed nine (101Oxxxx-l111xxxx),
these high-order bits are incremented by six, producing the proper BCD digit in the high-order nib-
ble. Again, this would set the carry flag if there was a carry-out of the high-order bits, but wouldn't
clear the carry. The carry flag thus indicates if the sum of the original two BCD variables is greater
than 100, allowing multiple precision decimal addition. OV is not affected.
All of this occurs during the one instruction cycle. Essentially, this instruction performs the decimal
conversion by adding OOH, 06H, 60H, or 66H to the accumulator, depending on initial accumulator
and PSW conditions.
3-24 AFN01739A
Note: DA A cannot simply convert a hexadecimal number in the accumulator to BCD notation, nor
does DA A apply to decimal subtraction.
Example: The accumulator holds the value 56H (0101011OB) representing the packed BCD digits of the
decimal number 56. Register 3 contains the value 67H (01100111 B) representing the packed BCD
digits of the decimal number 67. The carry flag is set. The instruction sequence,
ADDC A,R3
DA A
will first perform a standard twos-complement binary addition, resulting in the value OBEH
(10111110) in the accumulator. The carry and auxiliary carry flags will be cleared.
The Decimal Adjust instruction will then alter the accumulator to the value 24H (00100100B), in-
dicating the packed BCD digits of the decimal number 24, the low-order two digits of the decimal
sum of 56, 67, and the carry-in. The carry flag will be set by the Decimal Adjust instruction, in-
dicating that a decimal overflow occurred. The true sum 56, 67, and 1 is 124.
BCD variables can be incremented or decremented by adding 01H or 99H. If the accumulator in-
itially holds 30H (representing the digits of 30 decimal), then the instruction sequence,
ADD A,#99H
DA A
will leave the carry set and 29H in the accumulator, since 30 + 99 = 129. The low-order byte of'the
sum can be interpreted to mean 30 - 1 = 29.
Bytes: 1
Cycles:
Encoding:
Operation: DA
-contents of Accumulator are BCD
IF [[(A3-0) >9] V [(AC) = 1]]
THEN (A3-0).-(A3-0) + 6
AND
IF [[(A7-4) >9] V [(C) = 1]]
THEN (A7-4).-(A7-4) + 6
3-25 AFN-01739A
I"'lr-,... L. &_
1.11:"" uyn::
Function: Decrement
Description: The variable indicated is decremented by 1. An original value of OOH will underflow to OFFH. No
flags are affected. Four operand addressing modes are allowed: accumulator, register, direct, or
register = indirect.
Example: Register 0 contains 7FH (01111111B). Internal RAM locations 7EH and 7FH contain OOH and 40H,
respectively. The instruction sequence,
DEC @RO
DEC RO
DEC @RO
will leave register 0 set to 7EH and internal RAM locations 7EH and 7FH set to OFFH and 3FH.
DEC A
Bytes:
Cycles:
Encoding: I 0 0 0 1 1. 0 1 0 0 I
Operation: DEC
(A) ...... (A) - 1
DIV AB
Function: Divide
Description: DIV AB divides the unsigned eight-bit integer in the accumulator by the unsigned eight-bit integer in
register B. The accumulator receives the integer part of the quotient; register B receives the integer
remainder. The carry and OV flags will be cleared.
Exception: if B had originally contained OOH, the values returned in the accumulator and B-register
will be undefined and the overflow flag will be set. The carry flag is cleared in any case.
Example: The accumulator contains 251 (OFBH or 11111011B) and B contains 18 (l2H or 0001001OB). The in-
struction,
DIV AB
will leave 13 in the accumulator (OOH or 00001101B) and the value 17 (lIH or 00010001 B) in B,
since 251 = (13 x 18) + 17. Carry and OV will both be cleared.
Bytes: 1
Cycles: 4
Encoding: 1 1000 \0100\
Operation: DIV
(A) 15-84- (A) / (B)
(B)7-0
DEC Rn
Bytes:
Cycles:
3-26 AFN-01739A
Encoding:
1
0 0 0 111 r r r
Operation: DEC
(Rn)...- (Rn) - 1
DEC direct
Bytes: 2
Cycles: 1
Encoding:
1
0 0 0 1I 0 1 0 11 direct address
Operation: DEC
(direct) +- (direct) - 1
DEC @Ri
Bytes:
Cycles:
Encoding:
10 0 0 11 0 1 1 i I
Operation: DEC
Ri..--Ri - 1
3-27 AFN-01739A
DJNZ < byte>,<reladdr>
Function: Decrement and Jump if Not Zero

Description: DJNZ decrements the location indicated by 1, and branches to the address indicated by the second
operand if the resulting value is not zero. An original value of OOH will underflow to OFFH. No
flags are affected. The branch destination would be computed by adding the signed relative-
displacement value in the last instruction byte to the PC, after incrementing the PC to the first byte
of the following instruction.
The location decremented may be a register or directly addressed byte.
Example: Internal Ram locations 40H, 50H, and 60H contain the values 01H, 70H, and 15H, respectively.
The instruction sequence,
DJNZ 40H,LABEL_l
DJNZ 50H,LABEL~
DJNZ 60H,LABEL_3
will cause a jump to the instruction at label LABEL~ with the values OOH, 6FH, and 15H in the
three RAM locations. The first jump was not taken because the result was zero.
This instruction provides a simple way of executing a program loop a given number of times, or for
adding a moderate time delay (from 2 to 512 machine cycles) with a single instruction. The instruc-
tion sequence,
MOV R2,#8
TOGGLE: CPL P1.7
DJNZ R2,TOGGLE
will toggle P1.7 eight times, causing four output pulses to appear at bit 7 of output port 1. Each
pulse will last three machine cycles; two for DJNZ and one to alter the pin.
DJNZ Rn,rel
Bytes: 2
Cycles: 2
Encoding: 1'---1_ _0__

I ......I_l_r_r_......
r1 direct address
Operation: DJNZ
(PC)~(PC) + 2
(Rn)~(Rn) - 1
IF (Rn) > 0 or (Rn) < 0
THEN
(PC~(PC) + rei
DJNZ direct,rel
Bytes: 3
Cycles: 2
Encoding: L.1_l_ _0_l.....l..I_0_l_0_l.....11 1 direct address I reI. address I

Operation: DJNZ
(PC)~(PC) +2
(direct)~(direct) -
IF (direct) > 0 or (direct) < 0
THEN
(PC)~(PC) + rei
3-28 AFN01739A
INC <byte>
Function: Increment
Descrip.tion: INC increments the indicated variable by I. An original value of OFFH will overflow to OOH. No
flags are affected. Three addressing modes are allowed: register, direct, or register = indirect.
Example: Register 0 contains 7EH (01 11 111 lOB). Internal RAM locations 7EH and 7FH contain OFFH and
40H, respectively. The instruction sequence,
INC @RO
INC RO
INC @RO
will leave register 0 set to 7FH and internal RAM locations 7EH and 7FH holding (respectively) OOH
and 41H.
INC A
Bytes:
Cycles:
Encoding: I0 0 0 0 0 I 1 0 0
Operation: INC
(A).-(A) +
INC Rn
Bytes:
Cycles:
Encoding: I0 0 0 0 11 r r r
Operation: INC
(Rn) . - (Rn) +
INC direct
Bytes: 2
Cycles: 1
Encoding:
1
0 0 0 01 0 1 0 1 I I direct address
Operation: INC
(direct).-(direct) +
INC @Ri
Bytes:
Cycles:
Encoding: 10 0 0 0 0 I
Operation: INC
Ri.-Ri +
3-29 AFN01739A
INC DPTR
Function: Increment Data Pointer

Description: Increment the 16-bit data pointer by 1. A 16-bit increment (modulo 2 16) is performed; an overflow
of the low-order byte of the data pointer (DPL) from OFFH to OOH will increment the high-order
byte (DPH). No flags are affected.
This is the only 16-bit register which can be incremented.

Example: Registers DPH and DPL contain 12H and OFEH, respectively. The instruction sequence,
INC DPTR
INC DPTR
INC DPTR
will change DPH and DPL to 13H and 01H.
Bytes: 1
Cycles: 2
Encoding: IL-..l_0_ _0--,-10__

0_1_1......1
Operation: INC
(DPTR).-(DPTR) + 1
JB bit,rel
Function: Jump if Bit set

Description: If the indicated bit is a one, jump to the address indicated; otherwise proceed with the next instruc-
tion. The branch destination is computed by adding the signed relative-displacement in the third in-
struction byte to the PC, after incrementing the PC to the first byte of the next instruction. The bit
tested is not modified. No flags are affected.
Example: The data present at input port 1 is 1100101OB. The accumulator holds 56 (010101IOB). The instruc-
tion sequence,
JB PI.2,LABELl
JB ACC.2,LABEL2
will cause program execution to branch to the instruction at label LABEL2.
Bytes: 3
Cycles: 2
Encoding: I 1 I 1
bit address I reI. address I
Operation: JB
(PC)~ (PC) + 3
IF (bit) = 1
THEN
(PC)"-(PC) + reI
3-30 AFN-01739A
JBC bit,rel
Function: Jump if Bit is set and Clear bit

Description: If the indicated bit is one, branch to the address indicated: otherwise proceed with the next
instruction. In either case, clear the designated bit. The branch destination is computed by adding
the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC
to the first byte of the next instruction. No flags are affected.
Note: When this instruction is used to test an output pin, the value used as the original data will be
read from the output data latch, not the input pin.
Example: The accumulator holds 56H (OlOlOllOB). The instruction sequence,
JBC ACC.3,LABELl
JBC ACC.2,LABEL2
will cause program execution to continue at the instruction identified by the label LABEL2, with the
accumulator modified to 52H (OlOlOOlOB).
Bytes: 3
Cycles: 2
Encoding:
1
0 0 0 11 0 0 0 01 I bit address I reI. address I
Operation: JBC
(PC)~ (PC) +3
IF (bit) = 1
THEN
(bit)..-- 0
(PC)~(PC) + reI
JC rei
Function: Jump if Carry is set

Description: If the carry flag is set, branch to the address indicated; otherwise proceed with the next instruction.
The branch destination is computed by adding the signed relative-displacement in the second in-
struction byte to the PC, after incrementing the PC twice. No flags are affected.
Example: The carry flag is cleared. The instruction sequence,
JC LABELl
CPL C
JC LABEL2
will set the carry and cause program execution to continue at the instruction identified by the label
LABEL2.
Bytes: 2
Cycles: 2
Encoding: I 0 1 0 0 I 0 0 0 0 I I reI. address I

Operation: JC
(PC)~(PC) +2
IF (C) = 1
THEN
(PC)~(PC) + reI
3-31 AFN-01739A
JMP @A+DPTR
Function: Jump indirect

Description: Add the eight-bit unsigned contents of the accumulator with the sixteen-bit data pointer, and load
the resulting sum to the program counter. This will be the address for subsequent instruction
fetches. Sixteen-bit addition is performed (modulo 2 16): a carry-out from the low-order eight bits
propagates through the higher-order bits. Neither the accumulator nor the data pointer is altered.
No flags are affected.
Example:
An even number from to 6 is in the accumulator. The following sequence of instructions will
branch to one of four AJMP instructions in a jump table starting at JMP_ TBL:
MOV DPTR,#JMP_TBL
JMP @A+DPTR
JMP_ TBL: AJMP LABELO
AJMP LABELl
AJMP LABEL2
AJMP LABEL3
If the accumulator equals 04H when starting this sequence, execution will jump to label LABEL2.
Remember that AJMP is a two-byte instruction, so the jump instructions start at every other ad-
dress.
Bytes: 1
Cycles: 2
Encoding: 1....o___1. . 1_o_o_1

. _____I 1
Operation: JMP
(PC).-(A) + (DPTR)
JNB bit,rel
Function: Jump if Bit Not set

Description: If the indicated bit is a zero, branch to the indicated address; otherwise proceed with the next in-
struction. The branch destination is computed by adding the signed relative-displacement in the
third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction.
The bit tested is not modified. No flags are affected.
Example: The data present at input port 1 is 1100 10 lOB. The accumulator holds 56H (010101 lOB). The in-
struction sequence,
JNB P1.3,LABELl
JNB ACC.3,LABEL2
will cause program execution to continue at the instruction at label LABEL2.
Bytes: 3
Cycles: 2
Encoding: 1.....0_0_ _1......

1_0_0_0_0-,1 I bit address 1 IreI. address 1
Operation: JNB
(PC).-(PC) + 3
IF (bit) =
THEN (PC)..-- (PC) + reI.
3-32 AFN-01739A
JNC rei
Function: Jump if Carry not set

Description: If the carry flag is a zero, branch to the address indicated; otherwise proceed with the next instruc-
tion. The branch destination is computed by adding the signed relative-displacement in the second
instruction byte to the PC, after incrementing the PC twice to point to the next instruction. The
carry flag is not modified.
Example: The carry flag is set. The instruction sequence,
JNC LABELl
CPL C
JNC LABEL2
will clear the carry and cause program execution to continue at the instruction identified by the label
LABEL2.
Bytes: 2
Cycles: 2
Encoding: I-Io___o_l-al_o_o__o_o-J I reI. address I

Operation: JNC
(PC)~(PC) + 2
IF (C) =
THEN
(PC)~(PC) + reI
JNZ rei
Function: Jump if accumulator Not Zero

Description: If any bit of the accumulator is a one, branch to the indicated address; otherwise proceed with the
next instruction. The branch destination is computed by adding the signed relative-displacement in
the second instruction byte to the PC, after incrementing the PC twice. The accumulator is not
modified. No flags are affected.
Example: The accumulator originally holds OOH. The instruction sequence,
JNZ LABELl
INC A
JNZ LABEL2
will set the accumulator to OIH and continue at label LABEL2.
Bytes: 2
Cycles: 2
Encoding: 0
_ _ _ _.....
1-1 1 ____-11 1 reI. address I
Operation: JNZ
(PC)~(PC) + 2
IF (A) ~
THEN
(PC)~(PC) + reI
3-33 AFN01739A
JZ rei
Function: Jump if Accumulator Zero

Description: If all bits of the accumulator are zero, branch to the address indicated; otherwise proceed with the
next instruction. The branch destination is computed by adding the signed relative-displacement in
the second instruction byte to the PC, after incrementing the PC twice. The accumulator is not
modified. No flags are affected.
Example: The accumulator originally contains 01H. The instruction sequence,
JZ LABELl
DEC A
JZ LABEL2
will change the accumulator to OOH and cause program execution to continue at the instruction
identified by the label LABEL2.
Bytes: 2
Cycles: 2
Encoding: 1_o
..... ____
0...LI_o_o__o_o. . 1. reI. address I
Operation: JZ
(PC)~ (PC) + 2
IF (A) =
THEN (PC)~(PC) + rei
LCALL addr16
Function: Long Call

Description: LCALL calls a subroutine located at the indicated address. The instruction adds three to the pro-
gram counter to generate the address of the next instruction and then pushes the 16-bit result onto
the stack (low byte first), incrementing the stack pointer by two. The high-order and low-order
bytes of the PC are then loaded, respectively, with the second and third bytes of the LCALL in-
struction. Program execution continues with the instruction at this address. The subroutine may
therefore begin anywhere in the full 64K-byte program memory address space. No flags are af-
fected.
Example: Initially the stack pointer equals 07H. The label "SUBRTN" is assigned to program memory loca-
tion 1234H. After executing the instruction,
LCALL SUBRTN
at location 0123H, the stack pointer will contain 09H, internal RAM locations OSH and 09H will
contain 26H and 01H, and the PC will contain 1235H.
Bytes: 3
Cycles: 2
Encoding: 10
......__
0_0_--'-10__0_1_0.......1 addr 15 - addrS addr7 - addrO I
Operation: LCALL
(PC)~ (PC) + 3
(SP).-(SP) + 1
SP~ (PC7-0)
(SP).-(SP) + 1
SP1-( PC I5-S)
(PC).- addr I5-0
3-34 AFN01739A
LJMP addr16
Function: Long Jump

Description: LJMP causes an unconditional branch to the indicated address, by loading the high-order and low-
order bytes of the PC (respectively) with the second and third instruction bytes. The destination
may therefore be anywhere in the full 64K program memory address space. No flags are affected.
Example: The label "JMPADR" is assigned to the instruction at program memory location 1234H. The in-
struction,
LJMP JMPADR
at location 0123H will load the program counter with 1234H.
Bytes: 3
Cycles: 2
Encoding: I0 0 0 0 0 0I 1 0 Iaddr15 - addr8 I addr7 - addrO I

Operation: LJMP
(PC)~addq5-0
MOV <dest-byte>,<src-byte>
Function: Move byte variable

Description: The byte variable indicated by the second operand is copied into the location specified by the first
operand. The source byte is not affected. No other register or flag is affected.
This is by far the most flexible operation. Fifteen combinations of source and destination address-
ing modes are allowed.
Example: Internal RAM location 30H holds 40H. The value of RAM location 40H is lOH. The data present at
input port 1 is 1lOO lO lOB (OCAH).
MaV RO,#30H ;RO<= 30H
MaV A,@RO ;A <= 40H
MaV Rl,A ;Rl < = 40H
MaV R,@Rl ;B <= lOH
MaV @Rl,Pl ;RAM (40H) <= OCAH
MaV P2,P! ;P2 #OCAH
leaves the value 30H in register 0, 40H in both the accumulator and register 1, lOH in register B, and
OCAH (llOOlOlOB) both in RAM location 40H and output on port 2.
MOV A,Rn
Bytes:
Cycles:
Encoding: 11 011 r r r I
Operation: Mav
(A)~(Rn)
MOV A,direct
Bytes: 2
Cycles: 1
Encoding: 11 01 0 1 0 1 I Idirect address

Operation: Mav
(A}'-( direct)
3-35 AFN-01739A
MOV A,@R!
Bytes:
Cycles:
Encoding: 11 01 0 1 1 i I
Operation: MOV
(A) ' 4 - - Ri
MOV A,#data
Bytes: 2
Cycles: 1
Encoding:
10 11 0 1 0 01 1immediate data 1
Operation: MOV
(A)'-#data
MOV Rn,A
Bytes:
Cycles:
Encoding: I1 111 r r r I
Operation: MOV
(Rn)~(A)
MOV Rn,direct
Bytes: 2
Cycles: 2
Encoding: 11 0 o 11 r r r I direct addr.
Operation: MOV
(Rn).-(direct)
MOV Rn,#data
Bytes: 2
Cycles: 1
Encoding: I0 1I 1 r r r I immediate data
Operation: MOV
(Rn)~#data
MOV direct,A
Bytes: 2
Cycles: 1
Encoding:
I 1 1I 0 1 0 1I direct address I
Operation: MOV
(direct)~ (A)
MOV direct,Rn
Bytes: 2
Cycles: 2
Encoding: 0 0 o 11 r r r I direct address I

3-36 AFN-01739A
Operation: Mav
(direct)~ (Rn)
MOV direct,direct
Bytes: 3
Cycles: 2
Encoding: 11 0 0 o 10 1 0 1 I I dir. addr. (src) I I dir. addr. (dest) I

Operation: Mav
(direct)~ (direct)
MOV direct,@Ri
Bytes: 2
Cycles: 2
Encoding: 11 0 0 01 0 1 1 i I I direct addr. I

Operation: Mav
( direct)~Ri
MOV direct,#data
Bytes: 3
Cycles: 2
Encoding: I0 1 0 I 1 0 1 I I direct address I I immediate data I

Operation: Mav
(direct)~ #data
MOV @Ri,A
Bytes:
Cycles:
Encoding: 11 1 I0 1 1 i I
Operation: Mav
Ri~(A)
MOV @Ri,direct
Bytes: 2
Cycles: 2
Encoding: 11 0 01 0 1 1 I direct addr1
Operation: MaV
Ri~( direct)
MOV @Ri,#data
Bytes: 2
Cycles:
Encoding: 0 11 0 1 1 immediate data

1
Operation: Mav
RI)~ #data
3-37 AFN-01739A
MOV <destbit>,<srcbit>
Function: Move bit data

Description: The Boolean variable indicated by the second operand is copied into the location specified by the
first operand. One of the operands must be the carry flag; the other may be any directly addressable
bit. No other register or flag is affected.
Example: The carry flag is originally set. The data present at input port 3 is 11000101 B. The data previously
written to output port 1 is 35H (00110101B).
MOV P1.3,C
MOV C,P3.3
MOV Pl.2,C
will leave the carry cleared and change port 1 to 39H (00111001 B).
MOV C,bit
Bytes: 2
Cycles: 1
Encoding: 1...._1_o_ _0--L..I_o_0_1_0....J1 I bit address

Operation: MOV
(C)~(bit)
MOV bit,C
Bytes: 2
Cycles: 2
Encoding: 11 I
1 1 Ibit address
Operation: MOV
(bit) 4 - (C)
MOV DPTR,#data16
Function: Load Data Pointer with a 16-bit constant

Description: The data pointer is loaded with the 16-bit constant indicated. The 16-bit constant is loaded into the
second and third bytes of the instruction. The second byte (DPH) is the high-order byte, while the
third byte (DPL) holds the low-order byte. No flags are affected.
This is the only instruction which moves 16 bits of data at once.

Example: The instruction,
MOV DPTR,#1234H
will load the value 1234H into the data pointer: DPH will hold 12H and DPL will hold 34H.
Bytes: 3
Cycles: 2
Encoding: 11 1 10 I I immed. data15 - 8 I immed. data7 - I

Operation: MOV
(DPTR)4- #data15-0
338 AFN01739A
MOVC A,@A+<basereg>
Function: Move Code byte

Description: The MOVC instructions load the accumulator with a code byte, or constant from program memory.
The address of the byte fetched is the sum of the original unsigned eight-bit accumulator contents
and the contents of a sixteen-bit base register, which may be either the data pointer or the PC. In the
latter case, the PC is incremented to the address of the following instruction before being added
with the accumulator: otherwise the base register is not altered. Sixteen-bit addition is performed so
a carry-out from the low-order eight bits may propagate through higher-order bits. No flags are af-
fected.
Example: A value between 0 and 3 is in the accumulator. The following instructions will translate the value in
the accumulator to one of four values defined by the DB (define byte) directive.
REL_PC: INC A
MOVC A,@A+PC
RET
DB 66H
DB 77H
DB 88H
DB 99H
If the subroutine is called with the accumulator equal to 01H, it will return with 77B in the ac-
cumulator. The INC A before the MOVC instruction is needed to "get around" the RET instruction
above the table. If several bytes of code separated the MOVC from the table, the corresponding
number would be added to the accumulator instead.
MOVC A,@A+ DPTR
Bytes: 1
Cycles: 2
Encoding: .....
1_l_0_0_----'I_O_O__l_-.J
Operation: MOVC
(A)~ A) + (DPTR
MOVC A,@A+ PC
Bytes: 1
Cycles: 2
Encoding: 11 0 0 I 0 1
Operation: MOVC
(PC)~(PC) +1
(A)~A) + (PC
3-39 AFN-01739A
MOVX < destbyte> ,<srcbyte>
Function: Move External

Description: The MOVX instructions transfer data between the accumulator and a byte of external data
memory, hence the "X" appended to MOV. There are two types of instructions, differing in whether
they provide an eight-bit or sixteen-bit indirect address to the external data RAM.
In the first type, the contents of RO or RI in the current register bank provide an eight-bit address
multiplexed with data on po. Eight bits are sufficient for external I/O expansion decoding or a
relatively small RAM array. For somewhat larger arrays, any output port pins can be used to output
higher-order address bits. These pins would be controlled by an output instruction preceding the
MOVX.
In the second type of MOVX instruction, the data pointer generates a sixteen-bit address. P2 out-
puts the high-order eight address bits (the contents of DPH) while PO multiplexes the low-order
eight bits (DPL) with data. P2 retains the high-order bits; any data previously on P2 is lost. This
form is faster and more efficient when accessing very large data arrays (up to 64K bytes), since no
additional instructions are needed to set up the output ports.
It is possible in some situations to mix the two MOVX types. A large RAM array with its high-
order address lines driven by P2 can be addressed via the data pointer, or with code to output high-
order address bits to P2 followed by a MOVX instruction using RO or RI.
Example: An external 256 byte RAM using mUltiplexed address/data lines (e.g., an Intel 8155
RAM/I/O/Timer) is connected to the '8051 Port O. Port 3 provides leontrol ones for the external
RAM. Ports 1 and 2 are used for normal I/O. Registers 0 and 1 contain 12H and 34H. Location
34H of the external RAM holds the value 56H. The instruction sequence,
MOVX A,@Rl
MOVX @RO,A
copies the value 56H into both the accumulator and external RAM location 12H.
MOVX A,@Ri
Bytes: 1
Cycles: 2
Encoding: 11 0 0 0 1
1
Operation: MOVX
(A).-Ri
MOVX A,@DPTR
Bytes: 1
Cycles: 2
Encoding: 11 01 0 0 0 01
Operation: MOVX
(A)-DPTR
MOVX @Ri,A
Bytes: 1
Cycles: 2
Encoding: 11 11 0 0 1
Operation: MOVX
Ri-(A)
3-40 AFN-01739A
MOVX @DPTR,A
Bytes: 1
Cycles: 2
Encoding: 11 1 1 1 I
Operation: MOVX
(DPTR..-- (A)
MUL A
Function: Multiply
Description: MUL AB multiplies the unsigned eight-bit integers in the accumulator and register B. The low-order
byte of the sixteen-bit product is left in the accumulator, and the high-order byte in B. If the pro-
duct is greater than 255 (OFFH) the overflow flag is set; otherwise it is cleared. The carry flag is
always cleared.
Example: Originally the accumulator holds the value 80 (50H). Register B holds the value 160 (OAOH). The in-
struction,
MUL AB
will give the product 12,800 (3200H), so B is changed to 32H (00110010B) and the accumulator is
cleared. The overflow flag is set, carry is cleared.
Bytes: 1
Cycles: 4
Encoding: I'-_1_0_ _0.....J1,-0__

1 _0_0......1
Operation: MUL
(B) 15-8"-- (A) X (B)
(A) 7-0
NOP
Function: No Operation
Description: Execution continues at the following instruction. Other than the PC, no registers or flags are af-
fected.
Example: It is desired to produce a low-going output pulse on bit 7 of port 2 lasting exactly 5 cycles. A simple
SETB/CLR sequence would generate a one-cycle pulse, so four additional cycles must be inserted.
This may be done (assuming no interrupts are enabled) with the instruction sequence,
CLR P2.7
NOP
NOP
NOP
NOP
SETB P2.7
Bytes:
Cycles:
Encoding: I I
Operation: NOP
(PC)~(PC) +1
3-41 AFN01739A
ORL <destbyte> <srcbyte>
Function: Logical-OR for byte variables

Description: ORL performs the bitwise logical-OR operation between the indicated variables, storing the results
in the destination byte. No flags are affected.
destination is a direct address, the source can be the accumulator or immediate data.
Example: If the accumulator holds OC3H (11000011B) and RO holds 55H (01010101B) then the instruction,
.ORL A,RO
will leave the accumulator holding the value OD7H (11010111B).
When the destination is a directly addressed byte, the instruction can set combinations of bits in any
RAM location or hardware register. The pattern of bits to be set is determined by a mask byte, which
may be either a constant data value in the instruction or a variable computed in the accumulator at run-
time. The instruction,
ORL Pl,#00I1001OB
will set bits 5,4, and 1 of output port 1.
ORL A,Rn
Bytes:
Cycles:
Encoding: L..1_o_ _o__o--,-ll__r_r_r--l
Operation: ORL
(A)"-(A) V (Rn)
ORL A,direct
Bytes: 2
Cycles: 1
Encoding: 0 0 01 0 0 11 direct address

1
Operation: ORL
(A)..-(A) V (direct)
ORL A,@Ri
Bytes:
Cycles:
Encoding:
1
0 0 01 0 i I
Operation: ORL
(A)~(A) V Ri
ORL A,#data
Bytes: 2
Cycles: 1
Encoding: 0 1 0 01 0 1 0 01 immediate data

1
342 AFN01739A
Operation: ORL
(A)'-(A) V #data
ORL direct,A
Bytes: 2
Cycles: 1
Encoding: 1_0
..... __0_0--'-1_0_0_1_0. . .1 1 direct address
Operation: ORL
(direct).-(direct) V (A)
ORL direct,#data
Bytes: 3
Cycles: 2
Encoding: 1_0___0_0-,-'_0__0_1_1. . 1. I direct addr.

..... I immediate data I
Operation: ORL
(direct)~ (direct V #data
ORL C, <srcbit>
Function: Logical-OR for bit variables

Description Set the carry flag if the Boolean value is a logical I; leave the carry in its current state otherwise. A slash
("I") preceding the operand in the assembly language indicates that the logical complement of the ad-
dressed bit is used as the source value, but the source bit itself is not affected. No other flags are affected.
Example: Set the carry flag if and only if Pl.O = 1, ACe. 7 = 1, or OV = 0:
MOV C,Pl.O ; LOAD CARRY WITH INPUT PIN PI
ORL C,ACe.7 ;OR CARRY WITH THE ACe. BIT 7
ORL C,IOV :OR CARRY WITH THE INVERSE OF OV
ORL C,bit
Bytes: 2
Cycles: 2
Encoding: 10 11 1 01 I bit address I

Operation: ORL
(C)~(C) V (bit)
ORL C,/bit
Bytes: 2
Cycles: 2
Encoding: 11 01 0 01 1bit address I

Operation: ORL
(C)~(C) V I(bit)
343 AFN-01739A
POP direct
Function: Pop from stack

Description: The contents of the internal RAM location addressed by the stack pointer is read, and the stack
pointer is decremented by one. The value read is the transfer to the directly addressed byte
indicated. No flags are affected.
Example: The stack pointer originally contains the value 32H, and internal RAM locations 30H through 32H
contain the values 20H, 23H, and 01H, respectively. The instruction sequence,
POP DPH
POP DPL
will leave the stack pointer equal to the value 30H and the data pointer set to 0123H. At this point
the instruction,
POP SP
will leave the stack pointer set to 20H. Note that in this special case the stack pointer was
decremented to 2FH before being loaded with the value popped (20H).
Bytes: 2
Cycles: 2
Encoding: 0110 01 1 direct address
Operation: POP
(direct).-- SP
(SP) ~(SP) - 1
PUSH direct
Function: Push onto stack

Description: The stack pointer is incremented by one. The contents of the indicated variable is then copied into the in-
ternal RAM location addressed by the stack pointer. Otherwise no flags are affected.
Example: On entering an interrupt routine the stack pointer contains 09H. The data pointer holds the value
0123H. The instruction sequence,
PUSH DPL
PUSH DPH
will leave the stack pointer set to OBH and store 23 Hand 01 H in internal RAM locations OAH and
OBH, respectively.
Bytes: 2
Cycles: 2
Encoding: 1-1_1_ _0_0--1-1_0_o_o_0--JI direct address
Operation: PUSH
(SP)'-(SP) + 1
SP.--(direct)
3-44 AFN-01739A
RET
Function: Return from subroutine

Description: RET pops the high- and low-order bytes of the PC successively from the stack, decrementing the stack
pointer by two. Program execution continues at the resulting address, generally the instruction im-
mediately following an ACALL or LCALL. No flags are affected.
Example: The stack pointer originally contains the value OBH. Internal RAM locations OAH and OBH contain
the values 23H and 01 H, respectively. The instruction,
RET
will leave the stack pointer equal to the value 09H. Program execution will continue at location 0123H.
Bytes: 1
Cycles: 2
Encoding: 1_o_o
.... __o_l,-o_O__I_0...J1
Operation: RET
(PC 15-8)'-((SP
(SP).-(SP) - 1
(PC 7-0)'-( (SP
(SP)~SP) - 1
RETI
Function: Return from interrupt

Description: RET! pops the high- and low-order bytes of the PC successively from the stack, and restores the inter-
rupt logic to accept additional interrupts at the same priority level as the one just processed. The stack
pointer is left decremented by two. No other registers are affected; the PSW is not automatically
restored to its pre-interrupt status. Program execution continues at the resulting address, which is
generally the instruction immediately after the point at which the interrupt request was detected. If a
lower- or same-level interrupt had been pending when the RET! instruction is executed, that one in-
struction will be executed before the pending interrupt is processed.
Example: The stack pointer originally contains the value OBH. An interrupt was detected during the instruction
ending at location 0122H. Internal RAM locations OAH and OBH contain the values 23H and 01H,
respectively. The instruction,
RET!
will leave the stack pointer equal to 09H and return program execution to location 0123H.
Bytes: 1
Cycles: 2
Encoding: ..... 0_1_0.. J1

1_0_0_ _--'-10__
Operation: RETI
(PCI5-8)~SP
(SP)~(SP) - i
(PC7 _O)~ SP
.(SP~(SP) - 1
3-45 AFN01739A
Rl A
Function: Rotate accumulator Left
Description: The eight bits in the accumulator are rotated one bit to the left. Bit 7 is rotated into the bit 0 position. No
flags are affected.
Example: The accumulator holds the value OC5H (11000101B). The instruction,
RL A
leaves the accumulator holding the value 8BH (10001011B) with the carry unaffected.
Bytes: 1
Cycles: 1
Encoding: 10 0 1 010 0 1
Operation: RL
(An+ })~(An) n=0-6
(AO~(A7)
RLC A
Function: Rotate accumulator Left through the Carry flag

Description: The eight bits in the accumulator and the carry flag are together rotated one bit to the left. Bit 7 moves in-
to the carry flag; the original state of the carry flag moves into the bit 0 position. No other flags are af-
fected.
Example: The accumulator holds the value OC5H (11000101 B), and the carry is zero. The instruction,
RLC A
leaves the accumulator holding the value 8BH (1 000 10 lOB) with the carry set.
Bytes: 1
Cycles: 1
Encoding: L.1_O_O_ _l_L..IO__

O_I_......J
Operation: RLC
(An + t)~ (An) n=0-6
(AO)~(C)
(C)'-(A7)
RR A
Function: Rotate accumulator Right

Description: The eight bits in the accumulator are rotated one bit to the right. Bit 0 is rotated into the bit 7 posi-
tion. No flags are affected.
Example: The accumulator holds the value OC5H (11000101B). The instruction,
RR A
leaves the accumulator holding the value OE2H (1110001OB) with the carry unaffected.
Bytes: 1
Cycles: 1
Encoding: I0 0 0 I
0 0 0 1
Operation: RR
(An)~(An + I) n=0-6
(A7)~(AO)
3-46 AFN01739A
RRC A
Function: Rotate accumulator Right through Carry flag
Description: The eight bits in the accumulator and the carry flag are together rotated one bit to the right. Bit 0
moves into the carry flag; the original value of the carry flag moves into the bit 7 position. No other
flags are affected.
Example: The accumulator holds the value OC5H (11000101B), the carry is zero. The instruction,
RRC A
leaves the accumulator holding the value 62 (011000IOB) with the carry set.
Bytes: 1
Cycles: 1
Encoding: I0 0 0 I
1 0 0 1
Operation: RRC
(An)'-(An + I) n=0-6
(A7)~(C)
(C)..-(AO)
SETB <bit>
Function: Set Bit

Description: SETB sets the indicated bit to one. SETB can operate on the carry flag or any directly addressable
bit. No other flags are affected.
Example: The carry flag is cleared. Output port 1 has been written with the value 34H (00110100B). The in-
structions,
SETB C
SETB Pl.O
will leave the carry flag set to 1 and change the data output on port 1 to 35H (00110101B).
SETB C
Bytes:
Cycles:
Encoding: 11 0 I
1 0 0 1 1 I
Operation: SETB
(C)~1
SETB bit
Bytes: 2
Cycles:
Encoding: 11 0 1 10 0 1 01 Ibit address

Operation: SETB
(bit)-1
3-47 AFN01739A
SJfv1P ial
Function: Short Jump

Description: Program control branches unconditionally to the address indicated. The branch destination is com-
puted by adding the signed displacement in the second instruction byte to the PC, after incremen-
ting the PC twice. Therefore, the range of destinations allowed is from 128 bytes preceding this in-
struction to 127 bytes following it.
Example: The label "RELADR" is assigned to an instruction at program memory location 0123H. The in-
struction,
SJMP RELADR
will assemble into location OlOOH. After the instruction is executed, the PC will contain the value
0123H.
(Note: Under the above conditions the instruction following SJMP will be at 102H. Therefore, the
displacement byte of the instruction will be the relative offset (OI23H-0102H) = 21 H. Put another
way, an SJMP with a displacement of OFEH would be a one-instruction infinite loop.)
Bytes: 2
Cycles: 2
Encoding: 11 0 0 010 0 0 0 I reI. address

Operation: SJMP
(PC~(PC) + 2
(PC)~(PC) + reI
SUBB A, <srcbyte>
Function: Subtract with borrow

Description: SUBB subtracts the indicated variable and the carry flag together from the accumulator, leaving the
result in the accumulator. SUBB sets the carry (borrow) flag if a borrow is needed for bit 7, and
clears C otherwise. (If C was set before executing a SUBB instruction, this indicates that a borrow
was needed for the previous step in a multiple precision subtraction, so the carry is subtracted from
the accumulator along with the source operand.) AC is set if a borrow is needed for bit 3, and
cleared otherwise. OV is set if a borrow is needed into bit 6, but not into bit 7, or into bit 7, but not
bit 6.
When subtracting signed integers OV indicates a negative number produced when a negative value is
subtracted from a positive value, or a positive result when a positive number is subtracted from a
negative number.
The source operand allows four addressing modes: register, direct, register-indirect, or immediate.
Example: The accumulator holds OC9H (11001001B), register 2 holds 54H (01010100B), and the carry flag is
set. The instruction,
SUBB A,R2
will leave the value 74H (01110100B) in the accumulator, with the carry flag and AC cleared but OV
set.
Notice that OC9H minus 54H is 75H. The difference between this and the above result is due to the
carry (borrow) flag being set before the operation. If the state of the carry is not known before star-
ting a single or multiple-precision subtraction, it should be explicitly cleared by a CLR C instruc-
tion.
348 AFN-01739A
SUBB A,Rn
Bytes:
Cycles:
Encoding: 11 0 0 1 11 r r r ]
Operation: SUBB
(A)..-(A) - (C) - (Rn)
SUBB A,direct
Bytes: 2
Cycles:
Encoding: 11 0 0 1 0 I 1 0 1 I I direct address

Operation: SUBB
(A)~(A) - (C) - (direct)
SUBB A,@Ri
Bytes:
Cycles:
Encoding: 11 0 0 1 0 I i I
Operation: SUBB
(A)...--(A) - (C) - Ri
SU B B A,#data
Bytes: 2
Cycles: 1
Encoding: 11 0 0 1 0 I 1 0 0 I I immediate data I

Operation: SUBB
(A)~ (A) - (C) - #data
SWAP A
Function: Swap nibbles within the Accumulator

Description: SWAP A interchanges the low- and high-order nibbles (four-bit fields) of the accumulator (bits 3-0
and bits 7-4). The operation can also be thought of as a four-bit rotate instruction. No flags are af-
fected.
Example: The accumulator holds the value OC5H (11000101 B). The instruction,
SWAP A
leaves the accumulator holding the value 5CH (01011100B).
Bytes: 1
Cycles:
Encoding: 11 1 0 0 I
0 1 0 0 I
Operation: SWAP
(A3-0)~(A7-4), (A7-4)~(A3-0)
3-49 AFN-01739A
XCH A,<byte>
Function: Exchange Accumulator with byte variable

Description: XCH loads the accumulator with the contents of the indicated variable, at the same time writing the
original accumulator contents to the indicated variable. The source/destination operand can use
register, direct, or register-indirect addressing.
Example: RO contains the address 20H. The accumulator holds the value 3FH (00111111 B). Internal RAM
location 20H holds the value 75H (01110101B). The instruction,
XCH A,@RO
will leave RAM location 20H holding the values 3FH (00111111B) and 75H (01110101B) in the ac-
cumulator.
XCH A,Rn
Bytes:
Cycles:
Encoding: 1...._1_ _0
__0-'-11__r_r_r--l
Operation: XCH
(A). (Rn)
XCH A,direct
Bytes: 2
Cycles: 1
Encoding: 1L...-1 _ _O_ 0--L..1_0_1_0_1-.J1 Idirect address

Operation: XCH
(A)~ (direct)
XCH A,@Ri
Bytes:
Cycles:
Encoding: 1_1 0......I_o____i .....1

.... _ _0__
Operation: XCH
(A)~Ri
XCHD A,@Ri
Function: Exchange Digit

Description: XCHD exchanges the low-order nibble of the accumulator (bits 3-0),generally representing a hex-
adecimal or BCD digit) with that of the internal RAM location indirectly addressed by the specified
register. The high-order nibbles (bits 7-4) of each register are not affected. No flags are affected.
Example: RO contains the address 20H. The accumulator holds the value 36H (00110110B). Internal RAM
location 20H holds the value 75H (01110101 B). The instruction,
XCHD A,@RO
will leave RAM location 20H holding the value 76H (0111011OB) and 35H (00110101B) in the ac-
cumulator.
Bytes: 1
Cycles:
Encoding: 11 1 I
Operation: XCHD
(A3-0)~Ri3-0
3-50 AFN01739A
XRL <destbyte>,<srcbyte>
Function: Logical Exclusive-OR for byte variables

Description: XRL performs the bitwise logical Exclusive-OR operation between the indicated variables, storing
the results in the destination. No flags are affected.
destination is a direct address, the source can be the accumulator or immediate data .
.(Note: When this instruction is used to modify an output port, the value used as the original port
data will be read from the output data latch, not the input pins.)
Example: If the accumulator holds OC3H (llOOOOIIB) and register 0 holds OAAH (lOlOlOlOB) then the in-
struction,
XRL A,RO
will leave the accumulator holding the value 69H (01 101001 B).
When the destination is a directly addressed byte, this instruction can complement combinations of
bits in any RAM location or hardware register. The pattern of bits to be complemented is then
determined by a mask byte, either a constant contained in the instruction or a variable computed in
the accumulator at run-time. The instruction,
XRL Pl,#OOllOOOIB
will complement bits 5, 4, and 0 of output port 1.
XRL A,Rn
Bytes:
Cycles:
Encoding: ....
1_O____0---LI_l_r__r_r-J
Operation: XRL
(A)~(A) EB (Rn)
XRL A,direct
Bytes: 2
Cycles:
Encoding: 0 01 0 1 0 11 direct address

1
Operation: XRL
(A).-(A) EB (direct)
XRL A,@Ri
Bytes:
Cycles:
Encoding: I0 01 0 i I
Operation: XRL
(A)~(A) EB Ri
XRL A,#data
Bytes: 2
Cycles: 1
Encoding: 0 01 0 1 0 01 I immediate data

3-51 AFN-017:1~A
Operation: XRL
(A)~ (A) EB #data
XRL direct,A
Bytes: 2
Cycles:
Encoding: 0____0_11-__0_1_-11
1-1
1 direct address 1
Operation: XRL
(direct)..- (direct) EB (A)
XRL direct,#data
Bytes: 3
Cycles: 2
Encoding: L.. 1_O____0..J.I_O_O__1_~ Idirect address 1 immediate data 1
Operation: XRL
(direct)~ (direct) EB #data
3-52 AFN-01739A
I
I'
'I
Chapter 4
EXPANDED 8051 FAMILY
This chapter shows in very general terms some basic

circuits for expanding the 8051 Family. As the product
matures and Intel tests specific circuits, the User
Manual will be updated. Also application notes wiII be
published to help show actual, tested circuits designed
by Intel personnel. The schematics included in this
chapter should give the designer an insight into connec-
ting external peripherals and memories to the 8051.
AFN-01739A
4-1
Figure 41. The Standalone 8051
AFN-01739A
42
+5V
+ 5V
40
Vee P40 2
:~~ !~
P41 3
P42 4
D P1.2
P1.3 5
}I/O 8243
1/0
P43 5
P50 1
P1.4 6 EXPANDER P51 23
18 XTAL 2 P1.5 7
P52 22
P1.6 8
P1.7 P53 21
110
8051 11 P20 P60 20
9
8751 10 P21 P61 19
>----.----+1 RESET/VPD 9 P22 P62 18
8 P23 P63 17
7 13
PROG P70 14
31 _ P71
'------10-1 EAIVDD P72 ~~
P73
10
11
P3.0
P3.1
PO.O ;~
PO.1 37 1/0
12 P3.2
PO.2 36 The following software driver is required to
13 P3.3 Interface to the 8243.
PO.3 35
14 P3.4
PO.4 34 Mixing Parallel Output. Input. and
15 P3.5 Control Strobes on Port 2
PO.5 33
16 P3.6
PO.6 32 ;IN8243 INPUT DATA FROM AN 82431/0 EXPANDER
17 P3.7 PO.7
CONNECTED TO P23P20
P25 & P24 MIMIC CSI & PROG
P27P26 USED AS INPUTS
PORT TO BE READ IN ACC
Any 110 Port Pins can be used. IN8243: ORL A,'11010000B

MOV P2,A ;OUTPUT INSTRUCTION CODE
CLR P2,4 ;FALLING EDGE OF PROG
ORL P2, '00001111 B ,SET FOR INPUT
MOV A,P2 ;READ INPUT DATA
SETB P2,4 ;RETURN PROG HIGH
Figure 42. 110 Expansion Using an 8243
AFN-01739A
4-3
+5V
40
Vee
-=
8051
8751
lo P~RT
31
RESETIVpo
EAIVOO
lo P0 RT
2
~~
lo
P3.0
12 P3.1
,{ 13
14
15
16
17
P3.2
P3.3
P3.4
P3.5
:~:~
P'1
RT
(Any 110 Port Line Can Be Used)
Additional Inputs
3 Serial 11 3 11
L-t-+---.::t 08 CD4014 In,...-----1"'"'6 08 CD4014
16
+5V Voo CMOS SHIFT REG. +5V 8 voo CMOS SHIFT REG.
8v~ v~
'-------------+-----------,---------4- - - - -- - - --
Figure 43. Expanding Input Lines via Serial Port
AFN-01739A
4-4
+5V
40
VCC
P1.0 1
lo
P1.1 2
P1.2 3
D P1.3 4
P0 RT
P1.4 5
1
P1.5 6
P1.6 7
P1.7 8
8051
= 8751 P2.0 21
lo
P2.1 22
RESETIVPO P2.2 23
P2.3 24
P2.4 25 P~RT
P2.5 26
31 _ P2.6 27
EAIVOO P2.7 28
10 P3.0 (RXO)
lo
11 P3.1 (TXO)
,,{
12 P3.2 (INTO)
13 P3.3 (INT1)
14 P3.4 (TO) POORT
15 P3.5 (T1)
16 P3.6 (WR)
17 P3.7 (RD)
29
(Any I/O Port Line Can Be Used)
Additional Outputs
L-f-+--~OATA
2 ~1~0______~2~OATA
+5V 16 VOO CD4094 +5V 16 VOO CD4094
8 Vss CMOS SHIFT REG. OE 15 8 Vss CMOS SHIFT REG. OE 15
Figure 44. Expanding Output Lines via Serial Port
AFN-01739A
45
+5V
[l:
+(20
Vee
~
GND
1,,,
Vee Vpp
112
L~
CE
r
40
Vee VSS
XTAL 1 P1.0 DIO DOO 1 A7
P1.1
P1.2
t=}
~
t=
DI1
DI2 8282
D01
D02
2
3
A6
A5
A8~
~
P1.3 DI3 D03 4 A4 A9~
P1.4 I/O D04 5 A3 m
XTAL 2 P1.5 ~
DI4
DI5 D05 ; A2
2716
A10 ~ ><
8031
8051
8751
P1.6
P1.7
~
~. .---
DI6
DI7
D06
D07
8 A1
Ao "z

P2.0
21
c
'- 9 P2.1
22
m
".. RESET/VPD P2.2
23
c
~}
.J:>,
m +5
805
8751,
IGND
P2.3
P2.4
co
o
for
P2.5 ~
STB 6E
110 U'I
31 _
EAIVDD
P2.6 ~
P2.7 ~.
t ~
"'T1

{~
P3.0
P3.1
(RXD)
(TXD)
PO.O 39
PO.1 38
1~ 00
3:
01
~ P3.2 (INTO) PO.2 ;~
11
13 02 r-
~ P3.3
I/O ~ P3.4
(fNT1)
(TO)
PO.3
PO.4 35
14
15
03
04
-<
--l P3.5 (T1) PO.5 34
16 05
~ P3.6 (WR) PO.6 33
17 06
_-17 P3.7 (AD) PO.? 32 07
ALE/PROG PSEN 6E
30
1 - - -
29
1
- - ---- ------------- - - - - -
120
For 8751, 8051 CE of the 2716 must be

driven by P2.4 through an inverter

-n
Z
~ Figure 45. External Program Memory Using a 2716

I
I
+5V
[1-
I
~
+5V
I
~
+r:
124 118 l12 I
Vee GNO Vee eE GNO

40
I
Vee Vss
~l
XTAL 1 P1.0 1 010 000 19 1 A7
~
23 '
PU ~ 2 011 001 18 2 A6 A8~
P1.2 ~ 3
012 8282 002 17 3 A5
4
A9~
t=J
003 16
P1.3 013 4 A4
m
~
5
P1.4
P1.5
~
6
014
015
004 15
~~
5
6
A3
M A10 r!L- ><
"Z
XTAL 2 7 005
7 A1
8031 ~~~
016
~. l>
P1.6
P1.7 ~ 017 12 8 AO 2732A An ~
8051
8751 P2.0 ~ c
9 P2.1
22 m
~
.....
'"
RESETIVPO P2.2
23
24
c
+5 B751. P2.3 Q)
~
~}
805
for
IGNO P2,4
26 STB OE
o(J'1
P2.5
~ .....
~
1/0
31 _ P2.6
EAlVoO P2.7 ~. ~
l>
;~
9
s:
{~
P3.0 (RXO) PO.O 00
~ P3.1 (TXO) PO.1 37 :~ 01
~ P3.2 (INTO) PO.2 36 02 r-
I/O
13
P3.3
~ P3,4
(INT1)
(TO)
PO.3 35
13
14 03
04
-<
POA 34
15 P3.5 (T1)
15
05
16 P3.6 (WR)
PO.5 33 16
.:E P3.7 (RO)
PO.6
PO.7
32 17 06
07
OElVpp
ALE/PROG PSEN
30 29 20
1 1
1 - - - - - - - -----------_._-
For 8751, 8051 CE on 2732A must be

driven by P2.4 through an Inverter.
~
z
6
~
~ Figure 46. External Program Memory Using a 2732
+5V
-=
40 20
19 VCC VSS
XTAL 1 P1.0 1
P1.1 2
Jo
P1.2 3
CJ P1.3 4
P1.4 ~
18 XTAL 2 P1.5 7
P1.6 8
-= 8051
P1.7
8751 P2.0 ~~
9
}o
P2.1 23 + 5V GND
RESETIVPD
P2.2 24
P2.3 25 20
:~:: 26 PAO 21
31 _ P2.6 27 PA1 22
EA/VDD P2.7 28 PA2 23
PA3 24
,,{
10 P3.0 (RXD) PO.O 39 12 ADO PM 25
11 P3.1 (TXD) PO.1 38 13 AD1 PA5 26
12 P3.2 (INTO) PO.2 ;~ ~: AD2 PA6 27
13 P3.3 (INT1) PA7 28
14 P3.4 (TO) :~~ 35
16 AD3
17 AD4
15 P3.5 (T1) PO.5 34
18 AD5
16 P3.6 (WR) PO.6 33 8155 PCO 37
17 P3.7 (RO) _ _ PO.7 32 19 ~~~ 256 x 8 PC1 38
ALE/PROG PSEN RAM PC2 39
110
30 29 PC3 1
101M
PC4 2
9_ PC5 5
RD
10_
WR PBO 29
PB1 30
11 PB2 31
ALE
PB3 32
PB4 ~~
PB5 35
::~ 36
CAN BE SUPPLIED BY SYSTEM RESET L....--.:;:.;r.~--..:r:::----'

OR PORT LINE OF 8051
Both I/O and RAM are addressed as data memory.

Writing a bit to P2.0 determines whether RAM or I/O is to be accessed.
Figure 47. Adding a Data Memory and 110 Expander
AFN01739A
48
EXTERNAL
2581-------1
2571-------1
2561-------1
255 +5V +5V GND GND
4095
I I I I
INTERNAL VCC VDD VSS CE
21 A8 PAO ~
0
PROGRAM
0
EXTERNAL
22 A9 PA1 ~
MEMORY DATA
23 A10 PA2 ~
MEMORY PA3 ~
+5V
PO.O
PA4 ~
PO.1
12 ADO PA5 ~
13 AD1 ~
[l 8755A PA6
PO.2 14 AD2 PA7 ~
PO.3 15 AD3 I/O
40 PO.4 16 AD4 ~
r
PBO
Vee VSS PO.5
XTAL 1 P1.0 PO.6
17 AD5 PB1 ~
18 AD6 ~
CJ
P1.1
P1.2 "-l
~
~
PO.? 19 AD?
PB2
PB3
PB4
~
~
t=J
P1.3 8 _
~
~
lOR PB5
P1.4
~
XTAL2 P1.5 iL- ~9 lOW
PB6
PB7 a-
P1.6 ~ _
P1.7 ~ RD
8051 ~ ALE
8751 P2.0 ~ 2_
9 22 CE
P2.1
RESETIVPD 23 RESET
P2.2
+5 V for 8751, P2.3 ~IIO
25 ~4 ~
[3
NC
16
NC
805 1, and GND P2.4
for 8031 P2.5 ~--,
31 _
EAIVDD
P2.6 ~IIO
P2.7 ~--1
+r 40
G,D
20
Vec VSS
39 ADO
{~
P3.0 (RXD) PO.O 12 ADO PAO ~
-1.lP3.1 (TXD) PO.1 38 AD1 13 AD1 PA1 lL
12 37 AD2
110
P3.2
::::::U (INTO) PO.2 14 AD2 PA2 ~
P3.3 (INT1) PO.3 36 AD3 15 AD3 PA3 ~
-.J4P3.4 (TO) PO.4 35 AD4 16 AD4 PA4 ~
-~ P3.5 (T1) P05 34 AD5 17 AD5 PA5 ~
16 P3.6 (WR) PO.6 33 AD6 18 AD6 8155 PA6 ~
,.--1Z P3.7 (AD) PO.7 32 AD7 19 AD7 PA7 ~
ALEIPROG PSEN
7 -
30 f29 101M
PCO a-
9 _ PC1 ~
RD PC2 ~
PC3 ~ 110
PC4 ~
10_
WR
PC5 ~
11
ALE
PBO ~
PB1 ~
PB2 ~
8- PB3 ~
For 8031 P2.4 should connect CE PB4 ~
to Pin 1 (CE) of 8755 PB5 ~
PB6 ~
CAN BE SUPPLIED BY
~ RESET 'i'iME"R TIMER PB7 ~
OUT IN
SYSTEM RESET OR PORT -
LINE OF 8051 .6 P
i
TIMER
Figure 48. The ThreeChip System
AFN01739A
4-9
+5V
40
Vee
XTAL 1
CJ
8031
8051
-= 8751
RESET/VPD
+5V for 8751.
I/O
8051. and GND
for 8031
31 _
EA/VDD
10 P3.0
11 P3.1
,,{
12 P3.2
13 P3.3
14 P3.4
15 P3.5
16 P3.6
17 P3.7
29
+5V
40
Vee
1
Pl.0 2
Pl.1 3
P1.2 4
0 Pl.3 5
Pl.4 6
P1.5 7
P1.6 8
8031 PH
8051
-= 8751
RESETIVPD
+5V for 8751.
I/O
8051. and GND
for 8031
31 _
EAIVDD
10 P3.0
11 P3.1
I 12 P3.2
I 13 P3.3
I
I
I
I
I
I
"o{ 14
15
16
17
P3.4
P3.5
P3.6
P3.7
I
I Asynchronous
: Line
Figure 49. Multiple 8051'5 Using HalfDuplex Serial Communication
AFN-01739A
410
+5V
40
VCC
P1.0 1
P1.1 2
P1.2 3
D P1.3 4
P1.4 5
P1.5 6
P1.6 7
8051 P1.7 8
8751
P2.0 21
-= P2.1 22 I/O
RESET/VPD P2.2 23
P2.3 24
P2.4 25
OPEN P2.5 26
COLLECTOR
INVERTERS P2.6 27
+ 5V 31 -
DEVICE EAIVDD P2.7 28
1
10 P3.0 (RXD) PO.O 39
1/0-[ 11 P3.1 (TXD) PO.1 38
12 P3.2 (iNfO) PO.2 37
,,{
13 P3.3 (lNT1) PO.3 36
14 P3.4 (TO) PO.4 35
15 P3.5 (T1) PO.5 34
16 P3.6 (WR) PO.6 33
17 P3.7 (AD) PO.7 32
ALE/PROG
29
-All devices equal priority

-Processor polls Port 0 to determine interrupting device
Figure 410. Multiple Interrupt Sources
AFN-01739A
411
I
11
I
"
li,l
i
I
CHAPTER 5
8051 SOFTWARE ROUTINES
Chapter 5 contains two sections: 8051 PROGRAMMING TECHNIQUES

8051 Programming Techniques
Peripheral Interfacing Techniques Radix Conversion Routines
The first section has 8051 software examples for some
The divide instruction can be used to convert a number
common routines in controller applications. Some
from one radix to another. BINBCD is a short
routines included are multiple-precision arithmetic and
subroutine to convert an eight-bit unsigned binary in-
table look-up techniques.
teger in the accumulator (between 0 & 255) to a three-
digit (two byte) BCD representation. The hundred's
Peripheral Interfacing Techniques include routines for
digit is returned in one variable (HUND) and the ten's
handling the 8051 's 110 ports, serial channel and
and one's digits returned as packed BCD in another
timer/counters. Discussed in this section is 110 port
(TENONE).
reconfiguration, software delay timing, and transmit-
ting serial port character strings along with other
routines.
,
;BINBCD CONVERT 8BIT BINARY VARIABLE IN ACCUMULATOR
TO 3DIGIT PACKED BCD FORMAT.
HUNDREDS' PLACE LEFT IN VARIABLE 'HUND',
TENS' AND ONES' PLACES IN 'TENONE'.
,
HUND DATA 21H
TENONE DATA 22H
,
BINBCD: MOV B,#100 ;DIVIDED BY 100 TO
DIV AB ;DETERMINE NUMBER OF HUNDREDS
MOV HUND,A
MOV A,#10 ;DIVIDE REMAINDER BY TEN TO
XCH A,B ;DETERMINE NUMBER OF TENS LEFT
DIV AB ;TEN'S DIGIT IN ACC, REMAINDER IS
;ONE'S DIGIT
SWAP A
ADD A,B ;PACK BCD DIGITS IN ACC
MOV TENONE,A
RET
The divide instruction can also separate data in the ac- the digits can be processed individually. This example
cumulator into sub-fields. For example, dividing packed receives two packed BCD digits in the accumulator,
BCD data by 16 will separate the two nibbles, leaving separates the digits, computes their product, and returns
the high-order digit in the accumulator and the low- the product in packed BCD format in the accumulator.
order digit (remainder) in B. Each is right-justified, so
,
;MULBCD UNPACK TWO BCD DIGITS RECEIVED IN ACCUMULATOR,
FIND THEIR PRODUCT, AND RETURN PRODUCT
IN PACKED BCD FORMAT IN ACCUMULATOR
5-1
iviUi..BCD: ..,,"
IYIVY
a U1nu
u,rr "I' ;D!V!DE !NPUT BY 16
DIV AB ;A & B HOLD SEPARATED DIGITS
;(EACH RIGHT JUSTIFIED IN REGISTER).
MUL AB ;A HOLDS PRODUCT IN BINARY FORMAT (0
;99 (DECIMAL) = 0 - 63H)
MOV B,#10 ;DIVIDE PRODUCT BY 10
DIV AB ;A HOLDS NUMBER OF TENS, B HOLDS
;REMAINDER
SWAP A
ORL A,B ;PACK DIGITS
RET
Multiple Precision Arithmetic

The AD DC and SUBB instructions incorporate the completion if an overflow (for ADDC) or underflow
previous state of the carry (borrow) flag to allow (for SUBB) occurs. With two's complement signed data,
mUltiple-precision calculations by repeating the opera- the most significant bit of the original input data's most
tion with successively higher-order operand bytes. If the significant byte indicates the sign of the string, so the
input data for a multiple-precision operation is an un- overflow flag (OV) will indicate if overflow or
signed string of integers, the carry flag will be set upon underflow occurred.
,
;SUBSTR SUBTRACT STRING INDICATED BY R1
FROM STRING INDICATED BY RO TO
PRECISION INDICATED BY R2.
CHECK FOR SIGNED UNDERFLOW WHEN DONE.
,
SUBSTR: CLR C ;BORROW =0.
SUBS1: MOV A,@RO ;LOAD MINUEND BYTE
SUBB A,@R1 ;SUBTRACT SUBTRAHEND BYTE
MOV @RO,A ;STORE DIFFERENCE BYTE
INC RO ;BUMP POINTERS TO NEXT PLACE
INC R1
DJNZ R2,SUBS1 ;LOOP UNTIL DONE
WHEN DONE, TEST IF OVERFLOW OCCURRED

ON LAST ITERATION OF LOOP.
JNB OV,OV_OK
(OVERFLOW RECOVERY ROUTINE)
OVOK: RET ;RETURN
Table Look-Up Sequences

The two versions of the MOVC instructions are used as significant. Again, a look-up sequence takes three steps:
part of a three-step sequence to access look-up tables in load the accumulator with the index; compensate for the
ROM. To use the DPTR version, load the Data Pointer offset from the look-up instruction's address to the start
with the starting address of a look-up table; load the ac- of the table by adding that offset to the accumulator;
cumulator with (or compute) the index of the entry then execute the MOVC A,@A+PC instruction.
desired; and execute MOVC A,@A+DPTR. The data
pointer may be loaded with a constant for short tables, As a non-trivial situation where this instruction would
or to allow more complicated data structures, and tables be used, consider applications which store large multi-
with more than 256 entries, the values for DPH and dimensional look-up tables of dot matrix patterns, non-
DPL may be computed or modified with the standard linear calibration parameters, and so on in the linear
arithmetic instruction set. (one-dimensional) program memory. To retrieve data
from the tables, variables representing matrix indices
The PC-based version is used with smaller, "local" must be converted to the desired entry's memory ad-
tables, and has the advantage of not affecting the data dress. For a matrix of dimensions (MDIMEN x
pointer. This makes it useful in interrupt routines or NDIMEN) starting at address BASE and respective in-
other situations where the DPTR contents might be dices INDEXI and INDEXJ, the address of element
5-2 AFN-01739A
(lNDEXI, INDEXl) is determined by the formula, the assembly object code as part of the accessing
subroutine itself.
Entry Address = [BASE + (NDIMEN x INDEXI) +
INDEXl]
To handle the more general case, subroutine MATRX2
The subroutine MATRXI can access an entry in any ar- allows tables to be unlimited in size, by combining the
ray with less than 255 elements (e.g., an 11x21 array MUL instruction, double-precision addition, and the
with 231 elements). The table entries are defined using data pointer-based version of MOVe. The only restric-
the Data Byte ("DB") directive, and will be contained in tion is that each index be between 0 and 255.
,
;MATRX1 LOAD CONSTANT READ FROM TWO DIMENSIONAL LOOKUP
TABLE IN PROGRAM MEMORY INTO ACCUMULATOR
USING LOCAL TABLE LOOKUP INSTRUCTION, 'MOVC A,@A+PC'.
THE TOTAL NUMBER OF TABLE ENTRIES IS ASSUMED TO
BE SMALL, I.E. LESS THAN ABOUT 255 ENTRIES.
TABLE USED IN THIS EXAMPLE IS 11 x 21.
DESIRED ENTRY ADDRESS IS GIVEN BY THE FORMULA,
[(BASE ADDRESS) + (21 X INDEXI) + (INDEXJ)]

,
INDEXI Eau R6 ;FIRST COORDINATE OF ENTRY (010).
INDEXJ DATA 23H ;SECOND COORDINATE OF ENTRY (020).
,
MATRX1: MOV A,INDEXI
MOV B, #21
MUL AB ;(21 X INDEXI)
ADD A,INDEXJ ;ADD IN OFFSET WITHIN ROW
ALLOW FOR INSTRUCTION BYTE BETWEEN "MOVC" AND

ENTRY (0,0).
INC A
MOVC A,@A+PC
RET
BASE1: DB 1 ;(entry 0,0)
DB 2 ;(entry 0,1)
DB 21 ;(entry 0,20)
DB 22 ;(entry 1,0)
DB 42 ;(entry 1,20)
DB 231 ;(entry 10,20)

MATRX2: MOV A,INDEXI ;LOAD FIRST COORDINATE
MOV B,#NDIMEN
MUL AB :INDEXI X NDIMEN
ADD A,#LOW(BASE2) ;ADD IN 16BIT BASE ADDRESS
MOV DPL,A
MOV A,B
ADDC A,#HIGH(BASE2)
MOV DPH,A ;DPTR=(BASE ADDR) + (INDEXI+NDIMEN)
MOV A,INDEXJ
MOVC A,@A+DPTR ;ADD INDEXJ AND FETCH BYTE
RET
53
BASE2: DB 0 t .... +r" n

,\-.wl"'., n\
"',""'/
DB 0 ;(entry 0,1)
DB 0 ;(entry 0, NDIMEN1)
DB 0 ;(entry 1,0)
DB 0 ;(entry 1, NDIMEN1)
DB 0 ;(entry MDIMEN1, NDIMEN1)
Saving CPU Status during Interrupts

When the 8051 hardware recognizes an interrupt re- second method of 110 port reconfiguration.) Resources
quest, program control branches automatically to the used or altered by the service routine (Accumulator,
corresponding service routine, by forcing the CPU to PSW, etc.) must be saved and restored to their previous
process a Long CALL (LCALL) instruction to the ap- value before returning from the service routine. PUSH
propriate address. The return address is stored on the and POP provide an efficient and convenient way to
top of the stack. After completing the service routine, save such registers on the stack.
an RETI instruction returns the processor to the
background program at the point from which it was in- If the SP register held 1FH when the interrupt was
terrupted. detected, then while the service routine was in progress
the stack would hold the registers shown in Figure 5-1;
Interrupt service routines must not change any variable SP would contain 26H. This is the most general case; if
or hardware registers modified by the main program, or the service routine doesn't alter the B-register and data
else the program may not resume correctly. (Such a pointer, for example, the instructions saving and restor-
change might look like a spontaneous random error. An ing those registers could be omitted.
example of this will be given later in this section, in the
,
LOC_TMP EQU $ ;REMEMBER LOCATION COUNTER
ORG 0003H ;STARTING ADDRESS FOR INTERRUPT ROUTINE

LJMP SERVER ;JUMP TO ACTUAL SERVICE ROUTINE LOCATE
;ELSEWHERE
ORG LOC_TMP ;RESTORE LOCATION COUNTER

SERVER: PUSH PSW
PUSH ACC ;SAVE ACCUMULATOR (NOTE DIRECT ADDRESS
;NOTATION)
PUSH B ;SAVE B REGISTER
PUSH DPL ;SAVE DATA POINTER
PUSH DPH ,
MOV PSW,#00001000B ;SELECT REGISTER BANK 1
POP DPH ;RESTORE REGISTERS IN REVERSE ORDER

POP DPL
POP B
POP ACC
POP PSW ;RESTORE PSW AND RESELECT ORIGINAL
;REGISTER BANK
RETI ;RETURN TO MAIN PROGRAM AND RESTORE
;INTERRUPT LOGIC
5-4 . AFN01739A
Passing Parameters on the Stack RAM

ADDR
The stack may also pass parameters to and from 7FH
subroutines. The subroutine can indirectly address the
parameters derived from the contents of the stack
pointer, or simply pop the stack into registers before
26H DPH _(SP)
processing.
25H DPL
One advantage here is simplicity. Variables need not be 24H B
allocated for specific parameters, a potentially large 23H ACC

number of parameters may be passed, and different 22H PSW
calling programs may use different techniques for deter- 21H PC (HIGH)
mining or handling the variables. 20H PC (LOW)
1FH
For example, the subroutine HEXASC converts a hex-
adecimal value to ASCII code for its low-order digit. It
first reads a parameter stored on the stack by the calling OOH
program, then uses the low-order bits to access a local

16-entry look-up table holding ASCII codes, stores the
Figure 5-1. Stack contents during interrupt
appropriate code back in the stack and then returns.
The accumulator contents are left unchanged.
HEXASC: MOV RO,SP

DEC RO ;ACCESS LOCATION PARAMETER PUSHED INTO
DEC RO
XCH A,@RO ;READ INPUT PARAMETER AND SAVE ACCUMULATOR
ANL A,#OFH ;MASK ALL BUT LOW-ORDER 4 BITS
ADD A,#2 ;ALLOW FOR OFFSET FROM MOVC TO TABLE
MOVC A,@A+PC ;READ LOOK-UP TABLE ENTRY
XCH A,@RO ;PASS BACK TRANSLATED VALUE AND RESTORE
;ACCUMULATOR
RET ;RETURN TO BACKGROUND PROGRAM
ASCTBL: DB '0' ;ASCII CODE FOR OOH
DB '1 ' ;ASCII CODE FOR 01 H
DB '2' ;ASCII CODE FOR 02H
DB 'A' ;ASCII CODE FOR OAH
DB 'B' ;ASCII CODE FOR OBH
DB 'c' ;ASCII CODE FOR OCH
DB 'D' ;ASCII CODE FOR ODH
DB 'E' ;ASCII CODE FOR OEH
DB 'F' ;ASCII CODE FOR OFH
The background program may reach this subroutine be needed until later. The example below converts the
with several different calling sequences, all of which three-digit BCD value computed in the Radix Conver-
PUSH a value before calling the routine and POP the sion example above to a three-character string, calling a
result to any destination register or port later. There is subroutine SP _OUT to output an eight-bit code in the
even the option of leaving a value on the stack if it won't accumulator.
5-5 AFN-01739A
PUSH HUND
CALL HEXASC ;CONVERT HUNDREDS DIGIT
POP ACC
CALL SP_OUT ;TRANSMIT HUNDREDS CHARACTER
PUSH TENONE
CALL HEXASC ;CONVERT ONE'S PLACE DIGIT
;BUT LEAVE ON STACK!
MOV A, TENONE
SWAP A ;RIGHTJUSTIFY TEN'S PLACE
PUSH ACC ;CONVERT TEN'S PLACE DIGIT
CALL HEXASC
POP ACC
CALL SP_OUT ;TRANSMIT TEN'S PLACE CHARACTER
POP ACC
CALL SP_OUT ;TRANSMIT ONE'S PLACE CHARACTER
NWay Branching
There are several different means for branching to sec- execution. The instruction adds the eight-bit unsigned
tions of code determined or selected at run time. (The accumulator contents with the contents of the sixteen-
single destination addresses incorporated into condi- bit data pointer, just like MOVe A,@A+ DPTR. The
tional and unconditional jumps are, of course, fixed at resulting sum is loaded into the program counter and is
assembly time.) Each has advantages for different ap- used as the address for subsequent instruction fetches.
plications. Again, a sixteen-bit addition is performed: a carry-out
from the low-order eight-bits may propagate through
In a typical N-way branch situation, the potential the higher-order bits. In this case, neither the ac-
destinations are generally known at assembly time. One cumulator contents nor the data pointer is altered.
of a number of small routines is selected according to
the value of an index variable determined while the pro- The example subroutine below reads a byte of RAM in-
gram is running. The most efficient way to solve this to the accumulator from one of four alternate address
problem is with the MOVe and an indirect jump in- spaces, as selected by the contents of the variable
struction, using a short table of offset values in ROM to MEMSEL. The address of the byte to be read is deter-
indicate the relative starting addresses of the several mined by the contents of RO (and optionally Rl). It
routines. might find use in a printing terminal application, where
four different model printers all use the same ROM
JMP @A+ DPTR is an instruction which performs an code but use different types (and sizes) of buffer
indirect jump to an address determined during program memory for different speeds and options.
,
MEMSEL EQU R3
,
JUMP_4: MOV A,MEMSEL
MOV DPTR,#JMPTBL
MOVC A,@A+DPTR
JMP @A+DPTR
JMPTBL: DB MEMSPOJMPTBL
DB MEMSP1JMPTBL
DB MEMSP2JMPTBL
DB MEMSP3JMPTBL
MEMSPO: MOV A,@RO ;READ FROM INTERNAL RAM
RET
MEMSP1: MOVX A,@RO ;READ 256 BYTE EXTERNAL RAM
RET
MEMSP2: MOV DPL,RO ;READ 64K BYTE EXTERNAL RAM
MOV DPH,R1
MOVX A,@DPTR
RET
5-6 AFN01739A
MEMSP3: MOV A,R1 ;READ 4K BYTE EXTERNAL RAM

ANL A,#07H
ANL P1,#11111000B
ORL P1,A
MOVX A,@RO
RET
To use this approach, the size of the jump table plus the For applications where up to 128 destinations must be
length of the alternate routines must be less than 256 selected, all residing in the same 2K page of program
bytes. The jump table and routines may be located memory, the following technique may be used. In the
anywhere in program memory and are independent of printing terminal example, this sequence could process
256-byte program memory pages. 128 different codes for ASCII characters arriving via the
80S! serial port.
,
OPTION EOU R3
JMP128: MOV A,OPTION

RL A ;MULTIPLY BY 2 FOR 2BYTE JUMP TABLE
MOV DPTR,#INSTBL ;FIRST ENTRY IN JUMP TABLE
JMP @A+DPTR ;JUMP INTO JUMP TABLE
,
INSTBL: AJMP PROCOO ;128 CONSECUTIVE
AJMP PROC01 ;AJMP INSTRUCTIONS
AJMP PROC02
AJMP PROC7E
AJMP PROC7F
The destinations in the jump table (PROCOO-PROC7F) handled by computing the destination address at run-
are not all necessarily unique routines. A large number time with standard arithmetic or table look-up instruc-
of special control codes could each be processed with tions, then performing an indirect branch to that ad-
their own unique routine, with the remaining printing dress. There are two simple ways to execute this last
characters all causing a branch to a common routine for step, assuming the 16-bit destination address has
entering the character into the output queue. already been computed. The first is to load the address
into the DPH and DPL registers, clear the accumulator
and branch using the JMP @A + DPTR instruction; the
Computing Branch Destinations
second is to push the destination address onto the stack,
at Run Time
low-order byte first (so as to mimic a call instruction)
In some rare situations, 128 options are insufficient, the then pop that address into the PC by performing a
destination routines may cross a 2K page boundary, or a return instruction. This also adjusts the stack pointer to
branch destination is not known at assembly time (for its previous value. The code segment below illustrates
whatever reason), and therefore cannot be easily includ- the latter possibility.
ed in the assembled code. These situations can all be
RTEMP EOU R7
JMP256: MOV DPTR,#ADRTBL ;FIRST ADDRESS TABLE ENTRY

MOV A,OPTION ;LOAD INDEX INTO TABLE
CLR C
RLC A ;MULTIPLY BY 2 FOR 2BYTE JUMP TABLE
JNC LOW128
INC DPH ;FIX BASE IF INDEX >127.
5-7 AFN01739A
LOW128: MOV RTEMP,A ;SAVE ADJUSTED ACC FOR SECOND READ

INC A ;READ lOWORDER BYTE FIRST
MOVC A,@A+DPTR ;GET lOWORDER BYTE FROM TABLE
PUSH ACC
MOV A,RTEMP ;RElOAD ADJUSTED ACC
MOVC A,@A+DPTR ;GET HIGHORDERED BYTE FROM TABLE
PUSH ACC
THE TWO ACC PUSHES HAVE PRODUCED

A "RETURN ADDRESS" ON THE STACK WHICH CORRESPONDS
TO THE DESIRED STARTING ADDRESS.
IT MAY BE REACHED BY POPPING THE STACK
INTO THE PC.
RET
,
ADRTBl: OW PROCOO ;UP TO 256 CONSECUTIVE DATA
OW PROC01 ;WORDS INDICATING STARTING ADDRESSES
OW PROCFF
In-line-Code Parameter-Passing
Parameters can be passed by loading appropriate variable in internal RAM and stores the sum in a dif-
registers with values before calling the subroutine. This ferent two-byte buffer. The utility must be given the
technique is inefficient if a lot of the parameters are constant and both buffer addresses. Rather than using
constants, since each would require a separate register four working registers to carry this information, all four
to carry it, and a separate instruction to load the register bytes could be inserted into program memory each time
each time the routine is called. the utility is called. Specifically, the calling sequence
below invokes the utility to add 1234 (decimal) with the
If the routine is called frequently, a more code-efficient string at internal RAM address 56H, and store the sum
way to transfer constants is "in-line-code" parameter- in a buffer at location 78H.
passing. The constants are actually part of the program
code, immediately following the call instruction. The The ADDBCD subroutine determines at what point the
subroutine determines where to find them from the call was made by popping the return address from the
return address on the stack, and then reads the stack into the data pointer high- and low-order bytes. A
parameters it needs from program memory. MOVC instruction then reads the parameters from pro-
gram memory as they are needed. When done, ADD-
For example, assume a utility named ADDBCD adds a BCD resumes execution by jumping to the instruction
16-bit packed-BCD constant with a two-byte BCD following the last parameter.
CAll ADDBCD
OW 1234H ;BCD CONSTANT
DB 56H ;SOURCE STRING ADDRESS
DB 78H ;DESTINATION STRING ADDRESS
;CONTINUATION OF PROGRAM
58 AFN-01739A
ADDBCD: pOP DPH ;POP RETURN ADDRESS INTO DPTR

POP DPL
MOV A,#2 ;INDEX FOR SOURCE STRING PARAMETER
MOVC A,@A+DPTR ;GET SOURCE STRING LOCATION
MOV RO,A
MOV A,#3 ;INDEX FOR DESTINATION STRING PARAMETER
MOVC A,@A+DPTR ;GET DESTINATION ADDRESS
MOV R1,A
MOV A,#1 ;INDEX FOR 16BIT CONSTANT LOW BYTE
MOVC A,@A+DPTR ;GET LOWORDER VALUE
ADD A,@RO ;COMPUTE LOWORDER BYTE OF SUM
DA A ;DECIMAL ADJUST FOR ADDITION
MOV @R1,A ;SAVE IN BUFFER
INC RO
INC R1
CLR A ;INDEX FOR HIGHBYTE == 0
MOVC A,@A+DPTR ;GET HIGHORDER CONSTANT
ADDC A,@RO
DA A ;DECIMAL ADJUST FOR ADDITION
MOV @R1,A ;SAVE IN BUFFER
MOV A,#4 ;INDEX FOR CONTINUATION OF PROGRAM
JMP @A+DPTR ;JUMP BACK INTO MAIN PROGRAM
This example illustrates several points: pushed these registers onto the stack (after popping
the parameter list starting address), and popped
1) The "subroutine" does not end with a normal return before returning.
statement; instead, an indirect jump relative to the
data pointer returns execution to the first instruc- Passing parameters through in-line-code can be used in
tion following the parameter list. The two initial conjunction with other variable passing techniques.
POP instructions correct the stack pointer contents.
The utility can also get input variables from working
2) Either an ACALL or LCALL works with the registers or from the stack, and return output variables
subroutine, since each pushes the address of the to registers or to the stack.
next instruction or data byte onto the stack. The
call may be made from anywhere in the full 8051 PERIPHERAL INTERFACING
address space, since the MOVC instruction accesses
TECHNIQUES
all 64K bytes.
1/0 Port Reconfiguration (First Approach)
3) The parameters passed to the utility can be listed in
whatever order is most convenient, which may not 110 ports must often transmit or receive parallel data in
be that in which they're used. The utility has essen- formats other than as eight-bit bytes. For example, if an
tially "random access" to the parameter list, by application requires three five-bit latched output ports
loading the appropriate constant into the ac- (called X, Y, and Z), these "virtual" ports could be
cumulator before each MOVC instruction. mapped onto the pins of "physical" ports 1 and 2 as
shown below:
4) Other than the data pointer, the whole calling and
processing sequence only affects the accumulator,
PSW and pointer registers. The utility could have
PORT "Z" PORT "Y" PORT "X"
PZO PZI PZ2 PZ3 PZ4 PY4 PY3 PY2 PYI PYO PX4 PX3 PX2 PXI PXO
P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.I P2.0 Pl.7 Pl.6 Pl.5 PIA Pl.3 Pl.2 PI.I PI.O
This pin assignment leaves P2.7 free for use as a test

pin, input data pin, or control output through software.
59 AFN-01739A
Notice that the bits of port Z are reversed. The highest- Writing to the virtual ports must not affect any other
order port Z pin corresponds to pin P2.2, and the pins. Since the virtual output aigorithms are non-trivial,
lowest-order pin of port Z is P2.6, due to P.e. board a subroutine is needed for each port: OUT_PX,
layout considerations. When connecting an 8051 to an OUT_PY and OUT_PZ. Each is called with data to
immediately adjacent keyboard column decoder or output right-justified in the accumulator, and any data
another device with weighted inputs, the corresponding in bits ACe.7-ACC.5 is insignificant. Each subroutine
pins may not be aligned. The interconnections must be saves the data in a "map" variable for the virtual port,
"scrambled" to compensate either with interwoven then calls other subroutines which use the data in the
circuit board traces or through software (as shown various map bytes to compute and output the eight-bit
below). pattern needed for each physical port affected.
PX_MAP DATA 20H

PY_MAP DATA 21H
PZ_MAP DATA 22H
OUT_PX: ANL A,#00011111 B ;CLEAR BITS ACC.7 ACC. 5

MOV PX_MAP,A ;SAVE DATA IN MAP BYTE
ACALL OUT_P1 ;UPDATE PORT 1 OUTPUT LATCH
RET
OUT_PY: MOV PY_MAP,A ;SAVE IN MAP BYTE

ACALL OUT_P1 ;UPDATE PORT 1
ACALL OUT_P2 ;AND PORT 2 OUTPUT LATCHES
RET
,
OUT_PZ: MOV PZ_MAP,A ;SAVE DATA IN MAP BYTE
ACALL OUT_P2 ;UPDATE PORT 2.
RET
,
OUT_P1: MOV A,PY_MAP ;OUTPUT ALL P1 BITS
SWAP A
RL A ;SHIFT PY_MAP LEFT 5 BITS
ANL A,#11100000B ;MASK OUT GARBAGE
ORL A,PX_MAP ;INCLUDE PX_MAP BITS
MOV P1,A
RET
,
OUT_P2: MOV C,PZ_MAP.O ;LOAD CY WITH P2.6 BIT
RLC A ;AND SHIFT INTO ACC.
MOV C,PZ_MAP.1 ;LOAD CY WITH P2.5 BIT
SETB ACC.7 ;(ASSUMING INPUT ON P2.7)
MOV P2.A
RET
The two level structure of the above subroutines can be corresponding ACALL instructions. OUT_PY would
modified somewhat if code efficiency and execution not be changed, but now the destinations for its
speed are critical: incorporate the code shown as ACALL instructions would be alternate entry points in
subroutines OUT_PI and OUT_P2 directly into the OUT_PX and OUT_PZ, instead of isolated
code for OUT_PX and OUT_PZ, in place of the subroutines.
5-10 AFN01739A
1/0 Port Reconfiguration

(Second Approach)
A trickier situation arises if two sections of code which One solution is to disable interrupts around any section
write to the same port or register, or call virtual output of code which must not be interrupted (called a "critical
routines like those above, need to be executed at section"), but this would adversely affect interrupt
different interrupt levels. For example, suppose the latency. Another is to have interrupt routines set or
background program wants to rewrite Port X (using the clear a flag ("semaphore") when a common resource is
port associations in the previous example), and has altered - a rather complex and elaborate system.
computed the bit pattern needed for PI. An interrupt is
detected just before the MOY Pl,A instruction, and the An easier way to ensure that any instruction which
service routine tries to write Port Y. The service routine writes the port X field of PI does not change the port Y
would correctly update PI and P2, but upon returning field pins from their state at the beginning of that
to the background program PI is immediately re-written instruction, is shown next. A number of 8051 operations
with the data computed before the interrupt! Now pins read, modify, and write the output port latches all in
P2.1 and P2.0 indicate (correctly) data written to port Y one instruction. These are the arithmetic and logical
in the interrupt routine, but the earlier data written to instructions (INC, DEC, ANL, ORL, etc.), where an
PI.7-Pl.5 is no longer valid. The same sort of confusion addressed byte is both the destination variable and one
could arise if a high-level interrupt disrupted such an of the source operands. Using these instructions, instead
output sequence. of data moves, eliminates the critical section problem
entirely.
OUT_PX: ANL P1 ,#111 OOOOOB ;CLEAR BITS P1.4 . P1.0

ORL P1,A ;SET P1 PIN FOR EACH ACC BIT SET.
RET
OUT_ PY: MOV B,#20H

MUL AB ;SHIFT <B><A> LEFT 5 BITS.
ANL P1,#00011111B ;CLEAR PY FIELD OF PORT 1
ORL P1,A ;SET PY BITS ON PORT 1
MOV A,B ;LOAD 2 BITS SHIFTED INTO B
ANL P2,#11111100B ;AND UPDATE P2
ORL P2,A
RET
,
OUT PZ: RRC A ;MOVE ORIGINAL ACC.O INTO CY
MOV P2.6,C ;AND STORE TO PIN P2.6.
RRC A ;MOVE ORIGINAL ACC.1 INTO CY
MOV P2.S,C ;AN D STORE TO PIN P2.S.
RCC A ;MOVE ORIGINAL ACC.2 INTO CY
RET
8243 Interfacing
The 8051's quasi-bidirectional port structure lets each Even though the 8051 does not include 8048-type
110 pin input data, output data, or serve as a test pin or instructions for interfacing with an 8243, the parts can
output strobe under software control. An example of be interconnected and the protocol may be emulated
these modes operating in conjunction is the host- with simple software; see Figure 5.2.
processor interface expected by an 8243 110 expander.
5-11 AFN-01739A
,
;IN8243 INPUT DATA FROM AN 8243 I/O EXPANDER
CONNECTED TO P23P20.
P25 & P24 MIMIC CS &PROG.
P27P26 USED AS INPUTS. CODE FOR
PORT TO BE READ IN ACC.1ACC.0
,
PROG BIT P2.4 ;SYMBOLIC PIN DESCRIPTION
,
IN8243: ORL A,#11010000B ;SET PROG AND PINS USED AS INPUT
MOV P2,A ;OUTPUT PORT CODE AND OPERATION CODE
CLR PROG ;LOWER PROG TO LATCH ADDRESS
ORL P2,#00001111 B ;SET LOW ORDER PINS FOR INPUT
MOV A,P2 ;READ IN PORT DATA
ORL P2,#00110000B ;SET PROG AND CS HIGH
Software Delay Timing

Many 8051 applications involve exact control over delay into a piece of code, adding a moderate time delay
output timing. A software-generated output strobe, for of two instruction cycles per iteration. For example, two
instance, might have to be exactly 50 p.sec. wide. The instructions can add a 49-p.sec. software delay loop to
DJNZ operation can insert a one instruction software code to generate a pulse on the WR pin.
CLR WR
MOV R2,#24
DJNZ $2,$
SETB WR
The dollar sign in this example is a special character

meaning "the address of this instruction." It can be used 8351
to eliminate instruction labels on nearby source lines. 8751
8243
P4
P2.7
Serial Port and Timer Mode Configuration P2.&
} INPUTS
P2.5 cs P5
Configuring the 8051's Serial Port for a given data rate P2.4 PROG
and protocol requires essentially three short sections of
software. On power-up or hardware reset the serial port P2.3 P23 P&
P2.2 P22
and timer control words must be initialized to the P2.1 P21
appropriate values. Additional software is also needed P2.0 P20 P7
in the transmit routine to load the serial port data
register and in the receive routine to unload the data as
it arrives. Figure 52. Connecting an 8051 with an 8243
1/0 Expander
To choose one arbitrary example, assume the 8051
should communicate with a standard CRT operating at
2400 baud (bits per second). Each character is the output software know the output register is
transmitted as seven data bits, odd parity, and one stop available. All this can be set up with instruction at label
bit. The resulting character rate is 2400 baud/9bits, SPINIT.
approximately 265 characters per second.
Timer 1 will be used in auto-reload mode as a baud rate
For the sake of clarity, the transmit and receive generator. To achieve a data rate of 2400 baud, the
subroutines here are driven by simple-minded software timer must divide the IMHz internal clock by
status polling code rather than interrupts. The serial
port must be initialized to 8-bit UART mode (SMO, 1 x 106
SMI = 01), enabled to receive all messages (SM2=0, (32) (2400)
REN = 1). The flag indicating that the transmit register
is free for more data will be artificially set in order to let which equals 13 (actually, 13.02) instruction cycles. The
512 AFN01739A
timer must reload the value -13, or OF3H, as shown by

the code at label TIINIT. (ASM51 will accept both the
signed decimal or hexadecimal representations.)
INITIALIZE SERIAL PORT

FOR aBIT UART MODE
, & SET TRANSMIT READY FLAG.
SPINIT: MOV SCON,#01010010B
INITIALIZE TIMER 1 FOR
AUTORELOAD AT 32 X 2400HZ
(TO USED AS GATED 16BIT COUNTER.)
;TIINIT: MOV TCON,#11010010B
MOV TH1,#13
SETB TR1
Simple Serial 1/0 Drivers

SP _OUT is a simple subroutine to transmit the SP _IN is an equally simple routine which waits until a
character passed to it in the accumulator. First it must character is received, sets the carry flag if there is an
compute the parity bit, insert it into the data byte, wait odd-parity error, and returns the masked seven-bit code
until the transmitter is available, output the character, in the accumulator.
and then return.
,
;SP_OUT ADD ODD PARITY TO ACC AND
TRANSMIT WHEN SERIAL PORT READY.
,
SP_OUT: MOV C,P
CPL C
MOV ACC.7,C
JNB TI,$
CLR TI
MOV SBUF,A
RET
INPUT NEXT CHARACTER FROM SERIAL PORT.

SET CARRY IF ODDPARITY ERROR
,
SP IN: JNB RI,$
CLR RI
MOV A,SBUF
MOV C,P
CPL C
ANL A,#7FH
RET
Transmitting Serial Port Character

Strings
Any application which transmits characters through a messages, diagnostics, or operator instructions. These
serial port to an ASCII output device will on occasion character strings are most easily defined with in-line
need to output "canned" messages, including error data bytes defined with the DB directive.
5-13 AFN-01739A
CR EaU ODH ;ASCII CARRIAGE RET

LF EaU OAH ;ASCII LlNEFEED
ESC EaU 1BH ;ASCII ESCAPE CODE
CALL XSTRING
DB CR,LF ;NEW LINE
DB 'INTEL DELIVERS' ;MESSAGE
DB ESC ;ESCAPE CHARACTER
(CONTINUATION OF PROGRAM)
,
XSTRING: POP DPH ;LOAD DPTR WITH FIRST CHARACTER
POP DPL
XSTR_1: CLR A ;(ZERO OFFSET)
MOVC A,@A+DPTR ;FETCH FIRST CHARACTER OF STRING
XSTR_2: JNB TI,$ ;WAIT UNTIL TRANSMITTER READY
CLR TI ;MARK AS NOT READY
MOV SBUF,A ;OUTPUT NEXT CHARACTER
INC DPTR ;BUMP POINTER
CLR A
MOVC A,@A+DPTR ;GET NEXT OUTPUT CHARACTER
CJNE A,#ESC,XSTR_2 ;LOOP UNTIL ESCAPE READ
MOV A,#1
JMP @A+DPTR ;RETURN TO CODE AFTER ESCAPE
Recognizing and Processing

Special Cases
Before operating on the data it receives, a subroutine <BEL>,<ESC>, or <SP must invoke corresponding
might give "special handling" to certain input values. special routines. Any other character with an ASCII
Consider a word processing device which receives code less than 20H should be translated into the <NUL>
ASCII characters through the 8051 serial port and value, OOH, and processed with the printing characters.
drives a thermal hard-copy printer. A standard routine The CJNE operation provides essentially a one-
translates most printing characters to bit patterns, but instruction CASE statement.
certain control characters DEL>, <CR>, <LF>,
,
CHAR EaU R7 ;CHARACTER CODE VARIABLE
INTERP: CJNE CHAR,#7FH, INTP_1 ;SKIP UNLESS RUBOUT

(SPECIAL ROUTINE FOR RUBOUT CODE)
RET
INTP_1: CJNE CHAR,#07H,INTP _2 ;SKIP UNLESS BELL
(SPECIAL ROUTINE FOR BELL CODE)
RET
INTP_2: CJNE CHAR,#OAH,INTP_3 ;SKIP UNLESS LFEED
(SPECIAL ROUTINE FOR LFEED CODE)
RET
INTP_3: CJNE CHAR,#ODH,INTP_4 ;SKIP UNLESS RETURN
(SPECIAL ROUTINE FOR RETURN CODE)
RET
INTP_4: CJNE CHAR,#1 BH,INTP_5 ;SKIP UNLESS ESCAPE
(SPECIAL ROUTINE FOR ESCAPE CODE)
RET
INTP_5: CJNE CHAR,#20H,INTP _6 ;SKIP UNLESS SPACE
(SPECIAL ROUTINE FOR SPACE CODE)
RET
INTP_6: JC PRINTC ;JUMP IF CODE> 20 H
MOV CHAR,#O ;REPLACE CONTROL CHARACTER WITH
;NULL CODE
514 AFN-01739A
PRINTC: ;PROCESS STANDARD PRINTING

;CHARACTER
RET
Buffering Serial Port Output Characters

It is not always efficient to transmit characters through letting an interrupt routine transmit each character as
the serial port one-at-a-time. Most applications generate the serial port becomes available.
a short burst of characters all at once (English words or
multi-digit numbers, for instance), with the bursts Assume there is a 16-byte output data buffer starting at
themselves occurring at longer intervals. Instead of 70H. QHEAD and QT AIL keep track of the head and
waiting while the UART outputs each character, it tail portion of the buffer being used. The subroutine
would be more efficient if the background program ENTERQ waits until there is space in the queue, then
could enter all the characters into a first-in first-out copies a character code from the accumulator to the
(FIFO) data structure, and continue about its business, queue.
QHEAD DATA 6EH ;LAST BYTE ENTERED INTO QUEUE

QTAIL DATA 6FH ;LAST BYTE READ FROM QUEUE.
BOTLIM EQU 70H
TOPLIM EQU 7FH
QUEUE IS EMPTY WHEN QHEAD = QTAIL AND

FULL WHEN QHEAD + 1 (WITHIN RANGE) = QTAIL.
MOV QHEAD,#TOPLIM
MOV QTAIL,#TOPLIM
ENTERQ: MOV RO,A ;SAVE ACC DATA

MOV A,QHEAD ;LOAD HEAD POINTER
INC A ;PREINCREMENT POINTER
CJNE A,#TOPLIM + 1,ENTQ_1
MOV A,#BOTLIM ;RELOAD ON OVERFLOW
ENTQ_1: CJNE A,QTAIL,ENTQ_2 ;TEST IF QUEUE FULL
SJMP ENTQ_1 ;LOOP UNTIL SPACE AVAILABLE
ENTQ_2: XCH A,RO ;STORE POINTER AND RELOAD ACC
MOV @RO,A ;ENTER INTO QUEUE
MOV QHEAD,RO ;UPDATE HEAD POINTER
SETB ES ;ENABLE SERIAL PORT INTERRUPTS
RET
The interrupt routine DQUEUE is invoked when the fer (SBUF) and the pointers are updated. If not,
transmitter is ready for another character. First it deter- DQUEUE disables serial port interrupts and returns to
mines if any characters are available for transmission, the background program. ENTERQ will re-enable such
indicated by QHEAD and QT AIL being not equal. If interrupts as more data is available. (This example does
more data is available, it is written to the transmit buf- not consider interrupt-driven serial input.)
ORG 0023H
PUSH ACC ;SAVE CPU STATUS
PUSH PSW
MOV PSW,#30Q ;SELECT BANK 3
DQUEUE: MOV A,QTAIL
CJNE A,QHEAD,DQ_1 ;TEST IF QUEUE EMPTY
CLR ES ;IF SO, CLEAR ENABLE BIT AND RETURN
SJMP TI_RET
515 AFN-01739A
CLR TI ;ELSE ACKNOWLEDGE REQUEST

INC A ;COMPUTE NEXT BYTE'S ADDRESS
CJNE A,#TOPLIM + 1,DQ_2
MOV A,#BOTLIM :REVISE ACC IF POI'NTER OVERFLOWED
MOV RO,A ;LOAD INDEX REGISTER
MOV SBUF,@RO ;RELOAD TRANSMITTER
MOV QTAIL,A ;SAVE LAST POINTER USED.
POP PSW ;RESTORE STATUS AND RETURN
POP A
RETI
Synchronizing Timer Overflows

8051 timer overflows automatically generate an internal interrupt interval (averaged over time) must be accurate
interrupt request, which will vector program execution to 1 instruction cycle, the 16-bit value reload into the
to the appropriate interrupt service routine if interrupts timer must be computed, taking into account when the
are enabled and no other service routines are in progress timer actually overflowed.
at the time. However, it is not predictable exactly how
long it will take to reach the service routine. The service This simply requires reading the appropriate timer,
routine call takes two instruction cycles, but 1, 2, or 4 which has been incremented each cycle since the
additional cycles may be needed to complete the instruc- overflow occurred. A sequence like the one below can
tion in progress. If the background program ever stop the timer, compute how much time should elapse
disables interrupts, the response latency could further before the next interrupt, and reload and restart the
increase by a few instruction cycles. (Critical sections timer. The double-precision calculation shown here
generally involve simple instruction sequences - rarely compensates for any amount of timer overrun within
multiplies or divides.) Interrupt response delay is the maximum interval. Note that it also takes into ac-
generally negligible, but certain time-critical application count that the timer is stopped for seven instruction
must take the exact delay into account. For example, cycles in the process. All interrupts are disabled, so a
generating interrupts with timer 1 every millisecond higher priority request will not be able to disrupt the
(1000 instruction cycles) or so would normally call for time-critical code section.
reloading it with the value - 1000 (OFC30H). But if the
CLR EA ;DISABLE ALL INTERRUPTS

CLR TR1 ;STOP TIMER 1
MOV A,#LOW(-1000+ 7) ;LOAD LOWORDER DESIRED COUNT
ADD A,TL1 ;CORRECT FOR TIMER OVERRUN
MOV TL1,A ;RELOAD LOWORDER BYTE.
MOV A,#HIGH(-1000+ 7) ;REPEAT FOR HIGHORDER BYTE.
ADDC A,TH1
MOV TH1,A
SETB TH1 ;RESTART TIMER
Reading a Timer/Counter "OntheFly"

The preceding example simply stopped the timer before <RO> a sixteen-bit value indicating the count in timer O.
changing its contents. This is normally done when The instant at which the count was sampled is not as
reloading a timer so that the time at which the timer is critical as the fact that the value returned must have
started (i.e. the "run" flag is set) can be exactly con- been valid at some point while the routine was in pro-
trolled. There are situations, though, when it is desired gress. There is a potential problem that between reading
to read the current count without disrupting the timing the two halves, a low-order register overflow might in-
process. The 8051 timer/counter registers can all be read crement the high-order register, and the two data bytes
or written while they are running, but a few precautions returned would be "out of phase." The solution is to
must be taken. read the high-order byte first, then the low-order byte,
and then confirm that the high-order byte has not
Suppose the subroutine RDTIME should return in <Rl> changed. If it has, repeat the whole process.
5-16 AFN01739A
RDTIME: MOV A,THO ;SAMPLE TIMERO (HIGH)

MOV RO,TLO ;SAMPLE TIMERO (LOW)
CJNE A,THO,RDTIME ;REPEAT IF NECESSARY
MOV R1,A ;STORE VALID READ
RET
5-17 AFN01739A
8031/8051/8751
SINGLE-COMPONENT 8-BIT MICROCOMPUTER
8031 . Control Oriented CPU With RAM and I/O

8051 . An 8031 With Factory MaskProgrammable ROM
8751 . An 8031 With User ProgrammabletErasable EPROM
4K x 8 ROM/EPROM Boolean Processor

Four 8Bit
128x 8 RAM NonPaged Jumps
MCS48 Architecture Enhanced with:
Two 16BitPorts, 32 I/O Lines
HighPerformance FullDuplex
Timer/Event Counters Direct Addressing
Serial Channel Four 8Register Banks
Stack Depth Up to 128Bytes
Compatible
External Memory Expandable to 128K

Multiply, Divide, Subtract, Compare
Peripheralswith MCS80 /MCS85 Most Instructions Execute in 1jJs
4J.Js Multiply and Divide
The Intel 8031/8051/8751 is a stand-alone, high-performance single-chip computer fabricated with Intel's highly-reliable
+ 5 Volt, depletion-load, N-Channel, silicon-gate HMOS technolgy and packaged in a40-pin DIP.lt provides the hardware
features, architectural enhancements and new instructions that are necessary to make it a powerful and cost effective
controller for applications requiring up to 64K bytes of program memory and/or up to 64K bytes of data storage.
The 8051/8751 contains a non-volatile 4K x 8 read only program memory; a volatile 128 x 8 read/write data memory; 32110
Iines; two 16-bit timer/counters; a five-source, two-priority-Ievel, nested interrupt structure; a serial 110 port foreither multi-
processor communications, I/O expansion, or full duplex UART; and on-chip oscillator and clock circuits. The 8031 is in-
dentical, except that it lacks the program memory. For systems that require extra capabi lity, the 8051 can be expanded us-
ing standard TTL compatible memories and the byte oriented MCS-80 and MCS-85 peripherals.
The 8051 microcomputer, like its 8048 predecessor, is efficient both as a controller and as an arithmetic processor. The
8051 has extensive facilities for binary and BCD arithmetic and excels in bit-handling capabilities. Efficient use of pro-
gram memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% three-byte instructions.
With a 12 MHz crystal, 58% of the instructions execute in 1 ).IS, 40% in 2).1s and multiply and divide requireonly4 ).Is. Among
the many instructions added to the standard 8048 instruction set are multiply, divide, subtract and compare.
FREQUENCY
REFERENCE
-1
I
I
'--~--' ,
I
,
""-----'""---.',
I
.........--,--' I
r RXD
TXO~__
;:=: ;
t w-
L n __ AD
TO--. ~
PARALLEL PORTS,
ADDRESS/DATA BUS,
AND 1/0 PINS
SERIAL
IN
SERIAL
OUT t WA4-
RD4-
Figure 1. Figure 2. Figure 3. Pin

Block Diagram Logic Symbol Configuration
Intel Corporalion Assumes No Responsibilily for the Use of any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenses are Implied.
INTELCORPORATION,1980
6-1
8031/8051/8751
8051 FAMilY PIN DESCR!PTION for cou nter O.

- INT1 (P3.3). Interrupt 1 input or gate control
Vss input for counter 1.
Circuit ground potential.
Vee - TO (P3.4). Input to counter O.
+5V power supply during operation, programming -- T1 (P3.5). Input to counter 1.
and verification. - WR (P3.6). The write control signal latches the
Port 0 data byte from Port 0 into the External Data
Memory.
Port 0 is an 8-bit open drain bidirectional I/O port.
It is also the multiplexed low-order address and data - RD (P3.7). The read control signal enables External
bus when using external memory. It is used for data Data Memory to Port O.
input and output during programming and verifica- RST/VPD
tion. Port 0 can sink/source two TTL loads. A low to high transition on this pin (at approximately
Port 1 3V) resets the 8051. If VpD is held within its spec
Port 1 is an 8-bit quasi-bidirectional I/O port. It is (approximately +5V), while VCC drops below spec,
used for the low-order address byte during program- VpD will provide standby power to the RAM. When
ming and verification'. Port 1 can sink/source one VpD is low, the RAM's current is drawn from VCe-
TTL load.
ALE/PROG
Port 2 Provides Address Latch Enable output used for
Port 2 is an 8-bit quasi-bidirectional I/O port. It also latching the address into external memory during
emits the high-order 8 bits of address when accessing normal operation. Receives the program pulse
external memory. It is used for the high-order address input during EPROM programming.
and the control signals during programming and
verification. Port 2 can sink/source one TTL load. PSEN
The Program Store Enable output is a control signal
Port 3 that enables the external Program Memory to the
Port 3 is an 8-bit quasi-bidirectional I/O port. It also bus during normal fetch operations.
contains the interrupt, timer, serial port and RD and
WR pins that are used by various options. The out- EA/VDD
put latch corresponding to a special function must When held at a TTL high level, the 8051 executes
be programmed to a one (1) for that function to instructions from the internal ROM/EPROM when
operate. Port 3 can sink/source one TTL load. The the PC is less than 4096. When held at a TTL low
special functions are assigned to the pins of Port 3, level, the 8051 fetches all instuctions from external
as follows: Program Memory. The pin also receives the 21V
-RXD/data (P3.0). Serial port's receiver data input EPROM programming supply Voltage.
(asynchronous) or data input/output (synchro- XTAL1
nous).
Input to the oscillator's high gain amplifier. A crystal
- TXD/clock (p3.1). Serial port's transmitter data or external source can be used.
output (asynchronous) or clock output (synchro-
nous). XTAL2
- INTO (P3.2). Interrupt 0 input or gate control input Output from the oscillator's amplifier. Required when
a crystal is used.
6-2
inter 8031/8051/8751
* NOTICE.' Stresses above those listed under "Absolute

ABSOLUTE MAXIMUM RATINGS* Maximum Ratings" may cause permanent damage to the
0 0
Ambient Temperature Under Bias .......... 0 C to 70 C device. This is a stress rating only and functional operation
Storage Temperature ...... ,' .. , ... , .. , , -65 0 C to +1500 C of the device at these or any other conditions above those
Voltage on Any Pin With indicated in the operational sections of this specification
Respect to Ground (VSS) .. , , ... , , ....... -0.5V to +7V is not implied. Exposure to absolute maximum rating con-
Power Dissipation "'.,.,', .. " . , " ' .. ',.,.",. 2 Watts ditions for extended periods may affect device reliability.
D.C. CHARACTERISTICS TA = OC TO 70C; VCC = 5V 5%; VSS = OV

Symbol Parameter Min. Typ. Max. Units Test Conditions
VIL Input Low Voltage (All except XTAL 1) -0.5 0.8 V
VIL1 Input Low Voltage (XTAL1) -0.5 TBD V
VIH Input High Voltage 2.0 VCC+0.5 V

(All Except XTAL 1, RSTIVPD)
VIH1 Input High Voltage (XTAL 1) TBD VCC+0.5 V
VIH2 Input High Voltage (RST) 3.0 VCC + 0.5 V
VIH3 Input High Voltage (VpD) 4.5 5.5 V Power Down Only
(VCC = 0)
VOL Output Low Voltage 0.45 V 1,6mA

(All Outputs Except Port 0)
VOL1 Output Low Voltage (Port 0) 0.45 V 3.2mA
VOH Output High Voltage (All Outputs 2.4 V IOH=-100tJA

Except Port 0, ALE and PSEN)
VOH1 Output High Voltage (ALE and PSEN, 2.4 V IOH:= -400 tJA
Port 0 In External Bus Mode)
ILO Pullup Resistor Current (P1, P2, P3) -500 tJA .45V5. VIN 5.VCC
IL01 Output Leakage Current (PO) :t10 pA .45V 5. VIN 5. VCC
ICC Power Supply Current 150 mA TA =25 C

(All Outputs Disconnected)
IpO Power Down Supply Current 20 mA TA=25C, VpO=5V,

VCC=OV
CIO Capacitance Of 1/0 Buffer 10 pF fc=1MHz
6-3
8031/8051/8751
A.C. CHARACTER!ST!CS
TA = OC TO 70C; VCC=5V5% Port 0, ALE and PSEN Outputs - CL = 150 PF;
All Other Outputs - CL = 80PF
Program Memory Characteristics

Variable Clock
12MHz Clock 1/TCLCL=1.2 MHz to 12 MHz
Symbol Parameter Min. Max. Units Min. Max. Units
TCLCL Oscillator Period 83 ns ns
TCY Min Instruction Cycle Time 1.0 J,Js 12TCLCL 12TCLCL ns
TLHLL ALE Pulse Width 140 ns 2TCLCL-30 ns
TAVLL Address Set Up To ALE 60 ns TCLCL-25 ns
TLLAX Address Hold After ALE 50 ns TCLCL-35 ns
TPLPH PSEN Width 230 ns 3TCLCL-20 ns
TLHLH PSEN, ALE Cycle Time 500 ns 6TCLCL ns
TPLIV PSEN To Valid Data In 150 ns 3TCLCL-100 ns

--
TPHDX Input Data Hold After PSEN 0 ns 0 ns
--
TPHDZ Input Data Float After PSEN 75 ns TCLCL-10 ns
TAVIV. Address To Valid Data In 320 ns 5TCLCL-100 ns
TAZPL Address Float To PSEN 0 ns 0 ns
External Data Memory Characteristics

12MHz Clock Variable Clock
Symbol Parameter Min. Max. Units Min. Max. Units
-
TRLRH RD Pulse Width 400 ns 6TCLCL-100 ns
TWLWH WR Pulse Width 400 ns 6TCLCL-100 ns

-
TRLDV RD To Valid Data In 250 ns 5TCLCL-170 ns
TRHDX Data Hold After RD 0 ns 0 ns

-
TRHDZ Data Float After RD 100 ns 2TCLCL-70 ns
TAVDV Address To Valid Data In 600 ns 9TCLCL-150 ns
TAVWL Address To WR or RD 200 ns 4TCLCL-130 ns

-
TQVWH Data Setup Before WR 400 ns 7TCLCL-180 ns
-
TWHQX Data Held After WR 80 ns 2TCLCL-90 ns
NOTE:
There are 2 to 8 ALE cycles per instruction. Clocks and state timing are shown on the timing diagram for reference purposes only. They are
not accessible outside the package. TCV is the minimum instruction cycle time which consists of 12 oscillator clocks or two ALE cycles.
Address setup and hold time from ALE are the same for data and program memory.
6-4
8031/8051/8751
OSC
ALE
PSEN
RD, WR
ADDRESS OR
PORT 2
SFR P2
PORT 0 FLOAT
Program Memory Read Cycle
ALE
PSEN
TRLRH
RD ~
PORT 2 ADDR ESS OR

ADDRESS A1S-AS SFR P2
-TAVWL
TRLDV-l r--- r---TRHDZ - .
TAVDV TRHDX-t
r-
PORT 0 INSTR IN !FLOAT)< A7- A O
I FLOAT )< DATA IN
I FLOAT
"@ RESS
OR FLOAT
Data Memory Read Cycle
ALE
PSEN
- TWLWH
WR ~
ADDR ESS OR
PORT 2 ADDRESS A1S-AS
SFR P2
TAVWL
TOVWH TWHOX--1
PORTO ADDR ESS

INSTR IN IFLOAT)< A7- A O DATA OUT
)< OR Fl OAT
Data Memory Write Cycle
6-5
8031/8051/8751
Serial Port Characteiistics

12 MHz Clock Variable Clock
Symbol Parameter
Min. Max. Min. Max.
TDVPl Data Setup to PROG 10IJs 3 Tey + 10/Js
TPHDX Data Hold from PROG 10IJs 3 Tey + 10IJs
TAVQV Address to Data Valid 10IJs 3 Tey + 1Ol-'S
TElQV Output Enable (P27) to Data Valid 10IJs 3 Tey + 10/Js
TEHQZ Output Enable Off to Data Float 0 10IJs 0 3 Tey + 10/Js
TVHPl VDD Setup to PROG 10IJs 10",s
TPHVl VDD Hold after PROG 10",s 10,",s
TPlPH PROG Width 49ms 51ms 49ms 51ms
Input and Output Waveforms for A.C. Tests
2.4
V 2.0 _2.0V
0.45
_______ ~A 0.8::' TEST POINTS - 0.8_ A"--_______
-
PROGRAM VERIFY
\~--1
PORT 27
r--+
PORT 1017 ADDRESS ADDRESS ADDRESS. 1
TAVPL "I" -\
ADDRESS
R- TPHAX TAvav
ADDRESS ADDRESS T 1
;,---------..~~T_EHaz _
PORT 0007 DATA OUT STABLE DATA IN
-------------~\
I" ~ I" TPLPH
~~----------------------------------------
PROG/ALE ~
_V_DD_/E_A_ _ _ _ T_V_HP_L_~_p_PJ"~ ~ ~~ __
TP_H_V_L_____________________________________________
NOTES: 1) PSEN = VIL, VPD/RST = VIH1

2) MSB of address is Port 23, LSB is Port 0
3) All levels are VIL, VIH, VOL, VOH except VDD/EA.
6-6
8021
SINGLE COMPONENT 8-BIT MICROCOMPUTER
8-Bit CPU, ROM, RAM, I/O in Single 1K x 8 ROM

28-Pin Package 64 x 8 RAM
21 I/O Lines
Single SV Supply (+4.SV to 6.SV)
Interval Timer IEvent Counter
8.38 }lsec Cycle With 3.58 MHz XTAl;
All Instructions 1 or 2 Cycles Clock Generated With Single Inductor
or Crystal
Instructions- 8048 Subset Zero-Cross Detection Capability

High Current Drive Capability-2 Pins Easily Expandable I I 0
The Intel@ 8021 is a totally self-sufficient 8-bit parallel computer fabricated on a single silicon chip using Intel's N-
channel silicon gate MOS process. The features of the 8021 include a subset of the 8048 optimized for low cost,
high volume applications, plus additional I/O flexibility and power.
The 8021 contains 1K X 8 program memory, a 64 X 8 data memory, 21 I/O lines, and an 8-bit timer / event counter, in
addition to on-board oscillator and clock circuits. For systems that require extra I/O capability, the 8021 can be
expanded using the 8243 or discrete logic.
This microprocessor is designed to be an efficient controller as well as an arithmetic processor. The 8021 has bit
handling capability as well as facilities for both binary and BCD arithmetic. Efficient use of program memory results
from an instruction set consisting mostly of single byte instructions and no instructions over two bytes in length.
To minimize the development problems and maximize flexibility, an 8021 system can be easily designed using the
8021 emulation board, the EM-1. The EM-1 contains a 40-pin socket which can accommodate either the 8748
shipped with the board or an ICE-49 plug. Also, the necessary discrete logic to reproduce the 8021 's additional 1/0
features is included.
P22 VCC
PORT P23
XTAL \ P21
Jt()
PROG P20
PORT POO P1l
#1 POl P16
RESET P02 P15
PORT
P03 P14
#2
TEST P04 P13
ADDRESS P05 P12
LATCH P06 P11
ENABLE
POl P10
PORT ALE RESET
EXPANDER Tl XTAL 2
STROBE
VSS XTAL 1

Intel Corporation Assumes No Responsibility for the Use of any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenses are Implied
INTELCORPORATION,1980 7-1 AFNQ1567AQ1
8021
ABSOLUTE MAXiiViUiVi RATINGS *i"}OTiCE: Stres,ses a.bova t"1ose listed under ",4bso!ute
Maximum Ratings" may cause permanent damage to the
Ambient Temperature Under Bias. . . . . . .. 0 C to 70 C
device. This is a stress rating only and functional opera-
Storage Temperature ............... -65C to +150C tion of the device at these or any other conditions above
those indicated in the operational sections of this specifi-
Voltage on Any Pin with cation is not implied. Exposure to absolute maximum
Respect to Ground .................... -0.5V to +7V rating conditions for extended periods may affect device
Power Dissipation .............................. 1 W reliability.
D.C. CHARACTERISTICS TA:;;: OC to 70C, VCC:;;: 5.5V 1V, VSS == OV
Symbol Parameter Limits

Unit Test Conditions
Min. Typ. Max.
VIL Input Low Voltage -0.5 0.8 V
VIH Input High Voltage (All except 3.0 Vee V
XTAL 1 & 2, T1 RESET)
VIH1 Input High Voltage (XTAL 1 & 2, 3.S Vce V
T1 RESET)
VIH(1o%) Input high voltage (All except XTAL 2.0 Vee V Vee:;;: 5.0V 10%
1 & 2, T1, RESET)
VIH1 (10%) Input high voltage (XTAL 1 & 2, 3.5 Vec V Vee:;;: 5.0V 10%
T1, RESET)
VOL Output Low Voltage OA5 V IOL:;;: 1.6 mA
VOL1 Ovtput Low Voltage (P1 0, P11) 2.. 5 V IOL:;;: 7 mA
VOH Ol)tput High Voltage 2.4 V IOH:;;: 40 p.A
(All unless Open Drain)
ILO Output Leakage Current 10 p.A VSS+0.45::::;;VIN::::;;Vee
(Open Drain Option - Port 0)
ICC VCC Supply Current 40 75 mA
T1 ZERO CROSS CHARACTERISTICS TA:;;: ooe to 70C, Vcc:;;: 5.5V 1V, VSS:;;: OV, CL = SOpF
Symbol Parameter Min. Max. Unit Test Conditions

VZX Zero-Cross Detection Input (T1) 1 3 VPP Ae Coupled, C =.2p.F
AZX Zero-Cross Accuracy 135 mV 60 Hz Sine Wave
FZX Zero-Cross Detection Input Frequency (T1) 0.05 1 kHZ
7-2 AFN-ol567 A-02

8021
Table 1. Pin Description

Desig- Pin Desig- Pin
nation No. Function nation No. Function
Vss 14 Circuit GND potential CNT instruction. Also allows
Vce 28 +5V power supply zero-crossover sensing of slowly
moving inputs.
PROG 3 Output strobe for 8243 I/O
Expander RESET 17 Input used to initialize the proc-
essor by clearing status flip-flops
POO-P07 4-11 8-bit quasi~bidirectional port and setting program counters to
Port 0 zero.
P10-P17 1825 8-bit quasi-btdii'ectional port ALE 12 Address Latch Enable. Signal
occurring once every 30 input
Port 1
clocks, used as an output clock.
P20-P23 26-27 4-bit quasi-bidl-recti(mal port
XTAL 1 15 One side of crystal or inductor
Port 2 1-2 P20-P23 also s:erve as a 4-bit I/O input for internal oscillator. Also
expander bus for 8243 input for external source. (Not
T1 13 Input pin testable using the JT1 TTL compatible.)
and JNT1 instructions. Can be XTAL2 16 Other side of timing control
designated t~.timer/event element.
counter input using the STRT
Table 2. Instruction Set Summary
Hexadecimal Hexadecimal
Mnemonic Description Bytes CYCle Opcode Mnemonic Description Byles Cycle Opcode
ADD A,R r Add register to A 1 1 6S-6F JMP addr Jump unconditional 2 2 04,24,44,64,
ADD A,@R Add data memory to A 1 1 60-61
ADD A,#data
Add immediate to A 2 2 03 JMPP @ A Jump indirect 1 2 B3
ADDC A,R rAdd register with carry 1 1 7S-7F J:. DJNZ R,ro addr Decrement register and 2 2 ES-EF
ADDC A,@R Add data memory with 1 1 70-71 g jump on R not zero
III
carry ~ JC addr Jump on carry= 1 2 2 F6
ADDC A,#data Add immediate with 2 2 13 JNC addr Jump on carry=O 2 2 E6
carry JZ addr Jump on A zero 2 2 C6
ANL A,R r And register to A 1 1 5S-5F JNZ addr Jump on A not zero 2 2 96
ANL A,@R And data memory to A 1 1 50-51 JT1 addr Jump on Tl=1 :2 2 56
ANL A,#data And immediate to A 2 2 53 JNT1 addr Jump on T1=0 2 2 46
ORL A,R r Or register to A 1 1 4S-4F JTF addr Jump on timer flag 2 2 16
C5 ORL A,@R Or data memory to A 1 1 40-41
~ ORL A,#data Or immediate to A
:s
XRL A,R r Exclusive Or register
2
1
2
1
43
DS-DF ~e CALL addr Jump to subroutine 1 2 14,34,54,74
~
XRL A,@R
to A
Exclusive Or data 1 1 DO-Dl
-g
rn
RET Return 1 2 S3
memory to A til
97
CI CLR C Clear carry 1 1
XRL A,#data Exclusive Or immediate 2 2 03 III
Complement carry 1 A7
Li: CPL C 1
to A
INC A Increment A 1 1 17 MOV A,R r Move register to A 1 r FS-FF
DEC A Decrement A 1 1 07 MOV A,@R Move data memory to A 1 1 FO-Fl
CLR A Clear A 1 1 27 MOV A,#data Move immediate to A 2 2 23
CPL A Complement A 1 1 37 MOV Rr,A Move A to register 1 t AS-AF
DA A Decimal adjust A 1 1 57 MOV@ R,A Move A to data memory 1 1 AO-Al
SWAP A Swap nibbles of A 1 1 47 MOV Rr,#data Move immediate to 2 2 B8-BF
RL A Rotate A left 1 1 E7 til
register
RLC A Rotafe A left through 1 1 F7 ~
0 MOV@R,#data Move immediate to 2 2 BO-B1
carry ::E
co data memory
RR A Rotale A right 1 1 77 III XCH A,R, Exchange A and 1 1 2S-2F
RRC A Rotate A right through 1 1 67
c
register
carry XCH A,@R Exchange A and data 1 1 20-21
memory
IN A, Pp Input port to A 1 2 OS,09,OA
XCHDA,@R Exchange nibble of A 1 1 30-31
'S OUTLPpA Output A to port 1 '2 90,39,3A
and register
~ MOVD A,P p Inpu~ expander port 1 2 OC-OF
MOVP A,@A Move to A from current 1 2 A3
e'S MOVD Pp,A
to A
Output A to expander 1 2 3C-3F
page
CI.
.E port
~
ANLD Pp.A And A to expander port 1 2 9C-9F MOV A,T Read timer I counter 1 1 42
ORLD Pp.A Or A to expander port 1 2 SC-SF 0
MOV T,A Load timer I counter 1 1 62
~ STRT T Start timer 1 1 55
til iii STRT CNT Start counter 1 1 45
~ INC Rr Increment register 1 l lS-1F E
i= STOP TCNT Stop timer I counter 1 1 65
': INC@R Increment sata memory 1 1 ttl-l1
IX:
Nap No operation 1 1 00
8021L
LOW POWER 10mA
8-Bit CPU, ROM, RAM, I/O in Single

28-Pin Package
641K x8x 8 RAM
ROM
21 I/O Lines
Single 5V Supply (+4.5V to 8V)
Interval Timer/Event Counter
8.38 J..Lsec Cycle With 3.58 MHz XTAL;
All instructions 1 or 2 Cycles orClock Generated With Single Inductor
Crystal
Instructions - 8048 Subset Zero-Cross Detection Capability

High Current Drive Capability-2 Pins Easily Expandable I/O
The Intel 8021 L is a totally self-sufficient 8-bit parallel computer fabricated on a single silicon chip using
Intel's N-channel silicon gate MOS process. The features of the 8021 L include a subset of the 8048 optimized
for low cost, high volume applications, plus additional 1/0 flexibility and power.
The 8021 L contains 1 K X 8 program memory, a 64 X 8 data memory, 21 1/0 lines, and an 8-bit timerlevent
counter, in addition to on-board oscillator and clock circuits. For systems that require extra 1/0 capability, the
8021 L can be expanded using the 8243 or discrete logic.
This microprocessor is designed to be an efficient controller as well as an arithmetic processor. The 8021 L has
bit handling capability as well as facilities for both binary and BCD arithmetic. Efficient use of program
memory results from an instruction set consisting mostly of single byte instructions and no instructions over
two bytes in length.
To minimize the development problems and maximize flexibility, an 8021 L system can be easily designed using
the 8021 L emulation board, the EM-1. The EM-1 contains a 40-pin socket which can accommodate either the
8748 shipped with the board or an ICE-49 plug. Also, the necessary discrete logic to reproduce the 8021 L's
additional 1/0 features is included.
P22 VCC
PORT P23
XTAL\ P21
#Q
PROG P20
PORT POD P17
#1 POl P16
RESET P02 P15
PORT
P03 P14
#2
TEST P04 P13
ADDRESS P05
LATCH P06 Pll
ENABLE P07 Pl0
PORT ALE RESET
EXPANDER T1 XTAL 2
STROBE
Vss XTAL 1

Intel Corporation Assumes No Responsibility for the Use of any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent licenses are Implied.
INTELCORPORATION,1980 7-4 AFN-01813A-Ol
8021L
ABSOLUTE MAXIMUM RATINGS 'NOTICE: Stresses above those listed under "Absolute
Ambient Temperature Under Bias OC to 70C Maximum Ratings" may cause permanent damage to the
Storage Tem perature -65 C to +150 C device. This is a stress rating only and functional opera-
Voltage on Any Pin with tion of the device at these or any other conditions above
Respect to Ground -0.5V to +7V those indicated in the operational sections of this specifi-
Power Dissipation. 1 W cation is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
D.C. CHARACTERISTICS TA = OC to 70C, VCC = 5.5V 1V, VSS = OV
Symbol Parameter Limits Unit Test Conditions

Min. Typ. Max.
VIH Input High Voltage (All except 3.0 VCC V
XTAL 1 & 2, T1 RESET)
VIH1 Input High Voltage (XTAL 1 & 2, 3.8 VCC V
T1 RESET)
VIH(10%) Input high voltage (All except 2.0 VCC V VCC = 5.0V 10%
1 & 2, T1, RESET)
VIH1(10%) I nput high voltage (XTAL 1 & 2, 3.5 VCC V VCC = 5.0V 10%
T1, RESET)
VOL Output Low Voltage 0.45 V IOL + 1.6 mA
VOL1 Output Low Voltage (P10, P11) 2.5 V IOL = 7 mA
VOH Output High Voltage 2.4 V IOH=40jJ.A
(All unless Open Drain)
ILO Output Leakage Current 10 jJ.A VSS+0.45~VIN~VCC
(Open Drain Option - Port 0)
T1 ZERO CROSS CHARACTERISTICS TA = OC to 70C, VCC = 5.5V 1V, VSS = OV, CL = 80 pF

VZX Zero-Cross Detection Input (T1) 1 3 VPP AC Coupled, C =.2jJ.F
FZX Zero-Cross Detection Input 0.05 1 kHZ
Frequency (T1 )
tCY Cycle Time 8.38 50.0 3.58 MHz "XTAL =
8.38 jJ.s tCY
7-5 AFN-01813A-02
8022
SINGLE COMPONENT a-BIT MICROCOMPUTER
WiTH ON-CHiP AID CONVERTER
8-Bit CPU, ROM, RAM, I/O in Single 40-Pin
Package
2K x 8 ROM, 64 x 8 RAM, 28 I/O Lines
On-Chip 8-Bit A/D Converter; Two Input 8.38 ~sec Cycle; All Instructions 1 or 2
Cycles
Channels
8 Comparator Inputs (Port 0) Instructions-8048 Subset

Zero-Cross Detection Capability Interval Timer / Event Counter
Single SV Supply (4.SV to 6.SV) Clock Generated with Single Inductor or
High Current Drive Capability-2 Pins Crystal
Two Interrupts-External and Timer Easily Expanded I/O

The Intel@ 8022 is the newest member of the MCS-48 family of single chip 8-bit microcomputers. It is designed to
satisfy the requirements of low cost, high volume applications which involve analog signals, capacitive touchpanel
keyboards, and / or large ROM space. The 8022 addresses these applications by integrating many new functions on-
chip, such as A / 0 conversion, comparator inputs and zero-cross detection.
The features of the 8022 include 2K bytes of program memory (ROM), 64 bytes of data memory (RAM), 28 I/O lines,
an on-chip A / 0 converter with two input channels, an 8-bit port with comparator inputs for interfacing to low voltage
capacitive touchpanels or other non-TTL interfaces, external and timer interrupts, and zero-cross detection capabili-
ty. In addition, it contains the 8-bit interval timer / event counter, on-board oscillator and clock circuitry, single 5V
power supply requirement, and easily expandable I/O structure common to all members of the MCS-48 family.
The 8022 is designed to be an efficient controller as well as an arithmetic processor. It has bit handling capability
plus facilities for both binary and BCD arithmetic. Efficient use of program memory results from using the MCS-48
instruction set which consists mostly of single byte instructions and has extensive conditional jump and direct table
lookup capability. Program memory usage is further reduced via the 8022' s hardware implementation of the A /0
Vee
XTAL r PORTO
- - - THRESHOLD
REFERENCE P26
P27
Vee
P2S
AVec P24
RESET ~8~)PORTO VAREF PROG

ANI P23
ANO P22
TEST O. P21
AVss
a:)PORTl TO P20
8022
VTH PH
TEST I .
POO P16
~-:>PORT2 POl
P02
P1S
P14
AID P13
P03
REFERENCE
P04 P12
POS Pll
ADDRESS P06 Pl0

ANO. --LATCH P07 RESET
ENABLE
ALE XTAL 2
Tl XTAL 1
Vss SUBST
ANl PORT
--EXPANDER
STROBE
t t
AID
t
AID SUBSTRATE
Vee Vss
Intel Corporation Assumes No Responsibility for the Use of any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenses are Implied.
INTELCORPORATION,1980 7-6 AFN-00187A-Ol
8022
Deslg- Pin Deslg- Pin

nation No. Function nation No. Function
VSS 20 Circuit GND potential. RESET 24 Input used to initialize the pro-
40 + SV circuit power supply. cessor by clearing status flip-
VCC
flops and setting the program
PROG 37 Output strobe for Intel@ 8243 counter to zero.
I/O expander.
AVSS 7 AID converter GND Potential.
POO-P07 10-17 8-bit open-drain port with com- Also establishes the lower limit of
Port 0 parator inputs. The switching the conversion range.
threshold is set externally by
VTH. Optional pull-up resistors AVCC 3 AID + SV power supply.
may be added via ROM mask SUBST 21 Substrate pin used with a bypass
selection. capacitor to stabilize the sub-
9 Port 0 threshold reference pin. strate voltage and improve AID
VTH
accuracy.
P10-P17 2S-32 8-bit quasi-bidirectional port.
VAREF 4 AID converter reference voltage.
Port 1 Establishes the upper limit of the
P20-P27 33-36 8-bit quasi-bidirectional port. conversion range.
Port 2 38-39 P20-23 also serve as a 4-bit I/O ANO, AN1 6,S Analog inputs to AID converter.
1-2 expander for Intel@ 8243. Software selectable on-chip via
SEL ANO and SEL AN1 instruc-
TO 8 Interrupt input and input pin tions.
testable using the conditional
transfer instructions JTO and ALE 18 Address Latch Enable. Signal
JNTO. Initiates an interrupt fol- occurring once every 30 input
lowing a low level input if inter- clocks (once every cycle), used
rupt is enabled. Interrupt is as an output clock.
disabled after a reset. XTAL 1 22 One side of crystal or inductor
T1 19 Input pin testable using the JT1 input for internal oscillator. Also
and JNT1 conditional transfer input for external frequency
instructions. Can be designated source. (Not TTL compatible.)
the timerlevent counter input XTAL 2 23 Other side of timing control ele-
using the STRT CNT instruction. ment. This pin is not connected
Also serves as the zero-cross when an external frequency
detection input to allow zero- source is used.
crossover sensing of slowly mov-
ing AC inputs. Optional pull-up
resistor may be added via ROM
mask selection.
+SV
}-,
25
P10
26
Pll
27
VAAEF P12
28
P13 [ INPUT]
AVec 29 AND
P14
30 OUTPUT
P1S
10-200"F 31
P16
32
P17
AVss
}-,
20 33
Vss
34
P21
1"F 8022 35
P22
36
P23 [ INPUT]
SUBST 38 AND
P24
39 OUTPUT
P2S
AID INPUTS I ANO
ANl
P26
P27
VTH
10
POO
},~o
XTALl 11
POl
12
1M P02
13
P03 [ INPUT]
14 AND
XTAL2 P04 OUTPUT
15
POS
16
T1 P06
17
1"F P07
Figure 3.The Stand Alone 8022
7.7
8022
........ ~ ~.- . . . . " ft ......... "r-* "'''vOTiCE: Stresses above those listed undei "Absolute
AI:J~VLU I C MAAIMUM ""'. lI'fUo:J
Ambient Temperature Under Bias ....... 0 C to 70 C Maximum Ratings" may cause permanent damage to the
Storage Temperature ............... -65C to +150C device. This is a stress rating only and functional opera-
Voltage on Any Pin with tion of the device at these or any other conditions above
Respect to Ground .................... -0.5V to +7V those indicated in the operational sections of this specifi-
Power Dissipation ............................ 1 Watt cation is not implied. Exposure to absolute maximum
reliability.
D.C. CHARACTERISTICS TA = OC to 70C, VCC = 5.5V 1V, VSS = OV
Symbol Parameter Limits Unit Test Conditions

Min. Typ. Max.
VIL Input Low Voltage -0.5 0.8 V VTH Floating
VIH1 Input Low Voltage (Port 0) -0.5 VTH-Q.1 V
VIH High Voltage 2.0 VCC V VCC =5.0V 10%
(All except XTAL 1, RESET) VTH Floating
VIH1 Input High Voltage 3.0 VCC V VCC =5.5V 1V
(All except XTAL 1, RESET) VTH Floating
VIH2 Input High Voltage (Port 0) VTH+0.1 VCC V
VIH3 Input High Voltage (RESET, XTAL 1) 3.0 VCC V VCC =5.0V 10%
VTH Port 0 Threshold Reference Voltage 0 .4VCC V
VOL Output Low Voltage 0.45 V IOL=1.6 mA
VOl1 Output Low Voltage (P10, P11) 2.5 V IOl =7 mA
VOH Output High Voltage (all unless 2.4 V IOH =50 p.A
Open Drain Option - Port 0)
III Input Current (T1) 200 p.A VCC~VIN;;?,VSS+.45V
ILO Output Leakage Current 10 p.A VCC~VIN~ VSS+O.45V

(Open Drain Option-Port 0)
A.C. CHARACTERISTICS TA = OC to 70C, VCC = 5.5V 1V, VSS = OV

tcv Cycle Time 8.38 50.0 p.S 3 MHz XTAL = 10 p's tcv
VZX Zero-Cross Detection Input (T1) 1 3 VACpp AC Coupled
FZX Zero-Cross Detection Input 0.05 1 kHz
Frequency (T1)
AFN-00187 A-Q3
8022
A.C. CHARACTERISTICS TA = OC to 70C, VCC = 5.5V 1V, VSS = OV

Test Conditions: CL =80 pF tCy=8.38 J.LS
Symbol Parameter Min. Max. Unit Notes

tcp Port Control Setup Before Falling Edge of PROG 0.5 J.LS
tpc Port Control Hold After Falling Edge of PROG 0.8 J.LS
Expander tpR PROG to Time P2 Input Must Be Valid 1.0 J.Ls

Operation top Output Data Setup Time 7.0 J.Ls
tpo Output Data Hold Time 8.3 J.LS
tpF Input Data Hold Time 0 .150 J.LS
tpp PROG Pulse Width 8.3 J.LS
tpRL ALE to Time P2 Input Must Be Valid 3.6 J.LS

Normal tpl Output Data Setup Time 0.8 J.LS
Operation tLP Output Data Hold Time 1.6 J.Ls
tpFl Input Data Hold Time 0 J.LS
tLl ALE Pulse Width 3.9 23.0 j.1S tCy=8.38 J.Ls for min
Port 2 Timing
NORMAL OPERATION
--l I-- ILL
ALEr\ 1\
PORT
OUTPUT
:=x y--omy
IPL--j .-r I - I LP
ALEr\ 1\
PORT
INPUT
( DATA
X
I- IpRL
-I -1 r-
EXPANDER OPERATION
IPFL
ALE r\ 1\
PROG \ I
I- Ipp
-I
PORT
OUTPUT XC6~~JOLX X DATA
x:=
ICPi-r
I--IPC
IDPi
--r- ~lpD
ALE/\ 1\
PROG
\ I
PORT
INPUT XCb~nOL >---<: DATA
x==
'C'~L
--ll--IPF
IpR
~
7n
8022
AID CONVERTER CHARACTERISTICS TA =O"C io 70"C, vee = 5.5V 1V, Vss = av, AVec =5.5V 1V,
AVSS = OV, AVCC/2 ~ VAREF ~ AVCC
Parameter Min. Typ. Max. Unit Comments

Resolution 8 Bits
Absolute Accuracy .8% FSR V2 LSB LSB (Note 1)
Sample Setup Before Falling Edge of ALE (t55) 0.20 tey
Sample Hold After Falling Edge of ALE (t SH ) 0.10 tey
Input Capacitance (ANO, AN1) 1 pF
Conversion Time 4 4 tey
Analog Input Timing
ALE
ANALOG
INPUT
NOTE
1. The analog input must be maintained at a constant voltage during the sample time (tss + t SH )'
7-10 AFN-00187A-05
8022
Table 2. Instruction Set Summary
Hexadecimal Hexadecimal
Mnemonic Description Bytes Cycle Opcode Mnemonic Description Bytes Cycle Opcode
ADD A,R r Add register to A 1 1 68-6F JTOaddr Jump on TO= 1 2 2 36

ADD A,@R Add data memory to A 1 1 60-61 JNTOaddr Jump on TO=O 2 2 26
ADD A,#data Add immediate to A 2 2 03 JT1 addr Jump on T1=1 2 2 56
AD DC A,R r Add register with carry 1 1 78-7F JNT1 addr Jump on T1 =0 2 2 46
ADDC A,@R Add data memory with 1 1 70-71 JTF addr Jump on timer flag 2 2 16
carry
ADDC A,#data Add immediate with CII
2 2 13
carry ~ CALL addr Jump to subroutine 1 2 14,34,54,74
0 94,B4,D4,F4
ANL A,R r And register to A 1 1 58-5F
ANL A,@R And data memory to A 1 1 50-51 ~
en
RET Return 1 2 83
ANL A,#data And immediate to A 2 2 53
III
ORL A,R r Or register to A 1 1 48-4F CLR C Clear carry 1 1 97
g'
ORL A,@R Or data memory to A 1 1 40-41 ii: CPL C Complement carry 1 1 A7
ORL A,#data Or immediate to A 2 2 43
XRL A,R r Exclusive Or register 1 1 D8-DF MOV A,R r Move register to A 1 1 F8-FF
to A MOV A,@R Move data memory to A 1 1 FO-F1
XRL A,@R Exclusive Or data 1 1 00-01 MOV A,#data Move immediate to A 2 2 23
memory to A MOV Rr.A Move A to register 1 1 A8-AF
XRL A,#data Exclusive Or immediate 2 2 03 MOV@ R,A Move A to data memory 1 1 AO-A1
to A MOV Rr,#data Move immediate to 2 2 B8-BF
III
INC A Increment A 1 1 17 register
~
DEC A Decrement A 1 1 07 0 MOV@R,#data Move immediate to 2 2 BO-B1
::Ii
CLR A Clear A 1 1 27 co data memory
CPL A Complement A 1 1 37 OJ XCHA,R r
Q
Exchange A and 1 1 28-2F
DA A Decimal adjust A 1 1 57 register
SWAP A Swap nibbles of A 1 1 47 XCH A,@R Exchange A and data 1 1 20-21
RL -A Rotate A left 1 1 E7 memory
RLC A Rotate A left through 1 1 F7 XCHD a,@R Exchange nibble of A 1 1 30-31
carry and register
RR A Rotate A right 1 1 77 MOVP A,@A Move to A from current 1 2 A3
RRC A Rotate A right through 1 1 67 page
carry
~
MOV A,T Read timer I counter 1 1 42
IN A, Pp Input port to A 1 2 08,09,OA MOV T,A Load timer / counter 1 1 62
0
::0
OUTL Pp.A Output A to port 1 2 90,39,3A
~ STRT T Start timer 1 1 55
MOVD A.Pp Input expander port 1 2 OC-OF ~ STRT CNT Start counter 1 1 45
~ to A E STOP TCNT Stop timer / counter 1 1 65
~
j::
MOVD Pp,A Output A to expander 1 2 3C-3F
port
~ ANLD Pp.A And A to expander port 1 2 9C-9F
! RAD Move conversion resuli 1 2 80
~
register to A
ORLD Pp.A Or A to expander port 1 2 8C-8F SEL ANO Select analog input 1 1 85
0
u zero
III
e SEL AN1 Select analog input one 1 1 95
~.~ INC Rr
INC@R
Increment register
Increment data memory
1
1
1
1
18-1F
10-11
oCt
EN I Enable external 1 1 05
a:
interrupt
DIS I Disable external 1 1 15
JMP addr Jump unconditional 2 2 04,24,44,64,
III interrupt
~
84,A4,C4,E4
EN TCNTI Enable timer! counter 1 1 25
JMPP@ A Jump indirect 1 2 B3
~
.l: interrupt
u DJNZ R,addr Decrement register and 2 2 E8-EF
c: DIS TCNT! Disable timer / counter 1 1 35
co jump on R not zero
cD JC addr interrupt
Jump on carry= 1 2 2 F6
RET I Return from interrupt 1 2 93
JNC addr Jump on carry=O 2 2 E6
JZ addr Jump on A zero 2 2 C6
NOP No operation 1 1 00
JNZ addr Jump on A not zero 2 2 96
SYMBOLS AND ABBREVIATIONS USED
P Mnemonic for "in-page" Operation

A Accumulator Pp Port Designator (P=O, 1, 2 or 4-7)
addr 11-Bit Program Memory Address Rr Register Designator (r=O-7)
ANO,AN1 Analog Input 0, Analog Input 1 T Timer
CNT Event Counter TO, T1 Test 0, Test 1
data 8-Bit Number or Expression # Immediate Data Prefix
I Interrupt @ Indirect Address Prefix
7_11
8022H
HIGH PERFORMANCE
WITH ON-CHIP AID CONVERTER
8-Bit CPU, ROM, RAM, I/O in Single 40-Pin
Package
2K x 8 ROM, 64 x 8 RAM, 28 I/O Lines
On-Chip 8-Bit A/D Converter; Two Input 5 f1sec Cycle; All Instructions 1 or 2
Cycles (6 MHz Clock)
Channels
8Zero-Cross
Comparator Inputs (Port 0) IInstructions-8048 Subset
Single SV Supply
Detection Capability Clock
nterval Time/Event Counter
Two Interrupts-External
(4.SV to 6.SV) CrystalGenerated with Single Inductor or
and Timer
Easily Expanded I/O
The Intel@ S022H is designed to satisfy the requirements of low cost, high volume applications which involve
analog signals, capacitive touch panel keyboards, and/or large ROM space. The S022H addresses these
applications by integrating many new functions on-chip, such as A/D conversion, comparator inputs and
zero-cross detection.
The features of the S022H include 2K bytes of program memory (ROM), 64 bytes of data memory (RAM), 2S
I/O lines, an on-chip A/D converter with two input channels, an S-bit port with comparator inputs for
interfacing to low voltage capacitive touch panels or other non-TTL interfaces, external timer interrupts, and
zero-cross detection capability. In addition, it contains the S-bit interval timer/event counter, on-board
oscillator and clock circuitry, single 5V power supply requirement, and easily expandable I/O structure
common to all members of the MCS-4S family.
The S022H is designed to be an efficient controller as well as an arithmetic processor. It has bit handling
capability plus facilities for both binary and BCD arithmetic. Efficient use of program memory results from
using the MCS-4S instruction set which consists mostly of single byte instructions and has extensive
conditional jump and direct table lookup capability. Program memory usage is further reduced via the S022H's
hardware implementation of the A/D converter which simplifies interfacing to analog signals.
Vee Vss
XTAL r PORTO
- - THRESHOLD
REFERENCE P26
P27
Vee
P25
AVec P24
RESET _
=<> PORTO
VAREF
AN1
PROG
P23
P22
TEST ()..
~)PORT1
P21
P20
8022
VTH P17
TEST 1
po~ P16
~)PORT2 P15
P14
AID
P13
REFERENCE
P04 P12
P05 P11
ADDRESS P06 P10
-LATCH P07 RESET
ENABLE
ALE XTAL 2
T1 XTAL 1
Vss SUBST
AN1 PORT
--EXPANDER
STROBE
l l l
AID AID SU BSTRATE
Vee Vss
Intel Corporation Assumes No Responsibility for the Use of any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenses are Implied.
INTELCORPORATION,1980 7.12 AFN01814A
S04SH/S04SH-1/S035HLlS035H L-1
HMOS SINGLE COMPONENT S-BIT MICROCOMPUTER
8048H/8048H1 Mask Programmable ROM

8035HLl8035HL1 CPU Only with Power Down Mode
8BIT
Package
CPU, ROM, RAM, 110 in Single
64x
1Kx8 ROM
RAM
High Performance HMOS 27110 Lines
1.4 J,lsec and 1.9 J,lsec Cycle Versions
Reduced Power Consumption
All Easily Expandable Memory and 110
Instructions 1 or 2 Cycles
Compatible with 8080/8085 Series
Over 90 Instructions: 70% Single Byte Peripherals
Two Single Level Interrupts
The Intel 8048H/8048H1/8035HU8035HL-1 are totally self-sufficient, 8-bit parallel computers fabricated on single
silicon chips using Intel's advanced N-channel silicon gate HMOS process.
The8048H containsa 1KX8 program memory, a64X8 RAM data memory, 271/0 lines, and an 8-bit timer/counterin addition
to on-board oscillator and clock circuits. For systems that require extra capability the8048H can be expanded using stan-
dard memories and MCS-80 IMCS-85 peripherals. The 8035HL is the equivalent of the8048H without program memory
and can be used with external ROM and RAM.
To reduce development problems toa minimum and provide maximum flexibility, a logically and functionally pin compati-
ble version of the8048H with UV-erasable user-programmable EPROM program memory is available. The87 48 will emulate
the 8048H up to 6 MHz clock frequency with minor differences.
The 8048H is fully compatible with the 8048 when operated at 6MHz.
These microcomputers are designed to be efficient controllers as well as arithmetic processors. They have extensive bit
handling capability as well as facilities for both binary and BCD arithmetic. Efficient use of program memory results from
an instruction set consisting mostly of single byte instructions and no instructions over 2 bytes in length.
TO Vee
PORT
XTAL 1 T1
01
XTAL 2 P27
RESET P26
PORT 55 P25
02
INT P24
EA PH
AD P16
B04BH PSEN P15
B035HL Wi! P14
B04BH-1 ALE P13
B035HL-1
DBO P12
DB1 P11
DB2 P10
DB3 Voo
OB4 PROG
DBS P23
DB6 P22
DB7 P21
Vss P20

(top view)
Intel Corporation Assumes No Responsibilty for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent licenses are Implied.
INTEL CORPORATION, 1980 7-13 AFN-01491B-Ol
S04SH/S04SH-1 IS035H L/S035H L-1
Symbol Pin No. Function Symbol Pin No. Function
VSS 20 Circuit GND potential Also testable with conditional

26 Low power standby pin jump instruction. (Active low)
VDD -
40 Main power supply; +5V during RD 8 Output strobe activated during a
VCC
operation. BUS read. Can be used to enable
data onto the bus from an
PROG 25 Output strobe for 8243 I/O external device.
expander.
Used as a read strobe to external
P10-P17 27-34 8-bit quasi-bidirectional port. data memory. (Active low)
Port 1 ---
RESET 4 Input which is used to initialize
P20-P27 21-24 8-bit quasi-bidirectional port. the processor. (Active low)
Port 2 (Non TTL VIH)
-
35-38 P20-P23 contain the four high WR 10 Output strobe during a bus write.
order program counter bits dur- (Active low)
ing an external program memory
fetch and serve as a 4-bit I/O Used as write strobe to external
expander bus for 8243. data memory.
DBO-DB7 12-19 True bidirectional port which ALE 11 Address latch enable. This signal
BUS can be written or read occurs once during each cycle
synchronously using the RD, WR and is useful as a clock output.
strobes. The port can also be The negative edge of ALE strobes
statically latched. address into external data and
Contains the 8 low order pro- program memory.
--
gram counter bits during an PSEN 9 Program store enable. This out-
external program memory fetch, put occurs only during a fetch to
and receives the addressed external program memory.
instruction under the control of (Active low)
PSEN. Also contains the address -
SS 5 Single step input can be used
and data during an external RAM
in conjunction with ALE to "single
data store instruction, under
step" the processor through each
control of ALE, RD, and WR.
instruction. (Active low)
TO 1 Input pin testable using the
EA 7 External access input which
conditional transfer instructions
forces all program memory
JTO and JNTO. TO can be
fetches to reference external
designated as a clock output
memory. Useful for emulation
using ENTO CLK instruction.
and debug, and essential for
T1 39 Input pin testable using the JT1, testing and program verification.
and JNT1 instructions. Can be (Active high)
designated the timer/counter
XTAL1 2 One side of crystal input for
input using the STRT CNT
internal oscillator. Also input for
instruction.
- external source. (Non TTL VIH)
INT 6 Interrupt input. Initiates an
XTAL2 3 Other side of crystal input.
interrupt if interrupt is enabled.
Interrupt is disabled after a reset.
AFN-01491B-02
7-14
Table 2. Instruction Set
Accumulator Subroutine
Mnemonic Description Bytes Cycles Mnemonic Description Bytes Cycles

ADD A, R Add register to A 1 1 CAll addr Jump to subroutine 2 2
ADD A, @R Add data memory to A RETR Return
ADD A. # data Add immediate to A RETR Return and restore status
ADDC A, R Add register with carry
ADDC A, @R Add data memory with carry
ADDC A, # data Add immediate with carry Flags
ANl A, R And register to A Mnemonic Description Bytes Cycles
ANl A, @R And data memory to A ClR C Clear carry 1 1
ANl A, # data And immediate to A CPl C Complement carry
ORl A, R Or register to A ClR Fa Clear flag a
ORl A@R Or data memory to A CPl Fa Complement flag a
ORl A, # data Or immediate to A ClR F1 Clear flag 1
XRl A, R Exclusive or register to A CPl F1 Complement flag 1
XRl A, @R Exclusive or data memory to A
XRl, A, # data Exclusive or immediate to A
INC A Increment A Data Moves
DEC A Decrement A
ClR A Clear A Mnemonic Description Bytes Cycles
CPl A Complement A MOV A, R Move register to A 1 1
DA A Decimal adjust A MOV A. @R Move data memory to A
SWAP A Swap nibbles of A MOV A, # data Move immediate to A
Rl A Rotate A left MOV R, A Move A to register
RlC A Rotate A left through carry MOV@R,A Move A to data memory
RR A Rotate A right MOV R, # data Move immediate to register
RRC A Rotate A right through carry MOV @R, #data Move immediate to data memory
MOV A, PSW Move PSW to A
MOV PSW, A Move A to PSW
Input/Output XCH A, R Exchange A and register
XCH A, @R Exchange A and data memory
Mnemonic Description Bytes Cycles XCHD A, @R Exchange nibble of A and
IN A, P Input port to A 1 2 register
OUTl P, A Output A to port MOVX A, @R Move external data memory to A
ANl P, # data And immediate to port MOVX@R, A Move A to external data memory
ORl P, # data Or immediate to port MOVPA, @A Move to A from current page
INS A, BUS Input BUS to A MOVP3 A, @ Move to A from page 3
OUTl BUS, A Output A to BUS
ANl BUS, # data And immediate to BUS
ORl BUS, # data Or immediate to BUS
Timer/Counter
MOVD A,P Input expander port to A
MOVD P, A Output A to expander port Mnemonic Description Bytes Cycles
ANlD P, A And A to expander port MOV A, T Read timer/counter 1 1
ORlD P, A Or A to expander port MOV T, A load timer/counter
STRT T Start timer
STRT CNT Start counter
Registers STOP TCNT Stop timer/counter
EN TCNT1 Enable timer/counter interrupt
Mnemonic Description Bytes Cycles
DIS TCNT1 Disable timer/counter interrupt
INC R Increment register 1 1
INC@R Increment data memory
DEC R Decrement register Control

Branch EN 1 Enable external interrupt 1 1
DIS 1 Disable external interrupt
Mnemonic Description Bytes Cycles SEl RBO Select register bank a
JMP addr Jump unconditional 2 2
SEl RB1 Select register bank 1
JMPP@A Jump indirect
SEl MBa Select memory bank a
DJNZ R, addr Decrement register and skip
SEl MB1 Select memory bank 1
JC addr Jump on carry = 1 ENT a ClK Enable clock output on TO
JNC addr Jump on carry = a
JZ addr Jump on A zero
JNZ addr Jump on A not zero Mnemonic Description Bytes Cycles
JTO addr Jump on TO = 1 NOP 1 1
No operation
JNTO addr Jump on TO = a
JT1 addr Jump on T1 = 1
JNT1 addr Jump on T1 = a
JFO addr Jump on Fa" 1
JF1 addr Jump on F1 = 1
JTF addr Jump on timer flag
JN1 addr Jump on INT = a
JBb addr Jump on accumulator bit
AFN-01491B-03
7-15
S04SH/S04SH-1 IS035H L/S03SHL-1
ABSOLUTE MAXIMUM RATINGS* *NOTlCE: Stresses above those listed under "Absolute
Ambient Temperature Under Bias ....... OC to 70C Maximum Ratings" may cause permanent damage to the
Storage Temperature ................ -65C to +150C device. This is a stress rating only and functional opera-
Voitage On Any Pin 'vVith Respect tion of device at these 0; any othSi conditions above those
to Ground ........................... -0.5V to +7V indicated in the operational sections of this specification
Power Dissipation .......................... 1.5 Watt is not implied.
D.C. CHARACTERISTICS (TA = OC to 70C, VCC = VOO = 5V + 10%, VSS = OV)
Limits
Symbol Parameter Unit Test Conditions
Min. Typ. Max.
VIL Input Low Voltage -.5 .8 V

(All Except RESET, X1, X2)
V IL1 Input Low Voltage -.5 .6 V

(RESET, X1, X2)
V IH Input High Voltage 2.0 VCC V

(All Except XTAL 1, XTAL2, RESET)
VIH1 Input High Voltage (X1, X2, RESET) 3.8 VCC V
VOL Output Low Voltage (BUS) .45 V IOL = 2.0 mA
V OL1 Output Low Voltage .45 V IOL = 1.8 mA

(RO, WR, PSEN, ALE)
VOL2 Output Low Voltage (PROG) .45 V IOL = 1.0 mA
V OL3 Output Low Voltage .45 V IOL = 1.6 mA

(All Other Outputs)
VOH Output High Voltage (BUS) 2.4 V IOH = -400fLA
VOH1 O~p~igh Voltage 2.4 V IOH = -100fLA

(RO, WR, PSEN, ALE)
VOH2 Output High Voltage 2.4 V IOH = -40fLA

(All Other Outputs)
---
1L1 Input Leakage Current (T1, INT) 10 fLA VSS~VIN~VCC
I Ll1 Input Leakage Current _ -500 fLA VSS + .45~VIN~VCC

(p10-P17, P20-P27, EA, SS)
ILO Output Leakage Current (BUS, TO) 10 fLA VSS + .45~VIN~VCC

(High Impedance State)
100 VOO Supply Current 4 8 mA

-
100 + Total Supply Current 40 80 mA
ICC
VOO RAM Standby Pin Voltage 2.2 5.5 V Standby Mode, Reset ~0.6V
BUS P1. P2 BUS, P1, P2

50 mA -500 JlA so mA
J:
9
-30 mA
10 mA
OV 2V
VOH
4V
J:
9
300 Jl
1001lA
OV
VOH
9
...J 30 mA
10 mA
OV
~
~ 2V
VOL
4V
AFN-014918-04
7-16
S04SH/S04SH-1 /S035H L-1 /S035H L-1
A.C. CHARACTERISTICS (TA = OC to 70C, VCC = VDD = 5V 10%, VSS = OV)
8048H 8048H-1
8035HL 8035HL-1
6 MHz 8 MHz 11 MHz Conditions
Symbol Parameter F (tCY) Min. Max. Min. Max. Min. Max. Unit (Note 1)
tLL ALE Pulse Width 7/30 tCY -170 410 260 150
tAL Addr Setup to ALE 1/5 tCY -110 390 260 160
tLA Addr Hold from ALE 1/15 tCY -40 120 80 50
tCC1 Control Pulse Width 1/2 tCY -200 1050 730 480
(RD, WR)
tCC2 Control Pulse Width (PSEN) 2/5 tCY -200 800 550 350
tDW Data Setup before WR 13/30 tCY -200 880 610 390
tWD Data Hold after WR 1/5 tCY -150 350 220 120 (Note 2)
tDR Data Hold (RD, PSEN) 1/10 tCY -30 0 220 0 160 0 110
tRD1 RD to Data in 2/5 tCY -200 800 550 350
tRD2 PSEN to Data in 3/10 tCY -200 550 360 210
tAW Addr Setup to WR 2/5 tCY -150 850 600 300
tAD1 Addr Setup to Data (RD) 23/30 tCY -250 1670 1190 750
tAD2 Addr Setup to Data (PSEN) 3/5 tCY -250 1250 880 480
tAFC1 Addr Float to RD, WR 2/15 tCY -40 290 210 140
tAFC2 Addr Float to PSEN 1/30 tCY -40 40 20 10
tLAFC1 ALE to Control (RD, WR) 1/5 tCY -75 420 300 200
tLAFC2 ALE to Control (PSEN) 1/10 tCY -75 170 110 60
tCA1 Control to ALE 1/15 tCY -40 120 80 50

(RD, WR, PROG)
tCA2 Control to ALE (PSEN) 4/15 tCY -40 620 460 320
tcp Port Control Setup to PROG 1/10 tCY -40 210 140 100
tpc Port Control Hold to PROG 4/15 tCY -200 460 300 160
tpR PROG to P2 Input Valid 17/30tCY 1300 940 650
-120
tPF Input Data Hold from PROG 1/10 tCY 250 0 190 0 140
tDP Output Data Setup 2/5 tCY -150 850 600 400
tPD Output Data Hold 1/10 tCY -50 200 130 90
tpp PROG Pulse Width 7/10 tCY -250 1500 1060 700
tPL Port 2 I/O Setup to ALE 4/15 tCY -200 460 300 160
tLP Port 2 I/O Hold to ALE 1/10 tCY -100 150 80 40
tpv Port Output from ALE 3/10 tCY +100 850 660 510
tCY Cycle Time 2.5 1.875 1.36
tOPRR TO Rep Rate 3/15 tCY 500 370 270
Notes:
1. Control Outputs CL = 80pF
BUS Outputs CL = 1S0pF
2. BUS High Impedance Load 20pF
AFN-014918-05
a 'I..~~"r.
YY"'Yl:rvnm~
.....
~ILAFC1
L ALE
J I I I L
r- ICC1
-j ICA1
1-
j It: -\I
RD
IAFC1 tlDR
FLOATING
BUS ~ FLOATING
~ IAD1 S I R D 1
Instruction Fetch From External Program Memory Read From External Data Memory
ILAFC1n
ALE Jr-----'I L
i--
---------------------~
ICC1
WR
~X ::~ ~ TEST POINTS ~::: X. . ____

2.4V ----------__ ~----
O.4SV __________
BUS
Write to External Data Memory Input and Output for A.C.Tests.
PORT 2 TIMING
ALE J \'---_ _ _~V \'------~/

_IICA1~
EXPANDER
PORT I,,,-I'''l r'DP-r'PI
I
OUTPUT PCH PORT CONTROL OUTPUT DATA
EXPANDER
PORT
INPUT PCH PORT 20-23 DATA
PROG
AFN-01491B-06
7-18
1/0 PORT TIMING
1ST CYCLE 2ND CYCLE
J \ I'" 1~~r'" 1 j"-------'L

ALE
I 1 1'----1 - - - - I
PSEN
\'--_----'f
I
~~~~~T~------------PC-H------------~)(r--------p-O-R-T-2-0--2-3-D-A-TA---------,~~----N-E-W-P-2-0--23--DA-T-A----J)(~------PC-H------
P24-27
P10-17
OUTPUT
___________________________________________
PORT 24-27, PORT 10-17 DATA ...J
x. .____________________NEW PORT DATA
Crystal Oscillator Mode LC Oscillator Mode

1
C1
m
f~--
~
t----:'---...----;XTAL1 XTAL1
21njLC'
c,;~, = C'-~
c
-= t-~!--+----;XTAL2
d
-=
C
L
3
XTAL2
2
Cpp'" 5-10 pF
PIN-TO-PIN
CAPACITANCE
C3
C1 " 5pF . 1/2pF. STRAY 5pF
C2 CRYSTAL' STRAY 8pF
0
C NOMINAL f
C3 20pF , 1 pF . STRAY. 5pF
0 20pF 5.2 MHz
20pF 3.2 MHz
EACH C SHOULD BE APPROXIMATELY 20pF.

INCLUDING STRAY CAPACITANCE
Driving From External Source

+5V
470Q
D - - - - < . - - - - - - I XTAL1
+5V
OPEN COLLECTOR
TTL GATES
470Q
'---"'---1 XTAL2
AFN-01491 B-07
7-1~
8048L
SPECIAL LOW POWER CONSUMPTION SINGLE
COMPONENT 8-BIT MICROCOMPUTER
Typical Power Consumption 100mW 641K xx SSRAM
ROM
Typical Standby Power 10mW

VOD minimum of 2.2V
271/0 Lines

S-Bit CPU, ROM, RAM, I/O in Single
Package Easily Expandable Memory and I/O
Compatible with SOSO/SOS5 Series
4.17 J,lsec Instruction Cycle.
All Instructions 1 or 2 Cycles. Peripherals
Over 90 Instructions: 70% Single Byte Two Single Level Interrupts

The Intel 8048L is a totally self-sufficient 8-bit parallel computer fabricated on a single silicon chip using
Intel's advanced N-channel silicon gate HMOS process, using special techniques to reduce operating and
standby power consumption. The 8048L contains a 1K X 8 program memory, a 64 X 8 RAM data memory,
27 I/O lines, and an 8-bit timer/counter in addition to on-board oscillator and clock circuits. For systems that
require extra capability the 8048L can be expanded using standard memories and MCS-80/MCS-85 periph-
erals. The 8048L can be used with external ROM and RAM.
To reduce development problems to a minimum and provide maximum flexibility, a logically and functionally
pin compatible version of the 8048L with UV-erasable user-programmable EPROM program memory is avail-
able. The 8748 will emulate the 8048L with greater power and other minor differences.
This microcontroller is designed to be an efficient controller as well as an arithmetic processor. The 8048L has
extensive bit handling capability as well as facilities for both binary and BCD arithmetiC. Efficient use of pro-
gram memory results from an instruction set consisting mostly of single byte instructions and no instructions
over two bytes in length.
TO Vee
PORT
XTAL 1 T1
XTAL 2 P27
RESET P26
PORT
2
55 P2S
fNT P24
EA PH
AD P16
PSEN P1S
WR P14
8048L
ALE P13
DBO P12
DBl Pll
DB2 Pl0
DB3 VDD
DB4 PROG
DBS P23
BUS DB6 P22

DB7 P2l
VSS P20
Figure 1. Figure 2. Figure 3.

8048L Block Diagram 8048L Logic Symbol 8048L Pin Configuration
Intel Corporation Assumes No Responsibilty for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenses are Implied .
. INTEL CORPORATION, 1980 7-20 AFN-Q1591A-Ol
intel" 8048L [F)OO~[bn[M]n~~OO\1
PIN DESCRIPTION
Designation Pin = Function Designation Pin = Function
VSS 20 Circuit GND potential testable with conditional
VDD 26 low power standby pin jump instruction.
(Active low)
VCC 40 Main power supply; +5V
during operation. RD 8 Output strobe activated
during a BUS read. Can be
PROG 25 Output strobe for 8243 I/O used to enable data onto the
expander. bus from an external device.
P10-P17 27-34 8-bit quasi-bidirectional Used as a read strobe to
Port 1 port. external data memory.
P20-27 21-24 8-bit quasi-bidirectional (Active low)
Port 2 port.
RESET 4 Input which is used to
35-38 P20-P23 contain the four
initialize the processor.
high order program counter
(Active low)
bits during an external pro-
gram memory fetch and (Non TTL VIH)
serve as a 4-bit I/O expander WR 10 Output strobe during a bus
bus for 8243. write. (Active low)
DBO-DB7 12-19 True bidirectional port Used as write strobe to
BUS which can be written or read external data memory.
synchronously using the ALE 11 Address latch enable. This
RD, WR strobes. The port signal occurs once during
can also be statically each cycle and is useful as a
latched. clock output.
Contains the 8 low order The negative edge of ALE
program counter bits during strobes address into ex-
an external program ternal data and program
memory fetch, and receives memory.
the addressed instruction
PSEN 9 Program store enable. This
under the control of PSEN.
Also contains the address output occurs only during a
fetch to external program
and data during an external
memory. (Active low)
RAM data store instruction,
under control of ALE, RD, SS 5 Single step input can be
and WR. used in conjunction with
TO ALE to "single step" the
Input pin testable using the
processor through each
conditional transfer in-
instruction. (Active low)
structions JTO and JNTO. TO
can be designated as a clock EA 7 External access input which
output using ENTO ClK forces all program memory
instruction. fetches to reference external
T1 39 Input pin testable using the memory. Useful for emula-
JT1, and JNT1 instructions. tion and debug, and
Can be designated the essential for testing and
timer/counter input using program verification.
the STRT CNT instruction. (Active high)
INT 6 Interrupt input. Initiates an XTAl1 2 One side of crystal input for
interrupt if interrupt is internal oscillator. Also
enabled. Interrupt is dis- input for external source.
abled after a reset. Also (Non TTL VIH)
XTAl2 3 Other side of crystal input.
7.?1 AFN-01S91A-02
inter 8048L [F)[ffi ~[}J ~OOO&[ffiW
INSTRUCTION SET

,
ADD A, R Add register to A 1 1 CALL addr Jump to subroutine 2 2
ADDA,@R Add data memory to A 1 1 RET Return 2
ADD A, # data Add immediate to A 2 2 RETR Return and restore status
ADDC A, R Add register with carry
ADDC A, @R Add data memory with carry
ADDC A, # data Add immediate with carry Flags
ANL A, R And register to A Mnemonic Description Bytes Cycles
ANLA,@R And data memory to A CLR C Clear carry 1 1
ANL A, # data And immediate to A CPL C Complement carry
ORL A, R Or register to A CLR FO CLear flag 0
ORLA@R Or data memory to A CPL FO Complement flag 0
ORL A, # data Or immediate to A CLR Fl Clear flag 1
XRL A, R Exclusive or register to A CPL Fl Complement flag 1
XRL A, @R Exclusive or data memory to A
XRL, A, # data Exclusive or immediate to A
DEGA Decrement A
CLR A Clear A Mnemonic Description Bytes Cycles
CPL A Complement A MOV A, R Move register to A 1 1
DA A Decimal adjust A MOVA,@R Move data memory to A
SWAP A Swap nibbles of A MOV A, # data Move immediate to A
RL A Rotate A left MOV R, A Move A to register
RLCA Rotate A left through carry MOV@R,A Move A to data memory
RR A Rotate A right MOV R, # data Move immediate to register
RRGA Rotate A right through carry MOV @R, #data Move immediate to data memory
MOVA,PSW Move PSW to A
MOV PSW, A Move A to PSW
Input/Output XCH A, R Exchange A and register
XCH A, @R Exchange A and data memory
Mnemonic Description Bytes Cycles XCHD A, @R Exchange nibble of A and
IN A,P Input port to A 1 2 register
oun P, A Output A to port MOVX A, @R Move external data memory to A 2
ANL P, # data And immediate to port MOVX@R, A Move A to external data memory 2
ORL P, # data Or immediate to port MOVPA, @A Move to A from current page 2
INS A, BUS Input BUS to A MOVP3 A, @ Move to A from page 3 2
oun BUS, A Output A to BUS
ANL BUS, # data And immediate to BUS
ORL BUS, # data Or immediate to BUS
Timer/Counter
MOVD A,P Inpu,t expander port to A
MOVD P, A Output A to expander port MnemoniC Description Bytes Cycles
ANLD P, A And A to expander port MOV A, T Read timer/counter 1 1
ORLD P, A Or A to expander port MOV T, A Load timer/counter
STRT T Start timer
Registers STOP TCNT Stop timer/counter
EN TCNTI Enable timer/counter interrupt
DIS TCNTI Disable timer/counter interrupt
INC R Increment register 1
INC@R Increment data memory

DIS 1 Disable external interrupt 1
Mnemonic Description Bytes Cycles SEL RBO Select register bank 0
JMP addr Jump unconditional 2 2 SEL RBI Select register bank 1
JMPP@A Jump indirect SEL MBO Select memory bank 0
DJNZ R, addr Decrement register and skip SEL MBI Select memory bank 1
JC addr Jump on carry = 1 ENT 0 CLK Enable clock output on TO
JNC addr Jump on carry = 0
JTO addr Jump on TO = 1 NOP No operation 1 1
JNTOaddr Jump on TO = 0
JT1 addr JumponTl = 1
JNTI addr Jump on Tl = 0
JFO addr Jump on FO = 1
JF1 addr Jump on Fl = 1
JNl addr Jump on INT = 0
AFN-01591A-03
7-?2
8048L
ABSOLUTE MAXIMUM RATINGS COMMENT Stresses above those listed under "Abso-
Ambient Temperature Under Bias ....... 00 C to 70 0 C lute Maximum Ratings" may cause permanent damage to
Storage Temperature ............... -65 0 C to + 125 0 C the device. This is a stress rating only and functional
Voltage On Any Pin With Respect operation of device at these or any other conditions
to Ground ............................ -0.5V to +7V above those indicated in the operational sections of this
Power Dissipation ......................... 1.5 Watt specification is not implied.
D.C. AND OPERATING CHARACTERISTICS TA = OC to 70C, VCC = VOO = 5V 10%, VSS = OV
Limits
Min. Typ. Max.
V IL Input Low Voltage -.5 .8 V
V IL1 Input Low Voltage -.5 .6 V
(RESET, X1, X2)
(All Except XTAL1, XTAL2, RESET)
V IH1 Input High Voltage (X1, X2, RESET) 3.8 VCC V
VOL Output Low Voltage (BUS) .45 V VOL = 2.0 mA
V OL1 Output Low Voltage .45 V IOL =1.8 mA
(RO, WR, PSEN, ALE)
V OL2 Output Low Voltage (PROG) .45 V IOL =1.0 mA
VOL3 Output Low Voltage .45 V IOL =1.6 mA
(All Other Outputs)
V OH Output High Voltage (BUS) 2.4 V IOH = -400 /-L A
V OH1 Outp~igh Voltage 2.4 V IOH =-100 /-LA
(RO, WR, PSEN, ALE)
VOH2 Output High Voltage 2.4 V IOH =-40 /lA
(All Other Outputs)
1L1 Input Leakage Current (T1, INT) 10 /-LA VSS < VIN < VCC
IU1 Input Leakage Current -500 IlA VSS + .45~VIN~YCC
(P10-P17, P20-P27, EA, SS)
I LO Output Leakage Current (BUS, TO) 10 I1A VSS + .45 ~VIN ~Ycc
100 V DO Supply Current 2 4 mA
100+ Total Supply Current 20 40 mA
ICC
VOO Ram Standby Pin Voltage 2.2 5.5 V Standby Mode, Reset:50.6V
BUS Pl, P2 BUS, Pl, P2

50 rnA -500 /1A 50 rnA
:I:
.9
-10 rnA
OV 2V 4V
:I:
.9
-300 /1
-100/1A
OV 2V 4V
-' 30 rnA
.9
10 rnA
OV
~
0 2V
VOL
4V
VOH VOH
7_?1. AFN-01591A-04
8048L
A.C. CHARACTERISTICS (PORT 2 TIMING)

TA = oDe to 7oDe, vcc = 5V -+- 10%, Vss - OV
TCY =4.17 J,JS
tcp Port Control Setup Before Falling 185 ns
Edge of PROG
tpc Port Control Hold After Falling 160 ns
Edge of PROG
tpR PROG to Time P2 Input Must Be Valid 1.35 J..ls
tpF Input Data Hold Time 0 250 ns
tDP Output Data Setup Time 420 ns
tpD Output Data Hold Time 110 ns
tpp PROG Pulse Width 2.0 J..ls
tpL Port 2 I/O Data Setup 585 ns
tLP Port 2 I/O Data Hold 250 ns
PORT 2 TIMING
ALE J \~---~y
EXPANDER
PORT
I
OUTPUT PCH PORT CONTROL OUTPUT DATA
I
EXPANDER
PORT
INPUT PCH PORT 20 3 DATA
PROG ------------------4~
I 114.---tPP'----
V
I I
BUS TIMING AS A FUNCTION OF TCY *

SYMBOL FUNCTION OF TCY SYMBOL FUNCTION OF TCY
TLL 7/30 TCY MIN TRD (1) 2/5 TCY MAX TRD (1) : RD
TAL 2/15 TCY MIN TRD (2) 3/10 TCY MAX T RD (2) : PSEN
TLA 1/15 TCY MIN TAW 1/3 TCY MIN
TCC (1) 1/2 TCY MIN TCC (1) : RD/WR TAD (1) 11/15 TCY MAX TAD (1) : RD
TCC (2) 2/5 TCY MIN T cc (2) : PSEN TAD (2) 8/15 TCY MAX TAD (2) : PSEN
TOW 13/30 TCY MIN TAFC (1) 2/15 TCY MIN TAFC (1): RD
TWO 1/15 TCY MIN TAFC (2) 1/30 TCY MIN T AFC (2): PSEN
TOR 0 MIN TCA (1) 1/15 TCY MIN TCA (1) : RD, WR
APPROXIMATE VALUES NOT INCLUDING GATE DELAYS. TCA (2) 2/15 TCY MIN T CA (2) : PSEN
AFN-01591 A-OS
7-?A.
8048L
WAVEFORMS
i_
4
- - t L - L - _ - I - - tCY -------1
ALE J ,--I_ _ _----'1..------.L ALE J I L
I --tAFC!_TCC-1 TCA f.-
r------------
! _ tCC -1 tCA \-
--------~--r_~ --------~I 1
t
RD
tAFCj f-- -[ tOR

IFLOATING
BUS ~ -F-L-OA-T-IN-G---
BUS
l-tAD~1
ALE J L
WR
2.4V - - - - - - . . . . . ~-----
O.4SV _ _ _ _ _ _ .JX ~:~ ~ TEST POINTS ::~:~X'-____

BUS
Write to External Data Memory Input and Output for A.C.Tests,
A.C. CHARACTERISTICS TA =ODC to 70 DC, Vcc = Voo = 5V + 10%, Vss = OV
Symbol Parameter Unit Conditions (Note 1)

Min. Max.
tLL ALE Pulse Width 600 ns
tAL Address Setup to ALE 150 ns
tLA Address Hold from ALE 80 ns
tcc Control Pulse Width (PSEN, RD, WR) 1500 ns
tow Data Setup before WR 640 ns
two Data Hold After WR 120 ns CL = 20pF
tCY Cycle Time 4.17 15.0 gs
tOR Data Hold 0 200 ns

tRO PSEN, RD to Data In 750 ns
tAW Address Setup to WR 260 ns
tAO Address Setup to Data In 1450 ns
tAFC Address Float to RD, PSEN 0 ns
tCA Control Pulse to ALE 20 ns
Note 1: Control outputs: CL = 80 pF

BUS Outputs: C
L
= 150 pF
AFN-01591A-06
8048L
CRYSTAL OSCILLATOR MODE
~:f-l -::-lr-:-:--,L
. . . -.-~
-C-2 XTAll
~ ~3:1- _ _L...--_----<
T_.-----'-I3 XTAl2
<
Cl = 5pF 1/2pF + STRAY 5pF
C2 = CRYSTAL + STRAY < 8pF
C3 = 20pF lpF + STRAY < 5pF
CRYSTAL SERIES RESISTANCE SHOULD BE LESS THAN 75S} AT 6 MHz LESS THAN l80Q AT 3.6MHz
LC OSCILLATOR MODE
l C NOMINAL 1 1
45pH 20pF 5.2 MHz F---
120pH 20pF 3.2 MHz 2rrIjLC
2
rt
XTAll
C + Cpp
C
2
~
Jl
).
-= "'[C
3 XTAl2
Cpp 5-10 pF PIN TO PIN
0
CAPACITANCE
EACH C SHOULD BE APPROXIAMTELY 2OpF. INCLUDING STRAY CAPACITANCE
DRIVING FROM EXTERNAL SOURCE
+5V
470,1;1
D-......- - - - - ; XTAll
+5V
470,1;1
' - - -......---1 XTAl2
XTAL 1 MUST BE HIGH 35-65% OF THE PERIOD AND XTAL 2 MUST BE HIGH 35-65% OF THE
PERIOD. RISE AND FALL TIMES MUST NOT EXCEED 20n8.
AFN-01S91A-07
S049H/S039HL
HMOS SINGLE COMPONENT S-BIT MICROCOMPUTER
8049H Mask Programmable ROM
8039HL CPU Only with Power Down Mode
S-BIT CPU, ROM, RAM, 1/0 in Single

Package
64
1K x S ROM
x S RAM
27 1/0 Lines
High Performance HMOS
Reduced Power Consumption Interval TimerlEvent Counter
All
1.4 usec and 1.9 ~sec
Cycle Versions Easily Expandable Memory and 1/0
Instructions 1 or 2 Cycles. Compatible
Peripherals
with SOSO/SOS5 Series
Over 90 instructions: 70% Single Byte

Two Single Level Interrupts
The Intel 8049H/8039HL are totally self-sufficient, 8-bit parallel computers fabricated on single silicon chips
using Intel's advanced N-channel silicon gate HMOS process.
The 8049H contains a 2K X 8 program memory, a 128 X 8 RAM data memory, 27 I/O lines, and an 8-bit
timer/counter in addition to on-board oscillator and clock circuits. For systems that require extra capability
the 8049H can be expanded using standard memories and MCS-80/MCS-85 peripherals. The 8039HL is
the equivalent of the 8049H without program memory and can be used with external ROM and RAM.
To reduce development problems to a minimum and provide maximum flexibility, a logically and functionally
pin compatible version of the 8049H with UV-erasable user-programmable EPROM program memory will
soon be available. The 8749 will emulate the 8049H up to 1 MHz clock frequency with minor differences.
The 8049H is fully compatible with the 8049.
These microcomputers are designed to be efficient controllers as well as arithmetic processors. They have
extensive bit handling capability as well as facilities for both binary and BCD arithmetic. Efficient use of
program memory results from an instruction set consisting mostly of single byte instructions and no
instructions over 2 bytes in length.
TO Vee
PORT
01 XTAL 1 T1
XTAL 2 P27
RESET 4 P26
PORT 55 P2S
02
P24
8049H EA PH
8039HL
AD P16
PSEN 9 P1S
WR P14
P13
P12
DB1 P11
DB2 P10
DB3 VDD
DB4 PROG
DBS P23
DB6 P22
BUS
DB7 P21
VSS P20
Figure 1. Figure 2. Figure 3.

Block Diagram Logic Symbol Pin Configuration
Intel Corporation Assumes No Responsibilty for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenses are Implied
'INTEL CORPORATION, 1980 7-27 AFN-01784A-01
S049H/S039HL
Symbol Pin No. Function Symbol Pin No. Function

-
VSS 20 Circuit GND potential RD 8 Output strobe activated during a
26 low power standby pin BUS read. Can be used to enable
VDD
data onto the bus from an
VCC 40 Main power supply; +5V during external device.
operation.
Used as a read strobe to external
PROG 25 Output strobe for 8243 I/O data memory. (Active low)
expander. ---
RESET 4 Input which is used to initialize
P10-P17 27-34 8-bit quasi-bidirectional port. the processor. (Active low)
Port 1 (Non TTL V IH )
P20-P27 21-24 8-bit quasi-bidirectional port. -
WR 10 Output strobe during a bus write.
Port 2 (Active low)
35-38 P20-P23 contain the four high Used as write strobe to external
order program counter bits dur- data memory.
ing an external program memory
fetch and serve as a 4-bit I/O ALE 11 Address latch enable. This signal
expander bus for 8243. occurs once during each cycle
and is useful as a clock output.
DBO-DB7 12-19 True bidirectional port which
BUS can be written or read The negative edge of ALE strobes
synchronously using the RD, WR address into external data and
strobes. The port can also be program memory.
statically latched. PSEN 9 Program store enable. This out-
Contains the 8 low order pro- put occurs only during a fetch to
gram counter bits during an external program memory.
external program memory fetch, (Active low)
-
and receives the addressed SS 5 Single step input can be used
instruction under the control of in conjunction with ALE to "single
PSEN. Also contains the address step" the processor through each
and data during an external RAM instruction. (Active low)
data store instruction, under
EA 7 External access input which
control of ALE, RD, and WR.
forces all program memory
TO 1 Input pin testable using the fetches to reference external
conditional transfer instructions memory. Useful for emulation
JTO and JNTO. TO can be and debug, and essential for
designated as a clock output testing and program verification.
using ENTO ClK instruction. (Active high)
T1 39 Input pin testable using the JT1, XTAL1 2 One side of crystal input for
and JNT1 instructions. Can be internal oscillator. Also input for
designated the timer/counter external source. (Non TTL V IH )
input using the STRT CNT
XTAl2 3 Other side of crystal input.
instruction.
INT 6 Interrupt input. Initiates an
interrupt if interrupt is enabled.
Interrupt is disabled after a reset.
Also testable with conditional
jump instruction. (Active low)
7-28 AFN-01784A-02
S049H/S039HL
Table 2. Instruction Set

ADD A. R Add register to A 1 1 CALL addr Jump to subroutine 2 2
ADD A.@R Add data memory to A RETR Return
ADD A. # data Add immediate to A RETR Return and restore status
ADDC A. R Add register with carry
ADDC A.@R Add data memory with carry
ADDC A. # data Add immediate with carry Flags
ANL A. R And register to A Mnemonic Description Bytes Cycles
ANL A. @R And data memory to A CLR C Clear carry 1 1
ANL A. # data And immediate to A CPL C Complement carry
ORL A. R Or register to A CLR FO CLear flag 0
ORL A@R Or data memory to A CPL FO Complement flag 0
ORL A. # data Or immediate to A CLR F1 Clear flag 1
XRL A. R Exclusive or register to A CPL F1 Complement flag 1
XRL A. @R Exclusive or data memory to A
XRL. A. # data Exclusive or immediate to A
DEC A Decrement A
CLR A Clear A Mnemonic Description Bytes Cycles
CPL A Complement A MOV A. R Move register to A 1 1
DAA Decimal adjust A MOVA.@R Move data memory to A
SWAP A Swap nibbles of A MOV A. # data Move immediate to A
RL A Rotate A left MOV R. A Move A to register
RLC A Rotate A left through carry MOV@R.A Move A to data memory
RR A Rotate A right MOV R. # data Move immediate to register
RRC A Rotate A right through carry MOV @R. #data Move immediate to data memory
MOVA. PSW Move PSW to A
MOV PSW. A Move A to PSW
Input/Output XCH A. R Exchange A and register
XCH A. @R Exchange A and data memory
Mnemonic Description Bytes Cycles XCHD A. @R Exchange nibble of A and
IN A. P Input port to A 1 2 register
OUTL P. A Output A to port MOVX A. @R Move external data memory to A
ANL P. # data And immediate to port MOVX @R. A Move A to external data memory
ORL p. # data Or immediate to port MOVPA.@A Move to A from current page 2
INS A. BUS Input BUS to A MOVP3 A. @ Move to A from page 3 2
OUTL BUS. A Output A to BUS
ANL BUS. # data And immediate to BUS
ORL BUS. # data Or immediate to BUS
Timer/Counter
MOVD A.P Input expander port to A
MOVD P. A Output A to expander port Mnemonic Description Bytes Cycles
ANLD P. A And A to expander port MOV A. T Read timer/counter 1 1
ORLD P. A Or A to expander port MOV T. A Load timer/counter
STRT T Start timer
Registers STOP TeNT Stop timer/counter
EN TCNT1 Enable timer/counter interrupt
DIS TCNT1 Disable timer/counter interrupt
INC R Increment register 1 1
INC@R Increment data memory 1
Mnemonic Description Bytes. Cycles

DIS 1 Disable external interrupt
Mnemonic Description Bytes Cycles SEL RBO Select register bank 0
JMP addr Jump unconditional 2 2 SEL RB1 Select register bank 1
JMPP@A Jump indirect SEL MBO Select memory bank 0
DJNZ R. addr Decrement register and skip SEL MB1 Select memory bank 1
JC addr Jump on carry = 1 2 2 Enable clock output on TO
ENT 0 CLK
JNC addr Jump on carry = 0 2 2
JTO addr Jump on TO = 1 NOP No operation 1 1
JNTO addr Jump on TO = 0
JT1 addr Jump on T1 = 1
JNT1 addr Jump on T1 = 0
JFO addr Jump on FO = 1
JF1 addr Jump on F1 = 1
JN1 addr Jump on INT = 0
7-29 AFN-01784A-03
Intel S049H/S039H L
ABSOLUTE MAXIMUM RATINGS* *NOTlCE:Stresses above those listed under "Absolute

Ambient Temperature Under Bias ....... 0 C to 70 C Maximum Ratings" may cause permanent damage to the
Stoiage Temperature .............. -65C to + 150C device. This is a stress rating only and functional opera-
Voltage On Any Pin With Respect tion of device at these or any other conditions above those
to Ground ........................... -0.5V to +7V indicated in the operational sections of this specification
Power Dissipation .......................... 1.5 Watt is not implied.
D.C. CHARACTERISTICS (TA = OC to 70C, VCC = VDD = 5V 10%, VSS = OV)
Limits
Min. Typ. Max.
VIL Input Low Voltage -.5 .8 V

VIL1 Input Low Voltage -.5 .6 V

(RESET, X1, X2)

(All Except XTAL 1, XTAL2, RESET)
VIH1 Input High Voltage (X1, X2, RESET) 3.8 VCC V
VOL Output Low Voltage (BUS) .45 V IOL = 2.0 mA
VOL1 Outp~ow Voltage .45 V IOL=1.8mA

(RD, WR, PSEN, ALE)
VOL2 Output Low Voltage (PROG) .45 V IOL = 1.0 mA
VOL3 Output Low Voltage .45 V IOL = 1.6 rnA

(All Other Outputs)
VOH Output High Voltage (BUS) 2.4 V IOH=-400 JlA
VO H 1 Outp~High Voltage 2.4 V IOH=-100 JlA

(RD, WR, PSEN, ALE)
VOH2 Output High Voltage 2.4 V IOH =-40 Jl A

(All Other Outputs)
1L1 Input Leakage Current (T1, INT) :!:. 10 fLA VSS $ VIN $ VCC
IU1 Input Leakage Current _ -500 fLA VSS + .45 ~ VIN:5 VCC
(P10-P17, P20-P27, EA, SS)
ILO Output Leakage Current (BUS, TO) . 10 fLA VSS + .45:$ VIN :5 VCC
IDD V DD Supply Current 5 10 mA
IDD + Total Supply Current 50 100 mA

~CC
BUS Pl. P2 BUS, Pl, P2

50 mA -500/lA 50 mA
:z:
9
OV 2V
VOH
4V
9
:z: -300
-100/lA
/l
OV 2V
VOH
4V
....I
9
30 mA
10 mA
OV
~
~ 2V
VOL
4V
7-30 AFN-01784A-04
S049H/S039HL
A.C. CHARACTERISTICS (TA = OC to 70C, VCC = VDD = 5V 10%, VSS =OV)
f (tCY) 11 MHz Conditions

Symbol Parameter (Note 3) Min. Max. Unit (Note 1)
tLL ALE Pulse Width 7/30 tCY -170 150 ns
tAL Addr Setup to ALE 1I5tCy-110 160 ns
tLA Addr Hold from ALE 1/15 tCY -40 50 ns
tCC1 Control Pulse Width (RD, WR) 1/2 tCY -200 480 ns
--
tCC2 Control Pulse Width (PSEN) 2/5 tCY -200 350 ns
tow Data Setup before WR 13/30 tCY -200 390 ns

-
two Data Hold after WR 1/5 tCY -150 120 ns (Note 2)
Data Hold
---
(RD, PSEN) 0 110 ns
tOR 1/10 tCY -30
-
tRD1 RD to Data in 2/5 tCY -200 350 ns
tRD2 PSEN to Data in 3/10 tCY -200 210 ns

-
tAW Addr Setup to WR 2/5 tCY -150 300 ns
-
tAD1 Addr Setup to Data (RD) 23/30 tCY -250 750 ns
tAD2 Addr Setup to Data (PSEN) 3/5 tCY -250 480 ns

--
t AFC1 Addr Float to RD, WR 2/15 tCY -40 140 ns
tAFC2 Addr Float to PSEN 1/30 tCY -40 10 ns

--
tLAFC1 ALE to Control, (RD, WR) 1/5t Cy-75 200 ns
tLAFC2 ALE to Control (PSEN) 1/10 tCY -75 60 ns
tCA1 Control to ALE (RD, WR, PROG) 1/ 15t Cy-40 50 ns

--
tCA2 Control to ALE (PSEN) 4/15 tCY -40 320 ns
--
tcp Port Control Setup to PROG 1110 tCY -40 100 ns
tpc Port Control Hold to PROG 4/15 tCY -200 160 ns
tpR PROG to P2 Input Valid 17/30 tCY -120 650 ns

--
tpF Input Data Hold from PROG 1110 tCY 0 140 ns
top Output Data Setup 2/5 tCY -150 400 ns
tpD Output Data Hold 1/10 tCY -50 90 ns
tpp PROG Pulse Width 7/10 tCY -250 700 ns
tPL Port 2 I/O Setu p to ALE 4/15 tCY -200 160 ns
t LP Port 2 I/O Hold to ALE 1/10 tCY -100 40 ns
tpv Port Output from ALE 3/10 tCY +100 510 ns
tCY Cycle Time 1.36 IJs
t
OPRR
to Rep Rate 3/15 tCY 270 ns
Notes:
1. Control Outputs CL = 80pF 2. BUS High Impedance Load 20pF 3. Calculated values will be equal
BUS Outputs CL = 150pF to or better than published 8049 values.
7-31 AFN-01784A-05
S049H/S039HL
WAVEFORMS
----.l TLAFC1 L
ALE J---\L..__ 1_ _ _ _..... 1 L
RD ------i\
r- ICC1 -..j
1
ICA1 1-
IAFC1j
I~
FLOATING
-I tlDR
_ _ _ _ __
BUS ~ FLOATING
~ IAD1 i :IIRD1
---..j T LAFC1
ALE Jr"------. L
ICA1 1---
WR
2.4V - - - - _ _
0.4SV _ _ _ _ --JX~:: ~ TEST POINTS ~:::X'"
r-----
_____
BUS
Write to External Data Memory Input and Output for A.C. Tests
PORT 2 EXPANDER TIMING
ALE J \----------! \ /
'------~lrICA1
EXPANDER
PORT rIDP-ttPDl
I
OUTPUT PCH PORT 20-23 DATA I PORT CONTROL OUTPUT DATA
EXPANDER
PORT
1001----- IpR - - - - - . I
I
INPUT PCH PORT 20-23 DATA PORT CONTROL
PROG
AFN-01784A-06
7-32
S049H/S039HL
1/0 PORT TIMING
1ST CYCLE 2ND CYCLE
J \ I-' 1-----,t 1
ec
'ev /'--'----'L
ALE
I 1 1'-----1 - - - - I
PSEN
\-------1/
I
~~~~~T~~----------PC-H------------~)(~-------P-O-R-T-2-0--2-3-D-A-TA--------~)(~____N_E_W_P_2_0-_23__DA_T_A____J)(~ ______ PC_H
______
I
P24-27 ----------------------------------------------------------~xr----------------------------------
OUTPUT __________________________________________________________
P10-17 PORT 24-27, PORT 10-17 DATA - J ~______________________________
NEW PORT DATA ___
DRIVING FROM
OSCILLATOR MODE LC OSCILLATOR MODE EXTERNAL SOURCE
,. - -1 +5V
m
C1
27TVLC'
~ e';t' =
1----,--.....--tXTAL1 XTAL1
C = 3Cpp
JC C'=--2-
470Q
~C L Cpp'" 5-10 pF )o-~"""------1 XTAL1
':' 1-~!--....--tXTAL2 ':' 3

XTAL2
PIN-TO-PIN
CAPACITANCE
+5V
3
C3
OPEN
C1 =5pF 1/2pF + STRAY < 5pF COLLECTOR 470 Q
C NOMINAL'
C2 = CRYSTAL STRAY < 8pF TTL GATES 3
C3 = 20pF + 1pF STRAY < 5pF 20pF 5,2 MHz XTAL2
20pF 3.2 MHz
CRYSTAL SERIES RESISTANCE SHOULD EACH C SHOULD BE APPROXIMATELY 20pF, FOR THE 8048, XTAL 1 MUST BE HIGH
BE LESS THAN 75 II AT 6MHz; LESS THAN INCLUDING STRAY CAPACITANCE. 35-65% OF THE PERIOD AND XTAL2
180 II AT 3.6MHz. MUST BE HIGH 35-65% OF THE PERIOD
RISE AND FALL TIMES MUST

NOT EXCEED 20n5
AFN-01784A-07
7-33
8243
MCS-48 INPUT/OUTPUT EXPANDER
Low Cost 24-Pin DIP

Simple Interface to MCS-48 Single 5V Supply
Microcomputers High Output Drive
Four 4-Bit 1/0 Ports Direct Extension of Resident 8048 1/0
AND and OR Directly to Ports Ports
The Intel 8243 is an input/output expander designed specifically to provide a low cost means of 1/0
expansion for the MCS-48 falT)ily of single chip microcomputers. Fabricated in 5 volts NMOS, the 8243
combines low cost, single supply voltage and high drive current capability.
The 8243 consists of four 4-bit bidirectional static 1/0 ports and one 4-bit port which serves as an interface to
the MCS-48 microcomputers. The 4-bit interface requires that only 4 1/0 lines of the 8048 be used for 1/0
expansion, and also allows multiple 8243's to be added to the same bus.
The 1/0 ports of the 8243 serve as a direct extension of the resident 1/0 facilities of the MCS-48 microcomputers
and are accessed by their own MOV, ANL, and ORL instructions.
PORT4
PSO vee
P40 PS1
PORTS
1'41 P52
Pt12 PS3
PORT 2 P43 P60
CS P61
PROG P62
P23 P63
PORT 6
P22 P73
P21 P72
P20 P71
GND P70
PORT 7
Figure 2. 8243
Pin Configuration
Figure 1. 8243
Block Diagram
Intel Corporation Assumes No Responsibilty for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenses are Implied.
'INTEL CORPORATION. t980 7-34 AFN-D0214A-Ol
8243
Table 1. Pin Description Power On Initialization

Symbol Pin No. Function Initial application of power to the device forces
PROG 7 Clock Input. A high to low transi-
input/output ports 4, 5, 6, and 7 to the tri-state and
tion on PROG signifies that ad- port 2 to the input mode. The PROG pin may be
dress and control are available on either high or low when power is applied. The first
P20-P23, and a low to high transi- high to low transition of PROG causes device to
tion signifies that data is available exit power on mode. The power on sequence is
on P20-P23. initiated if vee drops below 1V.
CS 6 Chip Select Input. A high on CS
inhibits any change of output or
internal status. Address Instruction
P20-P23 11-8 Four (4) bit bi-directional port con- P21 P20 Code P23 P22 Code
tains the address and control bits 0 0 Port 4 0 0 Read
on a high to low transition of 0 1 Port 5 0 1 Write
PROG. During a low to high tran- 0 Port 6 0 ORlD
sition contains the data for a sel- Port 7 ANlD
ected output port if a write opera-
tion, or the data from a selected
port before the low to high transi-
tion if a read operation. Write Modes
GND 12 o volt supply. The device has three write modes. MOVD Pi, A dir-
P40-P43 2-5 Four (4) bit bi-directional I/O ports. ectly writes new data into the selected port and old
P50-P53 1, 23-21 May be programmed to be input data is lost. ORlD Pi, A takes new data, OR's it with
P60-P63 20-17 (during read), low impedance
the old data and then writes it to the port. ANlD Pi, A
P70-P73 13-16 latched output (after write), or a tri-
takes new data, AND's it with the old data and then
state (after read). Data on pins
P20-P23 may be directly written, writes it to the port. Operation code and port ad-
ANDed or ORed with previous dress are latched from the input port 2 on the high
data. to low transition of the PROG pin. On the low to high
VCC 24 +5 volt supply. transition of PROG data on port 2 is transferred to
the logic block of the specified output port.
FUNCTIONAL DESCRIPTION After the logic manipulation is performed, the data
is latched and outputed. The old data remains
General Operation latched until new valid outputs are entered.
The 8243 contains four 4-bit 1/0 ports which serve
as an extension of the on-chip 1/0 and are ad- Read Mode
dressed as ports 4-7. The following operations may
The device has one read mode. The operation code
be performed on these ports:
and port add ress are latched from the input port 2 on
Transfer Accumulator to Port. the high to low transition of the PROG pin. As soon
Transfer Port to Accumulator. as the read operation and port address are decoded,
AND Accumulator to Port. the appropriate outputs are tri-stated, and the input
OR Accumulator to Port. buffers switched on. The read operation is termina-
All communication between the 8048 and the 8243 ted by a low to high transition of the PROG pin. The
occurs over Port 2 (P20-P23) with timing provided port (4,5,6 or 7) that was selected is switched to the
by an output pulse on the PROG pin of the proces- tri-stated mode while port 2 is returned to the input
sor. Each transfer consists of two 4-bit nibbles: mode.
The first containing the "op code" and port address Normally, a port will be in an output (write mode) or
and the second containing the actual 4-bits of data. input (read mode). If modes are changed during
A high to low transition of the PROG line indicates operation, the first read following a write should
that address is present while a low to high transition be ignored; all following reads are valid. This is to
indicates the presence of data. Additional 8243's allow the external driver on the port to settle after
may be added to the 4-bit bus and chip selected the first read instruction removes the low imped-
using additional output lines from the 8048/87481 ance drive from the 8243 output. A read of any port
8035. will leave that port in a high impedance state.
7-35 AFN-00214A-02
8243
ABSOLUTE MAXIMUM RATINGS 'NOTlCE: Stresses above those listed under "Absolute
Ambient Temperature Under Bias ........ OC to 70C tion of the device at these or any other conditions above
Storage Temperature ............... -65C to +150C those indicated in the operational sections of this specifi-
Voltage on Any Pin cation is not implied. Exposure to absolute maximum
With Respect to Ground .............. -0.5 V to +7V rating conditions for extended periods may affect device
Power Dissipation ............................ 1 Watt reliability.
D.C. CHARACTERISTICS TA = OC to 70C, VCC = 5V 10%

Test
Symbol Parameter Min. Typ. Max. Units Conditions
VIH Input High Voltage 2.0 VCC+0.5 V
VOL1 Output Low Voltage Ports 4-7 0.45 V IOL = 4.5 mA'
VOL2 Output Low Voltage Port 7 1 V IOL = 20 mA
VOH1 Output High Voltage Ports 4-7 2.4 V IOH = 240/-LA
1IL1 Input Leakage Ports 4-7 -10 20 /-LA Vin = VCC to OV
IIL2 Input Leakage Port 2, CS, PROG -10 10 /-LA Vin = VCC to OV
VOL3 Output Low Voltage Port 2 .45 V IOL = 0.6 mA
VOH2 Output Voltage Port 2 2.4 IOH = 100/-LA
IOL Sum of all IOL from 16 Outputs 72 mA 4.5 mA Each Pin
'See following graph for additional sink current capability
A.C. CHARACTERISTICS TA = OC to 70C, VCC = 5V 10%

Symbol Parameter Min. Max. Units Test Conditions
tA Code Valid Before PROG 100 ns 80 pF Load
tB Code Valid After PROG 60 ns 20 pF Load
tc Data Valid Before PROG 200 ns 80 pF Load
tD Data Valid After PROG 20 ns 20 pF Load
tH Floating After PROG 0 150 ns 20 pF Load
tK PROG Negative Pulse Width 700 ns
tcs CS Valid Before! After PROG 50 ns
tpo Ports 4-7 Valid After PROG 700 ns 100 pF Load
tLP1 Ports 4-7 Valid Before! After PROG 100 ns
tACC Port 2 Valid After PROG 650 ns 80 pF Load
2.4
0.45----
-----'X > <::x_ 20
0 .8 TEST POINTS
7-36 AFN-00214A-03
8243
WAVEFORMS
PROG
IK
10
PORT2 FLOAT FLOAT
'ACC =>1 ~'Hx

PORT2 OUTPUT
VALID
IpO
PORTS 4-7 PREVIOUS OUTPUT VALID OUTPUT

VALID
liP
-- liP
PORTS 4-7 INPUT VALID
ICS ICS
AFN-00214A-04
7-37
Intel 8243
I
125
100
75
OF ANY I/O PORT PIN va. TOTAL

50 SINK CURRENT OF ALL PINS
25
10 11 12 13
MAXIMUM SINK CURRENT ON ANY PIN @ .45V

MAXIMUM 10L WORST CASE PIN (mAl
Figure 3
Sink Capability Example: This example shows how the use of the 20 mA
sink capability of Port 7 affects the sinking
capability of the other 1/0 lines.
The 8243 can si nk 5 rnA @ .45V on each of its 16 I/O
lines simultaneously. If, however, all lines are not
sinking simultaneously or all lines are not fully
An 8243 will drive the following loads simul-
loaded, the drive capability of any individual line
taneously.
increases as is shown by the accompanying curve.
For example, if only 5 of the 16 lines are to sink

current at one time, the curve shows that each of 2 loads-20 mA @ 1V (port 7 only)
8 loads-4 mA @ .45V
those 5 lines is capable of sinking 9 mA @ .45V (if 610ads-3.2 mA @ .45V
any lines are to sink 9 mA the total IOL must not Is this within the specified limits?
exceed 45 rnA or five 9 mA loads).
Example: How many pins can drive 5 TTL loads (1.6 mA)
assuming remaining pins are unloaded? flOl = (2 x 20) + (8 x 4) + (6 x 3.2) = 91.2 mA.
From the curve: for 10l = 4 mA, flOl "'" 93 mA.
since 91.2 mA < 93 mA the loads are within
10l = 5 x 1.6 mA = 8 mA specified limits.
flOl = 60 mA from curve
# pins =60 mA + 8 mAlpin =7.5 =7
I n this case, 7 lines can sink 8 mA for a total of Although the 20 mA @ 1V loads are used in
56mA. This leaves 4 mA sink current capability calculating fiOL. it is the largest current re-
which can be divided in any way among the quired @ .45V which determines the maximum
remaining 8 1/0 lines of the 8243. allowable EiOl.
NOTE: A 10 to SOK 0 pullup resistor to +SV should be added to 8243 outputs when driving to SV CMOS directly.
7-38 AFN-oG214A-05
8243
-::-
I/O
cs
P4 I/O
PROG PROG
TEST P5 I/O
INPUTS
8048 8243
P6 I/O
P20P23 DATA IN
P2
P7 I/O
Figure 4. Expander Interface
PROG ~\\....-._ _ _--J/ BITS 3,2 BITS 1,0
OO} READ
01 WRITE OO}
01 PORT
.IX'--_____.I)>-----
10 OR 10 ADDRESS
lL AND 11
P20P23 - - { " '_ _ _
ADDRESS (4-BITS) DATA (4-BITS)
Figure 5. Output Expander Timing
BUS
PORT 1
8048
PROG~---------------+----------------~----------------~~--------------~
Figure 6. Using Multiple 8243's
7-39 AFN-00214A-06
inter
8155/8156/8155-2/8156-2
2048 BIT STATIC MOS RAM WITH 1/0 PORTS AND TIMER
256 Word x 8 Bits 1 Programmable 6-Bit I/O Port

Single +5V Power Supply Programmable 14-Bit Binary Counter/
Timer
Completely Static Operation
Compatible with 808SA and 8088 CPU
Internal Address Latch Multiplexed Address and Data Bus
2 Programmable 8 Bit I/O Ports 40 Pin DIP
The 8155 and 8156 are RAM and I/O chips to be used in the 8085A and 8088 microprocessor systems. The RAM portion
is designed with 2048 static cells organized as 256 x 8. They have a maximum access time of 400 ns to permit use with
no wait states in 8085A CPU. The 81552 and 81562 have maximum access times of 330 ns for use with the 8085A2 and
the full speed 5 MHz 8088 CPU.
The I/O portion consists of three general purpose I/O ports. One of the three ports can be programmed to be status
pins, thus allowing the other two ports to operate in handshake mode.
A 14bit programmable counter/timer is also included on chip to provide either a square wave or terminal count pulse
for the CPU system depending on timer mode.
PIN CONFIGURATION BLOCK DIAGRAM
PC 3 Vee
PC 4 pC 2
TIMER IN PC,
0
101M
RESET PC o PA o- 7
PC s PB 7
ADo 7 256 X 8
TIMER OUT PB 6
STATIC
101M PBs RAM
AD
WR
ALE
ADo
PB 4
PB 3
PB 2
PB,
PB o
*
ALE
RD
0 PBo--7
WR
G
AD, PA 7 PC O- 5
AD2 PA 6 RESET TIMER
AD3 PAs
AD4
ADs
PA 4
PA 3
TIMER ClK Lvcc (+5VI
Vss (OVI
TIMER OUT
AD6 PA 2
AD7 PAl
Vss PAo
': 8155/81552 = CE, 8156/81562 = CE
740
8155/8156/8155-2/8156-2
8155/8156 PIN FUNCTIONS

.y'mbol Function ~y'mbol Function
RESET Pulse provided by the 8085A to ini- ALE Address Latch Enable: This control
(input) tialize the system (connect to 8085A (input) signal latches both the address on the
RESET OUT). Input high on this line ADo-7 lines and the state of the Chip
resets the chip and initializes the Enable and IO/M into the chip at the
three I/O ports to input mode. The falling edge of ALE.
width of RESETpulseshouldtypically 10/M Selects memory if low and I/O and
be two 8085A clock cycle times. (input) command/status registers if high.
ADO_7 3-state Address/Data lines that inter- PAO-7(8) These 8 pins are general purpose I/O
(input/output) face with the CPU lower 8-bit Ad- (input/output) pins. The in/out direction is selected
dress/Data Bus. The 8-bit address is by programming the command
latched into the address latch inside register.
the 8155/56 on the falling edge of
ALE. The address can be either for Pl3o-7(8) These 8 pins are general purpose I/O
the memory section or the I/O section (input/output) pins. The in/out direction is selected
depending on the 10iM input. The by programming the command
8-bit data is either written into the register.
chip or read from the chip, depending PCo-s(6) These 6 pins can function as either
on the WR or RD input signal. (input/output) input port, output port, or as control
CE or CE Chip Enable: On the 8155, this pin is signals for PA and PB. Programming
(input) CE and is ACTIVE LOW. On the 8156, is done through the command reg-
this pin is CE and is ACTIVE HIGH. ister. When PCo-s are used as control
signals, they will provide the fol-
RD Read control: Input low on this line lowing:
(input) with the Chip Enable active enables PCo - A INTR (Port A Interrupt)
and ADo-7 buffers. If 10iM pin is low, PC1 - ABF (Port A Buffer Full)
the RAM content will be read out to PC2 - A STB (Port A Strobe)
the AD bus. Otherwise the content PC3 - B INTR (Port B Interrupt)
of the selected I/O port or command/ PC4 - B BF (Port B Buffer Full)
status registers will be read to the PCs - B STB (Port B Strobe)
AD bus.
TIMER IN Input to the counter-timer.
WR Write control: Input low on this line (input)
(input) with the Chip Enable active causes
the data on the Address/Data bus to TIMER OUT Timer output. This output can be
be written to the RAM or I/O ports and (output) either a square wave or a pulse de-
command/status register depending pending on the timer mode.
on 10iM. Vee +5 volt supply.
Vss Ground Reference.
7-41
8155/8156/8155-2/8156-2
ABSOLUTE MAXIMUM RATINGS *COMMENT: Stresses above those listed under "Absolute
device. This is a stress rating only and functional opera
TemperatureUnderBias ................ 0Cto+70C tion of the device at these or any other conditions above
Storage Temperature ... . . . . . . . . . . .. -65C to +150 C those indicated in the operational sections of this specifi
With Respect to Ground ............... -0.5V to +7V rating conditions for extended periods may affect device
Power Dissipation ..... . . . . . . . . . . . . . . . . . . . . . . .. 1.5W reliability.
D.C. CHARACTERISTICS (TA = OC to 70C; Vee = 5V 5%)
SYMBOL PARAMETER MIN. MAX. UNITS TEST CONDITIONS

VIH Input High Voltage 2.0 Ve e +O 5 V
VOL Output Low Voltage 0.45 V IOL = 2mA

VOH Output High Voltage 2.4 V IOH = -400J.(A
IlL I n put Lea kage 10 iJ.A VIN = Vee to OV
ILO Output Leakage Current 10 iJ.A 0.45V ~ VOUT ~ Vec
Ice Vee Supply Current 180 mA
IldeE) Chip Enable Leakage

8155 +100 p.A V,N = Vee to OV
8156 -100 p.A
742
8155/8156/8155-2/8156-2
A.C. CHARACTERISTICS (TA = oc to 70C; VCC = 5V 5%)

8155/8156 8155-2/8156-2
(Preliminary)
SYMBOL PARAMETER MIN. MAX. MIN. MAX. UNITS
tAL Address to Latch Set Up Time 50 30 ns
tlA Address Hold Time after Latch 80 30 ns
tLC Latch to R EADIWR IT E Control 100 40 ns
tRO Valid Data Out Delay from READ Control 170 140 ns
tAo Address Stable to Data Out Valid 400 330 ns
tll Latch Enable Width 100 70 ns
tROF Data Bus Float After READ 0 100 0 80 ns
tel R EAD/WR ITE Control to Latch Enable 20 10 ns

tee READ/WR ITE Control Width 250 200 ns
tow Data In to WR ITE Set Up Time 150 100 ns
two Data In Hold Time After WR ITE 0 0 ns
tRV Recovery Time Between Controls 300 200 ns
twp WR ITE to Port Output 400 300 ns
tpR Port Input Setup Time 70 50 ns
tRP Port Input Hold Time 50 10 ns
tSBF Strobe to Buffer Full 400 300 ns
tss Strobe Width 200 150 ns
tRBE READ to Buffer Empty 400 300 ns
tSI Strobe to I NTR On 400 300 ns
tROI READ to INTR Off 400 300 ns
tpss Port Setup Time to Strobe Strobe 50 0 ns
tpHS Port Hold Time After Strobe 120 100 ns
tSBE Strobe to Buffer Empty 400 300 ns
tWBF WR ITE to Buffer Full 400 300 ns
tWI WR ITE to INTR Off 400 300 ns
tTL TIMER-IN to TIMER-OUT Low 400 300 ns
tTH TIMER-IN to TIMER-OUT High 400 300 ns
tROE Data Bus Enable from READ Control 10 10 ns
t1 TIMER-IN Low Time 80 40 ns
t2 TIMER-IN High Time 120 70 ns
Input Waveform for A.C. Tests:
7-43
8155/8156/8155-2/8156-2
WAVEFORMS
8. Read Cycle
CE (8155 )
\r- ~( '\
OR
CE (8156 ) jf- ~\
/
101M
\ ,/ '\
.. tAD
If- r-
~
-'I ~
~ ADDRESS
-J )t-- ~
DATA VALID
.., H
- t Al - - t LA -
AL E J<- ~I\.- .(
- tLL - l" tROE .. I-- t RoF ....
t><-
~~
~"--
___ tRO_
,I{
_ t LC - -
- tcc -
--
- tRV -
t CL -
b. Write Cycle
CE (8155)
OR
CE (8156)
101M
AD0-7 DATA VALID
ALE
_ t wo -
tRV-
Figure 12. 8155/8156 Read/Write Timing Diagrams
7-44
8155/8156/8155-2/8156-2
8. Strobed Input Mode
BF
INTR
INPUT DATA
FROMPORT _____________________ ~~_________~___~~~--------------------------------------------------------------------
b. Strobed Output Mode
BF
INTR
OUTPUT DATA
TOPORT ________________________________~~~------------------------------------------
Figure 13. Strobed I/O Timing

8155/8156/8155-2/8156-2
a. Basic Input Mode
DATA BUS" ==- =-= -=- -=- =><___________

b. Basic Output Mode
DATA BUS
OUTPUT
"DATA BUS TIMING IS SHOWN IN FIGURE 7.
Figure 14. Basic I/O Timing Waveform
I
LOAD COUNTER FROM CLR
2 I 1
--l
I
RELOAD COUNTER FROM CLR
I 2 I 1
-I
TIMER IN
TIMER OUT
(PULSE) "
'- (NOTE
___ 1)
J"
TIMER OUT , I
(SOUARE WAVE) , (NOTE 1) I
'- _ _ _ _ _ _ _ _ J
NOTE 1: THE TIMER OUTPUT IS PERIODIC IF IN AN AUTOMATIC

RELOAD MODE (M MODE BIT = 1)
1
Figure 15. Timer Output Waveform Countdown from 5 to 1
7-46
inter
8185/8185-2
1024 x 8-BIT STATIC RAM FOR MCS-85
Multiplexed Address and Data Bus Low Standby Power Dissipation
Directly Compatible with 808SA

and 8088 Microprocessors Single +5V Supply
Low Operating Power Dissipation High Density 18-Pin Package
The Intel@ 8185 is an 8192-bit static random access memory (RAM) organized as 1024 words by 8-bits using
N-channel Silicon-Gate MOS technology. The multiplexed address and data bus allows the 8185 to interface directly
to the 8085A and 8088 microprocessors to provide a maximum level of system integration.
The low standby power dissipation minimizes system power requirements when the 8185 is disabled.
The 8185-2 is a high-speed selected version of the 8185 that is compatible with the 5 MHz 8085A-2 and the full speed
5 MHz 8088.
ADO Vee
AD, RD
AD2
AD3
AD4
WR
ALE
-
CS
CE,
.
CS CE 2 R/W
AD5 CE, @ LOGIC
AD6 CE 2 WR
ALE
AD7 As
Vss As
l
-\ DATA lK x 8
RAM
r---v
BUS
BUFFER MEM0RY
ARRAY
xy DECODE
PIN NAMES
ADOAD 7 ADDRESSIDATA LINES

~ ~~
~
ADDRESS LINES ADDRESS
As. As
LATCH
CS CHIP SELECT
CHIP ENABLE (101M) As. As
CE,
CE 2 ALE
CHIP ENABLE
~E ADDRESS LATCH ENABLE
RD READ ENABLE
WR WRITE ENABLE
7-47 AFN-Q0201 A-D1

8185/8185-2
OPERATIONAL DESCRIPTION
Vss Vee
The 8185 has been designed to provide for direct interface
!!!
to the multiplexed bus structure and bus timing of the
8085A microprocessor. -- TRAP
x, x2 RESET IN
HOLD I-
At the beginning of an 8185 memory access cycle, the 8-
bit address on ADo-7, As and Ag, and the status of CE1 and -- RST7,5
RST6,5
8085A
HLDA
SOD
f--
f-
--
RST5,5 SIDI-
CE2 are all latched internally in the 8185 by the falling edge INTR s,i--
RESET
of ALE. If the latched status of both CE1 and CE2 are INTA
ADDRI OUT So i--
ADDR DATA ALE AD WR 101M RDY ClK
active, the 8185 powers itself up, but no action occurs until
Vee
the CS line goes low and the appropriate RD or WR control
signal input is activated.
(8) (8)'"
Tl
The CS input is not latched by the 8185 in order to allow r-- ~ POR~W
the maximum amount of time for address decoding in
selecting the 8185 chip. Maximum power consumption
WR
_
RD
PORT
8156 B
W (8)
savings will occur, however, only when CE1 and CE2 are
activated selectively to power down the 8185 when it is not
in use. A possible connection would be to wire the 808SA's
10iM line to the 8185's CE1 input, thereby keeping the
...
"
If
ALE
DATAl
ADDR
PORT
IN
C
W (6)
101M TIMER I--

8185 powered down during 1/0 and interrupt cycles. RESET
OUT r--
lOW
TABLE 1.
AD
TRUTH TABLE FOR
POWER DOWN AND FUNCTION ENABLE
W
ALE
PORT
Itr- eE A
CE 1 CE 2 CS (CS*)[2] 8185 StatuI L--

j..
As.,o
r-- 8355/
1 X X 0 Power Down and V
8755A
Function Disable[1] "- DATAl
ADDR
X 0 X 0 Power Down and ... If
0 1 1 0
Function Disable[ll
Powered Up and
101M
RESET
ROY
PORT
B
W
Function Disable[11
~ elK
0 1 0 1 Powered Up and
Enabled tttt
Vss Vee VDD PROG
Notes:
X: Don't Care. WR
1: Function Disable implies Data Bus in high impedance state AD
and not writing.
GE, 8185
2: CS = (CEl = 0) (CE2 = 1) (CS = 0) ALE
CS = 1 signifies all chip enables and chip select active
h-- CS, eE 2
!-t-- As, Ag
.II "-
TABLE 2. / AD o.7
TRUTH TABLE FOR

CONTROL AND DATA BUS PIN STATUS
Vss
t t Vee
Vee
ADo_7 During Data
Vee
(CS*) RD WR Portion of Cycle 8185 Function ~
7 "
0 X X Hi-Impedance No Function
1 0 1 Data from Memory Read Figure 1. 8185 in an MCS-85 System.
1 1 0 Data to Memory Write
4 Chips:
1 1 1 Hi-Impedance Reading, but not 2K Bytes ROM
Driving Data Bus 1.25K Bytes RAM
38 I/O Lines
1 Counter/Timer
Note: 2 Serial I/O Lines
X: Don't Care. 5 Interrupt Inputs
7-48 AFN-00201 A-Q2

8185/8185-2
ABSOLUTE MAXIMUM RATINGS*

'COMMENT
Temperature Under Bias .............. OC to +70C Stresses above those listed under "Absolute Maximum Ratings" may cause
Storage Temperature .............. -65C to +150C permanent damage to the device. This is a stress rating only and functional
Voltage on Any Pin operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied
with Respect to Ground .............. -0.5V to +7V Exposure to absolute maximum rating conditions for extended periods
Power Dissipation ............................. 1.5W may affect device reliability.
D.C. CHARACTERISTICS (TA = OC to 70C; VCC = 5V 5%)
Symbol Parameter Min. Max. Units Test Conditions

Vil Input Low Voltage -0.5 0.8 V
VIH Input High Voltage 2.0 Vcc+0.5 V
VOL Output Low Voltage 0.45 V IOl = 2mA
VOH Output High Voltage 2.4 IOH = - 400~A
III Input Leakage 10 ~A VIN = Vcc to OV

IlO Output Leakage Current 10 ~A 0.45V 5: VOUT 5: Vcc
Icc Vcc Supply Current
Powered Up 100 mA
Powered Down 35 mA
A.C. CHARACTERISTICS (TA = OC to 70C; Vcc = 5V 5%)
8185 8185-2
Preliminary Preliminary
Symbol Parameter [1] Min. Max. Min. Max. Units
tAL Address to Latch Set Up Time 50 30 ns
tlA Address Hold Time After Latch 80 30 ns
tLC Latch to READ/WRITE Control 100 40 ns
tLO ALE to Data Out Valid 300 200 ns
tLl Latch Enable Width 100 70 ns
tROF Data Bus Float After READ a 100 a 80 ns
tCl READ/WRITE Control to Latch Enable 20 10 ns
tcc READ/WRITE Control Width 250 200 ns
tow Data In to WRITE Set Up Time 150 150 ns
two Data In Hold Time After WRITE 20 20 ns
tsc Chip Select Set Up to Control Line 10 10 ns
tcs Chip Select Hold Time After Control 10 10 ns
tAlCE Chip Enable Set Up to ALE Falling 30 10 ns
tLACE Chip Enable Hold Time After ALE 50 30 ns
Notes:
1. All AC parameters are referenced at
a) 2.4V and .45V for inputs
b) 2.0V and .BV for outputs.
___..JX~::> TESTP'"NTS::::X"'-____
7-49 AFN-00201 A-03

8185/8185-2
ALE
(CE, =0)-
(C E 2' 1)
WR,RD
ADo-AD7
(READ CYCLE)
(AB, Ag)
--tcc----~I
(WRITE CYCLE)
(SELECTED) (DESELECTED)
Figure 3.8185 Timing.
7-50 AFN-00201 A-04

inter
8355/8355-2
16,384-8IT ROM WITH 1/0
2048 Words x 8 Bits Each 1/0 Port Line Individually

Programmable as Input or Output
Single + 5V Power Supply
Multiplexed Address and Data Bus
Directly compatible with 808SA
and 8088 Microprocessors Internal Address Latch
2 General Purpose 8-Bit 1/0 Ports 40Pin DIP
The Intel@ 8355 is a ROM and I/O chip to be used in the 8085A and 8088 microprocessor systems. The ROM por-
tion is organized as 2048 words by 8 bits. It has a maximum acess time of 400 ns to permit use with no wait states in
the 8085A CPU.
The I/O portion consists of 2 general purpose I/O ports. Each I/O port has 8 port lines and each I/O port line is
individually programmable as input or output.
The 8355-2 has a 300ns access time for compatibility with the 8085A-2 and full speed 5 MHz 8088 microprocessors.
GE, Vee
CE 2 PB 7 ClK
ClK PBs
RESET PBs
READY
N.C. (NOT CONNECTED) 5 PB 4
AD _
READY PB 3 o 7
~
101M PB 2
G
PB, PA o- 7
As-,o
AD PB o
row PA 7 CE2
GE, ROM
~
ALE PAs
101M
PAs
ALE PB O- 7
AD, PA 4
AD
AD2 PA 3
lOW
AD3 PA 2
RESET
AD4 PA,
iOR
ADs PAo
ADs
AD7
AlO
Ag ~Vec (+5V)
Vss (OV)
Vss
Intel Corporation Assumes No Responsibility tor the Use of Any CirCUitry Other Than Circuitry Embodied In an Intel PrOduct No Other CirCUit Patent licenses are Implied
7-51
8355/8355-2
Symbol Function Symbol Function

ALE When ALE (Address latc~, Enable is ClK The ClK is used to force the READY
(Input) high, ADo-7, 10/M, A8-10, CE, and CE (Input) into its high impedance state after it
enter address latched. The signals has been forced low by CE low, CE
(AD, 10/M, A8-10, CE, CE) are latched high and ALE high.
in at the trailing edge of ALE. READY Ready is a 3-state output controlled by
ADo-7 Bidirectional Address/Data bus. The (Output) CE1, CE2, ALE and ClK. READY is
(Input) lower 8-bits of the ROM or I/O address forced low when the Chip Enables are
are applied to the bus lines when ALE active during the time ALE is high, and
is high. remains low until the rising edge of the
During an I/O cycle, Port A or Bare next ClK (see Figure 6).
selected based on the latched value of PAO-7 These are general purpose I/O pins.
ADo. If RD or lOR is low when the latched (Input/ Their input/output direction is deter-
chip enables are active, the output Output) mined by the contents of Data Direction
buffers present data on the bus. Register (DDR). Port A is selected for
These are the high order bits of the ROM write operations when the Chip Enables
A8-10
(Input) address. They do not affect I/O oper- are active and iOW is low and a 0 was
ations. previously latched from ADo.
CE1 Chip Enable Inputs: CE1 is active low Read operation is selected by either
CE2 and CE2 is active.b.!.9!l. The 8355 can be lOR low and active Chip Enables and
(Input) accessed only when BOTH Chip En- ADo low, Q! 10/M high, RD low, active
ables are active at the time the ALE chip enables, and ADo low.
signal latches them up. If either Chip PBo-7 This general purpose I/O port is
Enable input is not active, the ADo-7 (Input/ identical to Port A except that it is
and READY outputs will be in a high Output) selected by a 1 latched from ADo.
impedance state.
RESET An input high on RESET causes all pins
10iM If the latched 10/M is high when RD is (Input) in Port A and B to assume input mode.
(Input) low, the output data comes from an
lOR When the Chip Enables are active, a low
I/O port. If it is low the output data (Input) on lOR will output the selected I/O port
comes from the ROM.
onto the AD bus. lOR low performs the
RD If the latched Chip Enables are active same function as the combination 10/M
(Input) when RD goes low, the ADo-7 output high and RD low. When lOR is not used
buffers are enabled and output either in a system, lOR should be tied to Vee
the selected ROM location or I/O port. ("1" ).
When both RD and lOR are high, the
Vee +5 volt supply.
ADo-7 output buffers are 3-state.
lOW If the latched Chip Enables are active,
Vss Ground Reference.
(Input) a Iowan lOW causes the output port
pointed to by the latched value of ADo
to be written with the data on ADo-7.
The state of 10/M is ignored.
7-52
8355/8355-2
ABSOLUTE MAXIMUM RATINGS 'COMMENT: Stresses above those listed under "Absolute
device. This is a stress rating onlv and functional opera
tion of the device at these or any other conditions above
Temperature Under Bias ................ aoc to +70C
Storage Temperature ............... -65 0 C to +150 C those indicated in the operational sections of this specifi-
With Respect to Ground ............... -0.5V to +7V rating conditions for ex tended periods may affect device
Power Dissipation ............................. 1.5W reliability.
D.C. CHARACTERISTICS (TA = oc to 70C; Vee = 5V 5%)
VIL Input Low Voltage -0.5 0.8 V Vee = 5.0V

VIH Input High Voltage 2.0 Vee +0.5 V Vee = 5.0V
VO H Output High Voltage 2.4 V IOH = -400J.LA
IlL Input leakage 10 J.LA VIN = Vee to OV

ILO Output leakage Current 10 J.LA 0.45V ~VOUT ~Vee
lee Vee Supply Current 180 mA
A.C. CHARACTERISTICS (TA = oc to 70C; Vee = 5V 5%)

8355 8355-2
Symbol Parameter Min. Max. Min. Max. Units
tCYC Clock Cycle Time 320 200 ns
T1 ClK Pulse Width 80 40 ns
tf. tr ClK Rise and Fall Time 30 30 ns
tAL Address to latch Set Up Time 50 30 ns
tLA Address Hold Time after latch 80 30 ns
tLC latch to READ/WRITE Control 100 40 ns
tAD Address Stable to Data Out Valid 400 330 ns
tll latch Enable Width 100 70 ns
tROF Data Bus Float after READ 0 100 0 85 ns
tCl READ/WRITE Control to latch Enable 20 10 ns
tce READ/WRITE Control Width 250 200 ns
tow Data In to Write Set Up Time 150 150 ns
twp WRITE to Port Output 400 400 ns
tpR Port Input Set Up Time 50 50 ns
tRP Port Input Hold Time 50 50 ns
tRYH READY HOLD Time 0 160 0 160 ns
tARY ADDRESS (CE) to READY 160 160 ns
tRY Recovery Time Between Controls 300 200 ns
tRoE READ Control to Data Bus Enable 10 10 ns
Note: CLOAD = 150pF

8355/8355-2
Figure 3. Clock Specification for 8355
A8-10
101M
1 4 - - - - - - - - tAo - - - - - - - - - . . I
ADo_7 DATA
ALE
1 + - - - - - tow - - - - - - - + I
Figure 4. ROM Read and 1/0 Read and Write
7-54
8355/8355-2
8. Input Mode
d::,~
PORT
INPUT
==x
DATA*- - -- - - -)(
BUS
------- ----------------------
b. Output Mode
GLITCH FREE
/OUTPUT
PORT
OUTPUT
~
J\ _______..JX\._____
DATA* - - - - -
BUS ____ _
*DATA BUS TIMING IS SHOWN IN FIGURE 4.
Figure 5. 1/0 Port Timing
Figure 6. Wait State Timing (Ready = 0)
7-55
intel~
8755A /8755A2
16,3848IT EPROM WITH I/O
2048 Words )( 8 Bits 2 General Purpose 8Bit 1/0 Ports
Single + 5V Power Supply (V cd Each 1/0 Port Line Individually

Programmable as Input or Output
Directly Compatible with 808SA
and 8088 Microprocessors Multiplexed Address and Data Bus
U.V. Erasable and Electrically 40Pin DIP

Reprogrammable
Internal Address Latch
The Intel@ 8755A is an erasable and electrically reprogrammable ROM (EPROM) and I/O chip to be used in the 8085A
and 8088 microprocessor systems. The EPROM portion is organized as 2048 words by 8 bits. It has a maximum
access time of 450 ns to permit use with no wait states in an 8085A CPU.
The I/O portion consists of 2 general purpose I/O ports. Each I/O port has 8 port lines, and each I/O port line is
individually programmable as input or output.
The 8755A-2 is a high speed selected version of the 8755A compatible with the 5 MHz 8085A-2 and the full speed 5
MHz 8088.
PROG AND CE,

CLK-----, CE 2
CLK
RESET
READY-----t
VDD PB 4
READY PB 3
101M PB 2
lOR PB,
RD PB o
CE2 - - - - I 2K x 8 lOW
IO/M----~ EPROM
ALE
ALE---_I ADo PA 5
Fill----I AD, PA 4
IOW----I AD2 PA 3
RESET-----t AD3 PA 2
iOR---_I AD4 PA,

ADs PA o
~VCC(+5VI AD6
AD7
A,O
A9
Vss (OVI
Vss
Figure 1. Block Diagram Figure 2. Pin Configuration
Intel Corporation Assumes No Responsibilty for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenses 8Je Implied.
"INTEL CORPORATION. 1980 7-56 AFN-01841B
8755A/8755A-2

Symbol Type Name and Function Symbol Typl; Name and Function
ALE I Address Latch Enable: When Address READY 0 Ready is a 3-state output controlled by
latch Enable goes high, ADO-7. 10/M, CE2, CE1 , ALE and elK. READY is forced
Aa-10. CE2. and CE 1 enter the address low when the Chip Enables are act ave
latches. The signals (AD, 10/M, AS-10. during the time ALE is high, and remains
CE) are latched in at the trailing edge of low until the rising edge of the next ClK.
ALE. (See Figure 6.)
ADO-7 I Bidirectional Address/Data Bus: The
PAO-7 110 Port A: These are general purpose 1/0
lower 8-bits of the PROM or I/O address
pins. Their input/output direction is de-
are applied to the bus lines when ALE is
termined by the contents of Data Direc-
high.
tion Register (DDR). Port A is selected for
During an I/O cycle, Port A or Bare write operations when the Chip Enables
selected based on the latched value of are active and lOW is low and a 0 was
ADo. IF RD or lOR is low when the latched previously latched from ADo, AD 1.
Chip Enables are active, the output buf-
Read Operation is selected by either lOR
fers present data on the bus.
low and active Chip Enables and ADo
Aa-10 I Address: These are the high order bits and AD1 low,or 101M high, RD low, active
of the PROM address. They do not affect Chip Enables, and ADo and AD1 low.
I/O operations.
PBO-7 I/O Port B: This general purpose I/O port is
PROG/CE1 I Chip Enable Inputs: CE 1 is active low identical to Port A except that it is
CE2 and CE2 is active high. The 8755A can be selected by a 1 latched from ADo and a 0
accessed only when both Chip Enables from AD 1.
are active at the time the ALE signal
RESET I Reset: In normal operation, an input
latches them up. If either C; ;:p Enable
high on RESET causes all pins in Ports A
input is not active, the ADo 1 and
and B to assume input mode (clear DDR
READY outp~ will be in a 'T1pe- register).
dance state.CE 1 is also used as a pro-
gramming pin. (See section on lOR I I/O Read: When the Chip Enables are
programming.) active, a Iowan lOR will output the
selected I/O port onto the AD bus. lOR
10/M I I/O Memory: If the latched 10/M is high
low performs the s~me functio~s the
when RD is low, the output data comes
combination of IO/M high and RD low.
from an I/O port. If it is low the output
When lOR is not used in a system, lOR
data comes from the PROM.
should be tied to Vee ("1").
RD I Read: If the latched Chip Enables are
Vee Power: +5 volt supply.
active when RD goes low, the ADO-7
output buffers are enabled and output Vss Ground: Reference.
either the selected PROM location or I/O Power Supply: Voo is a programming
Voo
port. When both RD and lOR are high, voltage, and must be tied to Vee when
the ADo-7 output buffers are 3-stated. the 8755A is being read.
lOW I I/O Write: If the latched Chip Enables are For programming, a high voltage is
active, a Iowan lOW causes the output supplied with Voo = 25V, typical. (See
port pointed to by the latched value of section on programming.)
ADo to bewritte~with the data on AD o-7.
The state of 10/M is ignored.
ClK I Clock: The ClK is used to force the
READY into its high impedance state
after it has been forced low by CE1 low,
CE2 high, and ALE high.
7-57 AFN-01B41B
intel 8755A/8755A-2
87,5A
FUNCTIONAL DESCRIPTION ONE BIT OF PORT A AND ODR A
PROM Section
The 8755A contains an 8-bit address latch which allows it
to interface directly to MCS-48, MCS-85 and iAPX 88/10
Microcomputers without additional hardware.
The PROM section of the chip is addressed by the 11-bit
address and CEo The address, CE 1 and CE2 are latched
into the address latches on the falling edge of ALE. If the
latched Chip Enables are active and 10iM is low when RD
goes low, the contents of the PROM location addressed
by the latched address are put out on the ADO-7 lines WRITE DDR A
(provided that Voo is tied to Vee.)

DO ~
1/0 Section
~
The I/O section of the chip is addressed by the latched READ PA
WRITE PA' liOW'O)oICHIP ENABLES ACTIVElolPORT A ADDRESS SELECTEOI
value of ADo-1. Two 8-bit Data Direction Registers DDR WRITE ODR A' liOW'OloiCHIP ENABLES ACTIVElolDDR A ADDRESS SELECTEDI
in 8755A determine the input/output status of each pin READ PA i [110 IMo,) 0 lAD 'Olj liOR '01; 0 ICH IP ENA BL ES ACTIVE I 0 (PORT A AD DR ESS SE LE CTE 0,
NOTE: WRITE PA IS NOT QUAlIFIEO BY 101M
in the corresponding ports. A "0" in a particular bit posi-
tion of a DDR signifies that the corresponding I/O port bit
is in the input mode. A "1" in a particular bit position signi- Note that hardware RESET or writing a zero to the DDR
fies that the corresponding I/O port bit is in the output latch will cause the output latch's output buffer to be
mode. In this manner the I/O ports of the 8755A are bit-by- disabled, preventing the data In the Output Latch from
bit programmable as inputs or outputs. The table being passed through to the pin. This is equivalent to
summarizes port and DDR designation. DDR's cannot be putting the port in the input mode. Note also that the data
read. can be written to the Output Latch even though the Output
Buffer has been disabled. This enables a port to be ini-
AD1 ADo Selection tialized with a value prior to enabling the output.
0 0 Port A The diagram also shows that the contents of PORT A and
0 1 Port B PORT B can be read even when the ports are configured
1 0 Port A Data Direction Register mDR Al as outputs.
1 1 Port B Data Direction Register (DDR B)
TABLE 1. 8755A PROGRAMMING MODULE CROSS
When lOW goes low and the Chip Enables are active, the REFERENCE
data on the AD is written into I/O port selected by the USE WITH
MODULE NAME
latched value of ADo-1. During this operation all I/O bits
of the selected port are affected, regardless of their I/O UPP 955 UPP(4)
mode and the state of 10/M'. The actual output level does UPP UP22) UPP 855
not change until lOW returns high. ,glitch free output, PROMPT 975 PROMPT 80/85(31
A port can be read out when the latched Chip Enables are PROMPT 475 PROMPT 48l 1/
active and either RD goes low with 10/M high, or lOR goes NOTES:
low. Both input and output mode bits of a selected port 1. Described on p.13-340f 1978 Data Catalog.
wiil appear on lines ADo-7. 2. Special adaptor socket.
To clarify the function of the I/O Ports and Data Directior 3. Described on p. 13-39 of 1978 Data Catalog.
Registers, the following diagram shows the configuration 4. Described on p. 13-71 of 1978 Data Catalog.
of one bit of PORT A and DDR A. The same logic applies
to PORT Band DDR B.
7-58 AFN-01B41B
8755A/8755A-2
ERASURE CHARACTERISTICS SYSTEM APPLICATIONS

The erasure characteristics of the 8755A are such that System Interface with 808SA and 8088
erasure begins to occur when exposed to light with A system using the 8755A can use either one of the two I/O
wavelengths shorter than approximately 4000 Angstroms Interface techniques:
IAI. It should be noted that sunlight and certain types of
fluorescent lamps have wavelengths in the 3000-4000A Standard I/O
range. Data show that constant exposure to room level
fluorescent lighting could erase the typical 8755A in Memory Mapped I/O
approximately 3 years while it would take approximately 1
week to cause erasure when exposed to direct sunlight. If a standard I/O technique is used, the system can use
If the 8755A is to be exposed to these types of lighting the feature of both CE3 and CE 1. By using a combination
conditions for extended periods of time, opaque labels of unused address lines A II - 15 and the Chip Enable
are available from Intel which should be placed over the inputs, the 8085A system can use up to 5 each 8755A's
8755 window to prevent unintentional erasure. without requiring a CE decoder. See Figure 2a and 2b.
The recommended erasure procedure for the 8755A is If a memory mapped I/O approach is used the 8755A will be
exposure to shortwave ultraviolet light which has a wave- sel~ted by the combination of both the Chip Enables and
length of 2537 Angstroms (AI. The integrated dose Ii.e., 10/M using the ADs-15 address lines. See Figure 1.
UV intensity X exposure time I for erasure should be a
minimum of 15W-sec/cm2. The erasure time with this
dosage is approximately 15 to 20 minutes using an ultra-
violet lamp with a 12000pW/cm2 power rating. The
8755A should be placed within one inch from the lamp
tubes during erasure. Some lamps have a filter on their
tubes and this filter should be removed before erasure.
/1
PROGRAMMING
Initially, and after each erasure, all bits of the EPROM
K;8.15 )
portions of the 8755A are in the "1" state. Information is 8085A
~D07
'J
"-
V
introduced by selectively programming "0" into the
ALE
desired bit locations. A programmed "0" can only be
RD
-
changed to a "1" by UV erasure.
WR
-
The 8755A can be programmed on the Intel Universal elK 10.,21
-
PROM Programmer (UPp i, and the PROMPr M 80/85 and READY
-
PROMPT-48 design aids. The appropriate programming -
modules and adapters for use in programming both
101M
f--- t
vee
8755A's and 8755's are shown in Table 1.
The program mode itself consists of programming a
r"'7 "(/
A/Do_7 A_
s 10 RD elK
I
101M
single address at a time, giving a single 50 msec pulse iDA ALE iOW READY CE
for every address. Generally, it is desirable to have a
8755A
verify cycle after a program cycle for the same address
as shown in the attached timing diagram. In the verify
cycle (i.e., normal memory read cycle I 'Voo' should
be at +5V.
Preliminary timing diagrams and parameter values per-
taining to the 8755A programming operation are con- Figure 3. 8755A in 80S5A System
tained in Figure 7. (Memory-Mapped I/O)
7-59
8755A/8755A2
ABSOLUTE MAXIMUM RATINGS 'NOTICE: Stresses above those listed under "Absolute
TemperatureUnderBias ................ OCto+70C tion of the device at these or any other conditions above
Storage Temperature ............... -65C to "150C those indicated in the operational sections of this specifi-
With Respect to Ground ............... -O.5V to +7V rating conditions for extended periods may affect device
Power Dissipation ............................. 1.5W reliability.
D.C. CHARACTERISTICS (TA = OC to 70, Vee = Voo = 5V 5%;

Vee = VOO = 5V 10% for 8755A-2)
VIL Input Low Voltage -0.5 0.8 V Vee = 5.0V

VIH Input High Voltage 2.0 Vee+0 . 5 V Vee = 5.0V
VOH Output High Voltage 2.4 V IOH = -400j1A
IlL Input Leakage 10 j1A VSS ~ VIN ~ Vee
ILO Output Leakage Current 10 j1A VSS"'; 0.45V ,.,; VOUT ,.,; Vee
100 Voo Supply Current 30 mA Voo = Vee

CIN Capacitance of Input Buffer 10 pF fe = 1JLHz
CI/o Capacitance of I/O Buffer 15 pF fe = 1JLHz
D.C. CHARACTERISTICS- PROGRAMMING (TA = 0Ct070, Vee = 5V 5%, Vss = OV, Voo = 25V 1V;
Vee = Voo = 5V 10% for 8755A-2)
Symbol Parameter Min. Typ. Max. Unit

Voo Programming Voltage (during Write
to EPROM) 24 25 26 V
IDO Prog Supply Current 15 30 mA
760 AFN-01841B
intel" 8755A18755A2
A.C. CHARACTERISTICS (TA = OC to 70, Vee = 5V 5%;

Vee = Voo = 5V 10% for 8755A-2)
8755A2
8755A (Preliminary)
Symbol Parameter Min. Max. Min. Max. Units
tCYC Clock Cycle Time 320 200 ns
tt,t r ClK Rise and Fall Time 30 30 ns
tAL Address to latch Set Up Time 50 30 ns
tlA Address Hold Time after latch 80 45 ns
tlC latch to READ/WRITE Control 100 40 ns
tRO Valid Data Out Delay from READ Control 170' 140' ns
tAD Address Stable to Data Out Valid 450 330 ns
tll latch Enable Width 100 70 ns
tROF Data Bus Float after READ 0 100 0 85 ns
tCl READ/WRITE Control to latch Enable 20 I 10 ns
tcc READ/WRITE Control Width 250 200 ns
tDW Data In to Write Set Up Time 150 150 ns
twp WRITE to Port Output 400 300 ns
tPR Port Input Set Up Time 50 50 ns
tRP Port Input Hold Time to Control 50 50 ns
tRYH READY HOLD Time to Control 0 160 0 160 ns
tARY ADDRESS (CEl to READY 160 160 ns
tRv Recovery Time Between Controls 300 200 ns
tRDE READ Control to Data Bus Enable 10 10 ns
--
tLO ALE to Data Out Valid 350 270 ns
NOTE:
eLOAD = 150pF.
'Or TAD - (TAL + he), whichever is greater.
A.C. CHARACTERISTICS-PROGRAMMING (TA =0Cto70, Vee = 5V 5%, Vss= OV,Voo = 25V1V;

Vee = Voo = 5V 10% for 8755A-2)
Symbol Parameter Min. Typ. Max. Unit

tps Data Setup Time 10 ns
tPD Data Hold Time 0 ns
ts Prog Pulse Setup Time 2 }J.s
tH Prog Pulse Hold Time 2 }J.s
tPR Prog Pulse Rise Time 0.01 2 }J.s
tPF Prog Pulse Fall Time 0.01 2 }J.s
tPRG Prog Pulse Width 45 50 msec
7-61 AFN-01841B
in1:el" 8755A/8755A2
A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT
!NPUT/OUTPUT
,. ~"'O<H"<
0.45
0.8
"X=
0.8
DEVICE
UNDER
"--____. . I
TEST
~
CL 150 pF
A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC 1 AND 0 45V FOR

A LOGIC O TIMING MEASUREMENTS ARE MADE AT 2 OV FOR A LOGIC 1
AND 08V FOR A LOGIC 0 CL 150pF
C, INCLUDES JIG CAPACITANCE
WAVEFORMS
CLOCK SPECIFICATION FOR 8755A
PROM READ, I/O READ AND WRITE
As,o
~ ADDRESS
I
ADDRESS
tAD
ADO7
~ ADDRESS )---~
--.J DATA
~>-----< ADDRESS
l-
ALE
e I-tLL--
,I
'k-
f.-tAL- I------ t LA - - -
-
(PROGI/CE, \k-
CE 2 )~ ~\
\
--
-'1\
I---tROE
-)~
tROF 1---
....
iORFili
!----tLc _ _
k-
~tR[) tow I----- t-two

L
-'~k- ,~
lOW
tcc
L
I----tCL-
Please note that GEl must remain low for the entire cycle. . tRV
762 AFN-Ol841B
8755A/8755A2
WAVEFORMS (Continued)
1/0 PORT
A. INPUT MODE
ROOR
iiYR
B. OUTPUT MODE
lOW
GLITCH FREE
~ ~/ OUTPUT
6~~;UT =========~ ~ ~ Xl;..;;.-______

~~~A -_____
- - - - -V
-A_______ X
--J. It..._ _ _ __
WAIT STATE (READY = 0)
CLK
ICE=1) ICE=O)
ALE
READY- - - -l"'"
I
4-
I
tAAY'"
, ...... _-----.
763 AFN-01B41B
8755A18755A2
WAVEFORMS (Continued)
8755A PROGRAM MODE
FUNCTION
I. . .~------ PROGRAM CYCLE -------~ .. 11.....- - - - - VERIFY CYCLE' --1_ PROGRAM CYCLE
ALEJ
\_--_1\_-
DATA TO BE
A/DO-7 PROGRAMMED
tPD--
AS-l0
tH _ _
+25
VDD
-
+5--------------------------~
'VERIFY CYCLE IS A REGULAR MEMORY READ CYCLE (WITH VDD = +5V FOR 8755A)
7-64 AFN-01841B
8041 AJ8641AJ8741 A
UNIVERSAL PERIPHERAL INTERFACE
8BIT MICROCOMPUTER
8Bit CPU plus ROM, RAM, I/O, Timer
and Clock in a Single Package
Fully Compatible with MCS48,
MCS80, MCS85, and MCS86
Microprocessor Families
ters
One 8Bit Status and Two Data Regis
for Asynchronous SlavetoMaster Versions
Interchangeable ROM and EPROM
Interface
Supported
DMA, Interrupt, or Polled Operation 3.6 MHz 8741A8 Available
Expandable I/O
8Bit
1024 x 8 ROM/EPROM, 64 x 8 RAM, RAM PowerDown Capability
Timer/Counter, 18 Programmable Over 90 Instructions: 700/0 Single Byte
I/O Pins Single 5V Supply
The Intel@ 8041A/8741A is a general purpose, programmable interface device designed for use with a variety of 8-bit
microprocessor systems. It contains a low cost microcomputer with program memory, data memory, 8-bit CPU, 1/0
ports, timerlcounter, and clock in a single 40-pin package. Interface registers are included to enable the UPI device to
function as a peripheral controller in MCS-48, MCS-80, MCS-85, MCS-86, and other 8-bit systems.
The UPI-41A has 1K words of program memory and 64 words of data memory on-chip. To allow full user flexibility the
program memory is available as ROM in the 8041A version or as UV-erasable EPROM in the 8741A version. The 8741A
and the 8041A are fully pin compatible for easy transition from prototype to production level designs. The 8641A is a
one-time programmable (at the factory) 8741A which can be ordered as the first 25 pieces of a new 8041A order. The
substitution of 8641A's for 8041A's allows for very fast turnaround for initial code verification and evaluation results.
The device has two 8-bit, TTL compatible 1/0 ports and two test inputs. Individual port lines can function as either in-
puts or outputs under software control. 1/0 can be expanded with the 8243 device which is directly compatible and has
16 1/0 lines. An 8-bit programmable timerlcounter is included in the UPI device for generating timing sequences or
counting external inputs. Additional UPI features include: single 5V supply, low power standby mode (in the 8041 A),
single-step mode for debug (in the 8741A), and dual working register banks.
Because it's a complete microcomputer, the UPI provides more flexibility for the designer than conventional LSI inter-
face devices. It is designed to be an efficient controller as well as an arithmetic processor. Applications include key-
board scanning, printer control, display multiplexing and similar functions which involve interfacing peripheral
devices to microprocessor systems.
TEST 0
XTALl
XTAL2
P281DRQ
P2s1iiiF
P2410BF
...
,
r
~. .,. .- - - M-~-:-b~-R-:~l;:' , ~;::
RANDOM
ACCESS
MEMORY
L..............,..,~~~
PERIPHERAL
INTERFACE
I-BIT
I'y------,/IEVEN~I~~~NTER
00188A
8041 AJ8641AJ8741 A
PIN DESCRIPTION UPI INSTRUCTION SET

Mn.monlc Dcrlptlon Byt Cycl
ACCUMULATOR
Signal Description Add register to A 1 1
ADD A.Rr
ADD A.@Rr Add data memory to A 1 1
Do- D7 Three-state, bidirectional DATA BUS BUFFER lines ADD A.#data Add immediate to A 2 2
(BUS) used to interface the UPI-41A to an 8-bit master ADDC A.Ar Add register to A with carry 1 1
system data bus. Add data memory to A with carry 1 1
ADDC A.@Ar
8-bit, PORT 1 quasi-bidirectional I/O lines. ADDC A.#data Add immed. to A with carry 2 2
ANL A.Ar AND register to A 1 1
8-bit, PORT 2 quasi-bidirectional 110 lines. The lower ANL A.@Rr AND data memory to A 1 1
4 bits (P 20 -P 23) interface directly to the 8243 I/O ex- ANL A.#data AND immediate to A 2 2
pander device and contain address and data infor- ORL A.Rr OA register to A 1 1
mation during PORT 4-7 access. The upper 4 bits ORL A.@Rr OA data memory to A 1 1
(P 24 -P27) can be programmed to provide Interrupt OAL A.#data OA immediate to A 2 2
Request and DMA Handshake capability. Software XRL A.Rr Exclusive OR register to A 1 1
control can configure P24 as OBF (Output Buffer XRL A.@Ar Exclusive OR data memory to A 1 1
Full), P25 as IBF (Input Buffer Full), P26 as DRO XRL A.#data Exclusive OR immediate to A 2 2
(DMA Request), and P 27 as DACK (DMA INC A Increment A 1 1
ACKnowledge). DEC A Decrement A 1 1
I/O write input which enables the master CPU to CLR A Clear A 1 1
write data and command words to the UPI-41A IN- CPL A Complement A 1 1
PUT DATA BUS BUFFER. DA A Decimal Adjust A 1 1
SWAP A Swap nibbles of A 1 1
I/O read input which enables the master CPU to RL A Rotate A left 1 1
read data and status words from the OUTPUT DATA RLC A Rotate A left through carry 1 1
BUS BUFFER or status register. RR A Rotate A right 1 1
Chip select input used to select one UPI-41A out of RRC A Rotate A right through carry 1 1
several connected to a common data bus.
INPUT /OUTPUT
Ao Address input used by the master processor to in-
dicate whether byte transfer is data or command. IN A.Pp Input port to A 2
OUTL Pp.A Output A to port 2
TEST 0, Input pins which can be directly tested using condi- ANL Pp.#data AND immediate to port 2
TEST 1 tional branch instructions. ORL Pp.#data OR immediate to port 2
T1 also functions as the event timer input (under IN A.DBB Input DBB to A. clear IBF 1
software control). To is used during PROM program- OUT DBB.A Output A to DBB. set OBF 1
ming and verification in the 8741A. MOV STS,A A4-A7 to Bits 4-7 of Status 1
MOVD A.Pp Input Expander port to A 2
XTAL 1, Inputs for a crystal, LC or an external timing signal MOVD Pp.A Output A to Expander port 2
XTAL2 to determine the internal oscillator frequency. ANLD Pp.A AND A to Expander port 2
SYNC Output Signal which occurs once per UPI-41A in- ORlD Pp.A OR A to Expander port 2
struction cycle. SYNC can be used as a strobe for
external circuitry; it is also used to synchronize OATA MOVES
single step operation.
MOV A.Rr Move register to A 1 1
EA External access input which allows emulation, MOV A.@Rr Move data memory to A 1 1
testing and PROM/ROM verification. MOV A.#data Move immediate to A 2 2
MOV Rr.A Move A to register 1 1
PROG Multifunction pin used as the program pulse input
MOV @Rr.A Move A to data memory 1 1
during PROM programming.
MOV Rr.#data Move immediate to register 2 2
During I/O expander access the PROG pin acts as MOV @Rr.#data Move immediate to data memory 2 2
an address/data strobe to the 8243. MOV A.PSW Move PSW to A 1 1
MOV PSW.A Move A to PSW 1 1
RESET Input used to reset status flip-flops and to set the
XCH A.Ar Exchange A and register 1 1
program counter to zero.
XCH A.@Rr Exchange A and data memory 1 1
RESET is also used during PROM programming and XCHD A.@Rr Exchange digit of A and register 1 1
verification. MOVP A.@A Move to A from current page 1 2
MOVP3. A.@A Move to A from page 3 1 2
SS Single step input used in the 8741A in conjunction
with the SYNC output to step the program through
each instruction. TIMER/COUNTER
MOV AJ Read Timer /Counter
Vee + 5V main power supply pin. MOV T,A Load Timer/Counter
Voo + 5V during normal operation. + 25V during pro- STAT T Start Timer
gramming operation. Low power standby pin in STRT CNT Start Counter
ROM version. STOP TCNT Stop Timer/Counter
EN TCNTI Enable Timer ICounter Interrupt
Vss Circuit ground potential. DIS TCNTI Disable Timer/Counter Interrupt
7-66 00 188A
8041 AJ8641 AJ8741 A
Mnemonic De.crlptlon Byte. Cycle. Mnemonic De.crlptlon Byte. Cycl
CONTROL CPL FO Complement Flag 0

EN DMA Enable DMA Handshake Lines CLR F1 Clear F1 Flag
EN I Enable IBF Interrupt CPL F1 Complement F1 Flag
DIS I Disable IBF Interrupt
EN FLAGS Enable Master Interrupts
SEL RBO Select register bank 0 BRANCH
SEL RB1 Select register bank 1
JMP addr Jump unconditional 2
NOP No Operation 1
JMPP @A Jump indirect
DJNZ Rr, addr Decrement register and jump 2
REGISTERS
JC addr Jump on Carry = 1 2
INC Rr Increment register JNC addr Jump on Carry = 0 2 2
INC@Rr Increment data memory JZ addr Jump on A Zero 2 2
DEC Rr Decrement register JNZ addr Jump on A not Zero 2 2
JTO addr Jump on TO= 1 2
SUBROUTINE JNTO addr Jump on TO=O 2
CALL addr Jump to subroutine JT1 addr Jump on T1 = 1 2
RET Return JNT1 addr Jump on T1 =0 2
RETR Return and restore status JFO addr Jump on FO Flag = 1 2
JF1 addr Jump on F1 Flag = 1 2
FLAGS JTF addr Jump on Timer Flag = 1, Clear Flag 2
CLR C Clear Carry JNIBF addr Jump on IBF Flag = 0 2
CPLC Complement Carry JOBF addr Jump on OBF Flag = 1 2
CLR FO Clear Flag 0 JBb addr Jump on Accumulator Bit 2
APPLICATIONS
DATA
W
AD AD
W
808SA
ADDR
TO
PERIPHERAL
DEVICES
8048
WR WR 8041A1
CS 8741A
W TO
PERIPHERAL
DEVICES
--TO PORT CONTROL 2 -TO
AO
CONTROL A
--T1 BUS DATA BUS 8 DBS -T1
~
Figure 1. SOSSA-S041A Interface Figure 2. S04S-S041A Interface
8243 KEYBOARD
EXPANDER MATRIX z
z 0
0 ~ i=
i= a: iii
iii 0 0
0
u.. 11.
11. u.. 0
I-
0 UJ
11. UJ
Z u..
~ 0
I- IU
11. Z
::.
PORT2
8041A/8741A
8041 Al8741 A
DATA SUS
CONTROL BUS
Figure 3. S041A-S243 Keyboad Scanner Figure 4. S041A Matrix Printer Interface
7_~7 00 188A
8041 AJ8641AJ8741 A
COMMENT: Stresses above those listed under "Absolute Maximum

ABSOLUTE MAXIMUM RATINGS Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
Ambient Temperature Under Bias. __ .... _.OC to 70C conditions above those indicated in the operational sections of this
Storage Temperature _. _. _.... _. _. - 65 c C to + 150 c C specification is not implied. Exposure to absolute maximum rating con-
Voltage on Any Pin With Respect ditions for extended periods may affect device reliability.
to Ground .......................... 0.5V to + 7V
Power Dissipation __ .......... _.. _......... 1.5 Watt
D.C. AND OPERATING CHARACTERISTICS

TA= OC to 70C, Vss= OV, 8041A: Vcc= Voo= +5V 10%, 8741A: Vce= Voo= +5V 5%
V il Input Low Voltage (Except XTAL 1, XTAL2, RESET) -0.5 0.8 V
V IL1 Input Low Voltage (XTAL1, XTAL2, RESET) - 0.5 0.6 V
V IH Input High Voltage (Except XTAL 1, XTAL2, RESET) 2.2 Vee
V IH1 Input High Voltage (XTAL 1, XTAL2, RESET) 3.8 Vee V
VOL Output Low Voltage (0 0-0 7) 0.45 V IOl= 2.0 rnA
VOL1 Output Low Voltage (P1OP17, P20 P27 , Sync) 0.45 V IOl = 1.6 rnA
VOl2 Output Low Voltage (Prog) 0.45 V IOl = 1.0 rnA
VOH Output High Voltage (0 0-0 7) 2.4 V IOH= - 400 p.A
VOH1 Output High Voltage (All Other Outputs) 2.4 V 'OH= -50 p.A
III Input Leakage Current (To, T 1, RD, WR, CS, A o, EA) 10 p.A Vss ::5 VIN ::5 Vee
loz Output Leakage Current (0 0-0 7, High Z State) 10 p.A Vss+0.45::5 VIN ::5 Vee
III Low Input Load Current (P 1O P17 , P20 P27 ) 0.5 rnA V ll = 0.8V
ILl1 Low Input Load Current (RESET, SS) 0.2 rnA V ll = 0.8V
100 Voo Supply Current 15 rnA Typical = 5 rnA
Icc + 100 Total Supply Current 125 rnA Typical = 60 rnA
A.C. CHARACTERISTICS
T A = OC to 70C, Vss= OV, 8041A: Vee= Voo= + 5V 10%, 8741A: Vee= Voo= + 5V 5%
DBB READ
tAR CS, Ao Setup to RDI 0 ns
tRA CS, Ao Hold After RDI 0 ns
tRR RD Pulse Width 250 ns
tAD CS, Ao to Data Out Delay 225 ns C l = 150 pF
t Ro RDI to Data Out Delay 225 ns C l = 150 pF
tOF Fml to Data Float Delay 100 ns
tey Cycle Time (Except 8741A-8) 2.5 15 P.s 6.0 MHz XTAL
tey Cycle Time (8741A-8) 4.17 15 P.s 3.6 MHz XTAL
DBB WRITE
tAW CS, Ao Setup to WRI 0 ns
tWA CS, Ao Hold After WRf 0 ns
tww WR Pulse Width 250 ns
tow Data Setup to WRf 150 ns
two Data Hold After WRf 0 ns
7-nR 00188A
8041 AJ8641AJ8741 A
INPUT AND OUTPUT WAVEFORMS FOR A.C. TESTS
2.4 ----""')(2.2......... .-2.2V

_ _____ O.S ......... TEST POINTS ......... CL =150 pF
0.45
sA' - - - - - -
O
WAVEFORMS
1. READ OPERATION-DATA BUS BUFFER REGISTER.
(SYSTEM'S
~OR Ao ADDRESS BUSI
+-'AR----I
--+----1' 1--- ---'RR------~_ _ _~
1
(READ CONTROLI
__ 'AD~___-~D=I .-- l 'OF
~oA~T~~~~----------I--- om "uod---------
2. WRITE OPERATION-DATA BUS BUFFER REGISTER.
~ OR Ao
~
--fT--------------------'I r ~__________
(SYSTEM'S
ADDRESS BUSI
i-'AW-i 1-- ---'WW---~I.-~'WA~ ._ _

{~ ~
'{ (WRITE CONTROL I
~-'ow--- ------ 'wo
DATA BUS DATA

(I NPUTI _ _ _ _M_A_Y_CH_A_NG_E_ _
'J -----DATAVALlD---X~____M_A_YDATA
--JI'I _CH_A_NG_E_ _ __
TYPICAL 8041/8741A CURRENT

80 rnA
60 rnA
40 rnA
20 rnA
20 40 60 80
TEMP (C)
7-69 00l88A
8041 A/8641 Al8741 A
A.C. CHARACTERISTICS-PORT 2
T A= O'C to 70'C, 8041 A: Vcc= + 5V 10%, 8741A: Vcc = + 5V 5%.
Symbol P..arameter Mln. Max. Unit Test Conditions

tcp Port Control Setup Before Falling
Edge of PROG 110 ns
tpc Port Control Hold After Falling
Edge of PROG 100 ns
tpR PROG to Time P2 Input Must Be Valid 810 ns
tpF Input Data Hold Time 0 150 ns
tDP Output Data Setup Time 250 ns
tPD Output Data Hold Time 65 ns
tpp PROG Pulse Width 1200 ns
PORT 2 TIMING
SYNC
EXPANDER
PORT
OUTPUT PORT 20-3 DATA
EXPANDER
PORT
INPUT peRT 20-3 DATA
PROG
A.C. CHARACTERISTICS-DMA
t ACC DACK to WR orRD 0 ns
t CAC RD or WR to DACK 0 ns
t ACD DACK to Data Valid 225 ns C L = 150 pF
tCRQ RD or WR to DRO Cleared 200 ns
WAVEFORMS-DMA
DATA BUS ----t-+-____. ,-----,. ,..--------t-""""' r--"", r------
DRQ -----t---"I
7.7fl DD188A
8041 AJ8641AJ8741 A
CRYSTAL OSCILLATOR MODE DRIVING FROM EXTERNAL SOURCE
+5V
r----- XTAL1
I
I 470Q
< 15 pF I
(INCLUDES XTAL,
SOC:(ET, STRAY)
...,
....L
I
J>---+------i XTAL 1
I +5V
I
L ____ _
470Q
15 - 25 pF
(INCLUDES SOCKET,
STRAY)
I-=- ' - - - - + - - - i XTAL2
CRYSTAL SERIES RESISTANCE SHOULD BE <75Q AT 6 MHz; <180Q AT 3.6 MHz.
BOTH XTAL 1 AND XTAL2 SHOULD BE DRIVEN.

RESISTORS TO Vcc ARE NEEDED TO ENSURE VIH = 3.8V
IF TTL CIRCUITRY IS USED.
LC OSCILLATOR MODE
..l.. ..Q.. NOMINAL f
45 ~H 20 pF 5.2 MHz
120 ~H 20 pF 3.2 MHz
.--_-~ XTAL1
C'= C+3Cpp
2
Cpp "5 -10 pF PINTOPIN

l...--...+----i XTAL2 CAPACITANCE
EACH C SHOULD BE APPROXIMATELY 20 pF. INCLUDING STRAY CAPACITANCE.
WARNING:
PROGRAMMING, VERIFYING, AND
An attempt to program a missocketed 8741A will result in severe
ERASING THE 8741A EPROM
damage to the part. An indication of a properly socketed part is the
appearance of the SYNC clock output. The lack of this clock may
Programming Verification be used to disable the programmer.
In brief, the programming process consists of: activating The Program/Verify sequence is:
the program mode, applying an address, latching the 1. AO= OV, CS = 5V, EA = 5V, RESET = OV, TESTO = 5V,
address, applying data, and applying a programming pulse. V DD = 5V , clock applied or internal oscillator operating,
Each word is programmed completely before moving on to BUS and PROG floating.
the next and is followed by a verification step. The follow- 2. Insert 8741 A in programming socket
ing is a list of the pins used for programming and a descrip- 3. TEST 0 = Ov (select program mode)
tion of their functions:
4. EA = 23V (activate program mode)
5. Address applied to BUS and P2(}'1
Pin Function
6. RESET = 5v (latch address)
7. Data applied to BUS
XTAL1 Clock Input (1 to 6MHz)
8. V DO = 25v (programm ing power)
Reset Initialization and Address Latching
9. PROG = Ov followed by one 50ms pulse to 23V
Test 0 Selection of Program or Verify Mode
10. V OD= 5v
EA Activation of Program/Verify Modes
11. TEST 0 = 5v (verify mode)
BUS Addre~sand Data Input
12. Read and verify data on BUS
Data Output During Verify
P20-1 Address Input 13. TEST 0 = Ov
14. RESET = Ov and repeat from step 5
VOO Programming Power Supply
15. Programmer should be at conditions of step 1 when
PROG Program Pulse Input
8741 A is removed from socket.
7-71 00188A
8041 A/8641 A18741 A
8741A Erasure Characteristics should be placed over the 8741A window to prevent
unintentional erasure.
The erasure characteristics of the 8741A are such that
erasure begins to occur when exposed to light with
wavelengths shorter than approximately 4000 Ang- The recommended erasure procedure for the 8741A is
stroms (A). It should be noted that sunlight and certain exposure to shortwave ultraviolet light which has a
types of fluorescent lamps have wavelengths in the wavelength of 2537 A. The integrated dose (Le., UV inten-
3000-4000A range. Data show that constant exposure to sity x exposure time) for erasure should be a minimum
room level fluorescent lighting could erase the typical of 15 w-sec/cm 2. The erasure time with this dosage is
8741A in approximately 3 years while it would take ap- approximately 15 to 20 minutes using an ultraviolet
proximately one week to cause erasure when exposed lamp with a 12,000 p.W/cm 2 power rating. The 8741A
to direct sunlight. If the 8741 A is to be exposed to these should be placed within one inch of the lamp tubes dur-
types of lighting conditions for extended periods of ing erasure. Some lamps have a filter on their tubes
time, opaque labels are available from Intel which which should be removed before erasure.
A.C. TIMING SPECIFICATION FOR PROGRAMMING

TA = 25C 5C, Vee = 5V 5%, Voo = 25V 1V

tAW Address Setup Time to RESET I 4tcy
tWA Address Hold Time After RESET I 4tcy
tow Data in Setup Time to PROG I 4tcy
two Data in Hold Time After PROG I 4tcy
tPH RESET Hold Time to Verify 4tcy
tvoow Voo Setup Time to PROG I 4tcy
tVOOH Voo Hold Time After PROG I 0
tpw Program Pulse Width 50 60 mS
tTW Test 0 Setup Time for Program Mode 4tcy
tWT Test 0 Hold Time After Program Mode 4tcy
too Test 0 to Data Out Delay 4tcy
tww RESET Pulse Width to Latch Address 4tcy
tr, tf Voo and PROG Rise and Fall Times 0.5 2.0 }J.s
tey CPU Operation Cycle Time 5.0 }J.s
tRE RESET Setup Time Before EA I. 4tcy
Note: If TEST 0 is high, too can be triggered by RESET I.
D.C. SPECIFICATION FOR PROGRAMMING

T A = 25C 5C, Vee = 5V 5%, Voo = 25V 1V

VOOH Voo Program Voltage High Level 24.0 26.0 V
VOOL Voo Voltage Low Level 4.75 5.25 V
VPH PROG Program Voltage High Level 21.5 24.5 V
VPL PROG Voltage Low Level 0.2 V
VEAH EA Program or Verify Voltage High Level 21.5 24.5 V
VEAL EA Voltage Low Level 5.25 V
100 Voo High Voltage Supply Current 30.0 mA
IpROG PROG High Voltage Supply Current 16.0 mA
lEA EA High Voltage Supply Current 1.0 mA
7_7? onlRRA
8041 AJ8641 AJ8741 A
WAVEFORMS FOR PROGRAMMING
COMBINATION PROGRAMiVERIFY MODE (EPROM'S ONLYI
_----II
23V
EA
_.'""1'>------
5V
- - - - - - - - - - - - - PROGRAM - ----~+-- VERIFY PROGRAM - - - - -
TESTO
-------
DBO-DB7 J-- DATA TO BE

PROGRAMMED VALID
---< NEXT ADDR
VALID
x==
LAST NEXT
ADDRESS ADDRESS
Voo '" ,"oowa'"oo~w,
+5 W
I'~ i-two- - - -
trr-TI
~ I
PROG +5------------
+0
I
' ----'
r----------,~.-----------------
VERIFY MODE (ROM/EPROMI
~\\..-. _ _- J/ \\...-_---J/
RESET
\'-----
=>--- ADDRESS
10-7) VALID - - -<I..____A_~_~_~E_T ~XI.._~_~_~_\_~_~_i~--I>- - - - - - - -
S_S__
ADDRESS 18-9) VALID NEXT ADDRESS VALID
NOTES:
1. PROG MUST FLOAT IF EA IS LOW (I.e., *23V), OR IF TO = 5V FOR THE 8741A. FOR THE
8041A PROG MUST ALWAYS FLOAT.
2. XTAL 1 AND XTAL 2 DRIVEN BY 3.6 MHz CLOCK WILL GIVE 4.17 !,sec tCY' THIS IS ACCEPT
ABLE FOR 8741A8 PARTS AS WELL AS STANDARD PARTS.
3. AO MUST BE HELD LOW (I.e., = OV) DURING PROGRAMNERIFY MODES.
The 8741A EPROM can be programmed by either of two

Intel products:
1. PROMPT-48 Microcomputer Design Aid, or
2. Universal PROM Programmer (UPP series) peripheral
of the Intellec Development System with a UPP-848
Personality Card.
7-73 00188A
inter
8205
HIGH SPEED 1 OUT OF 8 BINARY DECODER
110 Port or Memory Selector Low Input Load Current - 0.25 mA
Max, 116 Standard TTL Input Load
Simple Expansion -' Enable Inputs
Minimum Line Reflection - Low
High Speed Schottky Bipolar Voltage Diode Input Clamp
Technology - 18 ns Max Delay Outputs Sink 10 mA Min
Directly Compatible with TTL Logic 16Pin Dual In-Line Ceramic or Plastic
Circuits Package
The Intel@ 8205 decoder can be used for expansion of systems which utilize input ports, output ports, and memory
components with active low chip select input. When the 8205 is enabled, one of its 8 outputs goes "low", thus a single
row of a memory system is selected. The 3-chip enable inputs on the 8205 allow easy system expansion. For very large
systems, 8205 decoders can be cascaded such that each decoder can drive 8 other decoders for arbitrary memory
expansions.
The 8205 is packaged in a standard 16-pin dual in-line package, and its performance is specified over the temperature
range of OC to +75C, ambient. The use of Schottky barrier diode clamped transistors to obtain fast switching speeds
results in higher performance than equivalent devices made with a gold diffussion process.
PIN CONFIGURATION LOGIC SYMBOL
Ao 16 V-cc Ao
Al 15 00 Al 0,
A2 14
1 A2 02
El 4 13 2 03
8205 8205
E2 12 03
04
E3 6 11 4 E, 05
07 10 5 E2 Os
GRD 8 9 06
E3 07
ADDRESS ENABLE OUTPUTS

PIN NAMES Ao A, A2 E, E2 EJ 0 1 2 3 4 S 6 7
L L L L L H L H H H H H H H
H L L L L H H L H H H H H H
~' ~ADD~~ INPUTS. J L Ii L L L H H H L H H H H H
E I' E3
00' 07
ENABLE INPUTS
DECODED OUTPUTS
1 H
L
H
H
L
L
L
H
H L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
L
H
H
H
L
H
H
H
H
H
H
L H H L L H H Ii H H H H L H
H H H L l H H H H H H H H L
X X X l l L H H H H H H H H
X X X H L L H H H H H H H H
X X X L H L H H H H H H H H
X X X H H L H H H H H H H H
X X X H L H H H H H H H H H
X X X l H H H H H H H H H H
X X X H H H H H H H H H H H
7-74 AFN-00204B-01
8205
Decoder
AO ~
The 8205 contains a one out of eight binary decoder. It ac-
A, 0,
cepts a three bit binary code and by gating this input. creates
an exclusive output that represents the value of the input A2 2
code.
3
For example. if a binary code of 101 was present on the AO. DECODER
A 1 and A2 address input lines. and the device was enabled. 4
an active low signal wou Id appear on the 05 output line.
Os
Note that all of the other output pins are sitting at a logic
high. thus the decoded output is said to be exclusive. The Os
decoders outputs will follow the truth table shown below in
0;
the same manner for all other input variations.
Enable Gate
When using a decoder it is often necessary to gate the out- (E"1-E2"-E3)
puts with timing or enabling signals so that the exclusive

output of the decoded value is synchronous with the overall
system.
The 8205 has a bu ilt-in function for such gating. The three Figure 1. Enable Gate
enable inputs (El E2. E3) are ANDed together and create
a single enable signal for the decoder. The combination of ADDRESS ENABLE OUTPUTS
both active "high" and active "low" device enable inputs Ao A, A2 E, E2 E3 a 1 2 3 4 5 6 7
provides the designer with a powerfully flexible gating func- L L L L L H L H H H H H H H
H L L L L H H L H H H H H H
tion to help reduce package count in his system.
L H L L L H H H L H H H H H
H H L L L H H H H L H H H H
L L H L L H H H H H L H H H
H L H L L H H H H H H L H H
l H H L L H H H H H H H L H
H H H L L H H H H H H H H L
X X X L L L H H H H H H H H
X X X H L L H H H H H H H H
X X X L H L H H H H H H H H
X X X H H L H H H H H H H H
X X X H L H H H H H H H H H
X X X L H H H H H H H H H H
X X X H H H H H H H H H H H
7-75 AFN-00204B-02
8205
Temperature Under Bias: Ceramic -65C to +1250 C "COMMENT

Plastic -65C to +75C Stresses above those listed under "Absolute Maximum Rat
ing" may cause permanent damage to the device. This is a stress
Storage Temperature -65C to +160o C rating only and functional operation of the device at these or at
All Output or Supply Voltages -0.5 to +7 Volts any other condition above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
All Input Voltages -1.0 to +5.5 Volts maximum rating conditions for extended periods may affect
Output Currents 125 mA device reliability.
D.C. CHARACTERISTICS
8205
LIMIT
SYMBOL PARAMETER UNIT TEST CONDITIONS
MIN. MAX.
IF INPUT LOAD CURRENT -0.25 mA Vee = 5.25V, V F = 0.45V
IR INPUT LEAKAGE CURRENT 10 J-IA Vee = 5.25V, V R = 5.25V
Vc INPUT FORWARD CLAMP VOLTAGE -1.0 V Vee = 4.75V, Ie = -5.0 mA
VOL OUTPUT "LOW" VOLTAGE 0.45 V Vee = 4.75V, IOL = 10.0 mA

VOH OUTPUT HIGH VOLTAGE 2.4 V Vee = 4.75V, IOH = -1.5 mA
V1L INPUT "LOW" VOLTAGE 0.85 V Vee = 5.0V
V 1H INPUT "HIGH" VOLTAGE 2.0 V Vee = 5.0V
Ise OUTPUT HIGH SHORT -AO -120 mA Vee = 5.0V, VOUT = OV

CIRCUIT CURRENT
Vox OUTPUT "LOW" VOLTAGE 0.8 V Vee = 5.0V, lox = 40 mA

@ HIGH CURRENT
lee POWER SUPPLY CURRENT 70 mA Vee = 5.25V

-
TYPICAL CHARACTERISTICS
OUTPUT CURRENT VS. OUTPUT CURRENT VS.

OUTPUT "LOW" VOLTAGE OUTPUT "HIGH" VOLTAGE DATA TRANSFER FUNCTION
100 5.0
TA = 7SOC __
V I I .I. fl-.V I .I
Vee = 5.0V - f--
-Vee = 5.0V
TA = 2S"C ___
r...... ~ I W/. i;, =isoc
80
~ TA -:: ooc
-10
TA = OC-
uV 4.0
,
vee = 5.0V TA = 750C
II
"
TA = OOC
60 -20 3.0
J [\ ~
J' I TA = 25"C-
-,
-\- --\1\
,
40 2.0
-30
I[ \
"
TA = 75OC- \
20
TA = 75OC ........
~ -40 I 1.0 \
1. '- t- \ \
..M
.2
-.4
T~ = ooc
t- TA = 25"C
.6 .8 1.0
-50
1.0
/J
2.0 3.0 4.0 5.0 o .2 .4 .6 .8 1.0
\.. ~ ~
1.2 1.4 1.6 1.8 2.0
OUTPUT "LOW" VOL TAGE (V) OUTPUT "HIGH" VOLTAGE (V) INPUT VOLTAGE (V)
7-76 AFN-00204B-05
8205
SWITCHING CHARACTERISTICS
Conditions of Test: Test Load

390rl
I nput pulse amplitudes: 2.5V
I nput rise and fall times: 5 nsec

between 1V and 2V
Measurements are made at 1.5V
All Transistors 2N2369 or Equivalent. C = 30 pF

L
Test Waveforms
ADDRESS OR ENABLE
INPUT PULSE
OUTPUT
A.C. CHARACTRISTICS
TA = QOCto +75C,V CC = 5V 5% unless otherwise specified.
SYMBOL PARAMETER MAX. LIMIT UNIT TEST CONDITIONS
t++ 18 ns
t_+ ADDRESS OR ENABLE TO 18 ns
OUTPUT DE LA Y 18 ns
t+_ --
t -- 18 ns
CIN (1) INPUT CAPACITANCE P8205 4(typ.) pF f = 1 MHz, Vee = OV
C8205 5(typ.) pF VBIAS = 2.0V, T A ~ 250 e
1. This parameter IS periodically sampled and IS not 100% tested.
ADDRESS OR ENABLE TO OUTPUT ADDRESS OR ENABLE TO OUTPUT
DELAY VS. LOAD CAPACITANCE DELAY VS. AMBIENT TEMPERATURE
20,-----,-----,------,-----, 20,-------,--------.-1------.
Vec = 5.0V
CL = 30 pF
15 15r--------~-------.~1~----~
-:~~.:.~~-~------
10
O~------~------~------~
50 100 150 200 o 25 50 75
LOAD CAPACITANCE (pFI AMBIENT TEMPERATURE lOCI
7-77 AFN-00204B-06
8251A/S2657
PROGRAMMABLE COMMUNICATION INTERFACE
Ii Synchionous and Asynchronous Asynchronous Baud Rate - DC to
Operation 19.2K Baud
Full Duplex, Double Buffered, Trans
Synchronous 58 Bit Characters; mitter and Receiver
Internal or External Character Synchro
nization; Automatic Sync Insertion Error Detection - Parity, Overrun and
Framing
Asynchronous 58 Bit Characters; Fully Compatible with 8080/8085 CPU
Clock Rate-1, 16 or 64 Times Baud
Rate; Break Character Generation; 1, 28Pin DIP Package
1112, or 2 Stop Bits; False Start Bit
Detection; Automatic Break Detect All Inputs and Outputs are TTL
and Handling. Compatible
Single + 5V Supply
Synchronous Baud Rate - DC to 64K
Baud Single TTL Clock
The Intel 8251A is the enhanced version of the industry standard, Intel 8251 Universal Synchronous/Asynchronous
Receiver/Transmitter (USART), designed for data communications with Intel's new high performance family of
microprocessors such as the 8085. The 8251A is used as a peripheral device and is programmed by the CPU to operate
using virtually any serial data transmission technique presently in use (including IBM "bi-sync"). The USART accepts
data characters from the CPU in parallel format and then converts them into a continuous serial data stream for
transmission. Simultaneously, it can receive serial data streams and convert them into parallel data characters for the
CPU. The USART will signal the CPU whenever it can accept a new character for transmission or whenever it has
received a character for the CPU. The CPU can read the complete status of the USART at any time. These include data
transmission errors and control signals such as SYNDET, TxEMPTY. The chip is constructed using N-channel silicon
gate technology.
~-- ---~-~-----~--~~--
PIN CONFIGURATION
BLOCK DIAGRAM
DI
Do
RxD Vel
GND RxC
DTR 0 7 "0 0
RTS
Dr, DSR
D, RESET
TxC ClK
WR TxD
CS TxEMPTY
C/O CTS
RD SYNDET/SO
RxRDY TxRDY
--......----~
PIN NAMES
--_._-------
~;~~r~~~:8D~lt~11S i
01- 0 0 OSR Data Set Ready
C/O !O be Written or Redd OTR Data Terminal Ready
fill
~R
~::t~ ~:~: ~~~':nat~:1 Commdnd II
SYNOET/SO SyncOetectl
Break Detect
CS Chip Enable I RTS Request to Send Data
CLK Clock Pulse ITTLI
RESET Reset CTS Clear to Send Data
hl Transmitter Clock TxE Transmitter Empty
TxD Transmitter Data Vee +5 Volt Supply
RXC Receiver Clock
GNO Ground
RxD Receiver Data
RxRDY Receiver Ready (has chClracter for 80801
TxRDY Transmitter Ready (ready for char from BOBOl
7-78
8251 A/~2t)5 7
FEATURES AND ENHANCEMENTS Tx Enable logic enhancement prevents a

8251 A is an advanced design of the industry stan- Tx Disable command from halting trans-
dard USART, the Intel 8251. The 8251A oper- mission until all data previously written has
ates with an extended range of Intel micropro- been transmitted. The logic also prevents
cessors that includes the new 8085 CPU and main- the transmitter from turning off in the middle
tains compatibility with the 8251. Familiarization of a word.
time is minimal because of compatibility and When External Sync Detect is programmed,
involves only knowing the additional features and Internal Sync Detect is disabled, and an Ex-
enhancements, and reviewing the AC and DC speci- ternal Sync Detect status is provided via a
fications of the 8251 A. flip-flop which clears itself upon a status read.
Possibility of false sync detect is. minimized
The 8251A incorporates all the key features of by ensuring that if double character sync is
the 8251 and has the following additional features programmed, the characters be contiguously
and enhancements: detected and also by clearing the Rx register
to all ones whenever Enter Hunt command is
8251A has double-buffered data paths with issued in Sync mode.
separate I/O registers for control, status,
Data In, and Data Out, which considerably As long as the 8251A is not selected, the
simplifies control programming and mini- RD and WR do not affect the internal opera-
mizes CPU overhead. tion of the device.
In asynchronous operations, the Receiver The 8251 A Status can be read at any time
detects and handles "break" automatically, but the status update will be inhibited during
relieving the CPU of this task. status read.
A refined Rx initialization prevents the The 8251 A is free from extraneous gl itches
Receiver from starting when in "break" and has enhanced AC and DC characteristics,
state, preventing unwanted interrupts from providing higher speed and better operating
a disconnected USART. margins.
At the conclusion of a transmission, TxD Synchronous Baud rate from DC to 64K.
line will always return to the marking state Fully compatible with Intel's new industry
unless SBRK is programmed. standard, the MCS-85.
7-79 00216A
8251 A/S2657
ABSOLUTE MAXIMUM RATINGS* *COMMENT: Stresses above those listed under "Absolute
device. This is a stress rating only and functional opera
c
.A.mbient Temperature Under Bias . . . . . . . . . OC to 70 e tio{1 of the device at these or any other conditions above
Storage Temperatur~ . . . . . . . . . . . . . . -65C to +150C those indicated in the operational sections of this specifi-
Voltage On Any Pin cation is not implied. Exposure to absolute maximum
With Respect to Ground . . . . . . . . . . . . -0.5V to + 7V rating conditions for extended periods may affect device
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 1 Watt reliability.
T A = OC to 70C; Vee = 5.0V 5%; GND = OV
VIH Input High Voltage 2.2 Vee V
VOL Output Low Voltage 0.45 V IOL = 2.2 mA
VOH Output High Voltage 2.4 V IOH = -400 J.lA
IOFL Output Float Leakage 10 J.lA V OUT = Vee TO 0.45V
IlL Input Leakage 10 J.lA VIN= Vee TO 0.45V
Icc Power Supply Current 100 mA All Outputs = High
CAPACITANCE
TA = 25C; Vee = GND = OV
CIN I nput Capacitance 10 pF fc = 1MHz
ClIO I/O Capacitance 20 pF Unmeasured pins returned to GND
+20
+10
0:
2V >
~Cl
....
~
lN914
....
::l
0
-1
8251A t-----,--+---o OUT -10
6K
-20 L--.....J.'--...J....._ _--L_ _ _. L -_ _ ~
-100 -50 . +50 +100

Cl = 150pF.
.:, CAPACITANCE (pF)
Figure 16. Test Load Circuit Figure 17. Typlcalll Output Delay vs. Il
Capacitance (pF)
780 00216A
8251 A/S2657
Bus Parameters (Note 1)

Read Cycle:
SYMBOL PARAMETER MIN. MAX. UNIT TEST CONDITIONS
tAR Address Stable Before READ (CS, C/D) 50 ns Note 2

tRA Address Hold Time for READ (CS, C/D) 50 ns Note 2
tRR READ Pulse Width 250 ns
tRD Data Delay from READ 250 ns 3, CL = 150 pF
tDF READ to Data Floating 10 100 ns
Write Cycle:

tAW Address Stable Before WRITE 50 ns
tWA Address Hold Time for WR ITE 50 ns
tww WRITE Pulse Width 250 ns
tDW Data Set Up Time for WR ITE 150 ns
tWD Data Hold Time for WR ITE 50 ns
tRV Recovery Time Between WRITES 6 tCY Note 4
NOTES: 1. AC timings measured VOH = 2.0, VOL = 0.8, and with load circuit of Figure 1.
2. Chip Select (CS) and Command/Data (C/O) are considered as Addresses.
3. Assumes that Address is valid before R Dt.
4. This recovery time is for Mode Initialization only. Write Data is allowed only when TxRDY = 1.
Recovery Time between Writes for Asynchronous Mode is 8 tCY and for Synchronous Mode is 16 tCY.
Input Waveforms for AC Tests
0.45
______X:::
2.4 - - - - - - , . ,.----------------...
p6~~is ::: X_____

,....----
7-81 00216A
8251A/S2657
Other Timings:
SYMBOL PARAMETER IMIN. MAX. UNIT TEST CONDITIONS
tCY Ciock Period 320 1350 ns Notes 5, 6
tq> Clock High Pulse Width 140 tCY-9O ns
qj Clock Low Pulse Width 90 ns
tR, tF Clock Rise and Fall Time 20 ns
tDTx TxD Delay from Falling Edge of TxC 1 ps
fTx Transmitter Input Clock Frequency
1x Baud Rate DC 64 kHz
tTPw Transmitter Input Clock Pulse Width
1x Baud Rate 12 tCY
16x and 64x Baud Rate 1 tCY
tTPD Transmitter Input Clock Pulse Delay
1x Baud Rate 15 tCY
fRx Receiver Input Clock Frequency
tRPW Receiver Input Clock Pulse Width
1x Baud Rate 12 tCY
tRPD Receiver Input Clock Pulse Delay
1x Baud Rate 15 tCY
tTxRDY TxRDY Pin Delay from Center of last Bit 8 tCY Note 7
tTxRDY CLEAR TxRDY t from Leading Edge of WR 6 tCY Note 7
tRxRDY RxRDY Pin Delay from Center of last Bit 24 tCY Note 7
tRxRDY CLEAR RxRDY ,} from Leading Edge of RD 6 tCY Note 7
tiS Internal SYNDET Delay from Rising
24 tCY Note 7
Edge of RxC
tES External SYNDET Set-Up Time Before
16 tCY Note 7
Falling Edge of RxC
tTxEMPTY TxEMPTY Delay from Center of Last Bit 20 tCY Note 7
twc Control Delay from Rising Edge of 8 tCY Note 7
WRITE {TxEn, DTR, RTS)
tCR Control to READ Set-Up Time (DSR, CTS) 20 tCY Note 7
5. The TxC and RxC frequencies have the following limitations with respect to ClK.
For 1x Baud Rate, fTx or fRx ,,;; 1/(30 tCY)
For 16x and 64x Baud Rate, fTx or fRx";; 1/(4.5 tCY)
6. Reset Pulse Width = 6 tCY minimum; System Clock must be running during Reset.
7. Status update can have a maximum delay of 28 clock periods from the event affecting the status.
7-82 00216A
inter
8253/82535
PROGRAMMABLE INTERVAL TIMER
MCS-85 Compatible 82535 Count Binary or BCD
3 Independent 16Bit Counters Single + 5V Supply

DC to 2 MHz
Programmable Counter Modes 24Pin Dual InLine Package
The Intel\!) 8253 is a programmable counter/timer chip designed for use as an Intel microcornputer peripheral. It uses
nMOS technology with a single +5V supply and is packaged in a 24-pin plastic DIP.
It is organized as 3 independent 16-bit counters, each with a count rate of up to 2 MHz. All modes of operation are soft-
ware programmable.
D7 Vee
ClK 0
D6 WR DATA
Ds AD BUS GATE 0
BUFFER
D4 cs OUT 0
D3 A,
D2 Ao
D, eLK 2
Do OUT 2
RD---Cf
eLK 0 GATE 2 ClK 1
OUT 0 eLK 1
GATE 1
GATE 0 GATE 1
GND OUT 1 OUT 1
CS--------'
PIN NAMES CLK 2

D7 D O DATA BUS 18 BIT! COUNTER
CLK N COUNTER CLOCK INPUTS =2 GATE 2
GATE N COUNTER GATE INPUTS

-OUT2
OUT N COUNTER OUTPUTS
RD READ COUNTER
WR WRITE COMMAND OR DATA
CS CHIP SELECT
Ao A COUNTER SELECT
Vee +5 VOL TS
GND GI'IOUND INTERNAL BUS /
INTel CORPORATION ASSUMES NO RESPONSIBILITY FOR THE USE OF ANY CIRCUITRY OTHER THAN CIRCUITRY EMBODIED IN AN INTel PRODUCT. NO OTHER CIRCUIT PATENT LICENSES ARE IMPliED.
'0 INTel CORPORATION. 1979 7-83 AFN-00745A-Ol
8253/82535
FUNCTIONAL DESCRIPTION AO,A1

General These inputs are normally connected to the address bus.
The 8253 is a programmable interval timer/counter Their function is to select one of the three counters to be
specifically designed for use with the Intel n Micro- operated on and to address the control word register for
computer systems. Its function is that of a general mode selection.
purpose, multi-timing element that can be treated as an CS (Chip Select)
array of I/O ports in the system software.
A "low" on this input enables the 8253. No reading or
The 8253 solves one of the most common problems in any writing will occur unless the device is selected. The CS
microcomputer system, the generation of accurate time input has no effect upon the actual operation of the
delays undersoftware control. I nstead of setting up timing counters.
loops in systems software, the programmer configures the
8253 to match his requirements, initializes one of the
counters of the 8253 with the desired quantity, then upon
command the 8253 will count out the delay and interrupt
the CPU when it has completed its tasks. It is easy to see
that the software overhead is minimal and that multiple
delays can easily be maintained by assignment of priority
levels.
Other counter/timer functions that are non-delay in
nature but also common to most microcomputers can be
implemented with the 8253.
Programmable Rate Generator
Event Counter
Binary Rate Multiplier
Real Time Clock
Digital One-Shot
Complex Motor Controller
Data Bus Buffer
This 3-state, bi-directional, 8-bit buffer is used to interface
the 8253 to the system data bus. Data is transmitted or
received by the buffer upon execution of I Nput or OUTput
CPU instructions. The Data Bus Buffer has three basic
functions.
1. Programming the MODES of the 8253.
2. Loading the count registers.
3. Reading the count values.
Read/Write Logic
The Read/Write Logic accepts inputs from the system bus Figure 1. Block Diagram Showing Data Bus Buffer and
and in turn generates control signals for overall device Read/Write logic Functions
operation. It is enabled or disabled by CS so that no
operation can occur to change the function unless the
device has been selected by the system logic.
RD (Read) -
CS RD WR A, Ao
A "low" on this input informs the 8253 that the CPU is
0 1 0 0 0 Load Counter No. 0
inputting data in the form of a counters value.
0 1 0 0 1 Load Counter No.1
WR (Write) 0 1 0 1 0 Load Counter No. 2
A "low" on this input informs the 8253 that the CPU is
0 1 0 1 1 Write Mode Word
outputting data in the form of mode information or loading
counters. 0 0 1 0 0 Read Counter No. 0
0 0 1 0 1 Read Counter No. 1
0 0 1 1 0 Read Counter No.2
0 0 1 1 1 No-Operation 3-State
1 X X X X Disable 3-State
0 1 1 X X No-Operation 3State
784 AFN-0074SA-02
8253/82535
Control Word Register

The Control Word Register is selected when AO. A 1 are 11.
It then accepts information from the data bus buffer and
stores it in a register. The information stored in this
register controls the operational MODE of each counter.
selection of binary or BCD counting and the loading of
each count register.
The Control Word Register can only be written into; no
read operation of its contents is available.
Counter #0, Counter #1, Counter #2

These three functional blocks are identical in operation so
only a single Counter will be described. Each Counter
consists of a single. 16-bit. pre-settable. DOWN counter.
The counter can operate in either binary or BCD and its
input. gate and output are configured by the selection of
MODES stored in the Control Word Register.
The counters are fully independent and each can have
separate Mode configuration and counting operation.
binary or BCD. Also. there are special features in the
control word that handle the loading of the count value so
that software overhead can be minimized for these
functions.
The reading of the contents of each counter is available to
the programmer with simple READ operations for event
counting applications and special commands and logic
are included in the 8253 so that the contents of each_
counter can be read "on the fly" without having to inhibit
the clock input.
Figure 2. Block Diagram Showing Control Word
8253 SYSTEM INTERFACE Register and Counter Functions
The 8253 is a component of the Intel Microcomputer
Systems and interfaces in the same manner as all other
ADDRESS BUS (16)
peripherals of the family. It is treated by the systems
software as an array of peripheral I/O ports; three are
counters and the fourth is a control register for MODE
CONTROL BUS
programming.
Basically. the select inputs AO. A 1 connect to the AO. A 1
address bus signals of the CPU. The CS can be derived
directly from the address bus using a linear select method.
Or it can be connected to the output of a decoder. such as
an Intel 8205 for larger systems.
8253
11
Figure 3. 8253 System Interface
7-85 AFN-00745A-03
8253/82535
MODE 0: Interrupt on Terminal Count MODE 3: Square Wave Generator
CLOCK CLOCK
2 4
WRn~ I OUTPUT In =4)
I
o OUTPUT In =5)
OUTPUT (INTERRUPT) I
In=4) I-+-n-:
I I
I I
WRm~
, ,
GATE :L........Jr .....:.'----

5 4 .1
OUTPUT (INTERRUPT)
1m =5) '----'
A
A+8=m
MODE 1: Programmable OneShot MODE 4: Software Triggered Strobe
TRIGGER
~
4
OUTPUT
~~--------~
LOADn~
TRIGGER~
4 3 2 3 2 1 GATE -----~~~------
OUTPUT - - , L_ _ _ _ _ _ _ _- ' o
OUTPUT ------~----~~--~~
MODE 2: Rate Generator MODE 5: Hardware Triggered Strobe
CLOCK
GATE -----1
4
OUTPUT In = 4)
LJ
GATE~
4343210
OUTPUT In = 4) U
Figure 5. 8253 Timing Diagrams
786 AFN-00745A-06
8253/8253-5
8253 READ/WRITE PROCEDURE

Write Operations
MODE Control Word
The systems software must program each counter of the Counter n
8253 with the mode and quantity desired. The program-
mer must write out to the 8253 a MODE control word and Count Register byte
LSB
the programmed number of count register bytes (1 or 2) Counter n
prior to actually using the selected counter. Count Register byte
MSB
The actual order of the programming is quite flexible. Counter n
Writing out of the MODE control word can be in any
sequence of counter selection, e.g., counter #0 does not Note: Format shown is a simple example of loading the 8253 and
have to be first or counter #2 last. Each counter's MODE does not imply that it is the only format that can be used.
control word register has a separate address so that its
loading is completely sequence independent. (SCO, SC1) Figure 6. Programming Format
The loading of the Count Register with the actual count
value, however, must be done in exactly the sequence
programmed in the MODE control word (RLO, RL 1). This
loading of the counter's count register is still sequence Al AO
independent like the MODE control word loading, but
when a selected count register is to be loaded it must be
loaded with the number of bytes programmed in the
No. ,
MODE Control Word
Counter 0
, ,
MODE control word (RLO, RL 1). The one or two bytes to
be loaded in the count register do not have to follow the No. 2
MODE Control Word
Counter'
, ,
associated MODE control word. They can be programmed
at any time following the MODE control word loading as
long as the correct number of bytes is loaded in order.
No. 3
MODE Control Word
Counter 2
, 1
All counters are down counters. Thus, the value loaded Count Register Byte
into the count register will actually be decremented.
No.4 LSB 0 1
Counter'
Loading all zeroes into a count register will result in the
Count Register Byte
maximum count (2 '6 for Binary or 104 for BCD). In MODE a 0 1
the new count will not restart until the load has been No. 5 MSB Counter'
completed. It will accept one of two bytes depending on
how the MODE control words (RLO. RL 1) are program- No.6 LSB
Count Register Byte
Counter 2
, 0
med. Then proceed with the restart operation.
No. 7 MSB
Count Register Byte
Counter 2
, 0
Count Register Byte

No.8 LSB 0 0
Counter 0
Count Register Byte
No.9 MSB 0 0
Counter 0
Note: The exclusive addresses of each counter's count register make

the task of programming the 8253 a very simple matter, and
maximum effective use of the device will result if this feature
is fully utilized.
Figure 7. Alternate Programming Formats
7-87 AFN-0074SA-07
8253/82535
Read Operations Read Operation Chart

In most counter applications it becomes necessary to read
the value of the count in progress and make a
Al AO RD
computational decision based on ihis quaniiiy. Eveni 0 0 0 Read Counter No. a
counters are probably the most common application that
uses this function. The 8253 contains logic that will allow
O. 1 a Read Counter No. 1
the programmer to easily read the contents of any of the 1 a 0 Read Counter No.2
three counters without disturbing the actual count in
progress.
1 1 a Illegal
There are two methods that the programmer can use to Reading While Counting
read the value ot'the counters.' The first method involves
the use of simple 1/0 read operations of the selected In order for the programmer to read the contents of any
counter. By controlling the AD, A 1 inputs to the 8253 the counter without effecting or disturbing the counting
programmer can select the counter to be read (remember operation the 8253 has special internal logic that can be
that no read operation of the mode register is allowed AD, accessed using. simple WR commands to the MODE
A1-11). The only requirement with this method is that in register. Basically, when the programmer wishes to read
order to assure a stable count reading the actual operation the contents of a selected counter "on the fly" he loads the
of the selected counter must ~ inhibited either by MODE register with a speCial code which latches the
controlling the Gate input or by external logic that inhibits present count value into a storage register so that its
the clock input. The contents of the counter selected will contents contain an accurate, stable quantity. The
be available as follows: programmer then issues a normal read command to the
selected counter and the contents of the latched register is
first 1/0 Read contains the least significant byte (LSB). ayatlable.
second 1/0 Read contains the most significant byte
(MSB). MODE Register for Latching Count
Due to the .internal logic of the 8253 It is absolutely AO, A1 11
necessary to complete the entire reading procedure. If two
bytes are programmed to be read then two bytes must be
read before any loading WR command can be sent to the
same counter.
se 1,SeD - specify counter to be latched.

05,04 00 designates counter latching operation
X don't care.
The same limitation applies to this mode of reading the
counter as the previous method. That is, it is mandatory
to complete the entire read operation as programmed.
This command has no effect on the counter's mode.
3MHz 1.5MHz
CLK 2 CLK
8085 8253-5
*If an 8085 clock output is to drive an 8253-5 clOck input, it must be reduced to 2 MHz or less_
Figure 8. r.1CS8S Clock' Interface
7-88 AFN-0074SA-08
8253/82535
Ambient Temperature Under Bias OCto 70C
Storage Temperature -65 C to +150 C
Voltage On Any Pin those indicated in the operational sections of this specifi-
With Respect to Ground -0.5 Vto +7 V cation is not implied. Exposure to absolute maximum
Power Dissipation 1 Watt rating conditions for ex tended periods may affect device
reliabili tv.
D
D.C. CHARACTERISTICS (TA = ODC to 70 C; Vee = 5V 5%)

VIH Input High Voltage 2.2 Vee+ 5V V
VOL Output Low Voltage 0.45 V Note 1
VOH Output High Voltage 2.4 V Note 2
IlL Input Load Current 10 f.1A V IN = Vee to OV
IOFL Output Float Leakage 10 f.1A VOUT = Vee to OV
lee Vee Supply Current I 140 I mA
Note 1: 8253, IOL = 1.6 mA; 8253-5, IOL = 2.2 mA.
Note 2: 8253, IOH = -150 f.1A; 8253-5, IOH = -400 f.1A.
D
CAPACITANCE TA = 25 C; Vee = GND = OV
Symbol Parameter Min. Typ. Max. Unit Test Conditions

CIN Input Capacitance 10 pF fc = 1 MHz
CliO I/O Capacitance 20 pF Unmeasured pins returned to Vss
7-89 AFN-00745A-09
8253/82535
A.C. CHARACTERISTICS TA = oc to 70C; Vee = 5.0V 5%; GND = OV

Read Cycle:
8253 8253-5
SYMBOL PARAMETER MIN. MAX. MIN. MAX. UNIT
tAR Address Stable Before READ 50 30 ns

tRA Address Hold Time for READ 5 5 ns
tRR READ Pulse Width 400 300 ns
tRO Data Delay From READI21 300 200 ns
tOF READ to Data Floating 25 125 25 100 ns
tRY Recovery Time Between READ

1 1 J,LS
and Any Other Control Signal
Write Cycle:
8253 8253-5
tAW Address Stable Before WR ITE 50 30 ns
tWA Address Hold Time for WR ITE 30 30 ns
tww WR ITE Pulse Width 400 300 ns
tow Data Set Up Time for WR ITE 300 250 ns
two Data Hold Time for WR ITE 40 30 ns
tRV Recovery Time Between WRiTE 1 1 J1S

and Any Other Control Signal
Notes: 1. AC timings measured at Vo H = 2.2, Vo L = 0.8

2. Test Conditions: 8253, CL = 1OOpF; 8253-5: CL = 150pF.
Write Timing: Read Timing:
____
Ao-1. CS
J~~--------------~~~-------
DATA BUS
Input Waveforms for A.C. Tests:
2 . 4 - - -...
0.45 _ _ _..J X
> 2
_ '0 . 8 TEST POINTS
<:::x'----
7-90 AFN-00745A-l0
8253/82535
Clock and Gate Timing:
8253 82535
tCLK Clock Per iod 380 de 380 de ns
tPWH High Pulse Width 230 230 ns
tPWL low Pulse Width 150 150 ns
tGW Gate Width High 150 150 ns
tGL Gate Width low 100 100 ns
tGS Gate Set Up Time to ClKt 100 100 ns
tGH Gate Hold Time After ClKt 50 50 ns
too Output Delay From ClK-!-11 J 400 400 ns
tODG Output Delay From Gate-!-11] 300 300 ns
Note 1: Test Conditions: 8253: CL = 1OOpF; 82535: CL = 150pF.
AFN-Q0745A-11
7-91
8255A/8255A5
PROGRAMMABLE PERIPHERAL INTERFACE
MCS85 Compatible 8255A5 Direct Bit Set/Reset Capability Easing

Control Application Interface
24 Programmable I/O Pins
Completely TTL Compatible 40Pin Dual InLine Package
Fully Compatible with Intel Micro
Reduces System Package Count
processor Families
Improved Timing Characteristics Improved DC Driving Capability
The Intel@ 8255A is a general purpose programmable 1/0 device designed for use with Intel@ microprocessors. It has
241/0 pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation. In the first
mode (MODE 0), each group of 121/0 pins may be programmed in sets of 4 to be input or output. In MODE 1, the second
mode, each group may be programmed to have 8 lines of input or output. Of the remaining 4 pins, 3 are used for hand-
shaking and interrupt control signals. The third mode of operation (MODE 2) is a bidirectional bus mode which uses 8
lines for a bidirectional bus, and 5 lines, borrowing one from the other group, for handshaking.
PIN CONFIGURATION 8255A BLOCK DIAGRAM
S~~:L~~S { - - +5V
-_GND 10
PA7-PAO
10
pe7- pee
PIN NAMES
0 7 -0. DATA BUS (BI-DIRECTIONAL)
RESET RESET INPUT
CS CHIP SElECT
RD READ INPUT
WR WRITE INPUT
AO.A1 PORT ADDRESS
PA7PAO PORT A (BIT)
P87P80 PORTB (BIT)
PC7.f'CO PORTe (BIT)
Vee +5 VOLTS
GND 'VOLTS
AFN-00744A-01
7-92
8255A18255A5
8255A FUNCTIONAL DESCRIPTION (RD)

Read. A "low" on this input pin enables the 8255A to
General
send the data or status information to the CPU on the
The 8255A is a programmable peripheral interface (PPI) data bus. In essence, it allows the CPU to "read from"
device designed for use in Intel microcomputer the 8255A.
systems. Its function is that of a general purpose 1/0
component to interface peripheral equipment to the (WR)
microcomputer system bus. The functional configura- Write. A "low" on this input pin enables the CPU to write
tion of the 8255A is programmed by the system software data or control words into the 8255A.
so that normally no external logic is necessary to inter-
face peripheral devices or structures. (Ao and A 1)
Port Select 0 and Port Select 1. These input signals, in
Data Bus Buffer conjunction with the RD and WR inputs, control the
This 3-state bidirectional 8-bit buffer is used to interface selection of one of the three ports or the control word
the 8255A to the system data bus. Data is transmitted or registers. They are normally connected to the least
received by the buffer upon execution of input or output significant bits of the address bus (Ao and A 1).
instructions by the CPU. Control words and status infor-
mation are also transferred through the data bus buffer.
8255A BASIC OPERATION
Al AO RD WR CS INPUT OPERATION (READ)
Read/Write and Control Logic 0 0 0 1 0 PORT A =
DATA BUS
0 1 0 1 0 =
PORT B DATA BUS
The function of this block is to manage all of the internal 1 0 0 1 0 =
PORT C DATA BUS
and external transfers of both Data and Control or Status OUTPUT OPERATION
words. It accepts inputs from the CPU Address and Con- (WRITE)
trol busses and in turn, issues commands to both of the 0 0 1 0 0 DATA BUS = PORT A
Control Groups. 0 1 1 0 0 DATA BUS = PORT B
1 0 1 0 0 DATA BUS = PORT C
1 1 1 0 0 DATA BUS = CONTROL
DISABLE FUNCTION
(CS) X X X X 1 DATA BUS =
3-STATE
1 1 0 1 0 I LLEGAL CONDITION
Chip Select. A "low" on this input pin enables the com-
muniction between the 8255A and the CPU. X X 1 1 0 DATA BUS=3-STATE
Figure 1. 8255A Block Diagram Showing Data Bus Buffer and Read/Write Control Logic Functions
7-93 AFN-00744A-02
8255A18255A5
(RESEn Ports At St and C

Reset A "high on this input clears the control register The 8255A contains three a. bit ports (A, B, and C). All
and all ports (A, C, C) are set to the input mode. can be configured in a wide variety of functional charac-
teristics by the system software but each has its own
special features or "personality" to further enhance the
Group A and Group B Controls
power and flexibility of the 8255A.
The functional configuration of each port is program-
med by the systems software. In essence, the CPU "out-
puts" a control word to the 8255A. The control word con- Port A. One 8-bit data output latch/buffer and one 8-bit
tains information such as "mode", "bit set", "bit reset", data input latch.
etc., that initializes the functional configuration of the Port B. One 8-bit data input/output latch/buffer and one
8255. 8-bit data input buffer.
Each of the Control blocks (Group A and Group B) accepts
Port C. One 8-bit data output latch/buffer and one 8-bit
"commands" from the Read/Write Control Logic, receives data input buffer (no latch for input). This port can be
"control words" from the internal data bus and issues the divided into two 4-bit ports under the mode control.
proper commands to its associated ports. Each 4-bit port contains a 4-bit latch and it can be used
Control Group A - Port A and Port C upper (C7-C4) for the control signal outputs and status signal inputs in
Control Group B - Port B and Port Clower (C3-CO) conjunction with ports A and B.
The Control Word Register can Only be written into. No
Read operation of the Control Word Register is allowed.
PIN CONFIGURATION
PAl
PA6
_ _ +,v
POWER
SUPPLIES { -_GNO 10
FlA7-PAO Do
0,
0,
OJ
8255A D.
0,
10
PC7-PC4
10
PC3-PCO P85
PBl l 19 22 "l P84
P82f 20 21 1 PBJ
10 PIN NAMES
PB7-PBO
D7 Do DATA BUS (BIDIRECTION~

RESET RESET INPUT
:
CS CHIP SelECT -
RD READ INPUT - --~=:1
WR WRITE INPUT
AD. AT PORT ADDRESS
PA7PAD PORT A (BIT) _.
PB7PBD PORT B (BIT)
Pe7PCD PORT C (BITI
-----
Vee ~5VOL1S I
GND (J VOLTS i
Figure 2. 8225A Block Diagram Showing Group A and
Group B Control Functions
794 AFN-00744A-03
's18255A18255Ao5 ~
Ambient Temperature Under Bias . . . . . . . . . OC to 70C tion of the device at these or any other conditions above
Storage Temperature . . . . . . . . . . . . . . -65"C to +150C those indicated in the operational sections of this specifi-
With Respect to Ground . . . . . . . . . . . . -O.5V to + 7V rating conditions for ex tended periods may affect device
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 1 Watt reliabili tv.
TA = OC to 70C. Vee = +5V 5%; GND = OV

V IL Input Low Voltage -0.5 0.8 V
VIH Input High Voltage 2.0 Vee V

VOL (DB) Output Low Voltage (Data Bus) 0.45 V IOL = 2.5mA
VOL(PER) Output Low Voltage (Peripheral Port) 0.45 V IOL = 1.7mA
VOH (DB) Output High Voltage (Data Bus) 2.4 V IOH =' -400J.LA
VOH(PER) Output High Voltage (Peripheral Port) 2.4 V IOH = -200J.LA
IOARI11 Darlington Drive Current -1.0 -4.0 mA R EXT = 750[2; VEXT= 1.5V
lee Power Supply Current 120 mA
IlL Input Load Current 10 J.LA VIN = Vce to OV

IOFL Output Float Leakage 10 J.LA VOUT = Vec to OV
Note1: Available on any 8 pins from Port Band C.
CAPACITANCE
TA = 25C; Vee = GND = ov
SYMBOL PARAMETER MIN. TYP. MAX. UNIT TEST CONDITIONS
CIN I nput Capacitance 10 pF fc=1MHz
CliO I/O Capacitance 20 pF Unmeasured pins returned to GN D
~~~!~
L:.:.J l ___ :YV ------,.., VEXT*
I 100PF
'VEXT is set at various voltages during testing to guarantee the specification.
Figure 24. Test Load Circuit (for dB)
AFN-00744A-17
795
8255A/8255A5
TA = oc to 70C; VCC = +5V 5%; GND = OV
Bus Parameters
Read:
8255A
SYMBOL PARAMETER MIN. MAX. UNIT
tAR Address Stable Before READ 0 ns
tRA Address Stable After READ 0 ns
tRD Data Valid From R EAD[l) 250 ns
tDF Data Float After READ 10 150 ns
tRV Time Between READs and/or WR ITEs 850 ns
Write:
8255A
tAW Address Stable Before WR ITE a ns
tWA Address Stable After WR ITE 20 ns
tww WR ITE Pulse Width 400 ns
tDW Data Valid to WR ITE (T.E.) 100 ns
tWD Data Valid After WR ITE 30 ns
Other Timings:
8255A
tWB WR = 1 to Output[ 1) 350 ns
tlR Periphera I Data Before R D a ns
tHR Peripheral Data After RD a ns
tAK ACK Pulse Width 300 ns
tST STB Pulse Width 500 ns

tps Per. Data Before T. E. of STB a ns
tpH Per. Data After T.E. of STB 180 ns
tAD ACK = a to Output[ 1) 300 ns
tKD ACK = 1 to Output Float 20 250 ns
tWOB WR = 1 toOBF =0(1) 650 ns
tAOB ACK = a to OBF = 1(1) 350 ns
tSIB ST B = 0 to I B F = 1 (1) 300 ns
tRIB RD = 1 to IBF = all) 300 ns
tRIT RD = a to INTR = 0(1) 400 ns
tSIT STB = 1 to INTR = 1(1 ) 300 ns
tAIT ACK = 1 to INTR = 1(1 ) 350 ns
tWIT WR = 0 to INTR = 0(1 ) 850 ns
Notes: 1. Test Conditions: 8255A: CL = 100pF;8255A-5: CL = 150pF.

2. Period of Reset pulse must be at least 50~s during or after power on.
Subsequent Reset pulse can be 500 ns min.
7-96 AFN-00744A-18
8255A18255A5
2.4------....
~2.0X
X
2.O -.
0.45 _ _ _ _ ~ 0.8';::' TEST POINTS ---... O.~ '-_ _ _ __
Figure 25. Input Waveforms for A.C. Tests
RO
INPUT _ _ f""-1 ['""--X______

. ______
CS. Al. Ao-----------E=-: ['"'--1--------
-
7 0 - ________ -+1 (
f . .- ' - - --- - - tR- D
--
~-+--+-i-----J.t
-=--=--=--=--=--=--. ; f 4 .- - - - tDF - - - - - l
- --
Figure 26. MODE 0 (Basic Input)
WR
--~-'wD-j
i------tAW--------i i------'wA----~
CS. Al. AO
OUTPUT
Figure 27. MODE 0 (Basic Output)
7-97 AFN-00744A-19
8255A18255A5
______________~I------t.T------Ir_--~------------------------------~~-----------
IBF
INTR
INPUT FROM _ _ _
PERIPHERAL
I-----tps-------I
Figure 28. MODE 1 (Strobed Inut)
INTR
OUTPUT
Figure 29. MODE 1 (Strobed Output)
798 AFN-00744A-20
8255A18255A5
DATA FROM
~ 8080 TO 8255
INTR
IBF
PERIPHERAL _ _ _ _ _ _ _ _ _ _
BUS
DATA FROM
PERIPHERAL TO 8255
DATA FROM
8255 TO 8080
Figure 30. MODE 2 (Bidirectional)
NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible.
(INTR = IBF MASK STB RD + OBF MASK' ACK WR I
7.00
intel"
ftft.,
O~ I ..II '8ft .,..
~ I . - 6,'8 7" 8
ft
~
PROGRAMMABLE FLOPPY DISK CONTROLLER
IBM 3740 Soft Sectored Format Compatible Internal CRC Generation and Checking
Programmable Record Lengths Programmable Step Rate, Settle Time, Head
Load Time, Head Unload Index Count
MultlSector Capability
Overhead
Maintain Dual Drives with Minimum Software Fully MCSSOTM and MCSSS Compatible
Expandable to 4 Drives
Single + SV Supply
Automatic Read/Write Head Positioning and
Verification 40Pln Package
The Intel~ 8271 Programmable Floppy Disk Controller (FOC) is an LSI component designed to interface one to 4 floppy
disk drives to an 8bit microcomputer system. Its powerful control functions minimize both hardware and software
overhead normally associated with floppy disk controllers.
PIN CONfiGURATION BLOCK DIAGRAM
FAULT RESET/OPO Vee

SELECT 0 lOW CURRENT
4 MHz ClK lOAD HEAD
RESET DIRECTION
READY 1 SEEK/STEP
SELECT 1 WR ENBLE
DACK INDEX
ORO WR PROTECT
Ri5 READY 0
WR TRKO
INT COUNT/UP!
DBO WR DATA
DBl FAULT
DB2 UNSE~ DATA ORO
DB3 DATA WINDOW DACK
DB4 PLO/SS INT
DBS CS
DB6 INSYNC
AD
DB7 A,
VIR
GND Ao
PIN NAMES
~~-DBo DATA 8US IBIDlRECTlONAl) PLOISS
CLOCk INPUT ITTL) DATA WINDOW DATA WINDOW
!~~~CTT~E:ET/OPTIONAl OUTPUT
SELECT 1,0 UNSEPOATA UNSE'AAA TE 0 DA T A
FAUlTRSET/OPO fAul'T FAULT
RUU CHIPAESET WRDATA WRITE DATA
mIW'l . READY 1,0 ~ COUNT/OPTIONAllNPUT
~ OM" 4CkNOWLIEDGE mo THACkO
INTERNAL
""Q WAPAOTECT WAITEPAOTECT DATA BUS
Ii!5 iNDEX INDEX
iII1I WAITE ENABLE
SEEK/STEP SEEK/STEP
~~S:NC
DIRECTION
CPU INTERFACE
LOAD HEAD
~ lOWCUARENT
AFN-00223A
7100
8271/82716/82718
.----------
8271 BASIC FUNCTIONAL DESCRIPTION Pin Pin
Name No. 1/0 Description
General
A,-Ao (22-21) I These two lines are CPU Inter-
The 8271 Floppy Disk Controller (FOC) interfaces either
face Register select lines.
two single or one dual floppy drive to an eight bit
microprocessor and is fully compatible with Intel's DRQ (8) 0 The DMA request signal is used to
new high performance MCS-85 microcomputer system. request a transfer of data between
the 8271 and memory.
With minimum external circuitry, this innovative controller
supports most standard, commonly-available flexible disk (7) The DMA acknowledge signal
drives including the mini-floppy. notifies the 8271 that a DMA cycle
has been granted. For non-DMA
The 8271 FOC supports a comprehensive soft sectored transfers, this signal should be
format which is IBM 3740 compatible and includes driven in the manner of a "Chip
provision for the designating and handling of bad tracks. It Select".
is a high level controller that relieves the CPU (and used of
Select 1- (6) 0 These lines are used to specify the
many of the control tasks associated with implementing a
Select a (2) selected drive. These lines are set
floppy disk interface. The FOC supports a variety of high by the command byte.
level instructions which allow the user to store and retrieve
Fault Reset/ (1) 0 The optional fault reset output line
data on a floppy disk without dealing with the low level
OPO is used to reset an error condition
details of disk operation. which is latched by the drive. If
In addition to the standard read/write commands, a scan this line is not used for a fault
command is supported. The scan command allows the reset it can be used as an optional
user program to specify a data pattern and instructs the output line. This line is set with
FOC to search for that pattern on a track. Any application the write special register com-
mand.
that is required to search the disk for information (such as
point of sale price lookup, disk directory search, etc.), may Write Enable (35) O This signal enables the drive write
use the scan command to reduce the CPU overhead. Once logic.
the scan operation is initiated, no CPU intervention is Seek/Step (36) 0 This mUlti-function line is used dur-
required. ing drive seeks.
Direction (37) 0 The direction line specifies the
Hardware Description seek direction. A high level on
The 8271 is packaged in a 40 pin DIP. The following is a this pin steps the R/W head
functional description of each pin. toward the spindle (step-in), a
low level steps the head away
Pin Pin from the spindle (step-outl.
Name No. I/O Description
Load Head (38) 0 The load head line causes the
Vee (40) +5V supply drive to load the Read/Write head
GND (20) Ground against the diskette.
Clock (3) A square wave clock Low Current (39) 0 This line notifies the drive that track
43 or greater is selected.
Reset (4) A high signal on the reset input
forces the 8271 to an idle state. Ready 1, (5) These two lines indicate that the
The 8271 remains idle until a com- Ready a (32) specified drive is ready.
mand is issued by the CPU. The (28)
Fault This line is used by the drive to
output signals of the drive inter-
specify a file unsafe condition.
face are forced inactive (LOW).
Reset must be active for 10 or Count/OPI (30) If the optional seek/direction/
more clock cycles. count seek mode is selected, the
count pin receives pulses to step
(24) The 1/0 Read and 1/0 Write inputs the R/W head to the desired track.
are enabled by the chip select signal. Otherwise, this line can be used
DBrDBo (19-12) 1/0 The Data Bus lines are bidirection- as an optional input.
al, three-state lines (8080 data Write Protect (33) This signal specifies that the
bus compatible). diskette inserted is write pro-
(10) The Write signal is used to signal tected.
the control logic that a transfer of TRKO (31) This signal indicates when the RIW
data from the data bus to the 8271 head is positioned over track zero.
is required.
(9)
Index (34) The index signal gives an indication
The Read signal is used to signal
of the relative position of the diskette.
the control logic that a transfer of
data from the 8271 to the data bus PLO/SS (25) This pin is used to specify the type
is required. of data separator used. Phase-
INT (11) 0 The interrupt signal indicates that Locked Oscillator/Single Shot.
the 8271 requires service. Write Data (29) 0 Composite write data.
7-101 00223A
8271/82716/82718
Pin Pin Result Register

Name No. I/O Description
The Result Register is used to supply the outcome of FOC
command execution (such as a goodlbad completion) to
Unseparated (27) This input is the unsepar::lted data the CPU. The standard Result byte format is:
Data and clocks.
lilT L
Data Window (26) This is a data window established oI0 I I I I0 I
~,"'m""
by a single-shot or phase-locked
oscillator data separator.
INSYNC (23) 0 This line is high when 8271 has ::::~::::: ~~::
attained input data synchroni- DELETED DATA FOUND
zation, by detecting 2 bytes of L..-_ _ _ _ _ _ _ _ _ _ NOT USED = 00
zeros followed by an expected
Address Mark. It will stay high
until the end of the ID or data
field.
CPU Interface Description

This interface minimizes CPU involvement by supporting
a set of high level commands and both DMA and non-OMA
type data transfers and by providing hierarchical status
information regarding the result of command execution.
The CPU utilizes the control interface (see the Block

diagram) to specify the FOC commands and to determine
the result of an executed command. This interface is
supported by five Registers which are addressed by the
CPU via the A1, AQ, RO and WR signals. If an 8080 based
system is used, the RO and WR signals can be driven by
the 8228's IIOR and IIOW signals. The registers are
defined as follows:
Command Register Figure 1. 8271 Block Diagram Showing CPU

The CPU loads an appropriate command into the Interface Functions
Command Register which has the following format:
Status Register
Reflects the state of the FOC.
A, Ao 07 06 05 04 03 02 0, Do
I 0 I0 I I
I0 I0 I I I I I0 I0 I
ill ,"OO,"~ "m "o"'~

L..-_ _ _ _ _ COMMAND OPCODE
SURFACE/DRIVE
.
I 1 = INTERRUPT REQUEST
(SELECT o. 11
1 = RESULT REGISTER FULL
I = PARAMETER REGISTER FULL
L..--------'---1 = COMMAND REGISTER FULL

L -_ _ _ _ _ _ _ _ _~ 1 = COMMAND BUSY
Parameter Register
Accepts parameters of commands that require further
description; up to five parameters may be required, Reset Register
example: Allows the 8271 to be reset by the program. Reset must
be active for 11 or more chip clocks.
INT (Interrupt Line)

A, Ao 07 06 05 04 03 02 0, Do
I 0 11 I Another element of the control interface is the Interrupt
line (INT). This line is used to signal the CPU that an FOC
operation has been completed. It remains active until the
' - - - - - - - - EXPECTED PARAMETER result register is read.
7-102 00223A
8271/82716/82718
ABSOLUTE MAXIMUM RATINGS

Ambient Temperature Under Bias ........ 0 C to 70C 1 'COMMENT: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is a stress
Storage Temperature ............. - 65C to + 150C
Voltage on Any Pin with conditions above those indicated in the operational sections of this
Respect to Ground ................. - 0.5V to + 7V specification is not implied. Exposure to absolute maximum rating con
Power Dissipation .......................... 1 Watt ditions for extended periods may affect device reliability.
Vee= + 5.0V 5%
8721 and 8271-8: TA= OC to 70C; 8271-6: T A = OC to 50C

V IL Input Low Voltage -0.5 0.8 V
V IH Input High Voltage 2.0 (Vee + 0.5) V
YOLO Output Low Voltage (Data Bus) 0.45 V IOL=2.0 rnA
VOLI Output Low Voltage (Interface Pins) 0.5 V IOL = 1.6 rnA
VOH Output High Voltage 2.4 V IOH= -220 p.A
IlL Input Load Current 10 p.A V IN = Vee to OV
loz Off-State Output Current 10 p.A VOUT= Vee to OV
lee Vee Supply Current 180 rnA
CAPACITANCE
TA=25C, Vcc=GND=OV
CIN Input Capacitance 10 pF tc= 1 MHz
CliO I/O Capacitance 20 pF Unmeasured Pins Returned to GND
NOTE: 1. Ambient temperature under bias for 8271-6 is oe to 5oe.
7_1n~ nn??~A
8271/82716/82718
Vcc= + 5.0V 5%
8271 and 82718: TA = ooe to 7o oe; 82716: T A:: ooe to 50 0 e
Read Cycle
tAc Select Setup to RD 0 ns Note 2
tCA Select Hold from RD 0 ns Note 2
tAD Data Delay from Address 250 ns Note 2
tRO Data Delay from RD 150 ns C L = 150 pF, Note 2
C L = 20 pF for Minimum;
tOF Output Float Delay 20 100 ns
150 pF for Maximum
toc DACK Setup to RD 25 ns
tco DACK Hold from RD 25 ns
tKO Data Delay from DACK 250 ns
Write Cycle
tAC Select Setup to WR 0 ns
tCA Select Hold from WR 0 ns
tow Data Setup to WR 150 ns
two Data Hold from WR 0 ns
toc DACK Setup to WR 25 ns
tco DACK Hold from WR 25 ns
DMA
Symbol Parameter Test Conditions
tca Request Hold from WR or RD (for NonBurst Mode)
Other Timing
8271/82716 82718
Min. Max. Min. Max.
t RSTW Reset Pulse Width 10 10 tCY

tr Input Signal Rise Time 20 20 . ns
tf Input Signal Fall Time 20 20 ns
t RSTS Reset to First IOWR 2 2 tCY
tCY Clock Period 250 500 Note 3
tCl Clock Low Period 110 215 ns
tCH Clock High Period 125 250 ns
tos Data Window Setup to Unseparated Clock and Data 50 50 ns
tOH Data Window Hold from Unseparated Clock and Data 0 0 ns
NOTES:
1. All timing measurements are made at the reference voltages unless otherwise specified: Input "1" at 2.0V, "0" at O.BV
Output "1" at 2.0V, "0" at 0.8V
2. tAD, tRO, tAC, and tCA are not concurrent specs.
3. Standard Floppy: tCY = 250 ns 0.4% Mini-Floppy: tCY = 500 ns 0.4%
7104 00223A
8271/82716/82718
WAVEFORMS
Read Waveform,
OACK
=> -toc-
X
I---tco-------=I
) 1(
I
tRR . I-tcA-1
~ 1
~
-tAC-- tRO OF
I-t - } _______
DATA BUS --- ------------
. tAD
tKO
Write Waveforms
OACK
toc--" -tco-
-----:..- ..
~ i J(
I---tAC--' ,- tww -tCA-l
\... ,
DATA BUS )( )(
I tow tw~~
DMA Waveforms
__~I
r 'cc~
ORQ
\_--+-------------------------------
~ORWR ------------------~~ _______________________________________ _
CHIP CLOCK
7-105 OO223A
8271182716182718
WRITE DATA PW
r--F-I
PULSE WIDTH PW = tCY 30 ns *tCY = 250 ns 0.4% **tCY = 500 ns 0.4%
H (HALF BIT CELL) = 8 tCY 250 ns 30 ns 500 ns 30 ns
F (FULL BIT CELL) = 16 tCY 2.0 lAS 8 ns 4.0 lAS 16 ns
4.0 lAS 16 ns 8.0 lAS 32 ns
Figure 24. Write Data
READ DATA
*tCY = 250 ns **tCY = 500 ns
F = 16 tCY 8 tCY
H = 8 tCY 4 tCY
Figure 25. Read Data
*STANDARD FLEXIBLE DISK DRIVE TIMING

**MINIFLOPPY TIMING
7106 00223A
8271/82716/82718
UNSEPARATED
DATA
DATA
WINDOW
tDH~Ons-
Figure 26. SingleShot Data Separator
*DAfA
WINDOW
*DATA WINDOW MAY BE 180 0 OUT OF PHASE

IN PLO DATA SEPARATION MODE.
Figure 27. PLO Data Separator
7-107 00223A
8273, 8273-4, 8273-8
PROGRAMMABLE HOLC/SOLC PROTOCOL
CONTROLLER
CCITT X.25 Compatible Programmable N RZI Encode/ Decode
H OLC/SDLC Compatible Two User Programmable Modem
SOLC
Full Duplex, Half Duplex, or Loop
Operation
Control Ports
Recovery
Digital Phase Locked Loop Clock
Transfers
Up to 64K Baud Synchronous
Minimum CPU Overhead

Automatic
Checking
FCS (CRC) Generation and
8088/8086
Fully Compatible with 8048/8080/8085/
CPUs
Locked
Up to 9.6K Baud with OnBoard Phase
Loop Single +5V Supply
The Intel@ 8273 Programmable HOLC/SOLC Protocol Controller is a dedicated device designed to support the ISO/
CCITT's HOLC and IBM's SOLC communication line protocols. It is fully compatible with Intel's new high performance
microcomputer systems such as the MCS-88/86. A frame level command set is achieved by a unique microprogrammed
dual processor chip architecture. The processing capability supported by the 8273 relieves the system CPU of the low
level real-time tasks normally associated with controllers.

REGISTERS
FLAG DET Vee
T.INT RESULT COMMAND
T.INT PB. R.INT RESULT
CLK PB3 TEST MODE STATUS
RESET IJII2
RESUL T
T.DACK iiB,
T.DRQ RfS
R.DACK PAc
R.DRQ PAl
RD PA;
WR CD
DBO-7
R.INT rn T.D
DBO T.D T.C
DBl TiC
DB2 Axe
DB3 R.D
T.DRO
DB4 32.CLK DPLL
TxDACK
DB5 CS 32X CLK
RxDRO
DB6 DPLL RTS
RxDACK
DB7 AI ps, _,
GND Ao TxlNT CTS
RxlNT CO
AD PA 2 _,
ViR
Ao
A,
PIN NAMES RESET RxD
R;c
080-DB7 DATA BUS (8 BITS) CS CHIP SELECT
~ FLAG DETECT 32.CLK 32 TIMES CLOCK Cs
T.INT TRANSMITTER INTERRUPT R.D RECEIVER DATA CLK
FLAG DEl
CLK CLOCK INPUT R. C RECEIVER CLOCK
RESET RESET T. C TRANSMITTER CLOCK
~ TRANSMITTER DMA ACKNOWLEDGE T.D TRANSMITTER DATA
T.DRQ TRANSMITTER DMA REQUEST ill CLEAR TO SEND CPU INTERFACE MODEM INTERFACE
Rl5 READ INPUT ED CARRIER DETECT
iiII WRITE INPUT PA2-PAC GP INPUT PORTS
~-P84 ~~g~::~~6~~~~
R.DACK RECEIVER OMA ACKNOWLEDGE
R. DRQ RECEIVER OMA REQUEST
R. INT RECEIVER INTERRUPT Vee +5 VOLT SUPPL Y
AO-Al COMMAND REGISTER SELECT ADDRESS GND GROUND
l5nt DIGITAL PHASE LOCKED LOOP
7108
8273, 82734, 82738
A BRIEF DESCRIPTION OF HDLC/SDLC types of frames; an Information Frame is used to transfer

data, a Supervisory Frame is used for control purposes,
PROTOCOLS and a Non-sequenced Frame is used for initialization and
control of the secondary stations.
General
Frame Characteristics
The High Level Oata Link Control (HOLC) is a standard An important characteristic of a frame is that its con-
communication link protocol established by International tents are made code transparent by use of a zero bit
Standards Organization (ISOl. HOLC is the discipline
insertion and deletion technique. Thus, the user can adopt
used to implement ISO X.25 packet switching systems.
any format or code suitable for his system - it may even
The Synchronous Oata Link Control (SOLC) is an IBM be a computer word length or a "memory dump". The
communication link protocol used to implement the frame is bit oriented that is, bits, not characters in each
System Network Architecture (SNAl. Both the protocols field, have specific meanings. The Frame Check
are bit oriented, code independent, and ideal for full Sequence (FCS) is an error detection scheme similar to
duplex communication. Some common applications the Cyclic Redundancy Checkword (CRC) widely used in
include terminal to terminal, terminal to CPU, CPU to magnetic disk storage devices. The Command and
CPU, satellite communication, packet switching and other Response information frames contain sequence numbers
high speed data links. In systems which require expensive in the control fields identifying the sent and received
cabling and interconnect hardware, any of the two frames. The sequence numbers are used in Error
protocols could be used to simplify interfacing (by going Recovery Procedures (ERP) and as implicit acknowledge-
serial), thereby reducing interconnect hardware costs. ment of frame communication, enhancing the true full-
Since both the protocols are speed independent, reducing duplex nature of the HOLC/SOLC protocols.
interconnect hardware could become an important In contrast, BISYNC is basically half-duplex (two way
application.
alternate) because of necessity to transmit immediate
Network acknowledgement frames. HOLC/SOLC therefore saves
propagation delay times and have a potential of twice the
In both the HOLC and SOLC line protocols, according to a
throughput rate of BISYNC.
pre-assigned hierarchy, a PRIMARY (Control) STATION
controls the overall network (data link) and issues It is possible to use HOLC or SOLe over half duplex lines
commands to the SECONOARY (Slave) STATIONS. The but there is a corresponding loss in throughput because
latter comply with instructions and respond by sending both are primarily designed for full-duplex communi-
appropriate RESPONSES. Whenever a transmitting cation. As in any synchronous system, the bit rate is
station must end transmission prematurely it sends an determined by the clock bits supplied by the modem,
ABORT character. Upon detecting an abort character, a protocols themselves are speed independent.
receiving station ignores the transmission block called a A byproduct of the use of zero-bit insertion-deletion
FRAME. Time fill between frames can be accomplished by technique is the non-return-to-zero invert (NRZI) data
transmitting either continuous frame preambles called transmission/reception compatibility. The latter allows
FLAGS or an abort character. A time fill within a frame is HOLC/SOLC protocols to be used with asynchronous
not permitted. Whenever a station receives a string of data communication hardware in which the clocks are
more that fifteen consecutive ones, the station goes into derived from the NRZI encoded data.
an IDLE state.
References
Frames IBM Synchronous Data Link Control General Information, IBM, GA27-
A single communication element is called a FRAME which 3093-1.
can be used for both Link Control and data transfer Standard Network Access Protocol Specification, DATAPAC, Trans-
Canada Telephone System CCG111
purposes. The elements of a frame are the beginning eight Recommendation X.25, ISO/CCITT March 2, 1976.
bit FLAG (F) consisting of one zero, six ones, and a zero, IBM 3650 Retail Store System Loop Interface OEM Information, IBM, GA
an eight bit AOORESS FIELO (A), an eight bit CONTROL 27-3098-0
FIELO (C), a variable (N-bit) INFORMATION FIELO (I), a Guidebook to Data Communications, Training Manual, Hewlett-Packard
5955-1715
sixteen bit FRAME CHECK SEQUENCE (FCS), and an
IBM Introduction to Teleprocessing, IBM, GC 20-8095-02
eight bit end FLAG (F), having the same bit pattern as the System Network Architecture, Technical Overview, IBM, GA 27-3102
beginning flag. In HOLC the Address (A) and Control (C) System Network Architecture Format and ProtocOl, IBM GP. 27-3112
bytes are extendable. The HOLC and the SOLC use three
OPENING ADDRESS CONTROL INFORMATION FRAME CHECK CLOSING

FLAG (F) FIELD (A) FIELD (C) FIELD (I) SE~UENCE (FCS) FLAG (F)
VARIABLE LEN.GTH
01111110 8 BITS 8 BITS (ONL Y IN I FRAMES) 16 BITS 0' , , , '10
Figure 1. Frame Format
7-109
8273, 82734, 82738
FUNCTIONAL DESCRIPTION TxDRQ (6) a Requests a transfer of data be-

General tween memory and the 8273 for a
transmit operation
The Intel 8273 HDlC/SDlC controller IS a microcom-
puter peripheral device which supports the International RxRDQ (8) a Requests a transfer of data be-
Standards Organization (ISO) High level Data Link tween the 8273 and memory for a
Control (HDlC), and IBM Synchronous Data Link Control receive operation.
(SDlC) communications protocols. This controller
minimizes CPU software by supporting a comprehensive TxDACK (5) The Transmitter DMA acknow-
frame-level instruction set and by hardware implemen- ledge Signal notifies the 8273 that
tation of the low level tasks associated with frame the TxDMA cycle has been
assembly/disassembly and data integrity. The 8273 can be granted.
used in either synchronous or asynchronous applications. RxDACK (7) The Receiver DMA acknowledge
I n asynchronous applications the data can be program- signal notifies the 8273 that the
med to be encoded/decoded in NRZI code. The clock is RxDMA cycle has been granted.
derived from the NRZI data using a digital phase locked
loop. Th'e data transparency is achieved by using a zero- Al-Aa (22-21) These two lines are CPU Inter-
bit insertion/deletion technique. The frames are automati- face Register Select lines.
cally checked for errors during reception by verifying the TxD (29) a This line transmits the serial data
Frame Check Sequence (FCS); the FCS is automatically to the communication channel.
generated and appended before the final flag in transmit.
The 8273 recognizes and can generate flags (01111110), TxC (28) The transmitter clock is used to
Abort, Idle, and GA (EOP) characters. synchronize the transmit data.
The 8273 can assume either a primary (control) or a RxD (26) This line receives serial data from
secondary (slave) role. It can therefore be readily the communication channel.
implemented in an SDlC loop configuration as typified by
RxC (27) The Receiver Clock is used to
the IBM 3650 Retail Store System by programming the
8273 into a one-bit delay mode. In such a configuration, a synchronize the receive data.
two wire pair can be effectively used for data transfer 32X ClK (25) The 32X clock is used to provide
between controllers and loop stations. The digital phase clock .recovery when an asyn-
locked loop output pin can be used by the loop station chronous modem is used. In loop
without the presence of an accurate Tx clock. configuration the loop station
Hardware Description can run without an accurate 1X
The 8273 is packaged in a 40 pin DIP. The following is a clock by using the 32X ClK in
functional description of each pin. conjunction with the DPll out-
put. (This pin must be grounded
Pin Name (No.) I/O Description
when not used).
Vee (40) +5V Supply
GND (20) Ground
DPll (23) a Digital Phase locked loop out-
put can be tied to RxC and/or
RESET (4) A high signal on this pin will force
TxC when 1 X clock is not avail-
the 8273 to an idle state. The 8273
able. DPll is used with 32X ClK.
will remain idle until a command
is issued by the CPU. The modem FLAG DET (1) a Flag Detect signals that a flag
interface output signals are forc- (01111110) has been received by
ed high. Reset must be true for a an active receiver.
minimum of 10 TCY. RTS (35) a Request to Send signals that the
CS (24) The RD and WR inputs are en- 8273 is ready to transmit data.
abled by the chip select input.
DBl-DBa (19-12) I/O The Data Bus lines are bidirec- CTS (30l Clear to Send signals that the
tional three-state lines which in- modem is ready to accept data
terface with the system Data Bus. from the 8273.
WR (10) The Write signal is used to con- CD (31) Carrier Detect signals that the
trol the transfer of either a com- line transmission has started and
mand or data from CPU to the the 8273 may begin to sample
8273. data on RxD line.
RD (9) The Read signal is used to con-
PA2-4 (32-34) General purpose input ports. The
trol the transfer of either a data
logic levels on these lines can be
byte or a status word from the
Read by the CPU through the
8273 to the CPU.
Data Bus Buffer.
TxlNT (2) a The Transmitter interrupt signal
indicates that the transmitter PBl-4 (36-39) a General purpose output ports.
logic requires service. The CPU can write these output
RxlNT (11) a The Receiver interrupt signal in- lines through Data Bus Buffer.
dicates that the Receiver logic re-
ClK (3) A square wave TTL clock.
quires service.
7-110
8273, 82734, 82738
AmbientTemperatureUnderBias ........ OCt070C device. This is a stress rating only and functional
Storage Temperature ............... -65 C to +150C operation of the device at these or any other conditions
above those indicated in the operational sections of this
Voltage on Any Pin With
specification is not implied. Exposure to absolute
RespecttoGround ..................... -O.5Vto+7V
maximum rating conditions for extended periods may
Power Dissipation ......... . . . . . . . . . . . . . . . . .. 1 Watt affect device reliability.
D.C. CHARACTERISTICS (8273, 82734, 82738)

TA=OC to 70C, Vce= +5.0V5%

V il Input Low Voltage -0.5 0.8 V
V IH Input High Voltage 2.0 Vcc+ 0.5 V
10l = 2.0 mA for Data Bus Pins
VOL Output Low Voltage 0.45 V 10l = 1.0 mA for Output Port Pins
10l = 1.6 mA for All Other Pins
10H = - 200 /-IA for Data Bus Pins
VOH Output High Voltage 2.4 V
10H = -100/-IA for All Other Pins
III Input Load Current 10 /-I A VIN = Vcc to OV
loz OffState Output Current 10 /-I A Vour= Vcc to OV
Icc Vcc Supply Current 180 mA
CAPACITANCE (8273,82734,82738)
TA=25C, Vcc=GND=OV

C IN Input Capacitance 10 pF tc= 1 MHz
Unmeasured Pins
ClIO I/O Capacitance 20 pF
Returned to GND
TA=OC to 70C, Vcc= +5.0V5%
Clock Timing (8273)

tCY Clock 250 ns
64K Baud Max
tCl Clock Low 120 ns
Operating Rate
tCH Clock High 120 ns
Clock Timing (82734)

tCY Clock 286 ns
56K Baud Max
Operating Rate
Clock Timing (82738)

tCY Clock 330 ns
48K Baud Max
Operating Rate
7111
8273, 82734, 82738
A.C. CHARACTERISTICS (8273,8273-4,8273-8) TA=OC to 70C, VCC= +5.0V5%

Read Cycle
Symbol
I I I r lalli' I M'lin. Max. I Iunh
I '&I .65, "onuhions
tAC Select Setup to RD 0 ns Note 3
tCA Select Hold from RD 0 ns Note 3
tAD Data Delay from Address 300 ns Note 3
tRD Data Delay from RD 200 ns Cl = 150pF, Note 3
tOF Output Float Delay 20 100 ns
=
C l 20 pF for Minimum;
150pF for Maximum
toc DACK Setup to RD 25 ns
tCD DACK Hold from RD 25 ns
tKD Data Delay from DACK 300 ns
Write Cycle

tAC Select Setup to WR 0 ns
tCA Select Hold from WR 0 ns
tow Data Setup to WR 150 ns
tWD Data Hold from WR 0 ns
toc DACK Setup to WR 25 ns
tCD DACK Hold from WR 25 ns
DMA

Request Hold from WR or RD
tca 200 ns
(for Non-Burst Mode)
Other Timing

tRSTW Reset Pulse Width 10 tCY
tr Input Signal Rise Time 20 ns
tf Inr.>ut Signal Fall Time 20 ns
tRSTS Reset to First IOWR 2 tCY
tCY32 32X Clock Cycle Time 9.7' tCY ns
tCl32 32X Clock Low Time 4' tCY ns
tCH32 32X Clock High Time 4' tCY ns
tOPll DPLL Output Low 1 . tCY- 50 ns
tOCl Data Clock,Low 1 . tCY- 50 ns
tOCH Data Clock High 2 tCY ns
toCY Data Clock' 62.5' tCY ns
tTD Transmit Data Delay 200 ns
tos Data Setup Time 200 ns
tOH Data Hold Time 100 ns
t FlO FLAG DET Output Low 8 tCY 50 ns
NOTES:
1. All timing measurements are made at the reference voltages unless otherwise specified: Input "1" at 2.0V, "0" at 0.8V;
Output "1" at 2.0V, "0" at 0.8V.
2. tAD, tRO, tAC, and tCA are not concurrent specs.
7112
8273, 8273-4, 8273-8
WAVEFORMS
Read Waveforms
I
DACK
--
~
i---'oc
).
~~ICO
)(
1<.
~I
'RR _1~ICA--.:J
~
I---IDF-~
~
_IAC-- IRD
_______
DATA BUS -- - ~---------

lAD
I KO
Write Waveforms
DACK ~ I I 0
:;;::;;
AO' A,. csi
~ ](
~IAC---~- IWW I--ICA~
DATA BUS )( ](
I IDW two---J
DMA Waveforms
--II
r ICO~
DRQ __
\~----~-------------------------------
R5 OR WR --{L--_ _ __
t tCY =l
CHIP CLOCK
L."~.'" ----1--------J1
~ tCY32 =:1
32X CLOCK 1
CtCL32=--:CtCH32J-----J
7-113 00743A
8273,8273-4, 8273-8
Transmit Data Waveforms
,r
-'~
j
~~--------------~ ~~-----------------
- - - - - IDCl ---~----I 1---
k - - - - - - - - - - - - IDCY -------
TxD \J~
____________~---'A~~----------------------------------J
Receive Data Waveforms
DPLL Output Waveform
Flag Detect Output Waveform
7-114 00743A
8275
PROGRAMMABLE CRT CONTROLLER
Programmable
Format
Screen and Character Compatible
Fully MCSSO and MCSSS
6 Independent Visual Field Attributes Dual Row Buffers

11 Visual Character Attributes
(Graphic Capability) Programmable DMA Burst Mode
Cursor Control (4 Types) Single + SV Supply
Light Pen Detection and Registers 40Pln Package
The Intell!> 8275 Programmable CRT Controller is a single chip device to interface CRT raster scan displays with
Intell!> microcomputer systems. Its primary function is to refresh the display by buffering the information from main
memory and keeping track of the display position of the screen. The flexibility designed into the 8275 will allow simple
interface to almost any raster scan CRT display with a minimum of external hardware and software overhead.
LC3 vcc
LC2 LAO
LC, LA,
CCLK
LCO LTEN
ORO RVV
DACK VSP
HRTC GPA,
VRTC GPAO
RD HLGT 0110-7 CCO_6
WR IRa
LPEN CCLK
DBo CC6
DB, CC5
DB2 CC4
DB3 CC3 ORO _ - - - - - - , LCO_3
DB4 CC2 OACK
DB5 CC, IRa
DB6 CCo
DB7 cs
GND AO
LAo-l
HRTC
VRTC
HLGT
RVV
PIN NAMES LTEN
VSP
GPAO_l
~;-i- Bl-DIRECTIDNAL DATA BUS LCO-3 LINE COUNTER OUTPUTS
DRO DMA REOUEST OUTPUT LAo-l LINE ATTRIBUTE OUTPUTS
lim DMA ACKNOWLEDGE INPUT HRTC HORIZONTAL RETRACE OUTPUT LPEN
i-liia-- INTERRUPT REOUEST OUTPUT VRTC VERTICAL RETRACE OUTPUT
1m READ STROBE INPUT HLGT HIGHLIGHT OUTPUT
WI! WRITE STROBE INPUT RVV REVERSE VIDEO OUTPUT
1-1-=-csAo---+-c-CR=_HE=Glpl=STSE=ELRE=-=CAT=DID=NRPU=ESST=INP:::cU=-T_---tt_-H -:C-=-vspLT~E=N=~~LIG~H~T~EN~AB~L~EO~U~TP~UT~=======:::i
VIDEO SUPPRESS OUTPUT
CCLK CHARACTER CLOCK INPUT GPAo-l GENERAL PURPOSE ATTRIBUTE OUTPUTS
,-,-CC",-O_-'06-,-_C,-H_AR_A,,-,-CT-,-ER-,CO-,-DC-'E-,,-OU,,-,-T-,PU,--,TS= _LP_EN___ LIGHT PEN INPU'-T_ _ _ _ _--'
7-115 00224A
8275
PIN DESCRIPTIONS
Pin :# Pin Name 1/0 Pin Description Pln:# Pin Name 1/0 Pin Description
1 LC3 0 Line count. Output from the line count- 40 VCC +5V power supply
2 LC2 er which is used to address the character
3 generator for the line positions on the
39 LAO o Line attribute codes. These attribute
LCl 38 codes have to be decoded externally by
LAl
4 LCo screen.
the dot/timing logic to generate the
5 DRQ 0 DMA request. Output signal to the 8257 horizontal and vertical line combinations
DMA controller requesting a DMA cycle. for the graphic displays specified by the
DMA acknowledge. Input signal from character attribute codes.
6 DACK
the 8257 DMA controller acknowledging 37 LTEN o Light enable. Output signal used to
that the requested DMA cycle has been enable the video signal to the CRT. This
granted. output is active at the programmed
7 HRTC Horizontal retrace. Output signal which underline cursor position, and at posi-
0
tions specified by attribute codes.
is active during the programmed hori-
zontal retrace interval. During this peri- 36 RVV o Reverse video. Output signal used to
od the VSP output is high and the indicate the CRT circuitry to reverse the
L TEN output is low. video signal. This output is active at the
8 VRTC o Vertical retrace. Output signal which is cursor position if a revel~e video block
active during the programmed vertical cursor is programmed or at the positions
retrace interval. During this period the specified by the field attribute codes.
VSP output is high and the L TEN out- 35 VSP o Video suppression. Output signal, ed to
put is low. blank the video signal to the CRT. This
9 RD Read input. A control signal to read output is active:
registers. during the horizontal and vertical re-
10 WR Write input. A control signal to write trace intervals.
commands into the control registers or at the top and bottom lines of rows if
write data into the row buffers during a underline is programmed to be number
DMA cycle. 8 or greater.
11 LPEN Light pen. Input signal from the CRT when an end of row or end of screen
system signifying that a light pen signal code is detected.
has been detected. When a DMA underrun occurs.
12 DBO I/O Bi-directional three-state data bus lines. at regular intervals (1/16 frame fre-
13 DBl The outputs are enabled during a read of quency for cursor, 1/32 frame fre-
14 DB2 the C or P ports. quency for character and field attri-
15 DB3 butes) - to create blinking displays
16 DB4 as specified by cursor, character attri-
17 DB5 bute, or field attribute programming.
18 DB6 34 GPAl o General purpose attribute codes. Out-
19 DB7 33 GPAo puts which are enabled by the general
20 Ground Ground purpose field attribute codes.
32 HLGT o Highlight. Output signal used to intensi-
fy the display at particular positions on
the screen as specified by the character
attribute codes or field attribute codes.
31 IRQ o Interrupt request.
30 CCLK I Character clock (from dotltiming logic).
29 CC6 o Character codes. Output from the row
28 CC5 buffers used for character selection in
27 CC4 the character generator.
26 CC3
25 CC2
24 CCl
23 CCo
22 CS Chip select. The read and write are en-
abled by CS.
21 AO Port address. A high input on AO selects
the "c" port or command registers and a
low input selects the "P" port or param-
eter registers.
7-116 00224A
8275
Data Bus Buffer CCLK
This 3-state, bidirectional, 8-bit buffer is used to interface

the 8275 to the system Data Bus.
This functional block accepts inputs from the System Con-

trol Bus and generates control signals for overall device
CCO_6
operation. It contains the Command, Parameter, and Status
Registers that store the various control formats for the
device functional definition.
AO OPERATION REGISTER
ORO
LCO_3
0 Read PREG OACK
PREG IRa
0 Write
1 Read SREG
AD
1 Write CREG
LAo-l
HRTC
VRTC
HLGT
RVV
LTEN
RD (Read) VSP
cs GPAO_l
A "Iow" on this input informs the 8275 that the CPU is
reading data or status information from the 8275.
LPEN
WR (Write)
A "Iow" on this input informs the 8275 that the CPU is
writing data or control words to the 8275. Figure 1. 8275 Block Diagram Showing Data Bus Buffer
.and ReadlWrlte Functions
CS (Chip Select)
A "Iow" on this input selects the 8275. No reading or writ-
ing will occur unless the device is selected. When CS is high, Ao RD WR CS
the Data Bus in the float state and RD and WR will have no
0 0 1 0 Write 8275 Parameter
effect on the chip.
0 1 0 0 Read 8275 Parameter
DRQ (DMA Request) 1 0 1 0 Write 8275 Command
1 0 0 Read 8275 Status
A "high" on this output informs the DMA Controller that
X 0 Three-State
the 8275 desires a DMA transfer.
X X X Three-state
DACK (DMA Acknowledge)
A "Iow" on this input informs the 8275 that a DMA cycle
is in progress.
IRQ (Interrupt Request)

A "high" on this output informs the CPU that the 8275
desires interrupt service.
7-117 00224A
8275
Character Counter
CCLK
The Character Counter is a programmable counter that is
used to determine the number of characters to be displayed
per row and the length of the horizontal retrace interval. It
is driven by the CCLK (Character Clock) input, which
should be a derivative of the external dot clock.
CCO_6
Line Counter
The Line Counter is a programmable counter that is used to
determine the number of horizontal lines (Sweeps) per
character row. Its outputs are used to address the external DRQ _ _ _- - ,
character generator ROM. LCO-3
DACK
IRQ
Row Counter
The Row Counter is a programmable counter that is used to
determine the number of character rows to be displayed per LAO_l
frame and length of the vertical retrace interval. HRTC
VRTC
HLGT
RVV
LTEN
Light Pen Registers VSP
GPAO_l
The Light Pen Registers are two registers that store the con-
tents of the character counter and the row counter when- LPEN
ever there is a rising edge on the LPEN (Light Pen) input.
Note: Software correction is required.
Figure 2. 8275 Block Diagram Showing Counter and
Raster Timing and Video Controls Register Functions
The Raster Timing circuitry controls the timing of the
FIFOs
HRTC (Horizontal Retrace) and VRTC (Vertical Retrace)
outputs. The Video Control circuitry controls the genera- There are two 16 character FIFOs in the 8275. They are
tion of LAo_1 (Line Attribute), HGL T (Highlight), RVV used to provide extra row buffer length in the Transparent
(Reverse Video), LTEN (Light Enable), VSP (Video Sup- Attribute Mode (see Detailed Operation section).
press), and GPAO-1 (General Purpose Attribute) outputs.
Buffer Input/Output Controllers
Row Buffers The Buffer Input/Output Controllers decode the characters
The Row Buffers are two 80 character buffers. They are being placed in the row buffers. If the character is a charac-
filled from the microcomputer system memory with the ter attribute, field attribute or special code, these con-
character codes to be displayed. While one row buffer is trollers control the appropriate action. (Examples; An
displaying a row of characters, the other is being filled with "End of Screen-Stop DMA" special code will cause the
the next row of characters. Buffer Input Controller to stop further DMA requests. A
"Highlight" field attribute will cause the Buffer Output
Controller to activate the HG i.. T output.)
7-118 00224A
8275
SYSTEM OPERATION
The 8275 is programmable to a large number of different It is designed to interface with the 8257 DMA Controller
display formats. It provides raster timing, display row buf- and standard character generator ROMs for dot matrix
fering, visual attribute decoding, cursor timing, and light decoding. Dot level timing must be provided by external
pen detection. circuitry.
MEMORIES
U (
< SYSTEM BUS
DBO-7
MEMR AO
lOW DBO-7
MEMW WR
lOR lID
CS CS
HRQ IRQ
HACK
DRQ LCO-3
8257 VIDEO SIGNAL
DMA CHARACTER
CONTROLLER DACK GENERATOR
HORIZONTAL SYNC
8275 CCO-6 DOT
CRT
TIMING VERTICAL SYNC
CONTROLLER
CCLK AND
INTERFACE
INTENSITY
VIDEO CONTROLS
Figure 3. 8275 Systems Block Diagram Showing Systems Operation
7-119 00224A
8275
General Systems Operational Description The number of lines per character row, the underline posi-
tion, and blanking of top and bottom lines are program-
The 8275 provides a "window" into the microcomputer mable. (See Programrriing Section.)
system memory.
The 8275 provides special Control Codes which can be used
to minimize DMA or software overhead. It also provides
Display characters are retrieved from memory and dis-
, played on a row by row basis. The 8275 has two row buf- Visual Attribute Codes to cause special action or symbols
fers. While one row buffer is being used for display, the on the screen without the use of the character generator
other is being filled with the next row of characters to be (see Visual Attributes Section).
displayed. The number of display characters per row and The 8275 also controls raster timing. This is done by gen-
the number of character rows per frame are software pro- erating Horizontal Retrace (H RTC) and Vertical Retrace
grammable, providing easy interface to most CRT displays. (VRTC) signals. The timing of these signals is program-
(See Programming Section.) mable.
The 8275 can generate a cursor. Cursor location and format
The 8275 requests DMA to fill the row buffer that is not
are programmable. (See Programming Section.)
being used for display. DMA burst length and spacing is
programmable. (See Programming Section.) The 8275 has a light pen input and registers. The light pen
input is used to load the registers. Light pen registers can be
The 8275 displays character rows one line at a time. read on command. (See Programming Section.)
1st 2nd 3rd 4th 5th 6th 7t'l
---------------------
Character Character Character Character Character Character
00000.0000.00 000000000 0000 000.000.0

First Line of a Character Row
Character
1st 2nd 3rd 4th 5th 6th 7th
---------------------
00 000.0000.00 000000000 0000 000.000.0

0.0000.00 000.00.0000000000000.000.00.000.00.000.0
Second Line of a Character Row
Character
1st 2nd 3rd 4th 5th 6th 7th
-------------------..--
00000.0000.00 000000000 0000 000.000.0

0.0000.00 000.00.0000000000000.000.00.000.00.000.0
0.0000.00.0000.00.0000000000000.000.00.000.00.000.0
Character
Third Line of a Character Row
1st
Character
~..---"--"-..
2nd
Character
3rd
Character
4th
Character
5th
Character
6th
...---
Character
00 000.0000.00 000000000 0000 000.000.0

0.0000.00 000.00.0000000000000.000.00.000.00.000.0
0.0000.00.0.00.00.0000000000000.000.00.000.00.000.0
0.0000.00.0000.00 0000000000 000.000.00.0.0.0
7th
Character
0.0000.00.00.0.00.0000000000000.0.0000.000.00.0.0.0
o.oooo.oo.ooo co.ooooooooooooo.oo.ooo.ooo.oo.o.o.o
00000.0000.00 000000000.0 O. 0000 000 O. O. 0 0
Seventh Line of a Character Row
Figure 4. Display of a Character Row
7-120 00224A
8275
Display Row Buffering After all the lines of the character row are scanned, the
Before the start of a frame, the 8275 requests DMA and roles of the two row buffers are reversed and the same
one row buffer is filted with characters. procedure is followed for the next row.
CCLK
CCLK
DBO_7 CCO_6
DATA
DBO_7 _"-E3t"~'-+E>fw CCO-6
BUFFER
LCO_3
ORO
LCO_3
DACK
IRO
LAO_l R5
HRTC LAO_l
VRTC
HLGT HRTC
RVV VRTC
AO-- HLGT
LTEN
vsp RVV
LTEN
GPAO_l vsp
cs GPAO_l
LPEN
LPEN
Figure 5. First Row Buffer Filled

Figure 7. First Buffer Filled with Third Row,
When the first horizontal sweep is started, character codes
Second Row Displayed
are output to the character generator from the row buffer
just filled. Simultaneously, DMA begins filling the other
row buffer with the next row of characters. This is repeated until all of the character rows are dis-
played.
CCLK
DBO_7 CCO_6
LCO_3
READ/
WRITE/
LAO_l
WR-
CO~~~OL d HRTC
LOGIC VRTC
AO-- HLGT
RVV
LTEN
vsp
GPAO_l
LPEN
Figure 6. Second Buffer Filled, First Row Displayed
7-121 00224A
8275
Display Format Row Format

The 8275 is designed to hold the line count stable while
outputting the appropriate character codes during each
horizontal sweep. The line count is incremented during
Screen Format
horizontal retrace and the whole row of character codes are
The 8275 can be programmed to generate from 1 to 80 output again during the next sweep. This is continued until
characters per row, and from 1 to 64 rows per frame. the whole character row is displayed.
The number of lines (horizontal sweeps) per character row
is programmable from 1 to 16.
The output of the line counter can be programmed to be in
one of two modes.
123456789 . . . . . . . . . . . . . . 80 In mode 0, the output of the line counter is the same as the
2 line number.
3 In mode 1, the line counter is offset by one from the line
4
number.
5
6 Note: In mode 1, while the first line (line number 0) is being dis-
7 played, the last count is output by the line counter (see
8 examples).
9
Line Line
Line Counter Counter
Number Mode 0 Mode 1
64
0 0 0 0 0 0 0 0 0 0 0000 1111
\. 1 0 0 0 0
0 0 0 0 0001 0000
2 0 0 0
0 0
0 0 0 0010 0001
3 0 0
0 0
0 0 001 1 0010
Figure 8. Screen Format 4 0
0
0 0 0 0 0 0100 0011
5 0
0
0 0 0 0 0 0101 0100
6 0
0 01 10 0101
7 0
0
0 0 0 0 0 0111 0110
8 0
0
0 0 0 0 0 1000 01 1 1
The 8275 can also be programmed to blank alternate rows.

9
10
0
0

0
0
0
0
0
0
0
0
0
0
0 0
0
0
1001
1010
1000
1001
In this mode, the first row is displayed, the second blanked, 11 0 0 0 0 0 0 0 0 0 1011 1010
12 0 0 0 0 0 0 0 0 0 1100 101 1
the third displayed, etc. DMA is not requested for the
13 0 0 0 0 0 0 0 0 0 1 101 1 100
blanked rows.
14 0 0 0 0 0 0 0 0 0 1110 1 101
15 0 0 0 0 0 0 0 0 0 1111 1110
Figure 10. Example of a 16Llne Format
Line Line
123456789 . . . . . . . . . . . . . . . 80 Number Mode 0 Mode 1
2 0 0 0 0 0 D. 0 0 0000 1001
3 1 0 0 0
0 0 0 0001 0000
2 0 0
0 0 0 0010 0001
4 3 0
0
0 0 0 001 1 0010
5 4 0
0
0 0 0 0100 0011
5 0
0 0101 0100
6 0
0
0 0 0 0110 0101
7
8
0
0

0
0
0
0
0
0
0 0
0
0
0111
1000
01 10
01 1 1
9 0 0 0 0 0 0 0 1001 1000
64
Figure 11. Example of a 10Llne Format
Figure 9. Blank Alternate Rows Mode Mode 0 is useful for character generators that leave address
zero blank and start at address 1. Mode 1 is useful for char-
acter generators which start at address zero.
7-122 00224A
8275
Underline placement is also programmable (from line num- Dot Format

ber 0 to 15). This is independent of the line counter mode.
Dot width and character width are dependent upon the
If the line number of the underline is greater than 7 (line external timing and control circuitry.
number MSB = 1). then the top and bottom lines will be
blanked. Dot level timing circuitry should be designed to accept the
parallel output of the character generator and shift it out
serially at the rate required by the CRT display.
Line Line
a 0 0 0 0 0 [J 0 0 0 0000 1011
1 0 0 0 0
0 0 0 0 0001 0000
2 0 0 0
0
0 0 0 0010 0001
3 0 0
0 0 0
0 0 0011 0010
4 0
0 0 0 0 o 0 0100 00 11
5 0
0 0 0 0 0 0 a1a1 0100 LC
6 0
0 a 11 a 0101
7 0
.0 0 0 0 0 0 0111 0110 8275
8 0
0 0 0 0 0 0 1000 011 1 cc
9 0
0 0 0 0 0 0 100 1 1000
10
11

0 0 0 0 0 0 0 0 0
1010
1011
10 01
1010
VIDEO
vSP
Top and Bottom
Lines are Blanked Figure 14. Typical Dot Level Block Diagram
Figure 12. Underline In Line Number 10
If the line number of the underline is less than or equal to 7 Dot width is a function of dot clock frequency.
(line number MSB = 0). then the top and bottom lines will
Character width is a function of the character generator
not be blanked. width.
Horizontal character spacing is a function of the shift
register length.
Note: Video control and timing signals must be synchronized with
the video signal due to the character generator access delay.
Line Line
0 0 0 0
0 0 0 0000 0111
1 0 0
0
0 0 0001 0000
2 0
0 0 0 0 0010 0001
3 0
0 0 0 0 0011 0010
4 0
0 0100 00 11
5 0
0 0 0 0 a 10 1 0100
6 0
0 0 0 0 0110 a1a1
7 0111 0110
Top and Bottom

Lines are not Blanked
Figure 13. Underline In Line Number 7
If the line number of the underline is greater than the maxi-

mum number of lines, the underline will not appear.
Blanking is accomplished by the VSP (Video Suppression)
signal. Underline is accomplished by the LTEN (Light
Enable) signal.
7-123 00224A
8275
Raster Timing The row counter is an internal counter driven by the line
The character counter is driven by the character clock input counter. It controls the functions of the row buffers and
(CCLKI. !t counts out the characters being displayed counts the number of character rows displayed.
(programmable from 1 to 80). It then causes the line
counter to increment, and it 'starts counting out the hori- r
.
ONE CHARACTER ROW
\
zontal retrace interval (programmable from 2 to 32). This
is constantly repeated. HRTC ----U--UU-U-
CCLK
INTERNAL
ROW COUNTER
'''~''"~
PROGRAMMXBLE 1 TO 16
LINE COUNTS
HRTC Figure 16. Row Timing
PROGRAMMABLE 1 TO 80 CCLKS
After the row counter counts all of the rows in a frame
______________________ J NEXT
LC0-3 PRESENT LINE COUNT LINE COUNT (programmable from 1 to 64), it starts counting out the
vertical retrace interval (programmable from 1 to 4).
Figure 15. Line Timing ONE FRAME

4
"OW'~:;::''':i Jcx::><::x::x:2(:x:X:::x=
FIRST LAST FIRST LAST
The line counter is driven by the character counter. It is DISPLAY
ROW
DISPLAY
ROW
RETRACE RETRACE
ROW ROW
used to generate the line address outputs (LC _ ) for the
o
character generator. After it counts all of the lines in a
character row (programmable from 1 to 16), it increments
the row counter, and starts over again. (See Character For
PROGRAMMABLE
PROGRAMMABLE
mat Section for detailed description of Line Counter 1 TO 64 ROW COUNTS 1 TO 4 ROW COUNTS
functions.)
Figure 17. Frame Timing
The Video Suppression Output (VSP) is active during

horizontal and vertical retrace intervals.
Dot level timing circuitry must synchronize these outputs
with the video signal to the CRT Display.
7-124 00224A
8275
DMATlming Interrupt Timing
The 8275 can be programmed to request burst DMA trans- The 8275 can be programmed to generate an interrupt
fers of 1 to 8 characters. The interval between bursts is also request at the end of each frame. This can be used to
programmable (from 0 to 55 character clock periods 1). reinitialize the DMA controller. If the 8275 interrupt
This allows the user to tailor his DMA overhead to fit his enable flag is set, an interrupt request will occur at the
system needs. beginning of the last display row.
The first DMA request of the frame occurs one row time
before the end of vertical retrace. DMA requests continue
as programmed, until the row buffer is filled. If the row
buffer is filled in the middle of a burst, the 8275 terminates
the burst and resets the burst counter. No more DMA INTERNAL~
ROW
COUNTER
requests will occur until the beginning of the next row. L I
DISPLAY RETRACE
At that time, DMA requests are activated as programmed ROW ROW
until the other buffer is filled.
The first DMA request for a row will start at the first char-
VRTC ~'r---e--..1
acter clock of the preceding row. If the burst mode is used,
the first DMA request may occur a number of character
IRQ
clocks later. This number is equal to the programmed burst
space.
Figure 19. Beginning of Interrupt Request
If, for any reason, there is a DMA underrun, a flag in the
status word will be set.
I RQ will go inactive after the status register is read.
INTERNAL
ROW
COUNTER
"Q }
BUR~/
RD~~}-
_----J
-..----
~ffi
;~
~
ct
g
.. NEXT
ROW BUFFER
FILLED
""'a: ~:Ro~
:~ <~ ....
g~ gC~
---
a:: 0 a:
~~ Q
0..
Figure 20. End of Interrupt Request
ONE
ROW BUFFER
FILLED
Figure 18. DMA Timing
A reset command will also cause IRQ to go inactive, but

this is not recommended during normal service.
Another method of reinitializing the DMA controller is to
have the DMA controller itself interrupt on terminal count.
With this method, the 8275 interrupt enable flag should not
be set.
Note: Upon power-up, the 8275 Interrupt Enable Flag may be set.
The DMA controller is typically initialized for the next As a result, the user's cold start routine should write a reset
frame at the end of the current frame. command to the 8275 before system interrupts are enabled.
7-125 00224A
8275
VISUAL ATTRIBUTES AND SPECIAL Character Attribute Code.

CODES Character attribute codes are codes that can be used to gen-
eiate Qiaphics symbols without the USe of a character
generator. This is accomplished by selectively activating the
Line Attribute outputs (LAo-11. the Video Suppression
output (VSP), and the Light Enable output. The dot level
The characters processed by the 8275 are 8-bit quantities.
timing circuitry can use these signals to generate the proper
The character code outputs provide the character generator
svmbols.
with 7 bits of address. The Most Significant Bit is the extra
bit and it is used to determine if it is a normal display Character attributes can be programmed to blink or be
character (MSB = 0), or if it is a Visual Attribute or Special highlighted individually. Blinking is accomplished with the
Code (MSB = 1). Video Suppression output (VSP). Blink frequency is equal
There are two types of Visual Attribute Codes. They are to the screen refresh frequency divided by 32. Highlighting
Character Attributes and Field Attributes. is accomplished by activating the Highlight output (HGLT).
Character Attributes
MSB LSB
11CCCCBH
IL HIGHLIGHT
I
L _____
BLINK
CHARACTER ATTRIBUTE CODE
OO~------------~~ __~________~
O,~--------+---r-~ __~________~
02~--------+---r-~__~--------~
CHARACTER
GENERATOR
~?,~ OJ~--------+---~~__~==~==~~r=J
SHIFT
REGISTER
05.1----------+---r\-__~--+_____I--__I
8275
06~---------+---.,----).___+_--_+_--_+_-_I......JI
HORIZ. LEFT HALF
LA,
VIDEO
LAO
VSP
LTEN
HGLT t---------------- HIGHLIGHT
Figure 21. Typical Character Attribute Logic
7-126 00224A
8275
Character attributes were designed to produce the following graphics:
DESCRIPTION
0000 Top Left Corner
0001 Top Right Corner
0010 Bottom Left Corner
0011 Bottom Right Corner
0100 Top Intersect
0101 Right Intersect
0110 Left Intersect
0111 Bottom Intersect
1000 Horizontal Line
1001 Vertical Line
1010 Crossed Lines
1011 Not Recommended *
1100 Special Codes
1101 Illegal
1110 Illegal
1111 Illegal
*Character Attribute Code 1011 is not recommended for Character Attribute Codes 1101, 1110, and 1111 are illegal.
normal operation. Since none of the attribute outputs are
active, the character Generator will not be disabled, and Blinking is active when B = 1.
an indeterminate character will be generated. Highlight is active when H = 1.
7-127 00224A
8275
Specla. Code. character following the code up to, and including, the
Four special codes are available to help reduce memory, character which precedes the next field attribute code, or
software, or DMA overhead. up to the end of the frame. The field attributes are reset
during the vertical retrace interval.
Specla. Control Character
There are six field attributes:
MSB LSB
1 1 1 1 o 0 S S 1. Blink - Characters following the code are caused
~SPECIAL CONTROL CODE to blink by activating the Video Suppression out-

put (VSP). The blink frequency is equal to the
screen refresh frequency divided by 32.
S S FUNCTION
2. Highlight - Characters following the code are
o 0 End of Row caused to be highlighted by activating the High-
o End of Row-Stop DMA light output (HG LT).
o End of Screen
3. Reverse Video - Characters following the code are
End of Screen-Stop DMA
caused to appear with reverse video by activating
the Reverse Video output (RVV).
The End of Row Code (00) activates VSP and holds it to 4. Underline - Characters following the code are
the end of the line. caused to be underlined by activating the Light
The End of Row-Stop DMA Code (01) causes the DMA Enable output (L TEN).
Control Logic to stop DMA for the rest of the row when it 5,6. General Purpose - There are two additional 8275
is written into the Row Buffer. It affects the display in the outputs which act as general purpose, independ-
same way as the End of Row Code (00). ently programmable field attributes. GPAO-t are
The End of Screen Code (10) activates VSP and holds it to active high outputs.
the end of the frame.
The End of Screen-Stop DMA Code (11) causes the DMA Field Attribute Code
Control Logic to stop DMA for the rest of the frame when
MSB LSB
it is written into the Row Buffer. It affects the display in
1 0 U R G G B H
the same way as the End of Screen Code (10).
If the Stop DMA feature is not used, all characters after an T. . _'__
L
__- ~~~~~IGHT
End of Row character are ignored, except for the End of
Screen character, which operates normally. All characters
II -
L..-_ _ _ _ _ _ _
GENERAL PURPOSE
REVERSE VIDEO
UNDERLINE
after an End of Screen character are ignored.
H = 1 FOR HIGHLIGHTING
B = 1 FOR BLINKING
Note: If a Stop DMA character is not the last character in a burst or R = t FOR REVERSE VIDEO
row, DMA is not stopped until after the next character is U = t FOR UNDERLINE
read. In this situation, a dummy character must be placed in GG = GPA1, GPAo
memory after the Stop DMA character.
Field Attribute. *More than one attribute can be enabled at the same time.
The field attributes are control codes which affect the If the blinking and reverse video attributes are enabled
visual characteristics for a field of characters, starting at the simultaneously, only the reversed characters will blink.
7-128 00224A
8275
The 8275 can be programmed to provide visible or invisible Each row buffer has a correspond ing FIFO. These F IFOs
field attribute characters. are 16 characters by 7 bits in size.
If the 8275 is programmed in the visible field attribute When a field attribute is placed in the row buffer during
mode, all field attributes will occupy a position on the DMA, the buffer input controller recognizes it and places
screen. They will appear as blanks caused by activation of the next character in the proper FIFO.
the Video Suppression output (VSP). The chosen visual
When a field attribute is placed in the Buffer Output Con-
attributes are activated after this blanked character. troller during display, it causes the controller to immedi-
ately put a character from the FIFO on the Character Code
outputs (CCO-6). The chosen Visual Attributes are also
activated.
ABC 0 E F G H I J K L M Since the FIFO is 16 characters long, no more than 16 field

NOPORSTUV attribute characters may be used per line in this mode.
If more are used, a bit in the status word is set and the first
characters in the FIFO are written over and lost.
Note: Since the FIFO is 7 bits wide, the MSB of any characters put
in it are stripped off. Therefore, a Visual Attribute or Special
Code must not immediately follow a field attribute code. If
this situation does occur, the Visual Attribute or Special
1 2 3 4 5 6 7 8 9 Code wili be treated as a normal display character.
,'---------------------------------~
Figure 22. Example of the Visible Field Attribute Mode

(Underline Attribute)
If the 8275 is programmed in the invisible field attribute

mode, the 8275 FIFO is activated.
ABC 0 E F G H I J K L M
NOPORSTUV
1 234 5 6 7 8 9
I
Figure 24. Example of the Invisible Field Attribute
Mode (Underline Attribute)
Field and Character Attribute Interaction

Character Attribute Symbols are affected by the Reverse
Video (RVV) and General Purpose (GPAO-1) field attri-
butes. They are not affected by Underline, Blink or High-
light field attributes; however, these characteristics can be
programmed individually for Character Attribute Symbols.
Figure 23. Block Diagram Showing FIFO Activation
7129 00224A
8275
Cursor Timing Device Programming

The cursor location is determined by a cursor row register The 8275 has two programming registers, the Command
and a charactP.r position register which are loaded by com- Register (CREG) and the Paiametei Register (PREG). It
mand to the controller. The cursor can be programmed to also has a Status Register (SREG). The Command Register
appear on the display as: can only be written into and the Status Registers can only
1. a blinking underline be read from. They are addressed as follows:
2. a blinking reverse video block
AO OPERATION REGISTER
3. a non-blinking underline
4. a non-blinking reverse video block 0 Read PREG
The cursor blinking frequency is equal to the screen refresh 0 Write PREG
frequency divided by 16. 1 Read SREG
If a non-blinking reverse video cursor appears in a non- 1 Write CREG
blinking reverse video field, the cursor will appear as a
normal video block. The 8275 expects to receive a command and a sequence
If a non-blinking underline cursor appears in a non-blinking of 0 to 4 parameters, depending on the command. If the
underline field, the cursor will not be visible. proper number of parameter bytes are not received before
another command is given, a status flag is set, indicating an
Light Pen Detection improper command.
A light pen consists of a micro switch and a tiny light Instruction Set
sensor. When the light pen is pressed against the CRT screen, The 8275 instruction set consists of 8 commands.
the micro switch enables the light sensor. When the raster
sweep reaches the light sensor, it triggers the light pen COMMAND NO. OF PARAMETER BYTES
output. Reset 4
If the output of the light pen is presented to the 8275 Start Display o
LPEN input, the row and character position coordinates are Stop Display o
stored in a pair of registers. These registers can be read on Read Light Pen 2
command. A bit in the status word is set, indicating that Load Cursor 2
the light pen signal was detected. The LPEN input must be Enable Interrupt o
a 0 to 1 transition for proper operation. Disable Interrupt o
Preset Counters o
Note: Due to internal and external delays, the character position
coordinate will be off by at least three character positions. In addition, the status of the 8275 (SREG) can be read by
This has to be corrected in software. the CPU at any time.
7-130 00224A
8275
1. Reset Command: Parameter - UUUU Underline Placement

DATA BUS LINE NUMBER OF
OPERATION AO DESCRIPTION MSB lSB U U U U UNDERLINE
Command Write 1 Reset Command 0 0 0 0 0 0 0 0 0 0 0 0 1
Screen Comp 0 0 0 1 2
Write 0 S H H H H H H H
Byte 1
0 0 0 3
Screen Comp
Write 0 V V R R R R R R
Byte 2
Parameters
Screen Comp
Write 0 U U U U l l l l
Byte 3
1 1 16
Screen Comp
Write 0 M F C C Z Z Z Z
Byte 4
Action - After the reset command is written, DMA re-
quests stop, 8275 interrupts are disabled, and the VSP Parameter - LLLL Number of Lines per Character Row
output is used to blank the screen. HRTC and VRTC con-
L L L L NO. OF LINES/ROW
tinue to run. HRTC and VRTC timing are random on
power-up. 000 0 1
000 2
As parameters are written, the screen composition is
000 3
defined.
Parameter - S Spaced Rows

1 1 1 16
S FUNCTIONS
o Normal Rows
Spaced Rows
Parameter - M Line Counter Mode
M LINE COUNTER MODE
Parameter - HHHHHHH Horizontal Characters/Row o Mode 0 (Non-Offset)
NO. OF CHARACTERS Mode 1 (Offset by 1 Count)
H H H H H H H PER ROW
0 0 0 0 0 0 0
0 0 0 0 0 0 2
0 0 0 0 0 0 3 Parameter - F Field Attribute Mode
F FIELD ATTRIBUTE MODE
o Transparent
Non-Transparent
0 0 1 80
0 0 0 0 0 Undefined
Parameter - CC Cursor Format

C C CURSOR FORMAT
1 1 1 1 1 1 Undefined
o 0 Blinking reverse video block
o 1 Blinking underline
Parameter - VV Vertical Retrace Row Count o Nonblinking reverse video block

Nonblinking underling
V V NO. OF ROW COUNTS PER VRTC
o 0 1
o 1 2
o 3 Parameter - ZZZZ Horizontal Retrace Count
4 NO. OF CHARACTER
Z Z Z Z COUNTS PER HRTC
0 0 0 0 2
Parameter - RRRRRR Vertical Rows/Frame 0 0 0 1 4
R R R R R R NO. OF ROWS/FRAME 0 0 0 6
0 0 0 0 0 0 1
0 0 0 0 0 1 2
0 0 0 0 0 3
1 1 1 32
1 1 1 1 1 1 64 Note: uuuu MSB determines blanking of top and bottom lines

(1 = blanked, 0 = not blanked!'
7-131 00224A
8275
2. Start Display Command: 5. Load Cursor Position:
I
OPERATION AO I I DESCRIPTION I MSB
DATA BUS
LSB
I IOPERAT!ON I AO I DESCRIPTION I MSB
DATA BUS
Command o 0 1 S S S B B Command Write 1 Load Cursor 10000000
Parameters
Write o Char. Number (Char. Position in Row)
Write o Row Number (Row Numbed
SSS BURST SPACE CODE Action - The 8275 is conditioned to place the next two
NQ OF CHARACTER CLOCKS
parameter bytes into the cursor position registers. Status
S S S BETWEEN DMA REQUESTS flags not affected.
0 0 0 0
0 0 1 7
0 0 15
0 1 1 23
6. Enable Interrupt Command:
0 0 31
DATA BUS
0 1 39 IOPERATION AO DESCRIPTION MSB LSB
0 47
55 Command J Write 1 Enable Interrupt 1 0 1 0 0 0 0 0
No parameters
BB BURST COUNT CODE
NO. OF DMA CYCLES PER Action - The interrupt enable status flag is set and inter-
B B BURST rupts are enabled.
0 0
0 1 2
0 4
8
7. Disable Interrupt Command:
Action - 8275 interrupts are enabled, DMA requests begin,
video is enabled, Interrupt Enable and Video Enable status
flags are set.
I OPERATION AO DESCRIPTION MSB
DATA BUS
LSB
Command I Write 1 Disable Interrupt 1 1 0 0 0 0 0 0
3. Stop Display Command: No parameters

-
DATA BUS
IOPERATION AO DESCRIPTION MSB LSB
Action - Interrupts are disabled and the interrupt enable
Commandl Write 1 Stop Display 0 1 000 0 0 0 status flag is reset.
No parameters
Action - Disables video, interrupts remain enabled, HRTC
and VRTC continue to run, Video Enable status flag is
reset, and the "Start Display" command must be given to
re-enable the display. 8. Preset Counters Command:
DATA BUS
4. Read Light Pen Command jOPERATION AO DESCRIPTION MSB LSB
OPERATION AO DESCRIPTION MSB

DATA BUS
LSB
Command I Write 1 Preset Counters 1 1 1 0 0 0 0 0
Command Write 1 Read Light Pen 0 1 1 0 0 0 0 0 No parameters

Read 0 Char. Number (Char. Position in Row)
Parameters
Read 0 Row Number (Row Number) Action - The internal timing counters are preset, corre-
sponding to a screen display position at the top left corner.
Action - The 8275 is conditioned to supply the contents
Two character clocks are required for this operation. The
of the light pen position registers in the next two read
counters will remain in this state until any other command
cycles of the parameter register. Status flags are not af-
fected. is given.
This command is useful for system debug and synchroniza-
Nota: Software correction of light pen position is required. tion of clustered CRT displays on a single CPU.
7132 00224A
8275
Status Flags
IC - (Improper Command) This flag is set when a
DATA BUS
MSB LSB
command parameter string is too long or too
short. The flag is automatically reset after a
Command OlE IR LP ICVE au FO status read.
IE - (lntp.rrupt Enable) Set or reset by command. It VE - (Video Enable) This flag indicates that video
enables vertical retrace interrupt. It is auto- operation of the CRT is enabled. This flag is
matically set by a "Start Display" command set on a "Start Display" command, and reset
and reset with the "Reset" command. on a "Stop Display" or "Reset" command.
IR - (Interrupt Request) This flag is set at the begin- DU - (DMA Underrun) This flag is set whenever a
ning of display of the last row of the frame if data underrun occurs during DMA transfers.
the interrupt enable flag is set. It is reset after Upon detection of DU, the DMA operation is
a status read operation. stopped and the screen is blanked until after
LP - This flag is set when the light pen input (LPEN) the vertical retrace interval. This flag is reset
is activated and the light pen registers have been after a status read.
loaded. This flag is automatically reset after a FO - (FIFO Overrun) This flag is set whenever the
status read. FIFO is overrun. It is reset on a status read.
00224A
7-133
8275

Ambient Temperature Under Bias ......... OOC to 70C
Storage Temperature . . . . . . . . . . . . . . -65C to +150C COMMENT: Stresses above those listed under "Absolute Maxi-
Voltage On Any Pin mum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
With Respect to Ground ............ -0.5V to +7V any other conditions above those indicated in the operational sec-
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 1 Watt tions of this specification is not implied.
T A = OC to 70C; Vee = 5V 5%

VIH Input High Voltage 2.0 Vee+ 0. 5V V
VOH Output High Voltage 2.4 V IOH= -400~A
IlL Input Load Current 10 ~A VIN = Vee to OV
IOFL Output Float Leakage 10 ~A VOUT = Vee to OV
CAPACITANCE
T A = 25C; Vee = GND = OV

CIN Input Capacitance 10 pF fc= 1 MHz
CliO I/O Capacitance 20 pF Unmeasured pins returned to Vss.
7-134 00224A
8275
Other Timing:
tcc Character Code Output Delay 150 ns CL = 50 pF
tHA Horizontal Retrace Output Delay 200 ns CL = 50 pF
tLC Line Count Output Delay 400 ns CL = 50 pF
tAT Control/Attribute Output Delay 275 ns CL = 50 pF
tVA Vertical Retrace Output Delay 275 ns CL = 50 pF
tAl IRO~ from ROt 250 ns CL = 50 pF
twa DROt from WRt 250 ns CL = 50 pF
tAQ DRO~ from WR~ 200 ns CL = 50 pF
tLA DACK~ to WR~ 0 ns
tAL WRt to DACKt 0 ns
tpA LPEN Rise 50 ns
tpH LPEN Hold 100 ns
Note: Timing measurements are made at the following reference voltages: Output "1" = 2.0V, "0" = O.BV.
Input "1 "=2.4V , "0"=0.45V
WAVEFORMS
EXT OOTCLK
CCLK' l . .______. .
CCo-s FIRST CHARACTER CODE SECOND CHARACTER CODE
CHARACTER - - - - - - - - " " ' "

GENERATOR.
r------------'"""'"\ ,----------
FIRST CHARACTER SECOND CHARACTER
OUTPUT _ _ _ _ _ _ _ _J .... _ _ _ _ _ _ _ _ _ _ _ _.....J ......._ _ _ _ _ _ _ __
ATTRIBUTES
& CONTROLS
VIDEO
(FROM SHIFT
REGISTER)
FIRST CHARACTE,R SECOND CHARACTER

ATTRIBUTES
& CONTROLS ATTRIBUTES & CONTROLS
(FROM ATTRIBUTES & CONTROLS FOR FIRST CHAR.
FOR 2ND CHAR.
SYNCHRONIZER)
'CCLK IS A MULTIPLE OF THE DOT CLOCK AND AN INPUT TO THE 8215.
Figure 25. Typical Dot Level Timing
7-135 00224A
8275
~ n
r r
CCLK
I I '
CCO-6
HRTC
~l-tLC
LCO-3 -+-____P_RE_S_EN_T_L_IN_E_C_O_U_N_T_ _---I, 'r---------------.....~ NEXT LINE COUNT
VIDEO
CONTROLS
AND ATTRIBUTES'
'LAO_l' VSP, LTEN, HGLT, RVV, GPAO-l
Figure 26. Line Timing
CCLK
HRTC
LCO_3
f+----PROGRAMMABLE FROM 1 TO 16 LlNES----.\
INTERNAL - - - ' " ' " ' \ Jr-----------.. . . \------"'"

ROW _ _ _ _ _
COUNTER I'-_ _ _PRESENT
_ _ _ROW____ ~ ,.._ _ _ _ _.1
Figure 27. Row Timing
CCLK
~
INTERNAL AST
ROW RETRACE
COUNTER ROW
VRTC
Figure 28. Frame Timing
7-136 00224A
8275
\
CCLK
CCO_& LAST RETRACE

CHARACTER
IX FIRST RETRACE
CHARACTER
-----+' '-----
LCO_3 FIRST LINE COUNT
HRTC
IRQ
INTERNAL
-: ------LAS-~-T-D-IS+-PL-A-f-'-OW-~t-I-R--~-_-_-_-_-_-
Figure 29. Interrupt Timing
CCLK
-JtKQt----..
DRQJ \\,._ __
LPEN _ _
j ..}"'---_
Figure 30. DMA Timing
7-137 00224A
8275
T A = OC to 70C; VCC = 5.0V 5%; GND = OV

Read Cycle:
tAR Address Stable Before READ 0 ns
tRA Address Hold Time for READ 0 ns
tRO Data Delay from READ 200 ns CL=150pF
tOF READ to Data Floating 20 100 ns
Write Cycle:
tAW Address Stable Before WR ITE 0 ns

tWA Address Hold Time for WR ITE 0 ns
tww WR ITE Pulse Width 250 ns
tow Data Setup Time for WR ITE 150 ns
two Data Hold Time for WR ITE 0 ns
Clock Timing:
tCLK Clock Period 480 ns

tKH Clock High 240 ns
tKL Clock Low 160 ns
tKR Clock Rise 5 30 ns
tKF Clock Fall 5 30 ns
Note 1: AC timings measured at VOH = 2.0, VOL = 0.8 V =2.4, V1L=0.45
1H
Write Timing Read Timing
INVALID Ao.CS -Jt__ V_ALID_ _
---=:rtAR
RD
INVALID
Clock Timing Input Waveforms (For A.C. Tests)
CCLK
2.4
0.45
=:x:::> TEST POINTS :x==
<:.
7-138 00224A
inter
8279/82795
PROGRAMMABLE KEYBOARD/DISPLAY INTERFACE
MCS85 Compatible 82795 Dual 8 or 16Numerical Display
Simultaneous Keyboard Display
Single 16Character Display
Operations
Scanned Keyboard Mode Right or Left Entry 16Byte Display
RAM
Scanned Sensor Mode
Strobed Input Entry Mode Mode Programmable from CPU
8Character Keyboard FI FO
Programmable Scan Timing
2Key Lockout or NKey Rollover with
Contact Debounce Interrupt Output on Key Entry
The Intel@ 8279 is a general purpose programmable keyboard and display I/O interface deyice designed for use with
Intel@ microprocessors. The keyboard portion can provide a scanned interface to a 64-contact key matrix. The
keyboard portion will also interface to an array of sensors or a strobed interface keyboard, such as the hall effect and
ferrite variety. Key depressions can be 2-key lockout or N-key rollover. Keyboard entries are debounced and strobed in
an 8-character FIFO. If more than 8 characters are entered, overrun status is set. Key entries set the interrupt output
line to the CPU.
The display portion provides a scanned display interface for LED, incandescent, and other popular display
technologies. Both numeric and alphanumeric segment displays may be used as well as simple indicators. The 8279
has 16X8 display RAM which can be organized into dual 16X4. The RAM can be loaded or interrogated by the CPU. Both
right entry, calculator and left entry typewriter display formats are possible. Both read and write of the display RAM
can be done with auto-increment of the display RAM address.
PIN CONFIGURATION LOGIC SYMBOL
PIN NAMES
IRQ
DATA
BUS
SHIFT 1---- - KEY DATA
RD
CNTL'STB
WR
CPU
OUT B, INTERFACE
OUTB2 - CS
SLO_3 SCAN
OUT B3
OUT Ao AO
OUT A,
l-
I OUT AO-3
qUT A2
RESET
OUT A3
BD DISPLAY
cs CLK OUT B()'3 DATA
Vss
7_1~Q
8279/82795
HARDWARE DESCRIPTION SHIFT The shift input status is stored
The 8279 is packaged in a 40 pin DIP. The following is along with the key position on
a functional description of each pin. key closure in the Scanned
No. Of No. Of
Pins Designation Function Pins Designation Function
8 DBo-DB7 Bi-directional data bus. All data Keyboard modes. It has an ac-
and commands between the
tive internal pullup to keep it
CPU and the 8279 are trans-
high until a switch closure pulls
mitted on these lines.
it low.
ClK Clock from system used to gen-
erate internal timing. CNTLlSTB For keyboard modes this line is
RESET A high signal on this pin resets used as a control input and
the 8279. After being reset the stored like status on a key clo-
8279 is placed in the following sure. The line is also the strobe
mode: line that enters the data into the
1) 16 8-bit character display FIFO in the Strobed Input mode.
-left entry.
(Rising Edge). It has an active
2) Encoded scan keyboard-2
internal pullup to keep it high
key lockout.
until a switch closure pulls it
Along with this the program
low.
clock prescaler is set to 31.
Chip Select. A low on this pin 4 OUT Ao-OUT A3 These two ports are the outputs
enables the interface functions 4 OUT Bo-OUT B3 for the 16 x 4 display refresh
to receive or transmit. registers. The data from these
Ao Buffer Address. A high on this outputs is synchronized to the
line indicates the signals in or scan lines (Slo-Sl3) for multi-
out are interpreted as a com- plexed digit displays. The two 4
mand or status. A low indicates bit ports may be blanked inde-
that they are data. pendently. These two ports may
2 I nput/Output read and write. also be considered as one 8 bit
These signals enable the data port.
buffers to either send data to BD Blank Display. This output is
the external bus or receive it used to blank the display during
from the external bus. digit switching or by a display
IRO Interrupt Request. In a keyboard blanking command.
mode, the interrupt line is high
when there is data in the FIFO/
Sensor RAM. The interrupt line
PRINCIPLES OF OPERATION
goes low with each FIFO/
The following is a description of the major elements of the
Sensor RAM read and returns
8279 Programmable Keyboard/Display interface device.
high if there is still informa-
Refer to the block diagram in Figure 1.
tion in the RAM. In a sensor
mode, the interrupt line goes 110 Control and Data Buffers
high whenever a change in a
The I/O control section uses the CS, Ao, RD and WR lines
sensor is detected. to control data flow to and from the various internal
2 Vss , Vee Ground and power supply pins. registers and buffers. All data flow to and from the 8279 is
enabled by CS. The character of the information, given or
4 Slo-Sl3 Scan Lines which are used to
desired by the CPU, is identified by Ao. A logic one
scan the key switch or sensor means the information is a command or status. A logic
matrix and the display digits. zero means the information is data. RD and WR determine
These lines can be either en- the direction of data flow through the Data Buffers. The
coded (1 of 16) or decoded (1 of Data Buffers are bi-directional buffers that connect the
4). internal bus to the external bus. When the chip is not
selected (CS = 1), the devices are in a high impedance
8 Rlo-Rl7 Return line inputs which are
state. The drivers input during WR-CS and output during
connected to the scan lines
RD -CS.
through the keys or sensor
switches. They have active in- Control and Timing Registers and Timing Control
ternal pull ups to keep them These registers store the keyboard and display modes and
high until a switch closure pulls other operating conditions programmed by the CPU. The
one low. They also serve as an modes are programmed by presenting the proper
8-bit input in the Strobed Input command on the data lines with Ao = 1 and then sending
mode. a WR. The command is latched on the rising edge of WR.
AFN-00742A-02
7-140
8279/82795
Since data input and display are an integral part of many Scanned Sensor Matrix - with encoded (8 x a matrix
microprocessor designs. the system designer needs an switches) or decoded (4x8 matrix switches) scan lines.
interface that can control these functions without placing Key status (open orclosed) stored in RAM addressable
a large load on the CPU. The 8279 provides this function by CPU.
for a-bit microprocessors. Strobed Input -- Data on return lines during control
The 8279 has two sections: keyboard and display. The line strobe is transferred to FIFO.
keyboard section can interface to regular typewriter style
keyboards or random toggle or thumb switches. The
display section drives alphanumeric displays or a bank of Output Modes
indicator lights. Thus the CPU is relieved from scanning 8 or 16 character multiplexed displays that can be or-
the keyboard or refreshing the display. = =
ganized as dual 4-bit or single 8-bit (80 Do, A3 0 7 ).
The 8279 is designed to directly connect to the Right entry or left entry display formats.
microprocessor bus. The CPU can program all operating
modes for the 8279. These modes include: Other features of the 8279 include:
Mode programming from the CPU.
Input Modes Clock Prescaler
Scanned Keyboard - with encoded (8 x 8 key Interrupt output to signal CPU when there is keyboard
keyboard) or decoded (4 x 8 key keyboard) scan lines. or sensor data available.
A key depression generates a 6-bit encoding of key
An 8 byte FIFO to store keyboard information.
position. Position and shift and control status are
stored in the FIFO. Keys are automatically debounced 16 byte internal Display RAM tor display refresh. This
with 2-key lockout or N-key rollover. RAM can also be read by the CPU.
CLK RESET DBO-7 AD WR CS IRQ
DISPLAY
ADDRESS KEYBOARD
16 x 8 DEBOUNCE
REGISTERS DISPLAY AND
RAM CONTROL
TIMING
AND
CONTROL
OUT Ao.3 OUT B0-3 SL03
7-141 AFN-00742A-03
8279/82795
The command is then decoded and the appropriate SOFTWARE OPERATION

function is set. The timing control contains the basic
timing counter chain. The first counter is a + N prescaler 8279 commands
that can be piOgiammed to yield an intemal fiequency
of 100 kHz which gives a 5.1 ms keyboard scan time and The following commands program the 8279 operati!!S
modes. The commands are sent on the Data Bus with CS
a 10.3 ms debounce time. The other counters divide
low and Ao high and are loaded to the 8279 on the rising
down the basic internal frequency to provide the proper
edge of WR.
key scan, row scan, keyboard matrix scan, and display
scan times. Keyboard/Display Mode Set
MSB LSB
Scan Counter
Code: 1010101010lKIKIKI
The scan counter has two modes. In the encoded mode.
the counter provides a binary count that must be
externally decoded to provide the scan lines for the
Where DD is the Display Mode and KKK is the Keyboard
keyboard and display. In the decoded mode. the scan
counter decodes the least significant 2 bits and provides a Mode.
decoded 1 of 4 scan. Note than when the keyboard is in
decoded scan, so is the display. This means that only the
DO
first 4 characters in the Display RAM are displayed. o 0 8 8-bit character display - Left entry
In the encoded mode, the scan lines are active high o 16 8-bit character display - Left entry'
outputs. In the decoded mode, the scan lines are active
low outputs.
o 8 8-bit character display - Right entry
16 8-bit character display - Right entry
Return Buffers and Keyboard Debounce
For description of right and left entry, see Interface
and Control Considerations. Note that when decoded scan is set in
The 8 return lines are buffered and latched by the Return
Buffers. In the keyboard mode, these lines are scanned. keyboard mode, the display is reduced to 4 characters
looking for key closures in that row. If the debounce independent of display mode set.
circuit detects a closed switch, it waits about 10 msec to
check if the switch remains closed. If it does, the address KKK
of the switch in the matrix plus the status of SHIFT and 0 0 0 Encoded Scan Keyboard - 2 Key Lockout*
CONTROL are transferred to the FIFO. In the scanned
Sensor Matrix modes, the contents of the return lines is 0 0 Decoded Scan Keyboard - 2-Key Lockout
directly transferred to the corresponding row of the 0 0 Encoded Scan Keyboard - N-Key Rollover
Sensor RAM (FIFO) each key scan time. In Strobed Input
mode, the contents of the return lines are transferred to 0 1 Decoded Scan Keyboard - N-Key Rollover
the FIFO on the rising edge of the CNTL/STB line pulse. 0 0 Encoded Scan Sensor Matrix
FIFO/Sensor RAM and Status 0 Decoded Scan Sensor Matrix

This block is a dual function 8 x 8 RAM. In Keyboard or 0 Strobed Input, Encoded Display Scan
Strobed Input modes, it is a FIFO. Each new entry is Strobed Input, Decoded Display Scan
written into successive RAM positions and each is then
read in order of entry. FIFO status keeps track of the Program Clock
number of characters in the FIFO and whether it is full or
empty. Too many reads or writes will be recognized as an
error. The status can be read by an RD with CS low and
Code: 1.0 I 0 111 pip 1 pip 1P I
Ao high. The status logic also provides an IRQ signal
All timing and multiplexing Signals for the 8279 are
when the FIFO is not empty. In Scanned Sensor Matrix
mode, the memory is a Sensor RAM. Each row of the generated by an internal prescaler. This prescaler
Sensor RAM is loaded with the status of the correspond- divides the external clock (pin 3) by a programmable
ing row of sensor in the sensor matrix. In this mode, IRQ is integer. Bits PPPPP determine the value of this integer
high if a change in a sensor is detected. which ranges from 2 to 31. Choosing a divisor that YJe.l.9s
100 kHz will give the specified scan and debounce
Display Address Registers and Display RAM times. For instance, if Pin 3 of the 8279 is being clocked
The Display Address Registers hold the address of the by a 2 MHz Signal, PPPPP should be set to 10100 to
word currently being written or read by the CPU and the divide the clock by 20 to yield the proper 100 kHz operat-
two 4-bit nibbles being displayed. The read/write ing frequency.
addresses are programmed by CPU command. They also
can be set to auto increment after each read or write. The Read FIFO/Sensor RAM
Display RAM can be directly read by the CPU after the
correct mode and address is set. The addresses for the A
and B nibbles are automatically updated by the 8279 to Code: I 0 11 1 0 1 AI 1 X 1 A I TAl
A X = Don't Care
match data entry by the CPU. The A and B nibbles can be
entered independently or as one word, according to the The CPU sets up the 8279 for a read of the FIFO/Sensor
mode that is set by the CPU. Data entry to the display can RAM by first writing this command. In the Scan Key-
be set to either left or right entry. See Interface
Considerations for details. 'Default after reset.
7-142 AFN-00742A-04
8279/82795
board Mode, the Auto-Increment flag (AI) and the RAM Clear
address bits (AAA) are irrelevant. The 8279 will automati-
cally drive the data bus for each subsequent read (AD =0) The <;,bits are available in this command to clear all rows
in the same sequence in which the data first entered the of the Display RAM to a selectable blanking code as fol-
r
FIFO. All subsequent reads will be from the FIFO until lows:
another command is issued.
In the Sensor Matrix Mode, the RAM address bits AAA

select one of the 8 rows of the Sensor RAM. If the AI flag
Ie: r~ r All Z"o, (X Don', ea,,)
is set (AI = 1), each successive read will be from the sub- 1 0 AB = Hex 20 (0010 ooom
sequent row of the sensor RAM.
1 1 All Ones
Enable clear display when = 1 (or by CA = 1)
Read Display RAM
During the time the Display RAM is being cleared (""160 I-Is),
Code: I 0 11 11 1 AliA 1 A 1 A 1 A 1 it may not be written to. The most significant bit of the
FIFO status word is set during this time. When the Dis-
The CPU sets up the 8279 for a read of the Display RAM play RAM becomes available again, it automatically
by first writing this command. The address bits AAAA resets.
select one of the 16 rows of the Display RAM. If the AI
flag is set (AI = 1), this row address will be incremented If the C F bit is asserted (C F = 1), the FIFO status is
after each following read or write to the Display RAM. cleared and the interrupt output line is reset. Also, the
Since the same counter is used for both reading and Sensor RAM pointer is set to row O.
writing, this command sets the next read or write
address and the sense of the Auto-Increment mode for C A , the Clear All bit, has the combined effect of CD and
both operations. C F ; it uses the CD clearing code on the Display RAM and
also clears FIFO status. Furthermore, it resynchronizes
the internal timing chain.
Write Display RAM
End Interrupt/Error Mode Set
Code: 11 1 0 1 0 1 AliA 1 A 1 A 1 A 1
The CPU sets up the 8279 for a write to the Display RAM
Code: 11 11 11 IE IX Ix Ix Ix 1 X = Don't care.
by first writing this command. After writing the com-
= =
mand with AD 1, all subsequent writes with AD 0 wi II For the sensor matrix modes this command lowers the
be to the Display RAM. The addressing and Auto- IRQ line and enables further writing into RAM. (The IRQ
Increment functions are identical to those for the Read line would have been raised upon the detection of a
Display RAM. However, this command does not affect change in a sensor value. This would have also inhibited
the source of subsequent Data Reads; the CPU will read further writing into the RAM until resetl.
from whichever RAM (Display or FIFO/Sensor) which
For the N-key rollover mode - if the E bit is programmed
was last specified. If, indeed, the Display RAM was last
to "1" the chip will operate in the special Error mode. (For
specified, the Write Display RAM will, nevertheless,
further details, see Interface Considerations Section.)
change the next Read location.
Status Word
Display Write Inhibit/Blanking The status word contains the FIFO status, error, and
display unavailable signals. This word is read by the CPU
The IW Bits can be used to mask nibble A and nibble B when AD is high and CS and RD are low. See Interface
in applications requiring separate 4-bit display ports. By Considerations for more detail on status word.
setting the IW flag (IW = 1) for one of the ports, the port
becomes marked so that entries to the Display RAM
Data Read
from the CPU do not affect that port. Thus, if each nibble Data is read when AD, CS and RD are all low. The source
is input to a BCD decoder, the CPU may write a digit to of the data is specified by the Read FIFO or Read Display
the Display RAM without affecting the other digit being commands. The trailing edge of RD will cause the address
displayed. It is important to note that bit Bo corresponds of the RAM being read to be incremented if the Auto-
to bit Do on the CPU bus, and that bit A3 corresponds to Increment flag is set. FIFO reads always increment (if no
bit 0 7, error occurs) independent of AI.
If the user wishes to blank the display, the BL flags are Data Write
available for each nibble. The last Clear command issued Data that is written with AD. CS and WR low is always
determines the code to be used as a "blank." This code written to the Display RAM. The address is specified by the
defaults to all zeros after a reset. Note that both BL latest Read Display or Write Display command. Auto-
flags must be set to blank a display formatted with a Incrementing on the rising edge of WR occurs if AI set by
single 8-bit port. the latest display command.
7-143 AFN-00742A-05
8279, 8.279-5
Ambient Temperature . . . . . . . . . . . . . . OC to 70C
device. This is a Sti6SS iating only and functional opsia-
Storage Temperature . . . . . . . . . . . . . -65C to 125C
Voltage on any Pin with those indicated in the operational sections of this specifi-
Respect to Ground . . . . . . . . . . . . . . -0.5V to +7V cation is not implied. Exposure to absolute maximum
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . 1 Watt rating conditions for extended periods may affect device
reliability.
D.C. CHARACTERISTICS TA = ooe to 70 oe. Vss = OV. Note 1
VIL1 Input Low Voltage for Shift Control -0.5 1.4 V

and Return Lines
VIL2 Input Low Voltage for All Others -0.5 0.8 V

V 11_: 1 Input High Voltage for Shift, Control 2.2 V
and Return Lines
VIH2 Input High Voltage for All Others 2.0 V
VOL Output Low Voltage 0.45 'V Note 2

VOH Output High Voltage on Interrupt 3.5 V Note 3
Line
IIL1 Input Current on Shift, Control and +10 /lA VIN = Vee
Return Li nes -100 /lA VIN = OV
IIL2 Input Leakage Current on All Others 10 /lA VIN = Vee to OV
IOFL Output Float Leakage 10 /lA VOUT = Vee to OV
Icc Power Supply Current 120 mA
Notes:
1. 8279, vee = +5V 5%; 8279-5, Vee = +5V 10%.
2. 8279, IOL = 1.6mA; 82795, IOL = 2.2mA.
3. 8279, IOH = -100,uA; 8279-5, IOH = -400,uA.
CAPACITANCE
SYMBOL TEST TYP. MAX. UNIT TEST CONDITIONS
Cin Input Capacitance 5 10 pF Vin=Vee

Cout Output Capacitance 10 20 pF Vout=Vee
7144 AFN-00742A-09
8279, 8279-5
TA = oc to 70C, Vss = OV, (Note 1)
BUS PARAMETERS
READ CYCLE:
8279 8279-5
Symbol Parameter Min. Max. Min. Max. Unit
tAR Address Stable Before READ 50 0 ns
tRA Address Hold Time for READ 5 0 ns
tRR READ Pulse Width 420 250 ns
tRO[2] Data Delay from READ 300 150 ns
tAO[2] Address to Data Valid 450 250 ns
tDF READ to Data Floating 10 100 10 100 ns
tRCY Read Cycle Ti me 1 1 iJ.s
WRITE CYCLE:
8279 8279-5
tAW Address Stable Before WR ITE 50 0 ns
tWA Address Hold Time for WR ITE 20 0 ns
tww WR ITE Pulse Width 400 250 ns
tDW Data Set Up Time for WR ITE 300 150 ns
two Data Hold Time for WR ITE 40 0 ns
Notes:
1. 8279, V CC =+5V 5%; 8279-5, VCC = +5V 10%.
2. 8279, CL = 1OOpF; 8279-5, CL = 150pF.
OTHER TIMINGS:
8279 8279-5
t</>w Clock Pu Ise Width 230 120 nsec
tCY Clock Period 500 320 nsec
Keyboard Scan Time: 5.1 msec Digit-on Time: 480 iJ.sec

Keyboard Debounce Time: 10.3 msec Blanking Time: 160 iJ.sec
Key Scan Time: 80 iJ.sec Internal Clock Cycle: 10 iJ.sec
Display Scan Time: 10.3 msec
INPUT WAVEFORMS FOR A.C. TESTS:
"=X
0.45
2.0
0.8
> TEST POINTS < 2.0
0.8 )C
7-145 AFN-00742A-10
8279, 8279-5
WAVEFORMS
1. Read Operation
AO, ES (SYSTEM'S
ADDRESS BUS)
~-----------------------
-tAR - - 1....>---------------------'RCy ------+-'~-----------I
(READ CONTROL)
1.--------tAo--------
DATA BUS
(OUTPUT)
~~~~~~~~~~~+-----------------~~~~~~~~~~~~~
2. Write Operation
(SYSTEM'S
AO, CS ADDRESS BUS)
(WRITE CONTROL)
DATA BUS DATA DATA

- D A T A VALID
(INPUT) ______________________
MAY CHANGE --J
MAY CHANGE
3. Clock Input
7-146 AFN-00742A-11
8279 SCAN TIMING
SCAN WAVEFORMS
ENCODED
L
SCAN
L
L
~U U U U
DECODED
5.1
~ U U U
u
SCAN
u u
u u u LJ
DISPLAY WAVEFORMS
ASSUME INTERNAL FREQUENCY =100 kHz
1+-------640~$=64ICy------1 SO ICY= 10~$
Ao- A 3
ACTIVE HIGH A(1)
"BLANK CODE IS EITHER ALL

O's OR ALL 1'$ OR 20 HEX
Bo-B3
ACTIVE HIGH B(1)
NOTE: SHOWN IS ENCODED SCAN LEFT ENTRY

52-53 ARE NOT SHOWN BUT THEY ARE SIMPLY 51 DIVIDED BY 2 AND 4
7-147 AFN-00742A-12
intJ
8282/8283
OCTAL LATCH
Address Latch for iAPX 86,88, 3State Outputs

MCS80, MCS85, MCS48 Families
High Output Drive Capability for
Driving System Data Bus 20Pin Package with 0.3" Center
Fully Parallel 8Bit Data Register and

Buffer
No Output Low Noise when Entering
Transparent during Active Strobe or Leaving High Impedance State
The 8282 and 8283 are 8-bit bipolar latches with 3-state output buffers. They can be used to implement latches, buffers,
or multiplexers. The 8283 inverts the input data at its outputs while the 8282 does not. Thus, all of the principal periph-
eral and input/output functions of a microcomputer system can be implemented with these devices.
Dlo VCC 01 0 VCC

01 1 000 01 1 000
01 2 001 01 2 001
01 3 002 01 3 002
01 4 003 01 4 003
015 004 015 004
01 6 005 01 6 005
01 7 006 01 7 006
OE 007 OE 007
GNO STB GNO STB
Figure 1. 8282 Pin Configuration Figure 2. 8283 Pin Configuration
7-148
828218283
r-------, 8282
8--- I
D Q -t-B
I
I
8-.---+----f >---,--s
I
I
I
L ______ _ L ______ _
-------; {j
m -{:TI
Dis
~-------
:::::J --*O~
8-
01
6
L ______ _
'" FL------- -~
~
Figure 3. Logic Diagrams
PIN DEFINITIONS OPERATIONAL DESCRIPTION

Pin Description
STB STROBE (Input). STB is an input control The 8282 and 8283 octal latches are 8-bit' latches with
pulse used to strobe data at the data input 3-state output buffers. Data having satisfied the setup
pins (Ao-A7) into the data latches. This time requirements is latched into the data latches by
signal is active HIGH to admit input data. strobing the STB line HIGH to LOW. Holding the STB
The data is latched at the HIGH to LOW line in its active HIGH state makes the latches appear
transition of STB. transparent. Data is presented to the data output pins by
OUTPUT ENABLE (Input). OE is an input activating the OE input line. When OE is inactive HIGH
control signal which when active LOW the output buffers are in their high impedance state.
enables the contents of the data latches Enabling or disabling the output buffers will not cause
onto the data output pin (Bo-B7). OE being negative-going transients to appear on the data output
inactive HIGH forces the output buffers to bus.
their high impedance state.
DATA INPUT PINS (Input). Data presented
at these pins satisfying setup time re-
quirements when STB is strobed and
latched into the data input latches.
00 0-00 7 DATA OUTPUT PINS (Output). When OE is

(8282) true, the data in the data latches is pre-
000-00 7 sented as inverted (8283) or non-inverted
(8283) (8282) data onto the data output pins.
7-14Q
intJ 828218283

Temperature Under Bias ................. 0 C to 70C 'NOTICE: Stresses above those listed under "Absolute Maximum Ratings"
Storage Temperature ............. - 65C to + 150C may cause permanent damage to the device. This is astress rating only and
functional operation of the device at these or any other conditions above
All Output and Supply Voltages ........ - 0.5V to + 7V those indicated in the operational sections of this specification is not
All Input Voltages .................. - 1.0V to + 5.5V implied. Exposure to absolute maximum rating conditions for extended
Power Dissipation ......................... 1 Watt periods may affect device reliability.
Conditions: Vee = 5V 10%, TA = ooe to 70C
Symbol Parameter Min Max Units Test Conditions
Vc Input Clamp Voltage -1 V Ic = -5 mA
IF Forward Input Current -0.2 mA V F = 0.45V
IR Reverse Input Current 50 ~ V R = 5.25V
VOL Output low Voltage .45 V IOL = 32 mA

V OH Output High Voltage 2.4 V IOH = -5 mA
IOFF Output Off Current 50 ~ V OFF = 0.45 to 5.25V

V IL Input low Voltage 0.8 V Vcc= 5.0V See Note 1
V IH Input High Voltage 2.0 V Vee= 5.0V See Note 1
F = 1 MHz
CIN Input Capacitance 12 pF V SIAS = 2.5V, Vee= 5V
TA=25C
NOTE: 1. Output Loading IOL = 32 mA, IOH = - 5 mA, e L= 300 pF.
Conditions: Vee = 5V 10%, TA = ooe to 70C
Loading: Outputs - IOL = 32 mA, IOH = - 5 mA, C L = 300 pF

TIVOV Input to Output Delay (See Note 1)
-Inverting 5 22 ns
-Non-Inverting 5 30 ns
TSHOV STB to Output Delay
-Inverting 10 40 ns
-Non-Inverting 10 45 ns
TEHOZ Output Disable Time 5 18 ns
TElOV Output Enable Time 10 30 ns
TIVSl Input to STB Setup Time 0 ns
TSLIX Input to STB Hold Time 25 ns
TSHSl STB High Time 15 ns
NOTE: 1. See waveforms and test load circuit on following page.
7-150 AFN oo727B

828218283
WAVEFORMS
INPUTS
TlVSL
STB
~----~-TSHSL------~ ~------------------------------------------------------
OUTPUTS
TELOV
VO:~ _ _ _ _
-C
-----+__________- J 'fo-oI.......- - - - - - - - - - - - - - - - - - - - - - - - - - - , VOL +.1V
TSHOV
NOTE: 1.8283 ONLY - OUTPUT MAY BE MOMENTARILY INVALID FOLLOWING THE HIGH GOING STB TRANSITION.
2. ALL TIMING MEASUREMENTS ARE MADE AT 1.5V UNLESS OTHERWISE NOnD.
Figure 4. Timing Diagram
1.5V 1.5V 2.14V

-r - -,...
33Q : 180Q S2.7Q
OUT 0 - - - OUT C>----< OUTC>-----4
I~'F I3OO'F I~"F

3STATE TO VOL 3STATE TO VOH SWITCHING
Figure 5. Output Test Load Circuits
7-151 AFN 007278

ifltel' 828218283
50
8283
40
0
w
I/)
30
z
>-
<C
...I
W
Q
20
10
pF LOAD
50
8282
40
0
w
I/)
z 30
>-
<C
...I
W
Q
20
10
pF LOAD
Figure 6. Output Delay vs. Capacitance
7-152
8286/8287
OCTAL BUS TRANSCEIVER
Data Bus Buffer Driver for iAPX 86,88, 3State Outputs

MCS80, MCS8S, and MCS48
Families
20Pin Package with 0.3" Center
High Output Drive Capability for
Driving System Data Bus
No Output Low Noise when Entering
Fully Parallel 8Bit Transceivers or Leaving High Impedance State
The 8286 and 8287 are 8-bit bipolar transceivers with 3-state outputs. The 8287 inverts the input d~ta at its outputs
while the 8286 does not. Thus, a wide variety of applications for buffering in microcomputer systems can be met.
Ao Vee Ao Vee
A1 Bo A1 So
A2 B1 A2 B1
A3 B2 A3 B2
A4 B3 A4 B3
As B4 AS B4
AS BS A6 BS
A7 B6 A7 B6
OE B7 OE B7
GND T GND T
Figure 1. 8286 Pin Configuration Figure 2. 8287 Pin Configuration
'INTEL CORPORATION. 1980 7 -153 Mav 1980 AFN 01506A
8286/8287
r-------l 8286
r--------,
8287
I I I I
I I
I I
Figure 3. Logic Diagrams
Pin Description
T TRANSMIT (Input). T is an input control signal used to control the direction of the transceivers.
When HIGH, it configures the transceiver's Bo-B7 as outputs with Ao-A7 as inputs. T LOW con
figures Ao-A7 as the outputs with Bo-B7 serving as the inputs.
OE OUTPUT ENABLE (Input). OE is an input control signal used to enable the appropriate output
n
driver (as selected by onto its respective bus. This signal is active LOW.
Ao-A7 LOCAL BUS DATA PINS (Input/Output). These pins serve to either present data to or accept data
from the processor's local bus depending upon the state of the T pin.
~-~(8286) SYSTEM BUS DATA PINS (Input/Output). These pins serve to either present data to or accept
Bo-B7 (8287) data from the system bus depending upon the state of the T pin.
The 8286 and 8287 transceivers are 8-bit transceivers with high impedance outputs. With T active HIGH and OE active
LOW, data at the Ao-A7 pins is driven onto the Bo-B7 pins. With T inactive LOW and OE active LOW, data at the Bo-B7
pins is driven onto the Ao-A7 pins. No output low glitching will occur whenever the transceivers are entering or leaving
the high impedance state.
AFN 01506A
7-154
Intel 8286/8287

Temperature Under Bias ................. OC to 70C "NOTICE: Stresses above those listed under "Absolute Maximum Ratings"
Storage Temperature ............. - 65C to + 150C may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
All Output and Supply Voltages ........ - 0.5V to + 7V those indicated in the operational sections of this specification is not
All Input Voltages .................. - 1.0V to + 5.5V implied. Exposure to absolute maximum rating conditions for extended
Power Dissipation .......................... 1 Watt periods may affect device reliability.
D.C. CHARACTERISTICS FOR 8286/8287

Conditions: Vee = 5V 10% T A = 0 C to 70 C
Ve Input Clamp Voltage -1 V le=-5 mA
Icc Power Supply Current-8287 130 mA
-8286 160 mA
IF Forward Input Current -0.2 mA VF= 0.45V
IR Reverse Input Current 50 /AA VR= 5.25V
VOL Output low Voltage -BOutputs .45 V IOL = 32 mA
-A Outputs .45 V IOL = 16 mA
VOH Output High Voltage -B Outputs 2.4 V IOH = -5 mA
-A Outputs 2.4 V IOH= -1 mA
IOFF Output Off Current IF VOFF = 0.45V
IOFF Output Off Current IR VOFF = 5.25V
V IL Input low Voltage -A Side 0.8 V Vee= 5.0V, See Note 1
-B Side 0.9 V Vee= 5.0V, See Note 1
VIH Input High Voltage 2.0 V Vee = 5.0V, See Note 1
F= 1 MHz
CIN Input Capacitance 12 pF VBIAS=2.5V, Vee=5V
TA= 25C
NOTE: 1. B Outputs - IOL = 32mA, IOH= -5mA, e L = 300pF; A Outputs - IOL = 16mA, IOH= -1 rnA, eL = 100pF.
A.C. CHARACTERISTICS FOR 8286/8287

Conditions: Vee = 5V 10%, TA = OC to 70C
Loading: B Outputs - IOL = 32 mA, IOH = -5 mA, CL = 300 pF
A Outputs - IOL = 16 mA, IOH = -1 mA, CL = 100 pF
Symbol Parameter Min Max Units Test COllditions
TIVOV Input to Output Delay
Inverting 5 22 ns (See Note 1)
Non-Inverting 5 30 ns
TEHTV Transmit/Receive Hold Time 5 ns
TTVEl Transmit/Receive Setup 10 ns
TEHOZ Output Disable Time 5 18 ns
TElOV Output Enable Time 10 30 ns
NOTE: 1. See waveforms and test load circuit on following page.
AFN 01506A
7-155
8286/8287
WAVEFORMS
INPUTS \V
--------/~~---------------------------------------------
\
C=
V
1 I\~-------
-Tivov- -- TEHOZ I- TELOV-
VOH - .W
OUTPUTS
/1\\-.._____-:--____1--_~------
_________\V VOL + .W
1
--TEHTV-I I--TTVEL
T~------------------------------------~t~----------
NOTE: 1. All timing measurements are made at 1.5V unless otherwise noted.
Figure 4. 8286/8287 Timing
50 50
1287 8288
40 40
U U
UI III
I/) I/)
30 z 30
z
~ ~
j j
UI III
Q Q
20 20
10
pF LOAD pF LOAD
Figure 5. Output Delay vs. Capacitance
7-156 AFN 01506A

Intel 8286/8287
1.SV 1.SV 2.14V
O"'~''" OUT
66Q
O"'~""
1300 pF 1300 pF
3STATE TO VOL 3STATE TO VOL SWITCHING
B OUTPUT A OUTPUT B OUTPUT
1.SV 1.SV 2.28V
180Q 900Q 114Q
OUT 0-------< OUT 0-----< OUT 0-------<
roo, ! 100pF
1"0"
3STATE TO VOH 3STATE TO VOH SWITCHING
B OUTPUT A OUTPUT A OUTPUT
Figure 5. Test Load Circuits
7-157 AFN 01506A

inter
A?Q1
v .. "
GPIB TALKER/LISTENER
Designed to Interface Microprocessors

161 - Registers
8 M Hz Clock Range
(e.g., 8080, 8085, 8086, 8048) to an
IEEE Standard 488 Digital Interface Data Transfer,(8 the
Read, 8 Write), 2 for
Rest for Interface
Bus Function Control, Status, etc.
Complete Source and Acceptor
Programmable Data Transfer Rate
Directly Interfaces to External Non-
Handshake Inverting Transceivers for Connection
to the GPIB
Complete Talker and Listener

Functions with Extended Addressing
Provides Three Addressing Modes,
Allowing the Chip to be Addressed
Service Request, Parallel Poll, Device

Clear, Device Trigger, Remote/Local
Either as a Major or a Minor Talker/
Listener with Primary or Secondary
Functions Addressing
Selectable Interrupts DMA Handshake Provision Allows for

Bus Transfers without CPU Intervention
Address Recognition
On-Chip Primary and Secondary
Trigger Output Pin
Automatic Handling of Addressing and

Handshake Protocol
On-Chip EOS (End of Sequence)
Message Recognition Facilitates
Handling of Multi-Byte Transfers
Provision for Software Implementation
of Additional Features
The 8291 GPIB Talker/Listener is a microprocessor-controlled chip designed to interface microprocessors (e.g., 8048,
8080,8085,8086) to an IEEE Standard 488 Instrumentation Interface Bus. It implements all of the Standard's interface
functions except for the controller.
18291
GPIB DATA
INTERFACE
FUNCTIONS I/,-_-'=-~
SH GPIB CONTROL TO NON-INVERTING
i5i06 AH BUS TRANSCEIVERS
TE
DIOS
LE
Di04 SR
i5i03 I
T/R CONTROL
DI02
DiOi
D3 ill
D4 fiEiij
7-158
8291
PIN DESCRIPTION
Symbol I/O Pin No. Function Symbol I/O Pin No. Function
00-07 I/O 12-19 Data bus port, to be connected NRFO I/O 37 Not ready for data; GPIB hand-
to microprocessor data bus. shake control line. Indicates the
condition of readiness of de-
RSo-RS2 21-23 Register select inputs, to be con-
vice(s) connected to the bus to
nected to three non-multiplexed
accept data.
microprocessor address bus
lines. Select which of the 8 in- I/O 38 Not data accepted; GPIB hand-
ternal read (write) registers will shake control line. Indicates the
be read from (written into) with condition of acceptance of data
the execution of RO (WR). by the device(s) connected to
the bus.
8 Chip select. When low, enables
reading from or writing into the 26 Attention; GPIB command line.
register selected by RSo-RS2. Specifies how data on 010 lines
are to be interpreted.
9 Read strobe. When low, selected
register contents are read by the 24 Interface clear; GPIB command
CPU. line. Places the interface func-
tions in a known quiescent state.
WR 10 Write strobe. When low, data is
written into the selected register. o 27 Service request; GPIB command
line. Indicates the need for
INT (INT) 0 11 Interrupt request to the micro-
attention and requests an inter-
processor, set high for request
ruption of the current sequence
and cleared when the appropri-
of events on the GPIB.
ate register is accessed by the
CPU. May be software config- 25 Remote enable; GPIB command
ured to be active low. line. Selects (in conjunction with
other messages) remote or local
OREQ 0 6 OMA request, normally low, set
control of the device.
high to indicate byte output or
byte input, in OMA mode; reset I/O 39 End or identify; GPIB command
by OACK. line. Indicates the end of a
multiple byte transfer sequence
OMA acknowledge. When low,
or, in conjunction with ATN,
resets OREQ and selects data
addresses the device during a
in/data out register for OMA
polling sequence.
data transfer (actual transfer
done by RO/WR pulse). T/R1 o External transceivers control
Must be high if OMA is not used. line. Set high to indicate output
data/Signals on the 0101-010s
TRIG 0 5 Trigger output, normally low; and DAV lines and input signals
generates a triggering pulse with on the NRFO and NOAC lines
1,usec min. width in response to (active source handshake). Set
the GET bus command or low to indicate input datal
Trigger auxiliary command. signals on the 0101-010s and
CLOCK 3 External clock input, used only OAV lines and output signals on
for Tl delay generator. May be the NRFO and NOAC lines (ac-
any speed in 1-8 MHz range. tive acceptor handshake).
RESET 4 Reset input. When high, forces T/R2 o 2 External transceivers control
the device into an "Idle" (initiali- line. Set high to indicate output
zation) mode. The device will re- signals on the EOI line. Set low
main at "Idle" until released by to indicate expected input signal
the microprocessor. on the EOI line during parallel
poll.
8-bit GPIB data port, used for
bidirectional data byte transfer Vee P.S. 40 Positive power supply (5V
between 8291 and GPIB via non- 10%).
inverting external line trans-
GNO P.S. 20 Potential ground circuit.
ceivers.
I/O 36 Data valid; GPIB handshake
control line. Indicates the avail-
ability and validity of infor-
mation on the 010 lines.
Note: All signals on the S291 pins are specified with positive logic.
However, IEEE488 specifies negative I~ on its 16 signal lines. Thus, the
data is inverted once from 00-07 to OIO,-OIOa and non-inverting bus
transceivers should be used.
7-159
8291
8291 SYSTEM DIAGRAM

MICROPROCESSOR SYSTEM BUS
r - -
I DMA
- - 'I
1-------1
DREO r--~~-
8291
... T/R2
t-----,
I ~g~il~~~\~R ~I___D_AC_K_ _... INT~~I~ACE T/R1

L _____ ..I 1...--"'"7'II"----iI
GENERAL PURPOSE INTERFACE BUS
THE GENERAL PURPOSE INTERFACE

BUS (GPIB)
The General Purpose Interface Bus (GPIB) is defined in
the IEEE Standard 488-1978 "Digital Interface for DEVICE A
"- llJl1 rfr f~
Programmable Instrumentation." Although a knowledge ABLE TO
of this standard is assumed, Figure 1 provides the bus
TALK, LISTEN, I' I-
DATA BUS
AND (I.-
structure for quick reference. Also, Tables 1 and 2 CONTROL
(e.g. calculatorl
reference the interface state mnemonics and the interface
messages respectively. Mo<;lified state diagrams for the
8291 are presented in Appendix A. DEVICE B
ABLE TO
~
GENERAL DESCRIPTION TALK AND
LISTEN
t - -f---4
The 8291 is a microprocessor controlled device de- (e.g. digital DATA BYTE
signed to interface microprocessors e.g., 8048, 8080,
8085,8086 to the GPIB. It implements all of the interface
functions defined in the IEEE 488 Standard. If an imple-
multimeterl
DEVICE C
(e-
- TRANSFER
CONTROL
mentation of the Standard's Controller function is ONLY ABLE

desired, it can be connected with an Intel 8292 to form TO LISTEN I" i-"
a complete interface. (e.g. signal

generatorl GENERAL
The 8291 handles communication between a microproc- - .......
INTERFACE
MANAGEMENT
essor controlled device and the GPIB. Its capabilities in- A (
DEVICE D
clude data transfer, handshake protocol, talker/listener I'\.
ONLY ABLE
addressing procedures, device clearing and triggering, TO TALK I" )-
service request, and both serial and parallel polling
schemes. In most procedures, it does not disturb the (e.g. counterl
microprocessor unless a byte is waiting on input or a
byte sent on output (output buffer empty). ~}DI01 .. .8
The 8291 architecture includes 16 registers. Eight of these
registers may be written into by the microprocessor. The
DAV
other eight registers may be read by the microprocessor. NRFD
One each of these read and write registers is for direct data NDAC
transfers. The rest of the write registers control the various IFC
features of the chip, while the rest of the read registers ATN
SRO
provide the microprocessor with a monitor of GPIB states, REN
various bus conditions, and device conditions. EOI
Figure 1. Interface Capabilities and Bus Structure.
7-160
8291
GPIB Addressing second mode allows the user to implement a single

talker/listener with a two byte address (primary address +
Each device connected to the GPI B must have at least one secondary address). The third mode again allows for two
address whereby the controller device in charge of the bus distinct addresses but in this instance, they can each have
can configure it to talk, listen, or send status. An 8291 a two-byte address. However, this mode requires that the
implementation of the GPIB offers the user three secondary addresses be passed to the microprocessor for
addressing modes from which the device can be initialized verification. These three addressing schemes are des-
for each application. The first of these modes allows for cribed in more detail in the discussion of the Address
the device to have two separate primary addresses. The registers.
TABLE 1.
IEEE 488 INTERFACE STATE MNEMONICS
Mnemonic State Represented Mnemonic State Represented

ACDS Accept Data State PACS Parallel Poll Addressed to Configure State
ACRS Acceptor Ready State PPAS Parallel Poll Active State
AIDS Acceptor Idle State PPIS Parallel Poll Idle State
ANRS Acceptor Not Ready State PPSS Parallel Poll Standby State
APRS Affirmative Poll Response State PUCS Parallel Poll Unaddressed to Configure State
AWNS Acceptor Wait for New Cycle State REMS Remote State
- CA-CS - - -C~ntr;;!l;r-A~t~e-S;t; - - - - - - - --, RWLS Remote With Lockout State
CADS Controller Addressed State
SACS System Control Active State
CAWS Controller Active Wait State
SDYS Source Delay State
CIDS Controller Idle State
SGNS Source Generate State
CPPS Controller Parallel Poll State
SIAS System Control Interface Clear Active State
CPWS Controller Parallel Poll Wait State SIDS Source Idle State
CSBS Controller Standby State SIIS System Control Interface Clear Idle State
CSNS Controller Service Not Requested State SINS System Control Interface Clear Not Active State
CSRS Controller Service Requested State SIWS Source Idle Wait State
CSWS Controller Synchronous Wait State SNAS System Control Not Active State
L CTRS
_ _ _ _ _ Controller
_____ Transfer
_ _ _State
_______ _
SPAS Serial Poll Active State
DCAS Device Clear Active State SPIS Serial Poll Idle State
DCIS Device Clear Idle State SPMS Serial Poll Mode State
DT AS Device Trigger Active State SRAS System Control Remote Enable Active State
OTIS Device Trigger Idle State SRIS System Control Remote Enable Idle State
LACS Listener Active State SRNS System Control Remote Enable Not Active State
LADS Listener Addressed State SRQS Service Request State
LIDS Listener Idle State STRS Source Transfer State
LOCS Local State SWNS Source Wait for New Cycle State
LPAS Listener Primary Addressed State TACS Talker Active State
LPIS Listener Primary Idle State TAOS Talker Addressed State
LWLS Local With Lockout State TIDS Talker Idle State
NPRS Negative Poll Response State TPIS Talker Primary Idle State
- - - - - - The Controller function is implemented on the Intel'" 8292.
7-161
8291
TABLE 2.
IEEE 488 INTERFACE MESSAGE REFERENCE LIST
Mnemonic Message Interface Function(s)

LOCAL MESSAGES RECEIVED (By Interface Functions)
- gts go to standby C
ist individual status PP
Ion listen only L, LE
Ipe local poll enable PP
nba new byte available SH
pon power on SH,AH,T,TE,L,LE,SR,RL,PP,C
rdy ready AH
-rpp request parallel poll C
- rsc request system control C
rsv request service SR
rtl return to local RL
- sic send interface clear C
- sre send remote enable C
- tca take control asynchronously C
-tcs take control synchronously AH,C
ton talk only T, TE
REMOTE MESSAGES RECEIVED
ATN Attention SH,AH,T,TE,L,LE,PP,C
DAB Data Byte (Via L, LEI
DAC Data Accepted SH
DAV Data Valid AH
DCL Device Clear DC
END End (via L, LEI
GET Group Execute Trigger DT
GTL Go to Local RL
lOY Identify L,LE,PP
IFC Interface Clear T,TE,L,LE,C
LLO Local Lockout RL
MLA My Listen Address L,LE,RL,T,TE
MSA My Secondary Address TE,LE,RL
MTA My Talk Address T,TE,L,LE
OSA Other Secondary Address TE
OTA Other Talk Address T, TE
PCG Primary Command Group TE,LE,PP
t PPC Parallel Poll Configure PP
t [PPDI Parallel Poll Disable PP
t [PPE] Parallel Poll Enable PP
-PPRN Parallel Poll Response N (via C)
tPPu Parallel Poll Unconfigure PP
REN Remote Enable RL
RFD Ready for Data SH
RQS Request Service (via L, LE)
[SDC] Select Device Clear DC
SPD Serial Poll Disable T, TE
SPE Serial Poll Enable T, TE
-SQR Service Request (via C)
STB Status Byte (via L, LE)
TCT or [TCT] Take Control C
UNL Unlisten L, LE
-These messages are handled only by Intel's 8292.

tUndefined commands which may be passed to the microprocessor.
7-162
8291
TABLE 2. (Cont'd)
IEEE 488 INTERFACE MESSAGE REFERENCE LIST
Mnemonic Message ** Interface Function(s)
REMOTE MESSAGES SENT

ATN Attention C
DAB Data Byte (via T, TE)
DAC Data Accepted AH
DAV Data Valid SH
DCl Device Clear (via C)
END End (via T)
GET Group Execute Trigger (via C)
GTl Go to local (via C)
IDY Identify C
IFC Interface Clear C
llO local lockout (via C)
MlA or [MlA] My Listen Address (via C)
MSA or [MSA] My Secondary Address (via C)
MTA or [MTA] My Talk Address (via C)
OSA Other Secondary Address (via C)
OTA Other Talk Address (via C)
PCG Primary Command Group (via C)
PPC Parallel Poll Configure (via C)
[PPD] Parallel Poll Disable (via C)
[PPE] Parallel Poll Enable (via C)
PPRN Parallel Poll Response N PP
PPU Parallel Poll Unconfigure (via C)
REN Remote Enable C
RFD Ready for Data AH
ROS Request Service T, TE
[SDC] Selected Device Clear (via C)
SPD Serial Poll Disable (via C)
SPE Serial Poll Enable (via C)
SRO Service Request SR
STB Status Byte (via T, TE)
TCT Take Control (via C)
UNl Unlisten (via C)
"All Controller messages must be sent via Intel's 8292.
7-163
8291
DEVICE ELECTRICAL CHARACTERISTICS

TA = OC to 70C; Vee = 5V 10%

VIH Input High Voltage 2 Vee+0.5 V
VOL Output Low Voltage 0.45 V IOL=2mA (4mA for TR1 pin)
VOH Output High Voltage 2.4 V IOH = -400jlA (-150jlA for SRQ pin)
VOH-INT Interrupt Output High Voltage 2.4 V IOH=-400jlA
3.5 V IOH=-50jlA
ilL Input Leakage 10 jlA VIN=OV to Vee
ILOL Output Leakage Current -10 jlA VouT=0.45V
ILOH Output Leakage Current 10 jlA VOUT=Vee
lee Vee Supply Current 180 mA TA=OC
10%, Commercial: TA =
Vee = 5V OC to 70C
Symbol Parameter Min. Max. Unit

tAA Address Stable Before READ 0 nsecl 11
tAA Address Hold After READ 0 nsec l11
tAA READ width 140 nsec l21
tAO Address Stable to Data Valid 250 nsec l11
tAO READ to Data Valid 100 nsec[21
tAoF Data Float After READ 0 60 121 nsec
tAW Address Stable Before WRITE 0 nsec[11
tWA Address Hold After WRITE 0
tww WRITE Width 170 nsec[1[
tow Data Set Up Time to the Trailing
Edge of WRITE 150 nsec[11
two Data Hold Time After WRITE 0 nsec[11
tAKRQ DACKI to DREQI 130 nsec
tOKOA6 DACKI to Up Data Valid 200 nsec
Notes:
1. 8080 System CLmax = 100pF; CLmin = 15pF; 3 MHz clock.
2. 8085 System CL = 150pF; 4 MHz clock.
7-164
8291
TIMING WAVEFORMS
CS/RSj
1-.---t RR - - - . 1
!.------tAD---_
READ:
-tAR_ -tRD-
DATA BUS
(DATA OUT)
CS/RSj
WRITE - -......--....t
DATA BUS DATA MAY CHANGE

(DATA IN) _ _ _ _ _ _ _ _ _ _....J ~----~ ~_ _ _ _ _ _ __
DREQ -----/1 t __
----------""IIj _~'mo
DACK \
7-165
8291
GPIB TIMINGSl 1 1
~ymuol ,..aiamEhei ._.ax. II.

.... n:. T.,... .....
es. ,."cnwhlCU1S
TEOT13 EOII to TR11 135 nsec PPSS, A TN=0.45V

TEODI6 EOII to DIO Valid 155 nsec PPSS, A TN=0.45V
TEOT12 EOII to TR1 I 155 nsec PPSS, A TN=0.45V
TATND4 ATNI to NDACI 155 nsec TACS, AIDS
TATT14 ATNltoTR11 155 nsec TACS, AIDS
TATT24 ATNI to TR21 155 nsec TACS, AIDS
TDVND3-C DAVI to NDACI 650 nsec AH,CACS
TNDDV1 NDACI to DAVI 350 nsec SH,STRS
TNRDV2 NRFDI to DAVI 350 nsec SH, T1 True
TNDDR1 NDACI to DREQI 400 nsec SH
TDVDR3 DAVI to DREQI 600 nsec AH, LACS, ATN=2.4V
TDVND2-C DAVI to NDACI 350 nsec AH,LACS
TDVNR1-C DAVI to NRFD! 350 nsec AH, LACS, rdy=True
TRDNR3 RD~ to NRFDt 500 nsec AH, LACS
TWRDI5 WR to DIO Valid 250 nsec SH, TACS, RS=0.4V
TWRDV2 WRt to DAV~ 830 + tSYNC nsec High Speed Transfers Enabled,
NF = fc, tSYNC = 1/2fc
Notes:
1. All GPIB timings are at the pins of the 8291.
7-166
8291
Appendix A
MODIFIED STATE DIAGRAMS ically true at <O.8V and is equivalent to pin 36 on the
8291.
Figure A.1 presents the interface function state diagrams.
D. All remote multiline messages decoded are condi-
It is derived from IEEE Std. state diagrams, with the
tioned by ACDS. The multiplication by ACDS is not
following changes:
drawn to simplify the diagrams.
A. The 8291 supports the complete set of IEEE-488 E. The symbol
interface functions except for the controller. These
include: SH1, AH1, T5, TE5, L3, LE3, SR1, RL 1, PP1, DC1,
DT1, and CO. indicates:
B. Addressing modes included in T,L state diagrams. 1. When event X occurs, the function will return to
Note that in Mode 3, MSA, OSA are generated only after state S.
secondary address validity check by the microprocessor 2. X overrides any other transition condition in the
(APT interrupt). function.
C. In these modified state diagrams, the IEEE-488 con- Statement 2 simplifies the diagram, avoiding the explicit
vention of low true logic is followed. Thus, DAV is log- use of X to condition all transitions from S to other states.
,----1
I I
ISH I
IL _ _ _ _ ...lI
pon
DAC
ATN + Pi
(WITHIN t2) DAV
Fl = TACS + SPAS
r-----,
I I
I AH I
I I
L ____ J
"THIS TRANSITION WILL NEVER

OCCUR UNDER NORMAL OPERATION.
pon----IM tT DELAY IS ABOUT 300 NS
FOR DEBOUNCING DAV.
F2 = A TN + LACS + LADS
F3 = ATN + rdy
T3' = T3 CPT' APT
Figure A.1. 8291 State Diagrams (Continued next page)
7-167
8291
r-----,
I I
ton + MTA MODE 1 I TEl
+ MSA . TPAS . MODE 1 ATN'SPMS I I
L ____ j
pon---~ STB AND RQS AVAILABLE

TO SH
IFC
(WITHIN t4)
F4 = OTA + (OSA TPAS + MSA LPAS)

MODE 1 + MLA MODE 1
EOI IF DAB = EOS OR EDI IS TRUE.
r- --I
RQS IN STB I I
I SR a I
I I
L ____ J
IFC
(WITHIN (4)
r-----,
I I
I LE I
I I
L ____ J r----l
I I
I RL I
pon---~
I I
L ____ J
pon---~
F5 = (MLA MODE 1 + LPAS MSA MODE 1)
Figure A.1. 8291 State Diagrams (Continued next page)
7-168
8291
r----1
r-----, I I
I I DC I
PP2 I IL _ _ _ _ JI
I I
c:x:B
L ____ J
pon---~
F6
F6 = DCl + SDC lADS
IDY* r ----1
(WITHIN (5)
I I
I DT I
Il ____ ...JI
*IDY = ATN . EOI
Figure A.1. 8291 State Diagrams
Appendix B
IEEE 488 TIME VALUES
Time Value
Identifier* Function (Applies to) Description Value
T1 SH Settling Time for Multiline Messages ::::: 2/-lst
-
t2 LC,IC,SH,AH,T,L Response to A TN ::; 200ns
T3 AH Interface Message Accept Time t > 00
t4 T,TE,L,LE,C,CE Response to IFC or REN False < 100/-ls
ts PP Response to ATN+EOI ::; 200ns
Ta C Parallel Poll Execution Time ::::: 2/-ls
T7 C Controller Delay to Allow Current Talker ::::: 500ns
to see A TN Message
Ta C Length of IFC or REN False > 100/-ls
Tg C Delay for EOI ** ::::: 1.5/-lstt
* Time values specified by a lower case t indicate the maximum time allowed to make a state transition. Time values specified by an
upper case T indicate the minimum time that a function must remain in a state before exiting.
If three-state drivers are used on the DIO, DAV, and EOI lines, T1 may be:
1. 2: 11 OOns
2. Or 2: 700ns if it is known that within the controller ATN is driven by a three-state driver.
3. Or 2: 500ns for all subsequent bytes following the first sent after each false tranSition of ATN (the first byte must be sent in
accordance with (1) or (21.
4. Or 2: 350ns for all subsequent bytes following the first sent after each false transition of ATN under conditions specified in
Section 5.2.3 and warning note. See IEEE Standard 488.
t Time required for interface functions to accept, not necessarily respond to interface messages.
{) Implementation independent.
** Delay required for EOI, NDAC, and NRFD signal lines to indicate valid states.
tt 2: 600ns for three-state drivers.
7-169
8291
Appendix C
THE THREE WIRE HANDSHAKE
_TWRD15i
I VALID
I NOT VALID
I VALID
T1L
I----n
,
TDVNRl
I\.
!--TNDDV1-
}'t
~ t--TWRDV2-
,
-TRDNR3- I----
i\.-
I---- TNRDV2 ---
V-
)
!---TDVND3 ... !--TDVND2
) "
~mDD"J
DREO(SH)
~,"VD"J
DREO(AH)
\
V
WR
U
V
Figure C-1. 3-Wire Handshake Timing at 8291.
7170
8291
SOURCE ACCEPTOR
YES
YES
DATA IS VALID AND MAY

NOW BE ACCEPTED
NDAC SIGNAL LINE STAYS LOW UNTIL

ALL ACCEPTORS HAVE ACCEPTED IT
DATA IS NOT TO BE CONSIDERED

VALID AFTER THIS TIME
NO
FLOW DIAGRAM OUTLINES SE~UENCE OF EVENTS DURING TRANSFER OF

DATA BYTE. MORE THAN ONE LISTENER AT A TIME CAN ACCEPT DATA
BECAUSE OF LOGICAL AND CONNECTION OF NRFD AND NDAC LINES.
Figure C.2. Handshake Flowchart.
7-171
8291
Appendix D
FUNCTIONAL PARTITIONS
DEVICE (APPARATUS)
\
\
\
\
\
\
\
\
\
\
\
\ DRIVERS
\ AND
\ RECEIVERS
DEVICE MESSAGE
FUNCTIONS CODING
~_ _ _,--_ _ _----JIIL _ _ _ _ _ _ _ _~------------ll LI_----,_ _--'

MCS' 8291 8293
SYSTEM
A - CAPABILITY DEFINED BY THE 4881978 STANDARD.
B- CAPABILITY DEFINED BY THE DESIGNER.
1- INTERFACE BUS SIGNAL LINES.
2 - REMOTE INTERFACE MESSAGES TO AND FROM INTERFACE FUNCTIONS,
3 - DEVICE DEPENDENT MESSAGES TO AND FROM DEVICE FUNCTIONS.
4- STATE LINKAGES BETWEEN INTERFACE FUNCTIONS.
5 - LOCAL MESSAGES BETWEEN DEVICE FUNCTIONS AND INTERFACE
FUNCTIONS (MESSAGES TO INTERFACE FUNCTIONS ARE DEFINED,
MESSAGES FROM INTERFACE FUNCTIONS EXIST ACCORDING TO THE
DESIGNER'S CHOICE).
6 - CONTROL MESSAGES (8292 ONLY).
Figure 0.1. Functional Partition Within a Device.
7-172
8292
GPIB CONTROLLER
Complete IEEE Standard 488 Controller Complete Implementation of Transfer

Function Control Protocol
Interface Clear (IFC) Sending Capability
Allows Seizure of Bus Control and/or Synchronous Control Seizure Prevents
Initialization of the Bus the Destruction of Any Data
Transmission in Progress
Responds to Service Requests (SRQ)
Sends Remote Enable (REN), Allowing Connects with the 8291 to Form a
Instruments to Switch to Remote Complete IEEE Standard 488 Interface
Control Talker/ Listener/ Controller
The 8292 GPIB Controller is a microprocessor-controlled chip designed to function with the 8291 GPIB Talker/Listener
to implement the full IEEE Standard 488 controller function, including transfer control protocol. The 8292 is a pre-
programmed Intel 8041A.
PIN CONFIGURATION 8291,8292 SYSTEM DIAGRAM

IFCL Vcc
X1 COUNT
X2 REN r--- ---. DACK

RESET OAV I DREO 8291
I DMA GPIB
8292
Vec IBFI I CONTROLLER I TALKERI
GPIB
I (OPTIONAL) I CONTROLLER
Cs OBFI L ______ I LISTENER
GND EOI
RD SPI
T/R2
AO TCI
WR CIC
SYNC NC
DO ATNO TiAl
01 NC
02 CLTH
03 VCC 8293
BUS
04 NC TRANSCEIVERS
05 SYC
Os IFC
07 ATNI
VSS SRQ
7-173 00741C
8292
PIN DESCRIPTION
Function
~ymbOI I~~ I~i:"N~~ I ~. , Function
irvL. I I I r v neCeiVeU \laIClleU} - I lie O~l1~ vee t"".i). 0, ~O, QU +ov supply inpUt. ~ IU70.
monitors the IFC Line (when not COUNT. I 39 Count Input - When enabled by
system controller) through this
the proper command the internal
pin. counter will count external events
X 1, X2 I 2, 3 Inputs for a crystal, LC or an exter- through this pin. High to low tran-
nal timing signal to determine the sition will increment the internal
internal oscillator frequency. counter by one. The pin is sampled
RESET I 4 Used to initialize the chip to a once per three internal instruction
known state during power on. cycles (7.5J.1sec sample period
when using 6 MHz XTAL). It can be
CS I 6 Chip Select Input - Used to select used for byte counting when con-
the 8292 from other devices on the nected to NOAC, or for block
common data bus. counting when connected to the
RO I 8 1/0 write input which allows the EOL
master CPU to read from the 8292. REN 0 38 The Remote Enable bus signal
Ao I 9 Address Line - Used to select be- selects remote or local control of
tween the data bus and the status the device on the bus. A GPIB bus
register during read operations management line, as defined by
and to distinguish between data IEEE Std. 488-1978.
and commands written into the OAV 1/0 37 OAV Handshake Line - Used duro
8292 during write operations. ing parallel poll to force the 8291
-
WR I 10 1/0 read input which allows the to accept the parallel poll status
master CPU to write to the 8292. bits. It is also used during the tcs
procedure.
SYNC 0 11 8041A instruction cycle synchro-
nization signal; it is an output IBFI o 36 Input Buffer Not Full - Used to
clock with a frequency of interrupt the central processor
XTAL+ 15. while the input buffer of the 8292
is empty. This feature is enabled
0 0 -0 7 110 12-19 8 bidirectional lines used for com-
and disabled by the interrupt
munication between the central
mask register.
processor and the 8292's data bus
buffers and status register. OBFI o 35 Output Buffer Full - Used as an
interrupt to the central processor
Vss P.S. 7, 20 Circuit ground potential.
while the output buffer of the 8292
SRO I 21 Service Request - One of the is full. The feature can be enabled
IEEE control lines. Sampled by the and disabled by the interrupt
8292 when it is controller in mask register.
charge. If true, SPI interrupt to the
master will be generated.
EOl2 110 34 End Or Identify - One of the GPIB
management lines, as defined by
ATNI I 22 Attention In - Used by the 8292 to IEEE Std. 488-1978. Used with ATN
monitor the GPIB ATN control as Identify Message during paral-
line. It is used during the transfer lel poll.
control procedure.
SPI o 33 Special Interrupt - Used as an
IFC 1/0 23 Interface Clear - One of the GPIB interrupt on events not initiated by
management lines, as defined by the central processor.
IEEE Std. 488-1978, places all de-
vices in a known quiescent state.
TCI o 32 Task Complete Interrupt - Inter-
rupt to the control processor used
SYC I 24 System Controller - Monitors the to indicate that the task requested
system controller switch. was completed by the 8292 and
CLTH 0 27 CLEAR LATCH Output - Used to the information requested is ready
clear the IFCR latch after being in the data bus buffer.
recognized by the 8292. Usually CIC o 31 Controller In Charge - Controls
low (except after hardware Reset), the SIR input of the SRO bus
it will be pulsed high when IFCR is transceiver. It can also be used to
recognized by the 8292. indicate that the 8292 is in charge
ATNO 0 29 Attention Out - Controls the ATN of the GPIB bus.
control line of the bus through ex-
ternal logic for tcs and tca pro-
cedures. (ATN is a GPIB control
line, as defined by IEEE Std~
488-1978.)
7-174 00741C
8293
GPIB TRANSCEIVER
Nine Open-collector or Three-state On-chip Decoder for Mode

Line Drivers Configuration
48 mA Sink Current Capability on Power Up/Power Down Protection to

Each Line Driver Prevent Disrupting the IEEE Bus
Nine Schmitt-type Line Receivers Connects with the 8291 and 8292 to
High Capacitance Load Drive Form an IEEE Standard 488 Interface
Capability Talker/Listener/Controller with no
Additional Components
Single 5V Power Supply
Only Two 8293's Required per GPIB
28-Pin Package Interface
Low Power HMOS Design On-Chip IEEE-488 Bus Terminations
The Intel 8293 GPIB Transceiver is a high current, non-inverting buffer chip designed to interface the 8291 GPIB
Talker/Listener or the 8292 GPIB Controller with the 8291 to the IEEE Standard 488-1978 Instrumentation Interface
Bus. Each GPIB interface would contain two 8293 Bus Transceivers. In addition, the 8293 can also be used as a general
purpose bus driver.
PIN CONFIGURATION 8291,8292,8293 SYSTEM DIAGRAM
TIR1 Vee r--- ---. DACR

TIR2 OPTA I 8257 DRO 8291
8292
EOI OPTB
I DMA GPIB
GPIB
I CONTROllER I TALKERI
CONTROLLER
ATN DATA10 I (OPTIONAL) I LISTENER
DATA1
L______ J
DArA8
TIR 2
DATA3 BUS9
BUS8
DATA5 GND
BUS7
TIR1
BUSS
BUSS
BUS4
8293
BUS
TRANSCEIVERS
7-175
8293
PIN DESCRIPTION Symbol 1/0 Pin No. Function

Symbol 1/0 Pin No. Function I/O 3 End or Identify; this pin indi-
BUSi- iiO ;2, ;3, These are the IEEE488 bus cates the end of a multiple
BUS9 15-19, interface driver/receivers. byte transfer or, in conjunc-
21,22 Using the mode select pins, tion with ATN, addresses the
they can be configured .differ- device during a polling se-
ently to allow direct connec- quence. It connects to the
tions between the 8291 GPIB 8291 and is switched between
Talker/Listener and the 8292 transmit and receive by T/R2.
GPIB Controller. This pin is TTL compatible.
DATA1- 110 5-11, These are the pins to be Gon- o 4 Attention; this pin is used by
DATA10 23-25 nected to the 8291 and 8292 to the 8291 to monitor the GPIB
interface with the GPIB bus. ATN control line. It specifies
Their use is programmed by how data on the DIO lines is to
the two mode select pins, be interpreted. This output is
OPTA and OPTB. All these TTL compatible.
pins are TTL compatible. OPTA 27 These two pins are to control
T/R1 Transmit receive 1; this pin OPTB 26 the function of the 8293. A
controls the direction for truth table of how this pro-
NDAC, NRFD, DAV, and D101- grams the various modes is in
D108. Input is TTL compatible. Table 1.
T/R2 2 Transmit receive 2; this pin Vee P.S. 28 Positive power supply (5V
controls the direction for EOL 10%).
Input is TTL compatible. GND P.S. 14,20 Circuit ground potential.
Table 1. 8293 Mode Selection Pin Mapping
IEEE Implementation Name

Pin Name Pin No. Mode 0 Mode 1 Mode 2 Mode 3
OPTA 27 0 1 0 1
OPTB 26 0 0 1 1
DATA1 5 IFC DI08 IFC DI08

BUS1 12 IFC D108 IFC D108
DATA2 6 REN DI07 REN DI07
BUS2 13 REN* D107 REN DI07*
DATA3 7 NC Dl06 EOl2 DI06
BUS3 15 EOI D106 EOI D106
DATA4 8 SRO DI05 SRO DI05
BUS4 16 SRO D105 SRO D105
DATA5 9 NRFD 0{04 NRFD DI04
BUS5 17 NRFD D104 NRFD D104
DATA6 10 NDAC DI03 NDAC DI03
BUS6 18 NDAC D103 NDAC D103
DATA7 11 T/R101 NC ATNI ATNO
DATA8 23 T/RI02 DI02 ATNO DI02
BUS7 19 ATN D102 ATN* D102
DATA9 24 GI01 DAV CIC DAV
BUS8 21 G101 DAV CLTH DAV
DATA10 25 GI02 DI01 IFCL DI01
BUS9 22 G102 D101 SYC D101
T/A1 1 T/R1 T/R1 T/R1 TlR1

T/R2 2 T/R2 NC T/R2 IFCL
EOI 3 EOI EOI EOI EOI
ATN 4 ATN ATN ATN ATN
Note: These pins are the IEEE488 bus noninverting driver/receivers. They include all the bus terminations required by the Standard and may be
connected directly to the GPIB bus connector.
7-176
8293
MODEO
GENERAL DESCRIPTION
The 8293 is a bidirectional transceiver. It was designed OPTA
to interface the Intel 8291 GPIB Talker/Listener and the OPTB

Intel@ 8292 GPIB Controller to the IEEE Standard THREE
STATE ONLY
GI01 GI0 1"
488-1978. Instrumentation Bus (also referred to as the
GPIB Bus). The Intel GPIB Bus Transceiver meets or ex- TIRI01
THREE
ceeds all of the electrical specifications defined in the STATE ONLY
GI02 GI02"
IEEE Standard 488-1978, Section 3.3-3.5, including the
required bus termination specifications. TIRI02
iF(: INPUT ONLY

IFC"
The 8293 can be hardware programmed to one of four
modes of operation. These modes allow the 8293 to be
INPUT ONLY
configured to support both a Talker/Listener/Controller REN REN"
environment and Talker/Listener environment. In addi-

tion, the 8293 can be used as a general purpose three- INPUT ONLY
ATN ATN"
state (push-pull) or open-collector bus transceiver with
nine receiver/drivers. Two modes are used to support a OPEN COL
Talker/Listener environment (see Figure 1), and to sup- OUTPUT ONLY
SRO SRO"
port a Talker/Listener/Controller environment (see
Figure 2). Mode 1 is the general purpose mode. THREE
STATE ONLY
EOI EOI"
TIR2
GPIB
NRFD
OPTA
OPTB NDAC
12 8293
Tlih
MODE 1
TO
PROCESSOR
TIC 1 =THREE STATE
0= OPEN COLLECTOR 3 =+5V
BUS
14 8291 18 SIR 1 = SEND TO GPIB
0= RECEIVE FROM GPIB
-& =OV
" = IEEE488 BUS NONINVERTING DRIVERIRECEIVER
OPTA Figure 3. Talker/Listener Control Configuration

OPTB
8293
MODE 0 PIN DESCRIPTION
MODEO
Symbol I/O Pin No. Function
GPIB T/R1 Transmit receive 1; direction

control for NOAC and NRFO. If
Figure 1_ Talker/Listener Configuration T/R1 is high, then NOAC* and
NRFO* are receiving. Input is
TTL compatible.
GPIB
I/O 10 Not Oata Accepted; processor
GPIB bus handshake control
line; used to indicate the con-
TO dition of acceptance of data
PROCESSOR by device(s). It is TTL compati-
BUS
ble.
NOAC* I/O 18 Not Oata Accepted; IEEE
GPIB bus handshake control
line. When an input, it is a TTL
compatible Schmitt-trigger.
TO When an output, it is an open-
PROCESSOR collector driver with 48 mA
BUS
sinking capability.
I/O 9 Not Ready For Oata; proc-
essor GPIB handshake control
line; used to indicate the con-
GPIB dition of readiness of de-
vice(s) to accept data. This pin
Figure 2. Talker/Listener/Controller Configuration is TIL compatible.
7-177
8293
Symbol I/O Pin No. Function Symbol I/O Pin No. Function
NRFO" 110 17 Not Ready For Data; IEEE o 5 Interface Clear; processor
GPIB bus handshake control GPIB bus contiolline; used by
line, When an input, it is a TTL a controller to place the inter-
compatible Schmitttrigger. face system into a known
When an output, it is an open- quiescent state. It is a TTL
collector driver with a 48 mA compatible output.
current sinking capability. IFC* 12 Interface Clear; IEEE GPIB
T/R2 2 Transmit receive 2; direction bus control line. This input is
control for EOL If T/R2 is high, a TTL compatible Schmitt-
EOI* is sending. Input is TTL trigger.
compatible. T/RI01 11 Transmit receive General 10;
1/0 3 End or Identify; processor T/RI02 23 direction control for the two
GPIB bus control line; is used spare transceivers. Input is
by a talker by indicate the end TTL compatible.
of a multiple byte transfer. 110 24 General 10; this is the TTL
This pin is TTL compatible. 110 25 side of the two spare tran-
EOI" 1/0 15 End or Identify; IEEE GPIB bus sceivers. These pins are TTL
control line; is used by a talker compatible.
to indicate the end of a multi- 110 21 General 10; these are spare
G101*
ple byte transfer. This pin is a G102* 110 22 three-state (push-pull) driversl
three-state (push-pull) driver Schmitt-trigger receivers. The
capable of sinking 48 mA and drivers can sink 48 mAo
a TTL compatible receiver
with hysteresiS.
8 Service Request; processor
GPIB bus control line; used by MODEl
a device to indicate the need

OPTA
for service and to request an
interruption of the current se- OPTB
quence of events on the GPIB.
It is a TTL compatible input
SRQ* o 16 Service Request; IEEE GPIB
bus control line; it is an op~n
collector driver capable of
sinking 48 mAo
o 6 Remote Enable; processor
GPIB bus control line; used by
a controller (in conjunction
with other messages) to
select between two alternate
sources of device program-
ming data (remote or local
control). This output is TTL
compatible.
REN* 13 Remote Enable; IEEE GPfB
bus control line. This input is
a TTL compatible Schmitt-
trigger.
o 4 Attention; processor GPIB
bus control line; used by the
8291 to determine how data
on the 010 signal lines are to DTOa t - - - - - - - + - t
be interpreted. This is a TTL ATN
compatible output. EOi
ATN* 19 Attention; IEEE GPIB bus con-

trol line; this input is a TTL
compatible Schmitt-trigger. Figure 4. Talker/Listener Data Configuration
7178
8293
MODE 1 PIN DESCRIPTION MOOE2
OPTA
Symbol I/O Pin No. Function OPTB
T/R1 Transmit receive 1; controls NOAC NOAC"

the direction for DAV and the
DIO lines. If T/R1 is high, then
all these lines are sending in- NImi NRFO"
formation to the IEEE GPIB
TlR1
lines. This input is TTL com-
patible. ~ IFC"
SYC
RE"R REN"
3 End of Sequence and Atten-
4 tion; processor GPIB control
lines. These two control SRO"
SRO
signals are ANDed together to
determine whether all the
transceivers in the 8293 are A'i'Ni
ATN"
AfR
three-state (push-pull) or
open-collector. When both
signals are low (true), then the Ern2 EOI"
controller is performing a A'ftm
parallel poll and the tran-
sceivers are all open- EOi
collector. These inputs are T/R2
TTL compatible.
IFCL J--................
1/0 24 Data Valid; processor GPIB CLTH r----..._
bus handshake control line; CIC r - - - -........- '
used to indicate the condition
(availability and validity) of in-
formation on the DIO signals. Figure 5. Talker/Listener/Controller Control
It is TTL compatible. Configuration
DAV* 1/0 21 Data Valid; IEEE GPIB bus MODE 2 PIN DESCRIPTION
handshake control line. When
an input, it is a TTL compati- Symbol I/O Pin No. Function
ble Schmitt-trigger. When
DAV* is an output, it can sink T/R1 Transmit receive 1; direction
48 mA. control for NDAC and NRFD.
If T/R1 is high, then NDAC and
NRFD are receiving. Input is
1/0 25,23, Data InputlOutput; processor TTL compatible.
10,9, GPIB bus data lines; used to 1/0 10 Not Data Accepted; processor
8,7, carry message and data bytes GPIB bus handshake control
6,5 in a bit-parallel byte-serial line; used to indicate the con-
form controlled by the three dition of acceptance of data
handshake signals. These by device(s). This pin is TTL
lines are TTL compatible. compatible.
NDAC* 1/0 18 Not Data Accepted; IEEE
D101* 1/0 22, 19, Data Input/Output; IEEE GPIB GPIB bus handshake control
D108* 18,17, bus data lines. They are TTL line. It is a TTL compatible
16, 15, compatible Schmitt-triggers Schmitttrigger when used for
13, 12 when used for input and can input and an open-collector
sink 48 mA when used for out- driver with a 48 mA current
put. See ATN and EOI descrip- sink capability when used for
tion for output mode. output.
7-179
8293
Symbol 1/0 Pin No. Function Symbol I/O Pin No. Function
NRFO I/O 9 Not Ready For Data; processor is recognized by the 8292.
GPI8 bus handshake contiOl This input is TTL compatible.
line; used to indicate the con o 25 IFC Received Latched; the
dition of readiness of device(s) 8292 monitors the IFC line
to accept data. This pin is TTL when it is not the active con-
compatible. troller through this pin.
NRFO* 1/0 17 Not Ready For Data; IEEE 1/0 8 Service Request; processor
GPIB bus handshake control GPIB control line; indicates
line. It is a TTL compatible the need for attention and re-
Schmitttrigger when used for quests the active controller to
input and an open-collector interrupt the current sequence
driver with a 48 mA current of events on the GPIB bus.
sink capability when used for This pin is TTL compatible.
output.
SRO* I/O 16 Service Request; IEEE GPIB
SYC 22 System Controller; used to bus control line. When used
monitor the system controller as an input, this pin is a TTL
switch and control the direc- compatible Schmitt-trigger.
tion for IFC and REN. This pin When used as an output, it is
is a TTL compatible input. an open-collector driver with a
REN 1/0 6 Remote Enable; processor 48 mA current sinking capa-
GPIB control line; used by the bility.
active controller (in conjunc- T/R2 2 Transmit receive 2; controls
tion with other messages) to the direction for EOL This in-
select between two alternate put is TTL compatible.
sources of device program-
23 Attention Out; processor
ming data (remote or local con-
trol). This pin is TTL compa- the 8292 for ATN control of
tible. the IEEE bus during "take
REN* 1/0 13 Remote Enable; IEEE GPIB control synchronously" opera-
bus control line. When used as tions. A low on this input
an input, this is a TTL compati- causes ATN to be asserted if
ble Schmitt-trigger. When an CIC indicates that this 8292 is
output, it is a three-state driver in charge. ATNO is a TTL com-
with a 48 mA current sinking patible input.
capability. o 11 Attention In; processor GPIB
IFC 1/0 5 Interface Clear; processor bus control line; used by the
GPIB bus control line; used by 8292 to monitor the ATN line.
the active controller to place This output is TTL compatible.
the interface system into a
known quiescent state. This
o 4 Attention; processor GPIB
bus control live; used by the
pin is TTL compatible. 8292 to monitor the ATN line.
IFC* 1/0 12 Interface Clear; IEEEGPIB bus This output is TTL compatible.
control line. This is a TTL com- ATN* I/O 19 Attention; IEEE GPIB bus con-
patible Schmitt-trigger when trol line; used by a controller
used for input and a three- to specify how data on the
state driver capable of sinking 010 signal lines are to be in-
48 mA current when used for terpreted and which devices
output. must respond to data. When
24 Controller in Charge; used to used as an output, this pin is a
control the direction of the three-state driver capable of
SRO and to indicate that the sinking 48 rnA current. As an
8292 is in charge of the bus. input, it is a TTL compatible
CiC is a TTL compatible input. Schmitt-trigger.
CLTH 21 Clear Latch; used to clear the I/O 7 End or Identify 2; processor
IFC Received latch after it has GPIB bus control line; used in
been recognized by the 8292. conjunction with ATN by the
Normally low (except after active controller (the 8292) to
a hardware reset), it will be execute a polling sequence.
pulsed low when IFC Received This pin is TTL compatible.
7-180
8293
Symbol I/O Pin No. Function MODE 3 PIN DESCRIPTION
I/O 3 End or Identify; processor Symbol I/O Pin No. Function

a talker to indicate the end of
TiR1 Transmit receive 1; controls
the direction for DAV and the
a multiple byte transfer se
010 lines. If T/R1 is high, then
quence. This pin is TTL com
all these lines are sending
patible.
information to the IEEE GPIB
lines. This input is TTL com-
EOI I/O 15 End or Identify; IEEE GPIB bus patible.
control line; used by a talker 3 End of Sequence and Atten-
to indicate the end of a multi- 4 tion; processor GPIB control
ple byte transfer sequence or, lines. These two control lines
by a controller in Conjunction are ANDed together to deter-
with ATN, to execute a polling mine whether all the tran-
sequence. Whel'l an output, sceivers in the 8293 are push-
this pin can sink 48 mA cur- pull or open-collector. When
rent. When an input, it is a TTL both signals are low (true),
compatible Schmitt-trigger. then the controller is perform-
i ng a parallel poll and the
transceivers are all open-
collector. These inputs are
TTL compatible.
23 Attention Out; processor
GPIB control line; used by the
MODE3
8292 during "take control syn-
OPTA
chronously" operations. This
pin is TTL compatible.
OPTS
2 Interface Clean Latched; used
DAV to make DAV received after the
system controller asserts IFC.
TiRl This input is TTL compatible.
010 1 1 - - - - - - + - 1 I/O 24 Data Valid; processor GPIB
handshake control line; used
to indicate the condition
0102 1 - - - - - - + - 1 (availability and validity) of in-
formation on the 010 signals.
This pin is TTL compatible.
0 103 1 - - - - - - + - 1
DAV I/O 21 Data Valid; IEEE GPIB hand-
shake control line. When an
0104 1 - - - - - - + - 1 input, this pin is a TTL com-
patible Schmitt-trigger. When
010 5 1 - - - - - - + - 1
DAV is an output, it can sink
48 mA.
I/O 25,23, Data Inp~t/Output; processor
0106 ...------+~
10,9, GPIB bus data lines; used to
8,7, carry message and data bytes
6, 5 in a bit-parallel byte-serial
form controlled by the three
handshake signals. These
OIOS ~-----+-t lines are TTL compatible.
EOi 0101- I/O 22,19, Data Input/Output; IEEE GPIB
ATN 0108 18,17, bus data lines. They are TTL
16, 15, compatible Schmitt-triggers
13, 12 when used for input and can
sink 48 mA when used for out-
put.
Figure 6. Talker/Listener/Controller Data

Configuration
7-181
8293
8293
25
0101 0101 -1922
23
0102 0102 -
10
9
DT03 0103 -17
18
0104 0104 I--

TO
8291
8
7
0105 0105 -16
15
IEEE488
BUS
- 12 DO Di01 ~ 0106 0106 -
6
- 13 01 0102 ~ 0107 0107 -1312
~ 02 0103
30 5
0108 0108 -21
- 1516 03 0104
31 24
OAV OAV -
- 04 Di05
32 1
T/Rl OPTA E- Vee
-
17
05 0106
33
34
4
ATN OPTB -26
GNO
--.!!. 06 0107
3
,.---- EOI
....!! 07 35 MODEl
TO 0108
MICROPROCESSOR 36
INTERFACE
2 cs OAV
1
2 AD T/Rl
10 26
- WR ATN
39
8293
3
--.!.!. INT EOI EOI EOI ~
3 2 ~ ATN
- CLOCK T/R2 ATN ~
~ RESET 38 1
NOAC T/Rl
2 37 2
OREO NRFO T/R2
TO
-2
GPIB TRIGGER OUTPUT" -2.. TRIG
OACK SRO
27
25
10
9
NOAC
NRFO
NOAC
NRFO
-18
.E...
IEEE488
BUS
REN
IFC
24 I 8
SRO SRO r-!!..
6
REN REN ,..!.!..
5
IFC IFC r-!!..
OPTA ~ GNO
OPTB ~ GNO
MOOEO
= GPIB BUS TRANSCEIVER
Figure 7. 8291 and 8293 System Configuration
7-182
8293
TO MICROPROCESSOR
~ -0101 28 25
DO 0101 0101" rE-
~~ 01 -
0102
29 23
0102 0102" ~
t-~ 02
0103
30 10
0103 0103" ~
15
03 31 9
16
04
0104 0104 0104" ~
32 8
17
05 0105 0105 0105" ~ TO
7 IEEE488
18
06 0106
33
0106 0106" ~ BUS
19
0107" ~
34 6
07 0107 0107
21 8291 5 8293
Dl08'- ~
RSO 35
0108 0108
22
RS1 1 1
23 TlR1 Tlih
RS2
~
36 24
9 OAV OAV OAV"
Flo 39 3
10 EOI EOI
WR
4 26 4
TO RESET ATN ATN
6 27
MICROPROCESSOR OREO SRO
7
OACK 24
8 IFC
Cs 38
3 NOAC
CLOCK 37
11 NRFO
INT
TlR2
2
.....--2.!.. ATNO OPTA ~ Vee
GPIB
TRIGGER
5
TRIG REN 12-1-1- .-!. IFCL OPTB ~ Vee
OUTPUT MODE 3
..E.. DO OAV ,E. ' - I - .-!.. T/R1

~ 01 4
ATN
~ 02 10 -- 18
NOAC NDAC I - -
~ 03
16
9
NFRO NRFO ~
04 2
17 T/R2
05
~
18 21 8
SRO SRO SRO" TO
06
6 IEEE488
19
07 REN
38
REN REN" ~ BUS
9 8292 - 23 5 8293 12
AO IFC IFC IFC" I - -
8
10
RD ATNO
29 23
ATNO ATN" ~
WR
~
39 3
~
4 COUNT EOI EOI"
RESET -EOl2 34 7
6 EOl2
Cs 22 11
32 ATNI ATNI
TCI
MICROPROCESSOR
TO I 33
35
36
SPI
OBFI
IBFI
OSCILLATOR 11
SYNC
OUTPUT
Vee~ 1 25
IFCL IFCL
~ X,
CIC
31 24
CIC
~3
r
21
X2 CLTH
27
CLTH OPTA ~ GNO
22
SYC
24
SYC OPTB ~ Vee
1525 pF
Lr ON
0FF
1.
SYSTEM
CONTROLLER
SWITCH
MOOE2
" = GPIB BUS TRANSCEIVER
Figure 8. 8291,8292, and 8293 System Configuration
7-183
8293
Absolute Maximum Ratings

Ambient Temperature Under Bias ......... 0 C to 70C 'COMMENT: Stresses above those listed under "Abso/ute Maximum
Storage Temperature ............. - 65C to + 150C Ratings" may cause permanent damage to the device. This is a stress
rating only and functlona! operation of the device at these or any orne;
Voltage on any Pin with conditions above those indicated in the operational sections of this
Respect to Ground ................. - 1.0V to + 7V specification is not implied. Exposure to absolute maximum rating con-
Power Dissipation .......................... 1 Watt ditions for extended periods may affect device reliability.
D.C. and Operating Characteristics

TA=OC to 70C; VCC= 5.0V 10%; GND= OV
LIMITS
SYMBOL PARAMETER UNIT TEST CONDITIONS
MIN. TYP. MAX.
V IL1 Input Low Voltage (GPIB Bus Pins) 0.8 V

VIL2 Input Low Voltage (Option Pins) -0.1 0.1 V
V IL3 Input Low Voltage (All Others) 0.8 V
V IH1 Input High Voltage (GPIB Bus Pins) 2.0 V
VIH2 Input High Voltage (Option Pins) 4.5 5.5 V
V IH 3 Input High Voltage (All Others) 2.0 V
VOL1 Output Low Voltage (GPIB Bus Pins) 0.5 V IOL=48 mA
VOL2 Output Low Voltage (All Others) 0.5 V IOL= 16 mA
VOH1 Output High Voltage (GPIB Bus Pi,ns) 2.4 V IOH= -5.2 mA
VOH2 Output High Voltage (All Others) 2.4 V IOH= -400 IJA
VIH4 Receiver Input Hysteresis 400 600 mV
. High to Low 0.8 1.0
VIT Receiver Input Threshold Low to High V
1.6 2.0
IU1 Low Input Load Current (GPIB Bus Pins) -3.2 0.0 mA V IL=0.8V
IU2 Low Input Load Current (All Others) 10 IJA VIL=0.8V
Ipo Bus Power Down Leakage Current 10 IJA Vcc= OV
Capacitance
SYMBOL PARAMETER MIN. TYP. MAX. UNIT TEST CONDITIONS
CIN Input Capacitance 5 10 pF V IN = Vee

C OUT Output Capacitance 10 20 pF VouT=Vee
7184
8293
A.C. Characteristics
TA=OC to 70C; Vcc =5.0V 10%; GND=OV
SYMBOL PARAMETER TYP.* MAX. UNITS
tpLH1 Driver Propagation Delay (Low to High) 20 35 ns

t pHL1 Driver Propagation Delay (High to Low) 17 30 ns
tpLH2 Receiver Propagation Delay (Low to High) 22 35 ns
tpH L2 Receiver Propagation Delay (High to Low) 18 30 ns
t PHZ1 Driver Enable Delay (High to 3State) 20 35 ns
t pZH1 Driver Enable Delay (3State to High) 15 30 ns
t pLZ1 Driver Enable Delay (Low to 3State) 20 35 ns
tpZL1 Driver Enable Delay (3State to Low) 15 30 ns
t PHZ2 Receiver Enable Delay (High to 3State) 25 40 ns
t pZH2 Receiver Enable Delay (3State to High) 20 35 ns
tpLZ2 Receiver Enable Delay (Low to 3State) 25 40 ns
tpZL2 Receiver Enable Delay (3State to Low) 20 35 ns
"Typical @ TA = 25C.
6.0 5.0 , . - - - - , - - - , - - - , - - - , - - - , - - - " T " " " - - r - - - - .

I
--
4.0
I
fii 40 r - - - - vcc ~ 5.0 v-+--~r:::::1~~~::::~:::1
<"
2.0
I ~ g . TA=25C
.. ~
I-
z -2.0 ,.- " .
~
J
I w
~ 3.0 1 - - - + - - + - - + - - + - - + - - - + - + - - + - - - /
'"a:a: -4.0 ~ !:i
o
:;) I >
U -6.0
II) ~ 2.0 r--+--+--+--f--+--~f---+----I
:;)
NONSHADED AREA Q.
III -8.0 CONFORMS TO - I-
:;)
PARAGRAPH 3.5.3 OF
j -10 IEEE STANDARD
- ~ 1.01---+--+--+--+--+----+-+--+---/
-12 488 1978 - ~
Vcc=5.0V
-14
-4.0 -2.0 -0 2.0 4.0 6.0
U 1~ 1~ 2.0
VBUS, BUS VOLTAGE (VOLTS) VI, INPUT VOLTAGE (VOLTS)
Figure 9. Typical Bus Load Line Figure 10. Typical Receiver Hysteresis Characteristics
7185
8293
OUTPUT LOADING TEST CIRCUITS
TO SCOPE TO SCOPE
(OUTPUT) +2.3V (OUTPUT) +s.OV
38.3Q 240Q
BUS DATA
IN916
C, fOp, OR EQUIV.
CL INCLUDES JIG AND PROBE CAPACITANCE CL INCLUDES JIG AND PROBE CAPACITANCE
Figure 11. Data Input to Bus Output (Driver) Figure 12. Bus Input to Data Output (Receiver)
TO SCOPE TO SCOPE
(OUTPUT) 1.1V (OUTPUT) s.OV
280Q
BUS DATA (tpLZ2 tPZL2)
(tPHZ1. tPZH1) (tpHZ2. IpZH2)
f f
480Q 3 KQ
CL INCLUDES JIG AND PROBE CAPACITANCE CL INCLUDES JIG AND PROBE CAPACITANCE
Figure 13. Send/Receive Input to Bus Output (Driver) Figure 14. Send/Receive Input to Data Output (Receiver)
7~186
8293
8293 WAVEFORMS
tRISE = tFALL '" 5 ns

3.0V DUTY CYCLE 50%=
INPUT 1.5V 1.5V
OV
tpLHl
OUTPUT
(DRIVER PROP. DELAY) 2.0V
FIGURE 11 LOAD
tpLH2
OUTPUT
(RECEIVER PROP. DELAY) 1.5V
FIGURE 12 LOAD
tPZH1
OUTPUT I----------voH------+_----~
(DRIVER ENABLE DELAY 2.0V
WITH INPUT HIGH)
FIGURE 13 LOAD VZ== 1.0V
tPZL1
OUTPUT VZ== 1.13V
(DRIVER ENABLE DELAY
WITH INPUT LOW) O.SV
FIGURE 13 LOAD
OUTPUT
(RECEIVER ENABLE DELAY
-- tPZH2
I~---------VOL------+---~~
~--------VOH------+---~~
Inur
WITH INPUT HIGH) 1.5V
FIGURE 14 LOAD OV
OUTPUT
(RECEIVER ENABLE DELAY
I"" t:- 5V
WITH INPUT LOW) 1.5V

FIGURE 14 LOAD '-------VOL------------.;;lIj.10%
7187
8294
DATA ENCRYPTION UNIT
Certified by National Bureau of 7Bit User Output Port
Standards
Single 5V 100/0 Power Supply
SO Byte/Sec Data Conversion Rate
Peripheral to MCSS6, MCSS5,
64Bit Data Encryption Using 56Bit MCSSOTM and MCS48 Processors
Key
DMA Interface Implements Federal Information

Processing Data Encryption Standard
3 Interrupt Outputs to Aid in Loading
and Unloading Data Encrypt and Decrypt Modes Available
DESCRIPTION
The Intel@ 8294 Data Encryption Unit (DEU) is a microprocessor peripheral device designed to encrypt and decrypt
64-bit blocks of data using the algorithm specified in the Federal Information Processing Data Encryption Standard.
The DEU operates on 64-bit text words using a 56-bit user-specified key to produce 64-bit cipher words. The operation
is reversible: if the cipher word is operated upon, the original text word is produced. The algorithm itself is perma-
nently contained in the 8294; however, the 56-bit key is user-defined and may be changed at any time.
The 56-bit key and 64-bit message data are transferred to and from the 8294 in 8-bit bytes by way of the system data
bus. A DMA interface and three interrupt outputs are available to minimize software overhead associated with data
transfer. Also, by using the DMA interface two or more DEUs may be operated in parallel to achieve effective system
conversion rates which are virtually any multiple of 80 bytes/second. The 8294 also has a 7-bit TTL compatible output
port for user-specified functions.
Because the 8294 implements the NBS encrypti'on algorithm it can be used in a variety of Electronic Funds Transfer
applications as well as other electronic banking and data handling applications where data must be encrypted.
PIN
CONFIGURATION BLOCK DIAGRAM
VCC
DATA
Xl NC
BUS
X2
RESET ORQ
NC SRQ
cs OAV
NC
AD P6
AO P5 Ao
WR P4 SRO
P3 OAY
CCMP
Po'Ps
"m~
02
03 VOO
NC SYNC
NC X,
NC X2 TIMING
+5Y--
POWER-- INTERNAL
BUS
GNO--
7-188 002308
inter
8295
DOT MATRIX PRINTER CONTROLLER
Interfaces Dot Matrix Printers to Programmable Print Intensity

MCS-4S, MCS-SOISS, MCS-S6
Systems
Single or Double Width Printing
40 Character Buffer On Chip
Serial or Parallel Communication with Programmable Multiple Line Feeds
Host
DMA Transfer Capability 3 Tabulations
Programmable Character Density (10 or
12 Chararcters/lnch) 2 General Purpose Outputs
The Intel@ 8295 Dot Matrix Printer Controller provides an interface for microprocessors to the LRC 7040 Series dot
matrix impact printers. It may also be used as an interface to other similar printers.
The chip may be used in a serial or parallel communication mode with the host processor. In parallel mode, data
transfers are based on polling, interrupts, or DMA. Furthermore, it provides internal buffering of up to 40 characters
and contains a 7 x 7 matrix character generator accommodating 64 ASCII characters.
PIN
CONFIGURATION BLOCK DIAGRAM
INTERNAL
BUS
7-189 002318
8295
PIN DESCRIPTION
Name 110 Pin# Description Name iiO Pin;; Descripiion
PFEED Paper feed input switch. HOME 39 Home input switch, used by the
XTAL1 2 Inputs for a crystal to set internal 8295 to detect that the print head
XTAL2 3 oscillator frequency. For proper is in the home position.
operation use 6 MHz crystal. DACK/SIN 38 In the parallel mode used as DMA
acknowledgement; in the serial
4 Reset input, active low. After
mode, used as input for data.
reset the 8295 will be set for 12
characters/inch single width DRQ/CTS 0 37 In the parallel mode used as DMA
printing, solenoid strobe at 320 request output pin to indicate to
msec. the 8257 that a DMA transfer is re-
quested; in the serial mode used
NC 5 No connection or tied high. as clear-to-send signal.
CS 6 Chip select input used to enable IRQ/SER o 36 In parallel mode it is an interrupt
the RD and WR inputs except dur- request input to the master CPU;
ing DMA. in serial mode it should be
GND 7 This pin must be tied to ground. strapped to Vss.
RD 8 Read input which enables the MOT o 35 Main motor drive, active low.
master CPU to read data and STB o 34 Solenoid strobe output. Used to
status. In the serial mode this pin determine duration of solenoids
must be tied to Vee. activation.
Vee 9 + 5 volt power input: + 5V 10%. o 33 Solenoid drive outputs; active
32 low.
WR 10 Write input which enables the
31
master CPU to write data and
30
commands to the 8295. In the
29
serial mode this pin must be tied
28
to Vss.
27
SYNC o 11 2.5 '"'s clock output. Can be used
26 + 5V power input (+ 5V 10%).
as a strobe for external circuitry.
Low power standby pin.
Do I/O 12 Three-state bidirectional data bus
13 buffer lines used to interface the NC 25 No connection.
D1
D2 14 8295 to the host processor in the GP1 o 24 General purpose output pins.
D3 15 parallel mode. In the serial mode
16 Do- D2 sets up the baud rate.
GP2 o 23
D4
D5 17 TOF 22 Top of form input, used to sense
D6 18 top of form signal for type T
D7 19 printer.
GND 20 This pin must be tied to ground. o 21 Paper feed motor drive, active
Vee 40 + 5 volt power input: + 5V 10%. low.
7-190 002316
8295
FUNCTIONAL DESCRIPTION Communication between the 8295 and the host proc-
essor can be implemented in either a serial or parallel
mode. The parallel mode allows for character transfers
The 8295 interfaces microcomputers to the LRC 7040 into the buffer via DMA cycles. The serial mode features
Series dot matrix impact printers, and to other similar selectable data rates from 110 to 4800 baud.
printers. It provides internal buffering of up to 40 char- The 8295 also offers two general purpose output pins
acters. Printing begins automatically when the buffer is which can be set or cleared by the host processor. They
full or when a carriage return character is received. It can be used with various printers to implement such
provides a modified 7x7 matrix character generator. The functions as ribbon color selection, enabling form
character set includes 64 ASCII characters. release solenoid, and reverse document feed.
COMMAND SUMMARY
Hex Code Description Hex Code Description
00 Set GP1. This command brings the GP1 pin 09 Tab character.
to a logic high state. After power on it is
OA Line feed.
automatically set high.
01 Set GP2. Same as the above but for GP2. OB Multiple Line Feed; must be followed by a
byte specifying the number of line feeds.
02 Clear GP1. Sets GP1 pin to logic low state,
inverse of command 00. OC Top of Form. Enables the line feed output
until the Top of Form input is activated.
03 Clear GP2. Same as above but for GP2. In-
verse command 01. 00 Carriage Return. Signifies end of a line and
04 Software Reset. This is a pacify command. enables the printer to start printing.
This command is not effective immediately OE Set Tab #1, followed by tab position byte.
after commands requiring a parameter, as
the Reset command will be interpreted as a OF Set Tab #2, followed by tab position byte.
parameter. Should be greater than Tab #1.
05 Print 10 characterslin. density. 10 Set Tab #3, followed by tab position byte.
Should be greater than Tab #2.
06 Print 12 characterslin. density.
07 Print double width characters. This com- 11 Print Head Home on Right. On some
mand prints characters at twice the normal printers the print head home position is on
width, that is, at either 17 or 20 characters the right. This command would enable nor-
per line. mal left to right printing with such printers.
08 Enable DMA mode; must be followed by 12 Set Strobe Width; must be followed by
two bytes specifying the number of data strobe width selection byte. This command
characters to be fetched. Least significant adjusts the duration of the strobe activa-
byte accepted first. tion.
PROGRAMMABLE PRINTING OPTIONS 07-03 02 01 DO Solenoid On

CHARACTER DENSITY (mlcrosec)
The character density is programmable at 10 or 12 char- x 0 0 0 200

acterslinch (32 or 40 characterslline). The 8295 is auto- x 0 0 1 240
matically set to 12 characterslinch at power-up. Invoking x 0 1 0 280
the Print Double-Width command halves the character x 0 1 1 320
density (5 or 6 characterslinch). The 10 charlin or 12 x 1 0 0 360
char/in command must be re-issued to cancel the x 1 0 1 400
Double-Width mode. Different character density modes x 1 1 0 440
may not be mixed within a single line of printing. x 1 1 1 480
PRINT INTENSITY Table 1.

The intensity of the printed characters is determined by
the amount of time during which the solenoid is on. This
on-time is programmable via the Set Strobe-Width com- TABULATIONS
mand. A byte following' this command sets the solenoid Up to three tabulation positions may be specified with
on-time according to Table 1. Note that only the three the 8295. The column position of 'each tabulation is
least significant bits of this byte are important. selected by issuing the Set Tab commands, each fol-
002318
7-191
8295
lowed by a byte specifying the column. The tab posi- the 8257 DMA controller without further CPU interven-
tions will then remain valid until new Set Tab commands tion. Figure 2 shows a block diagram of the 8295 in DMA
are issued. mode.
Sending a tab character (09H) wiii automaticaiiy fiii the
character buffer with blanks up to the next tab position.
The character sent immediately after the tab character
will thus be stored and printed at that position.
CPU TO 8295 INTERFACE

Communication between the CPU and the 8295 may
take place in either a serial or parallel mode. However,
the selection of modes is inherent in the system hard-
ware; it is not software programmable. Thus, the two
modes cannot be mixed in a single 8295 application.
PARALLEL INTERFACE
Two internal registers on the 8295 are addressable by
the CPU: one for input, one for output. The following
table describes how these registers are accessed.
DONE
RD WR CS Register
Figure 1. Host to 8295 Protocol Flowchart
100 Input Data Register
010 Output Status Register
8257
Input Data Register-Data written to this register is DMA
' - - - - -.. '1 CONTROLLER
interpreted in one of two ways, depending on how the
DACKx
data is coded. DROx
1. A command to be executed (OXH or lXH).
OPTIONAL
2. A character to be stored in the character buffer for
printing (2XH, 3XH, 4XH, or 5XH). See the character
set, Table 2. X, X2
Output Status Register-8295 status is available in this I/)
::;,
ID
cs DRO
register at all times. ::IE AD DACK
....w
I/)
WR
>
I/) REID
STATUS BIT:
IBF
MOT
FUNCTION: PA DE
PFM
8295
PA-Parameter Required; PA = 1 indicates that a com- D7
mand requiring a parameter has been received. After the DO 57 PRINTER
necessary parameters have been received by the 8295,
the PA flag is cleared. IRO
DE-DMA Enabled; DE = 1 whenever the 8295 is in DMA PFEED

mode. Upon completion of the required DMA transfers, HOME
the DE flag is cleared.
ISF-Input Buffer Full; IBF = 1 whenever data is written Figure 2. Parallel System Interface
to the Input Data Register. No data should be written to
the 8295 when I BF = 1.
Data transferred in the DMA mode may be either com-
A flow chart describing communication with the 8295 is mands or characters or a mixture of both. The procedure
shown in Figure 1. is as follows:
The interrupt request output (IRQ, Pin 36) is available on 1. Set up the 8257 DMA controller channel by sending a
the 8295 for interrupt driven systems. This output is starting address and a block length.
asserted true whenever the 8295 is ready to receive data. 2. Set up the 8295 by issuing the "Enable DMA" com-
To improve bus efficiency and CPU overhead, data may mand (08H) followed by two bytes specifying the
be transferred from main memory to the 8295 via DMA block length (least significant byte first).
cycles. Sending the Enable DMA command (08H) acti- The DMA enabled flag (DE) will be true until the
vates the DMA channel of the 8295. This command must assigned data transfer is completed. Upon completion
be followed by two bytes specifying the length of the of the transfer, the flag is cleared and the interrupt re-
data string to be transferred (least significant byte first). quest (IRQ) signal is asserted. The 8295 then returns to
The 8295 will then assert the required DMA requests to the non-DMA mode of operation.
7-192 oo231B
8295
SERIAL INTERFACE +5
The 8295 may be hardware programmed to operate in

a serial mode of communication. By connecting the
STB
IRQ/SER pin (pin 36) to logic zero, the serial mode is
enabled immediately upon power-up. The serial Baud
rate is also hardware programmable; by strapping pins, Sf
14, 13, and 12 according to Table 2, the rate is selected.
CS, RD, and WR must be strapped as shown in Figure 3. 58
Pin 14 Pin 13 Pin 12 Baud Rate 55

TO
SOLENOID
a a a 110
8295
54 DRIVERS
a a 1 150
a 1 a 300
53
a 1 1 600 52
1 a a 1200
1 a 1 2400 51
a
I
4800 MOT
TO MOTOR
4800 DRIVERS
PFM
Table 2.
The serial data format is shown in Figure 3. The CPU Figure 4. 8295 To Printer Solenoid Interface
should wait for a clear to send signal (CTS) from the
8295 before sending data.
OSCILLATOR AND TIMING CIRCUITS
The 8295's internal timing generation is controlled by a
self-contained oscillator and timing circuit. A 6 MHz
crystal is used to derive the basic oscillator frequency.
The resident timing circuit consists of an oscillator, a
+5 state counter and a cycle counter as illustrated in Figure
5. The recommended crystal connection is shown in
Figure 6.
PRINTER
PFEED 1 - - - - - - - ;
HOME I------~
8251A TXD t---- SIN

USART CTS -1 CTS
SER
SYNC
OUTPUT
(2.5 "lee)
SERIAL
INPUT
STOP
BIT
INTERNAL TIMING
Figure 5. Oscillator Configuration
Figure 3. Serial Interface to UART (8251A)

2 XTAL1
8295 TO PRINTER INTERFACE 1-8 MHz ~ 8295
The strobe output signal of the 8295 determines the

duration of the solenoid outputs, which hold the data to .--_~~3 XTAL2
the printer. These solenoid outputs cannot drive the 2OPF~
printer solenoids directly. They should be buffered
through solenoid drivers as shown in Figure 4. Recom-
mended solenoid and motor driver circuits may be found
in the printer manufacturer's interface guide. Figure 6. Recommended Crystal Connection
7-193 OO231e
8295
8295 CHARACTER SET

Hex Code Print Char. Hex Code Print Char. Hex Code Print Char. Hex Code Print Char.
20 space 30 a 40 @ 50 P
21 31 1 41 A 51 Q
22 32 2 42 B 52 R
23 # 33 3 43 C 53 S
24 $ 34 4 44 D 54 T
25 % 35 5 45 E 55 U
26 & 36 6 46 F 56 V
27 37 7 47 G 57 W
28 38 8 48 H 58 X
29 39 9 49 I 59 y
2A 3A 5A J 5A Z
2B + 3B 4B K 5B [
2C 3C < 4C L 5C \
2D 3D 4D M 5D 1
2E 3E > 4E N 5E t
2F 3F ? 4F 0 5F

a
Ambient Temperature Under Bias ......... C to 70 C 'COMMENT: Stresses above those listed under "Absolute Maximum
Storage Temperature ............... - 65 to + 150 C Ratings" may cause permanent damage to the device. This is a stress
Voltage on Any Pin With conditions above those indicated in the operational sections of this
Respect to Ground ................... 0.5V to + 7V specification is not implied. Exposure to absolute maximum rating con
Power Dissipation ......................... 1.5 Watt ditions for extended periods may affect device reliability.

T A = OC to 70C, Vee = Voo= +5V 10%, Vss= OV
Limits
Min. Typ. Max.
VIL Input Low Voltage (All -0.5 0.8 V
Except X1, X2, RESEl)
VIL1 Input Low Voltage (X h X2, -0.5 0.6 V
RESEl)
VIH Input High Voltage (All 2.2 Vee V
Except X1, X2, RESEl)
VIH1 Input High Voltage (X 1, X2, 3.8 Vee V
RESEl)
VOL Output Low Voltage (Do- D 7) 0.45 V IOL=2.0mA
VOl1 Output Low Voltage (All 0.45 V 10L= 1.6mA
Other Outputs)
VOH Output High Voltage (00- 0 7) 2.4 V 10H= -400",A
VOH1 Output High Voltage (All 2.4 V 10H= -50",A
Other Outputs)
IlL Input Leakage Current 10 !lA Vss ~ VIN ~ Vee
(RD, WR, CS, A~
loz Output Leakage Current 10 !lA Vss+O.45~ VIN~ Vee
(Do-D7' High Z State)
100 Voo Supply Current 5 15 mA
100+ lee Total Supply Current 60 125 mA
lu Low Input Load Current 0.5 mA VIL=0.8V
(Pins 24, 27-38)
IU1 Low Input Load Current 0.2 mA VIL= 0.8V
(RESET)
7-194 002318
8295
TA=OC to 70C, Vcc=Voo= +5V 10%, VSS=OV
DBB READ
tAR CS, Ao Setup to RD + 0 ns
tRA CS, Ao Hold After RD t 0 ns
tAD CS, Ao to Data Out Delay 225 ns C L = 150 pF
tRO RD +to Data Out Delay 225 ns C L = 150 pF
tOF RD t to Data Float Delay 100 ns
tCY Cycle Time 2.5 15 ",s
DBB WRITE
tAW CS, Ao Setup to WR + 0 ns
tWA CS, Ao Hold After WR t 0 ns
tow Data Setup to WR t 150 ns
two Data Hold to WR t 0 ns
DMA AND INTERRUPT TIMING

tAcc DACK Setup to Control 0 ns
tCAC DACK Hold After Control 0 ns
tCRQ WR to ORO Cleared 200 ns
tACO DACK to Data Val id 225 ns
7-195 002318
8295
WAVEFORMS
1. READ OPERATIC~J - OUTPUT BUFFER REGISTER.
CS OR Ao ). K (SYSTEM'S
ADDRESS BUS)
-'AR,
- 'RR /- 'RA--
\ ~ (READ CONTROL)
--'RO-- '-'OF1
DATA OUs
(OUTPUT)
'AD -=j
-------------(j--DATAVALD---=v--------------
J)
2. WRITE OPERATION - INPUT BUFFER REGISTER.
~--"'11---'ww-------O.~-_'WA-+"-----
~
(SYSTEM'S
CS OR AO ADDRESS BUS)
- - _- _- _
WR '{ (WRITE CONTROL)
~------------'-Ow-------- - - 'WO
DATA BUS _ _ _ _ _ _ DATA

(INPUn
) _ - DATA VALID
_ _ _ _ _ _- - J
MAY CHANGE
--K ~_ _ _ _ _ _ _ MAY
DATA
_ _CHANGE
_ _ _ _ _ _ _ _ __ _
DMA AND INTERRUPT TIMING

,
1\
f--'ACC-
~
IcAC-
II
-
~ J
ORO
'CRO
}
D:~: ~---- --------V_AL_ID--------------J)(~--------------
-'ACO
_________________ __
7-196 002318
8295
PRINTER INTERFACE TIMING AND WAVEFORMS
MOTOR DRIVE
\ )
V
HOME
I , ....
J \
SOLENOID DATA
) K
- -SDS
- MHH ~
r--'~~U
.(\.
SOLENOID STROBE
J
I-- PDH--
Symbol Parameter Typical

POH Print delay from 1.8 ms
home inactive
--
Sos Solenoid data 25,..s
setup time before
strobe active
SHS Solenoid data >1 ms

hold after strobe
inactive
MHA Motor hold time

3.2 ms
after home active
PSP PFEED setup time 58 ms
after PFM active
PHP PFM hold time 9.75 ms
after PFEED active
7197 002318
inter
2ii4A
1024 X 4 BIT STATIC RAM
2114AL-1 2114AL-2 2114AL-3 2114AL-4 2114A-4 2114A-5
Max. Access Time (ns) 100 120 150 200 200 250
Max. Current (mA) 40 40 40 40 70 70
HMOS Technology orCompletely Static Memory - No Clock

Timing Strobe Required
Low Power, High Speed
Directly TTL Compatible: All Inputs
Identical Cycle and Access Times

and Outputs
Common Data Input and Output Using
Single +5V Supply 10% Three-State Outputs
High Density 18 Pin Package 2114 Upgrade
The Intel@! 2114A is a 409~bit static Random Access Memory organized as 1024 words by 4-bits using HMOS, a high per-
formance MOS technology. It uses fully DC stable (static) circuitry throughout, in both the array and the decoding, therefore it
requires no clocks or refreshing to operate. Data access is particularly simple since address setup times are not required. The
data is read out nondestructively and has the same polarity as the input data. Common input/output pins are provided.
The 2114A is designed for memory applications where the high performance and high reliability of HMOS, low cost, large bit
storage, and simple interfacing are important design objectives. The 2114A is placed in an 18-pin package for the highest
possible density.
It is directly TTL compatible in all respects: inputs, outputs, and a single +5V supply. A separate Chip Select (CS) lead allows
easy selection of an individual package when outputs are or-tied.
PIN CONFIGURATION LOGIC SYMBOL BLOCK DIAGRAM
~ @
~ vee Ao
A3
0)
--=-- vee
A4 --ill-GND
As A7 A, 110,
As MEMORY ARRAY
A2 ROW
A4 As '1) SELECT 64 ROWS
A .- 64COLUMNS
A3 Ag ~
1/2
6@
A7
A4
Ao 110, @
As
As
A, I/~ 1/3
A6
IIO,@
~ 1/3 A7
CS 1/4 As
1/4
GND WE Ag
WE CS
PIN NAMES
AO-A9 ADDRESS INPUTS Vee POWER (+5V) o = PIN NUMBERS

wr WRITE ENABLE GND GROUND
CS CHIP SELECT
I/O, -1/04 DATA INPUT/OUTPUT
INTEL CORPORA TlON ASSUMES NO RESPONSIBILITY FOR THE USE OF ANY CIRCUITRY OTHER THAN CIRCUITRY EMBODIED IN AN INTEL PRODUCT. NO OTHER CIRCUIT PATENT LICENSES ARE IMPLIED.
c INTEL CORPORATION_ 1977. 1979 7-198 DECEMBER. 1979
2114A FAMILY

Temperature Under Bias .................. -10C to BOC *COMMENT: Stresses above those listed under "Absolute
Storage Temperature .......... , ......... -65C to 150C Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation ofthe device
Voltage on any Pin
at these or any other conditions above those indicated in the
With Respect to Ground ..... , ............ -3.5V to +7V operational sections of this specification is not implied. Ex-
Power Dissipation ................................ , 1.0W posure is not implied. Exposure to absolute maximum rating
D.C. Output Current ................................ 5mA conditions for extended' periods may affect device reliability.

TA = OC to 70C, Vee = 5V 10%, unless otherwise noted.
2114AL-1/L-2/L-3/L-4 2114A-4/-5
SYMBOL PARAMETER Min. Typ.lll Max. Min. Typ.lll Max. UNIT CONDITIONS
III Input Load Current 10 10 J1A VIN = 0 to 5.5V

(All Input Pins)
llLOI I/O Leakage Current 10 10 J1A CS = V 1H

VI/O = GND to VCC
Icc Power Supply Current 25 40 50 70 mA Vee = max, 11/0 = 0 mA,

T A = OC
VIL Input Low Voltage -3.0 0.8 -3.0 0.8 V
VIH Input High Voltage 2.0 6.0 2.0 6.0 V
10L Output Low Current 2.1 9.0 2.1 9.0 mA VOL = O.4V
10H Output High Current -1.0 -2.5 -1.0 -2.5 mA VOH = 2.4V
105[21 Output Short Circu it 40 40 mA

Current
NOTE: 1. Typical values are for T A = 25 C and Vee = 5.0V.

2. Duration not to exceed 30 seconds.
CAPACITANCE
TA = 25C, f = 1.0 MHz
SYMBOL TEST MAX UNIT CONDITIONS
ClIO Input/Output Capacitance 5 pF Vila = OV
CIN Input Capacitance 5 pF VIN = OV
NOTE: This parameter is periodically sampled and not 100% tested.
A.C. CONDITIONS OF TEST

Input Pulse Levels ................................................... O.B Volt to 2.0 Volt
Input Rise and Fall Times ...................................................... 10 nsec
Input and Output Timing Levels ................................................ 1.5 Volts
Output Load ............................................... 1 TTL Gate and C L = 100 pF
7-199
2114A FAMILY
A.C. CHARACTERISTICS TA =OC to 70C, Vee =5V 10%, unless otherwise noted,
READ CYCLE [1]
2114AL-1 2114AL-2 2114AL-3 2114A-4/L-4 2114A-5
SYMBOL PARAMETER Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. UNIT
tRe Read Cycle Time 100 120 150 200 250 ns
tA Access Time 100 120 150 200 250 ns
teo Chip Selection to Output Valid 70 70 70 70 85 ns
tex Chip Selection to Output Active 10 10 10 10 10 ns
toTO Output 3-state from Deselection 30 35 40 50 60 ns
Output Hold from 15 15 15 15 15 ns

tOHA Address Change
WRITE CYCLE [2]
2114AL-1 2114AL-2 2114AL-3 2114A-4/L-4 2114A-5

SYMBOL PARAMETER Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. UNIT
twe Write Cycle Time 100 120 150 200 250 ns
tw Write Time 75 75 90 120 135 ns
tWR Write Release Time 0 0 0 0 0 ns
tOTW Output 3-state from Write 30 35 40 50 60 ns
tow Data to Write Time Overlap 70 70 90 120 135 ns
tOH Data Hold from Write Time 0 0 0 0 0 ns
NOTES:
1. A Read occurs during the overlap of a low CS and a high WE.
2. A Write occurs during the overlap of a low CS and a low WE. tw is measured from the latter of CS or WE going low to the earlier of CS or WE going high.
WAVEFORMS
READ CYCLE@ WRITE CYCLE
1-------tRc------+I twc
1------tA-------i
ADDRESS
ADDRE~ __ ~----------------------~--'I~------ i--twA-
,\\' l\\\2 l// / / / / / / / / / / /,

tw
~\\
-tOT~
NOTES: DOUT
3. WE is high for a Read Cycle.

4. If the CS low transition occurs simultaneously with the WE low
,tow I tOH
transition, the output buffers remain in a high impedance state. 'V V'
D,N ~
5. "WE must be high during all address transitions.
7-200
2114A FAMILY
TYPICAL D.C. AND A.C. CHARACTERISTICS
NORMALIZED ACCESS TIME VS. NORMALIZED ACCESS TIME VS.

SUPPLY VOLTAGE AMBIENT TEMPERATURE
1.2 1.2
1.1 1.1
:f.
Cl
w
N
::;

~
1.0
0.9
0.8
-- r--
:f.
fil
N
::;

~
1.0
0.9
0.8
~ ---
~f-""
II: II:
0
Z
oZ
0.7 0.7
0.6 0.6
0.5 0.5
4.50 4.75 5.00 5.25 5.50 o 20 40 60 80
NORMALIZED ACCESS TIME VS. NORMALIZED POWER SUPPLY CURRENT

OUTPUT LOAD CAPACITANCE VS. AMBIENT TEMPERATURE
1.4 1.2
!
1.3
// 1. 1
/"
----r----- ----
1.2 u 1.0
S?
:f. V fil
Cl
w 1.1 ./" N
::;
0.9
N
:::;

~ 1.0
//
~
II: 0.8
r---
II: o
0 Z
z I
0.9 0.7
0.8 0.6
0.7 0.5
100 150 200 250 300 350 o 20 40 60 80
OUTPUT SOURCE CURRENT OUTPUT SINK CURRENT

VS. OUTPUT VOLTAGE VS. OUTPUT VOLTAGE
40 80
/
//
30 60
20 40
~ V
10 ~ 20
/
~
o
o
o /
o
7201
1024 X 4 BIT STATIC RAM
2142-2 2142-3 2142 2142L2 2142L3 2142L
I Max. Access Time (ns) 200 300 450 200 300 450
I Max. Power Dissipation (mw) 525 525 525 370 370 370
Access
High Density 20 Pin Package No Clock or Timing Strobe Required
I dentlcalTime Selections From 200-450ns Directly
Completely Static Memory
Low Operating
Cycle and Access Times and Outputs
TTL Compatible: All Inputs
.1mW/Blt TypicalPower Dissipation
Three-State
Common Data Input and Output Using
Single +5V Supply Outputs
The Intel@ 2142 is a 4096-bit static Random Access Memory organized as 1024 words by 4-bits using N-channel Silicon-
Gate MOS technology. It uses fully DC stable (static) circuitry throughout - in both the array and the decoding - and
therefore requires no clocks or refreshing to operate. Data access is particularly simple since address setup times are not
required. The data is read out nondestructively and has the same polarity as the input data. Common input/output pins are
provided.
The 2142 is designed for memory applications where high performance, low cost, large bit storage, and simple interfacing
are important design objectives. It is directly TTL compatible in all respects: inputs, outputs, and a single +5V supply.
The 2142 is placed in a 2o-pin package. Two Chip Selects (CS1 and CS2) are provided for easy and flexible selection of
individual packages when outputs are OR-tied. An Output Disable is included for direct control of the output buffers.
The 2142 is fabricated with Intel's N-channel Silicon-Gate technology - a technology providing excellent protection
against contamination permitting the use of low cost plastic packaging.
A3

As Vcc AO @
A4 @
-----0 Vcc
A5 A7 A, I/O,
A5
MEMORY ARRAY
A4 As A2 ROW 64 ROWS @ 0 GND
G) SELECT 64 COLUMNS
A6
A3 Ag A3
1/02 @)
CS2 00 A7
A4
@)
Ao I/O, A5 AS
1/03
A, 1/0 2 A6
1/0,
A2 1/03 A7
cs, 1/04 AS 1/04 1/02
GNO WE
1/0 3
1/0 4
PIN NAMES
AO-A9 ADDRESS INPUTS DO OUTPUT DISABLE
WE WRITE ENABLE Vcc POWER (+5V)
CSi, CS2
1/01-1104
CHIP SELECT
DATA INPUT/OUTPUT
GND GROUND o = PIN NUMBERS
7-202
2142 FAMILY
ABSOLUTE MAXIMUM RATINGS* *COMMENT: Stresses above those listed under "Absolute
Temperature Under Bias . . . . . . . . . . . . _10C to a<tc
Storage Temperature . . . . . . . . . . . . . .-65C to +150C
Voltage on Any Pin
those indicated in the operational sections of this specifi-
With Respect to Ground ........... -0.5V to +7V
cation is not implied. Exposure to absolute maximum
Power Dissipation . . . . . . . . . . . . . . .. 1.0W
D.C. Output Current . . . . . . . . . . . . . . . . . . . . . lOrnA
reliability.

TA = oc to 70C, Vcc = 5V 5%, unless otherwise noted.
2142-2, 2142-3, 2142 2142L2,2142L3,2142L

SYMBOL PARAMETER Min. Typ.l1J Max. Min. Typ.l1J Max. UNIT CONDITIONS
Input Load Current 10 10 p.A VIN = 0 to 5.25V

'll
(All Input Pins)
"Lol I/O Leakage Current 10 10 p.A CS = 2.4V,

VI/a = O.4V to Vcc
ICC1 Power Supply Current 80 95 65 rnA VIN = 5.25V, 1110 = 0 mA,

TA = 25C
ICC2 Power Supply Current 100 70 rnA VIN = 5.25V, 1110 = 0 mA,
TA = OC
10L Output Low Current 2.1 6.0 2.1 6.0 rnA VOL = 0.4V
10H Output High Current -1.0 -1.4 -1.0 -1.4 rnA VOH = 2.4V
105[2J Output Short Circuit 40 40 rnA VI/a = GND to VCC
Current
NOTE: 1. Typical values are for T A = 25 C and Vee = 5.0V.

2. Duration not to exceed 30 seconds.
CAPACITANCE
TA = 25C, f = 1.0 MHz
SYMBOL TEST MAX UNIT CONDITIONS
CI/O Input/Output Capacitance 5 pF Vila = OV
CIN Input Capacitance 5 pF VIN = OV TEST NOTE: This circuit em-

ploys a self starting oscillator
NOTE: . This parameter is periodically sampled and not 100% tested. and a charge pump which
require a certain amount of
time after POWER ON to start
functioning properly. This
2142 circuit is conserva-
A.C. CONDITIONS OF TEST tively specified as requiring
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0.8 Volt to 2.4 Volt 500 !-,sec after Vcc reaches
its specified limit (4.75V).
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 nsec
Input and Output Timing Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . - . - ..... 1.5 Volts
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 TTL Gate and CL = 100 pF
7-203
2142 FAMILY
A.C. CHARACTERISTICS TA = oc to 70C, Vee = 5V 5%, unless otherwise noted.
READ CYCLE (1]
21422, 2142L2 2142-3, 2142L3 2142,2142L

SYMBOL PARAMETER Min. Max. Min. Max. Min. Max. UNIT
tRe Read Cycle Time 200 300 450 ns

tA Access Time 200 300 450 ns
too Output Enable to Output Valid 70 100 120 ns
toox Output Enable to Output Active 20 20 20 ns
teo Chip Selection to Output Valid 70 100 120 ns
tex Chip Selection to Output Active 20 20 20 ns
tOTO Output 3-state from Disable 60 80 100 ns
tOHA Output Hold from Address Change 50 50 50 ns
WR ITE CYCLE (2]
2142-2, 2142L2 2142-3, 2142L3 2142,2142L

SYMBOL PARAMETER Min. Max. Min. Max. Min. Max. UNIT
twe Write Cycle Time 200 300 450 ns
tw Write Time 120 150 200 ns
tWR Write Release Time 0 0 0 ns
tOTO Output 3-state from Disable 60 80 100 ns
tow Data to Write Time Overlap 120 150 200 ns
tOH Data Hold From Write Time 0 0 0 ns
NOTES:
1. A Read occurs during the overlap of a low CS and a high WE.
2. A Write occurs during the overlap of a low es and a low WE.
WAVEFORMS
READ CYCLE@ WRITE CYCLE
t+------tRC-----~ twc
1+-----tA - - - - - - I
ADDRESS ADDRESS
OD OD
(it
tWR-
- ).\\\\\\
-tOTO+-
\\\ \\\\ .\""~ '/ / / / / / / /
11/ 'il/. lL ,\ \ \ \ \ \ \ \
tw
DOUT --------------~~--~ \\\"" Xi
DOUT
NOTES:
@
D,N----~r--l.,+,.-x,....,...xx~x>
WE is high for a Read Cycle. tow- f.tOH
WE must be high during all address transitions.
7-204
2142 FAMILY
TYPICAL D.C. AND A.C. CHARACTERISTICS

NORMALIZED ACCESS TIME VS. NORMALIZED ACCESS TIME VS.
SUPPLY VOLTAGE AMBIENT TEMPERATURE
1.2 1.2
-- ---
1. 1 1.1
I'--..
--------
1.0 1.0
0.9
r--- :!
fa
N O.9
~
:::;
<{
0.8 ~ 0.8
~
0.7 0.7
0.6 0.6
0.5 0.5
4.50 4.75 5.00 5.25 5.50 o 20 60 80
Vee (V)
NORMALIZED ACCESS TIME VS. NORMALIZED POWER SUPPLY CURRENT

OUTPUT LOAD CAPACITANCE VS. AMBIENT TEMPERATURE
1.2
1.1
~
l..-- - - 1.2
1.1
1.0 ~ 1.0
:!
fa 0.9
~
faN 0.9 ~
~ "'-.
- --
N
:::; :::;
<{ <(
::0; 0.8 ::0; 0.8
a: a:
0 0
z z
0.7 0.7
0.6 0.6
0.5
100 200 300 400 500 600 20 60 80
CL (pF)
OUTPUT SOURCE CURRENT OUTPUT SINK CURRENT

VS. OUTPUT VOLTAGE VS. OUTPUT VOLTAGE
40 40
30 30
/
20
10
o
"" \
~
'"~
1...
.E
20
10
o /
/
V
./
o o
VOH (V) VOL IV)
7-205
2148
1024 x 4 BIT STATIC RAM
21483 2148 21486
Max. Access Time (ns) 55 70 85
Max. Active Current (rnA) 125 125 125
Max. Standby Current (rnA) 30 30 30
HMOS Technology Automatic Power Down

Completely Static Memory
- No Clock or Timing Strobe
High Density 18Pin Package
Required Directly TTL Compatible
- All Inputs and Outputs
Equal Access and Cycle Times Common Data Input and Output
Single + 5 V Supply ThreeState Output
The Intel 2148 is a 4096bit static Random Access Memory organized as 1024 words by 4 bits using HMOS, a high
performance MOS technology. It uses a uniquely innovative design approach which provides the ease-of-use features
associated with non-clocked static memories and the reduced standby power dissipation associated with clocked static
memories. To the user this means low standby power dissipation without the need for clocks, address setup and hold
times, nor reduced data rates due to cycle times that are longer than access times.
CS controls the power-down feature. In less than a cycle time after CS goes high - disabling the 2148 - the part
automatically reduces its power requirements and remains in this low power standby mode as long as CS remains high.
This device feature results in system power savings as great as 85% in larger systems, where the majority of devices are
disabled.
The 2148 is assembled in an 18-pin package configured with the industry standard 1K x 4 pinout. It is directly TIL
compatible in all respects: inputs, outputs, and a single +5V supply. The data is read out nondestructively and has the
same polarity as the input data.
A6 Vcc
AO ~VCC
AS A7
A1
1/01 ~GND
A2
A4 AS A6
A3 MEMORY ARRAY
ROW 64 ROWS
A3 Ag 1/02 SELECT
A7 64 COLUMNS
A4
Ao 1/01
AS AS
A1 1/02 1/03
A6
A2 1/03
A7
Ag
o = PIN NUMBERS
cs 1/04
AS
1104
@
1101
GND WE
@
1102
@
1103
PIN NAMES
Ao-Ag ADDRESS INPUTS 1104
WE WRITE ENABLE
cs CHIP SELECT
1/0 1 -1104 DATA INPUTIOUTPUT
Vcc POWER (+sV)
GND GROUND
TRUTH TABLE
CS WE MODE 1/0 POWER
H X NOT SELECTED HIGHZ STANDBY
L L WRITE DIN ACTIVE
L H READ DOUT ACTIVE
INTEL CORPORATION ASSUMES NO RESPONSIBILITY FOR THE USE OF ANY CIRCUITRY OTHER THAN CIRCUITRY EMBODIED IN AN INTel PRODUCT NO OTHER CIRCUIT PATENT LICENSES ARE IMPLIED.
(f INTEL CORPORATION 1979 7-206 June 1979
2148
ABSOLUTE MAXIMUM RATINGS COMMENT: Stresses above those listed under "Absolute
Temperature Under Bias ............ -10Cto +85C
Storage Temperature .............. - 65C to + 150C tion of the device at these or any other conditions above
Voltage on Any Pin with those indicated in the operational sections of this specifi-
Respect to Ground ................. -3.5V to + 7V cation is not implied. Exposure to absolute maximum
D.C. Output Current ......................... 20 mA rating conditions for extended periods may affect device
Power Dissipation ........................... 1.2W reliability.
D.C. AND OPERATING CHARACTERISTICS!1)

T A = OC to + 70 C, Vee = + 5 V 10% unless otherwise noted.
2148, 2148-3, 2148-6

Symbol Parameter Min. Typ.!2) Max. Unit Test Conditions
III Input Load Current (All Input Pins) 0.01 10 iJ. A Vee = max, V 1N = GND to Vee
CS = V 1H , Vee = max,
IILOI Output Leakage Current 0.1 50 iJ. A
VOUT = GND to 4.5V
75 115 mA -
TA = 25C Vee = max, CS = V 1L ,
Icc Operating Current
125 mA TA = OC Outputs Open
ISB Standby Current 12 30 mA Vee = min to max, CS = V 1H
Ipo!3) Vee = GND to Veemin,

Peak Power-On Current 25 50 mA
CS = Lower of Vee or V 1H min
V 1L Input Low Voltage -3.0 0.8 V
V 1H Input High Voltage 2.0 6.0 V
VOL Output Low Voltage 0.4 V 10L =8mA

VOH Output High Voltage 2.4 V 10H = -2.0mA
los Output Short Circuit Current TBD TBD mA VOUT = GND to Vee
Notes:
1. The operating ambient temperature range is guaranteed with transverse air flow exceeding 400 linear feet per minute.
2. Typical limits are at Vee = 5V, TA = +25C, and Load A.
3. A pullup resistor to Vee on the CS input is required to keep the device deselected; otherwise, poweron current approaches Icc
active.
+5V
A.C. TEST CONDITIONS
Input Pulse Levels GND to 3.0 Volts 510n
Input Rise and Fall Times 10 nsec DOUT - - - . . . . - - -.. +5V

30 pF
Input and Output Timing (INCLUDING
330n
Reference Levels 1.5 Volts SCOPE AND 5100
JIG)
Output Load See Load A. DOUT - - - . . . . - - -..
3300 5pF
CAPACITANCE (4)
LoadA.
TA = 25 C, f = 1.0 MHz
Symbol Parameter Max. Unit Conditions
C IN Input Capacitance 5 pF V 1N =OV Load B.
COUT Output Capacitance 7 pF VOUT=OV
Note 4. This parameter is sampled and not 100% tested.
7-207
2148
=
T A OC to + 70C, Vcc = +5V 10% unless otherwise noted.
READ CYCLE
21483 2148 21486

Test
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit Conditions
tRC Read Cycle Time 55 70 85 ns
tAA Address Access Time 55 70 85 ns
t ACS1 Chip Select Access Time 55 70 85 ns Note 1

t ACS2 Chip Select Access Time 65 80 95 ns Note 2
tOH Output Hold from Address Change 5 5 5 ns

t [8[
Chip Selection Output in Low Z 10 10 10 ns Note 7
Ll
t Hz[8[ Chip Deselection to Output in High Z 0 40 0 40 0 40 ns Note 7
tpu Chip Selection to Power Up Time 0 0 0 ns
tpD Chip Deselectio,n to Power Down Time 30 30 30 ns
WAVEFORMS
READ CYCLE NO.1 [3 4)
'00,," =::r-----~- - 'Re ---~~-- ----~--~1--
f-- ~1 -l
*
_"_1"_"
PREVIOUS DATA VALID X X *=======================================

READ CYCLE NO. 2[3 S)
1-------- tRC -------- ~-------.I
I
~-----
DATA VALID
Notes:
1. Chip deselected for greater than 55 ns prior to CS transition low.
2. Chip deselected for a finite time that is less than 55 ns prior to CS transition low. (If the deselect time is 0 ns, the chip is by
definition selected and access occurs according to Read Cycle No.1.)
3. WE is high for Read Cycles.
4. Device is continuously selected, CS =V1L.
5. Addresses valid prior to or coincident with CS transition low.
6. At any given temperature and voltage condition, tHZ max. is less than tLl min. both for a given device and from device to device.
7. Transition is measured 500mV from high impedance voltage with Load B. This parameter is sampled and not 100% tested.
7-208
2148
A.C. CHARACTERISTICS (continued)
WRITE CYCLE
21483 2148 21486

Test
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit Conditions
twe Write Cycle Time 55 70 85 ns
tew Chip Selection to End of Write 50 65 80 ns
tAW Address Valid to End of Write 50 65 80 ns
tAS Address Setup Time 0 0 0 ns
twp Write Pulse Width 40 50 60 ns
tWR Write Recovery Time 5 5 5 ns
tow Data Valid to End of Write 25 25 30 ns
tOH Data Hold Time 5 5 5 ns
twz Write Enabled to Output in High Z 0 15 0 25 0 30 ns Note 2
tow Output Active from End of Write 0 0 0 ns Note 2
WAVEFORMS
WRITE CYCLE #1 (WE CONTROLLED)
-----twc
'ew
CSllI
'AW
--~ ~-- twP
WE
\\1 1
---t [.~:~."" -+'."-~

_____________D_AT_A_U_ND_EF_'N_ED__________
WRITE CYCLE #2 (CS CONTROLLED)

J) "X,,~.~-~.--
~------ 'we ----------1
____________________________
DATA UNDEFINED
~~L----H-'GH-'-MP-ED-A-NC-E-------------
,.,-
_
Notes: 1. If CS goes high simultaneously with WE high, the output remains in a high impedance state.
2. Transition is measured 500 mV from high impedance voltage with Load B. This parameter is sampled and not 100% tested.
2148H
1024 x 481T STATIC RAM
2148H-3 2148H 2148HL-3 2148HL
Maximum Access Time (ns) 55 70 55 70
Maximum Active Current (mA) 180 180 125 125
Maximum Standby Current (mA) 30 30 20 20
Automatic Power Down Equal Access and Cycle Times
Industry Standard 2114A and 2148 High Density 18Pin Package

Pinout
Common Data Input and Output
HMOS II Technology
ThreeState Output
Functionally Compatible to the 2148 Single + 5V Supply
Completely Static Memory--No Clock
or Timing Strobe Required
Fast Chip Select Access 2149H
Available
The Intel 2148H is a 4096-bit static Random Access Memory organized as 1024 words by 4 bits using HMOS
II, a high performance MOS technology. It uses a uniquely innovative design approach which provides .the
ease-of-use features associated with non-clocked static memories and the reduced standby power
dissipation associated with clocked static memories. To the user this means low standby power dissipation
without the need for clocks, address setup and hold times, or reduced data rates due to cycle times that are
longer than access times.
CS controls the power-down feature. In less than a cycle time after CS goes high-disabling the 2148H-the
part automatically reduces its power requirements and remains in this low power standby mode as long as
CS remains high. This device feature results in system power savings as great as 85% in larger systems,
where the majority of devices are disabled. A non-power-down companion, the 2149H, is available to provide
a fast chip select access time for speed critical applications.
The 2148H is assembled in an 18-pin package configured with the industry standard 1K x 4 pinout. It is
directly TTL compatible in all respects: inputs, outputs, and a single + 5V supply. The data is read out non-
destructively and has the same polarity as the input data.
- AO
.- A,
101 -
A,
- A,
@
--Vee - A,
~GNO - A,
10) -
- Ab
MEMORY ARRAY
ROW 64 ROWS - A,
SELECT 64 COLUMNS
- A,
WE
o= P'N NUMBERS
?
PIN NAMES
Ao-A, ADDRESS INPUTS
WE WRITE ENABLE
Ci CHIP SELECT
UO,-U04 DATA INPUT/OUTPUT
Vee POWER (+SV)
GND GROUND
TRUTH TABLE
CS WE MODE 110 POWER
L L WRITE DIN ACTIVE
Figure 1_ 2148H Block Diagram Figure 2. 2148H Pin Diagram

'INTEL CORPORATION, 1980 7-210 AFN2148H/PDS/0980
2148H FAMILY
ABSOLUTE MAXIMUM RATINGS COMMENT: Stresses above those listed under "Ab-
solute Maximum Ratings" may cause permanent
Temperature Under Bias ............ - 10C to + 85C damage to the device. This is a stress rating only and
Storage Temperature ............. - 65C to + 150C functional operation of the device at these or any other
Voltage on Any Pin with conditions above those indicated in the operational sec-
Respect to Ground ................. - 3.5V to + 7V tions of this specification is not implied. Exposure to
D.C. Continuous Output Current ............. 20 mA absolute maximum rating conditions for extended
Power Dissipation ............................ 1.2W periods may affect device reliability.
D.C. AN D OPERATING CHARACTERISTICS"I

TA = 0 C to + 70C, Vee = +5V 10% unless otherwise noted.
2148H/H-3 2148HL/HL-3
(21 (21
Symbol Parameter Min. Typ Max. Min. Typ Max. Unit Test Conditions
III Input Load Current (All Input Pins) 0.01 10 0.01 10 f.1A Vee = max, VIN = GND to Vee
CS = VIH, Vee = max,
IILol Output Leakage Current 0.1 50 0.1 50 f.1A
VOUT = GND to 4.5V
Vee = max, CS = VIL,

lee Operating Current 120 180 90 125 mA
Outputs Open
ISB Standby Current 15 30 10 20 mA Vee = min to max, CS = VIH

(31 Vec = GND to Vcc min,
Ipo Peak Power-On Current 25 50 15 30 mA CS = Lower of Vcc or VIH min
VOL Output Low Voltage 0.4 0.4 V 10L =8 mA
VOH Output High Voltage 2.4 2.4 V 10H = -4.0 mA
los Output Short Circuit Current 150 200 150 200 mA VOUT = GND to Vcc
Notes:
1. The operating ambient temperature range is guaranteed with transverse air flow exceeding 400 linear feet per minute. Typical
thermal resistance values of the package at maximum temperatures are:
8JA (@ 400 fPM air flow) = 40 C/W
8JA (still air) = 70 C/W
8JC = 25 C/W
2. Typical limits are at Vcc = 5V, TA = +25C, and Load A.
3. A pull-up resistor to Vcc on the CS input is required to keep the deviee deselected during power-on. Otherwise, power-on current
approaches Icc active.
+5V
A.C. TEST CONDITIONS
Input Pulse Levels GND to 3.0 Volts 4800
Input Rise and Fall Times 5 nsec DOUT - - - - . - - -.. +5V

30 pF
Input and Output Timing (INCLUDING
2550
Reference Levels 1.5 Volts SCOPE AND 4800
JIG)
Output Load See Load A.
D O U T - - -.......- -....
2550 5pF
CAPACITANCE (4)
Load A.
TA =25C, f =1.0 MHz
Load B.
CIN Address/Control Capacitance 5 pF VIN = OV
CIO Input/Output Capacitance 7 pF VOUT = OV
Note 4. This parameter Is sampled and not 100% tested.

2148H FAMILY
TA =OC to + 70C, Vcc = +5V 10% unless otherwise noted.
READ CYCLE
2148H-3/HL-3 2148H/HL Test

Symbol Parameter Min. Max. Min. Max. Unit Conditions
tAC Read Cycle Time 55 70 ns
tAA Address Access Time 55 70 ns
tACS1 Chip Select Access Time 55 70 ns Note 1
tACS2 Chip Select Access Time 65 80 ns Note 2
tOH Output Hold from Address Change 5 5 ns

tLZ Chip Selection Output in Low Z 20 20 ns Note 6
tHZ Chip Deselection to Output in High Z 0 20 0 20 ns Note 6
tpu Chip Selection to Power Up Time 0 0 ns
tPD Chip Deselection to Power Down Time 30 30 ns
WAVEFORMS
READ CYCLE NO. 113. 1
~ ~~~~~~~C--~----~~~~
,
~~ 'O"~ "I
DATA OUT PREVIOUS DATA vAlID! XX*=============DA=T=A=VA=L-I_D================
READ CYCLE NO. 213&1
tRc--------------------~l
cs - ( --_l-
14-----t.cs - - - - - - - - - 1
tLz------..i
DATA OUT --+.....;.;.;,,;;;;,.;.;.;;.;...;=..;;.;;..._--( DATA VALID HIGH

1,,-,u....LJi.J ' - - - - - - -_ _ _ _ +-_--J IMPEDANCE
t pur
Icc---- - -J""---------------------
Is.------J
Notes:
1. Chip deselected for greater than 55 ns prior to CS transition low.
2. Chip deselected for a finite time that is less than 55 ns prior to CS transition low. (If the deselect time is 0 ns, the chip is
by definition selected and access occurs according to Read Cycle No 1.)
4. Device is continuously selected, CS = V 1L .
6. Transition is measured 500mV from high impedance voltage with Load B. This parameter is sampled and not 100%
tested.
2148H FAMILY
A.C. CHARACTERISTICS (continued)
WRITE CYCLE
2148H-3/HL-3 2148H/HL
Test
Symbol Parameter Min. Max. Min. Max. Unit Conditions
twe Write Cycle Time 55 70 ns

tew Chip Selection to End of Write 50 65 ns
tAW Address Valid to End of Write 50 65 ns
tAS Address Setup Time a a ns
twp Write Pulse Width 40 50 ns
tWR Write Recovery Time 5 5 ns
tow Data Valid to End of Write 20 25 ns
tOH Data Hold Time a a ns
twz Write Enabled to Output in High Z a 20 a 25 ns Note 2
tow Output Active from End of Write a a ns Note 2
WAVEFORMS
WRITE CYCLE No. 1 (WE CONTROLLED)
1---------- twc---------11
ADDRESS ____~-----------------------------------JI~--------
CS[1]
DATA IN
DATAOUT ______~~~~~~__~~=-------_t---rl-----------
WRITE CYCLE No. 2 (CS CONTROLLED)

Iwe
-
ADDRESS
IASI lew
- ~.
lAW
-IWR-
Iwp
,\\ \\\ \\\\\\\\'\ tlillIiiiiI III I I III!
, t::.IDW-_IDW~1
DATA IN I DATA IN VALID )(
f---Iwz
DATA OUT ------DA-T-A-U-N-DE-F-IN-E-O-..,;:.:..::=1...___H_IG_H_I_M_P_ED_A_N_C_E_____________
Notes: 1. If CS goes high simultaneously with WE high, the output remains in a high impedance state.
2. Transition is measured 500mV from high impedance voltage with Load B. This parameter is sampled and not
100% tested.
inter
2ii8 FAMilY
16,384 x 1 BIT DYNAMIC RAM
2118-3 2118-4 2118-7
Maximum Access Time (ns) 100 120 150
Read, Write Cycle (ns) 235 270 320
Read-Modify-Write Cycle (ns) 285 320 410
Single +5V Supply, 10% Tolerance Three-State,

CAS Controlled Output is
TTL Compatible
HMOS Technology Refresh Cycles Required
RAS Only Refresh
Low Power: 150 mW Max. Operating
11 mW Max. Standby
128
Every 2ms
Low Voo Current Transients Refresh

Page Mode and Hidden
Capability
TTL
All Inputs, Including Clocks,
Compatible
VIL min = -2V Overshoot
Allows Negative
The Intel 2118 is a 16,384 word by 1-bit Dynamic MOS RAM designed to operate from a single +5V power supply. The
2118 is fabricated using HMOS - a production proven process for high performance, high reliability, and high storage
density.
The 2118 uses a single transistor dynamic storage cell and advanced dynamic circuitry to achieve high speed with low
power dissipation. The circuit design minimizes the current transients typical of dynamic RAM operation. These low
current transients contribute to the high noise immunity of the 2118 in a system environment.
Multiplexing the 14 addreas bits into the 7 address input pins allows the 2118 to be packaged in the industry standard
16-pin DIP. The two 7-bit address words are latched into the 2118 by the two TTL clocks, Row Address Strobe (RAS) and
Column Address Strobe (CAS). Non-critical timing requirements for RAS and CAS allow use of the address multiplexing
technique while maintaining high performance.
The 2118 three-state output is controlled by CAS, independent of RAS. After a valid read or read-modify-write cycle, data
is latched on the output by holding CAS low. The data out pin is returned to the high impedance state by returning CAS to
a high state. The 2118 hidden refresh feature allows CAS to be held low to maintain latched data while RAS is used to
execute RAS-only refresh cycles.
The single transistor storage cell requires refreshing for data retention. Refreshing is accomplished by performing RAS-
only refresh cycles, hidden refresh cycles, or normal read or write cycles on the 128 address combinations of Ao through
A6 during a 2ms period. A write cycle will refresh stored data on all bits of the selected row except the bit which is
addressed.
PIN BLOCK DIAGRAM

CONFIGURATION LOGIC SYMBOL
_Voo
64 x 128 CELL _Vss
MEMORY ARRAY
OUTPUT
DOUT
BUFFER
AOA6 ADDRESS INPUTS

CAS COLUMN ADDRESS STROBE
D,N DATA IN
OOUT DATA OUT

WE WRITE ENABLE ~
RAS ROW ADDRESS STROBE WE
Voo POWER "5Vl
~N
Vss GROUND
2118 FAMILY
ABSOLUTE MAXIMUM RATINGS 'COMMENT:
AmbientTemperatureUnderBias ... -10Cto+80C Stresses above those listed under "Absolute Maximum
Storage Temperature ............. -65Cto+150C Rating" may cause permanent damage to the device. This
Voltage on Any Pin Relative to Vss ............ 7.5V is a stress rating only and functional operation of the de-
Data Out Current ............................ 50mA vice at these or at any other condition above those indi-
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . .. 1.0W cated in the operational sections of this specification is
not implied. EXPQsure to absolute maximum rating con-
ditions for extended periods may affect device reliability.
D.C. AND OPERATING CHARACTERISTICS[1]

TA = OC to 70C, Voo = 5V 10%, VSS = OV, unless otherwise noted.
Limits
Symbol Parameter Min. Typ,!2] Max. Unit Test Conditions Notes
IILlI Input Load Current (any input) 0.1 10 J.l.A VIN=VSS to Voo
IILOI Output Leakage Current for Chip Deselected: CAS at VIH,
High Impedance State 0.1 10 J.l.A Your = a to 5.5V
1001 Voo Supply Current, Standby 1.2 2 mA CAS and RAS at VIH
1002 Voo Supply Current, Operating 23 27 mA 2118-3, tRC = tRCMIN 3
21 25 mA 2118-4, tRC = tRCMIN 3
19 23 mA 2118-7, tRC = tRCMIN 3
1003 Voo Supply Current; RAS-Only 16 18 mA 2118-3, tRC = tRCMIN 3
Cycle 14 16 mA 2118-4, tRC = tRCMIN 3
12 14 mA 2118-7, tRC = tRCMIN 3
1005 Voo Supply Current, Standby, 2 4 mA CAS at VIL. RAS at VIH 3
Output Enabled
VIL Input Low Voltage (all inputs) -2.0 0.8 V
VIH Input High Voltage (all inputs) 2.4 7.0 V
VOL Output Low Voltage 0.4 V IOL = 4.2mA
VOH Output High Voltage 2.4 V IOH = -5mA
NOTES:
1. All voltages referenced to V55
2. Typical values are for TA = 25C and nominal supply voltages.
3. 100 is dependent on output loading when the device output is selected. Specified 100 MAX is measured with the output open.
CAPACITANCE!1)
TA = 25C, Voo = 5V 10%, VSS = OV, unless otherwise noted.
Symbol Parameter Typ. Max. Unit

CI1 Address, Data In 3 5 pF
CI2 RAS, CAS, WE, Data Out 4 7 pF
NOTES:
I. Capacitance measured with Boonton Meter or effective capacitance calculated from the equation:
C = Iolt with J.V equal to 3 volts and power supplies at nominal levels.
J.V
2118 FAMILY
A.C. CHARACTERISTICS[1,2,3)
TA = OC to 70C, VDD = 5V 10%, VSS = OV, unless otherwise noted,
READ, WRITE, READ-MODIFY-WRITE AND REFRESH CYCLES
2118-3 2118-4 2118-7
Symbol Parameter Min, Mu, Min, Mu. Min, Max, Unit Notel
tAAC Access Time From RAS 100 120 150 ns 4,5
tCAC Access Time From CAS 55 65 80 ns 4,5,6
tAEF Time Between Refresh 2 2 2 ms
tAP RAS Precharge Time 110 120 135 ns
tCPN CAS Precharge Time I nonpage cycles l 50 55 70 ns
tCRP CAS to RAS Precharge Time 0 0 0 ns
tRCO RAS to CAS Delay Time 25 45 25 55 25 70 ns 7
tASH RAS Hold Time 70 85 105 ns
tCSH CAS Hold Time 100 120 165 ns
tASA Row Address Set-Up Time 0 0 0 ns
tAAH Row Address Hold Time 15 15 15 ns
tASC Column Address Set-Up Time 0 0 0 ns
tCAH Column Address Hold Time 15 15 20 ns
tAR Column Address Hold Time, to RAS 60 70 90 ns
IT Transition Time (Rise and Fall! 3 50 3 50 3 50 ns 8
tOFF Output euffer Turn Off Delay 0 45 0 50 0 60 ns
READ AND REFRESH CYCLES

tAC Random Read Cycle Time 235 270 320 ns
tAAS RAS Pulse Width 115 10000 140 10000 175 10000 ns
tCAS CAS Pulse Width 55 10000 65 10000 95 10000 ns
tACS Read Command Set-Up Time 0 0 0 ns
tRCH Read Command Hold Time 0 0 0 ns
WRITE CYCLE
tAC Random Write Cycle Time 235 270 320 ns
tAAS RAS Pulse Width 115 10000 140 10000 175 10000 ns
twcs Write Command Set-Up Time 0 0 0 ns 9
tWCH Write Command Hold Time 25 30 45 ns
tWCR Write Command Hold Time, to RAS 70 85 115 ns
twp Write Command Pulse Width 25 30 50 ns
tAWL Write Command to RAS Lead Time 60 65 110 ns
tCWL Write Command to CAS Lead Time 45 50 100 ns
tos Data-In Set-Up Time 0 0 0 ns
tOH Data-In Hold Time 25 30 45 ns
tOHA Data-In Hold Time, to RAS 70 85 115' ns
READ-MODIFY-WRITE CYCLE
tAWC Read-Modify-Write Cycle Time 285 320 410 ns
tAAW RMW Cycle RAS Pulse Width 165 10000 190 10000 265 10000 ns
tCRW RMW Cycle CAS Pulse Width 105 10000 120 10000 185 10000 ns
tAwO RAS to WE Delay 100 120 150 ns 9
tcwo CAS to WE Delay 55 65 80 ns 9
NOTES
All voltages referenced to Vss 7 tACO Imax liS specified as a reference pOint only. "tACO IS less
Eight cycles are required after power-up or prolonged periods than tRCD Imax ! access time IS tRAC. If tRCO IS greater than tRCO
Igreater than 2msl of AAS inactivity before proper device Imax ) access time IS tRCD ~ tCAG
operation IS achieved Any 8 cycles which perform refresh are IT IS measured between VIH IMln I and VtL Imax I
adequate for thiS purpose twcs. tcwD and tAwD are specified as reference POints only If
A C Characteristics assume tT' = 5ns twcs c twcs Imln I the cycle IS an early write cycle and the data
Assume that tACO'" tACO Imax I. If tACO IS greater than tACO out pin Will remain high Impedance throughout the entire
Imax I then tAAC will Increase by the amount that tACO exceeds cycle If tCW') tcwD Imln.1 and tAwD ~ tAwD Imln I. the cycle IS
,>
tRCO (max I a read-modlfy-wrlte cycle and the data out will contain the data
Load = 2 TTL loads and 100pF read from the selected address If neither of the above
Assumes tRCD ? tRCD (max) conditions IS satisfied. the condition of the data out IS
7 ') ~ c:. indeterminate
2118 FAMILY
WAVEFORMS
READ CY CLE
V,H
- t AAS
tAC
l-tAP~
I
RAS
V ,L
031\10 ~
tCSH - tcP
tcAP-1 e.f-- NI
tACO tASH
V ,H
CAS
V ,L I CD
1\\\\l0
tAA
tCAS
.11
tASA f----o- -tAAH-1 I-- tAse I--tCAH-
"iH
ADDRESSES
V ,L ~
'2
ROW
ADDRESS
K ~
COLUMN
ADDRESS
K
V ,H
1--. t ACS Ht ACH
0
WE
V ,L d!I tCAC
\
tAAC !--tOFF-
VO H HIGH CD
DOUT
VOL IMPEDANCE o VALID
~D_A_T.....
A_O_U_T_ _ _ _..Jf
WRITE CY CLE t AC
tAAS l - t AP -
8 l\@
VI L
tCAP -1 \+t--
tRCO
tCSH
t RSH - - - - -
l-tCPN-1
J (i)
K\,\l\~
tAR
tCAS
)t
tASA ---t-- - t RAH ---1 tASC- t-- --tCAH-
ADDRESSES
V
V ,L
,H
){tJ)0 ROW
ADDRESS
XX COLUMN
ADDRESS
K
t AWL
'cWl
V,H -twcs- _ t WCH -
WE V,L i twp
tWCA
e.-@t os - _ t OH @ -
V ,H
} CD
D'N
V'L CD JK
tOHR
~~~--------------~I~M~~~~~:~N~C~E--------------------------------------------------------------------
NOTES: 1,2. V ,H MIN AND V ,l MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF INPUT SIGNALS.
3,4. V OH MIN AND Val MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF D oUT '
5. tOFF IS MEASURED TO lOUT'; lila I
6. tos AND tOH ARE REFERENCED TO CAS OR WE, WHICHEVER OCCURS LAST.
7. tACH IS REFERENCED TO THE TRAILING EDGE OF CAS OR RAS, WHICHEVER OCCURS FIRST
8. tCAP REQUIREMENT IS ONLY APPLICABLE FOR RAS/CAS CYCLES PRECEEDED BY A CAS-
ONLY CYCLE Il.e., FOR SYSTEMS WHERE CAS HAS NOT BEEN DECODED WITH RASI.
7-217
2118 FAMILY
WAVEFORMS
READMODIFYWRITE CYCLE
tRwe J
tRRW
'==-'RP_:I
(1, 1\2) '7 "\
(8)ICRP-j f.~'RCo-:--- I---'CPN-i
'cRW
'~ il)
~\\\ (2)
f----IAR - - t RWl -
H'RAH
tASR-t--- tAS~tw" 1- teAH ---t CWl- - -
ADDRESSES Vil
V ,H
)( (1) AD~~~SS }( X ;g~~~~ K
(2)
r;;'~
,3)
IRcsrl
tRWD
'cWO
,,-,wp-k
'OS 'I t-~loH-=-

XI}) DATA IN
VALID K
H HIGH
tRAe
tCAC-t
fiJI
I
CD
VALID
- "l;
tOFF
IMPEDANCE DATA OUT -

l 0~
RASONL Y REFRESH CYCLE

IRC .J
tRAS
_II=='RP-:I
~
V,H
RAS (i) I"l 1) 1\
Vil
V,H
I f--'CRP
CAS
Vil
---'IASRt- -'RAH!
V,H
ROW
ADDRESSES
Vil
X~ ADDRESS ](
"'"
VOH HIGH
DOUT
Val IMPEDANCE
HIDDEN REFRESH CYCLE

(For Hidden Refresh Operation order 2118-3 56445,2118-456446 or 2118-7 56447)
V,H
ADDRESSES
Vil
V,H
WE
Vil
DOUl
VOH "",Jr.."i"...C----------V-A-lI~~i-tD-AT-A-------------:!I~.,.0;..0_" _ _ __
VOL
NOTES: 1,2. V ,H MIN AND V ,l MAX ARE REFERENCE LEVELS FOR MEASURING T1MING OF INPUT SIGNALS.
3,4. V OH MIN AND VOL MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF DOllT '
5. IOFF IS MEASURED TO lOUT" IllO I
6. 'DS AND IDH ARE REFERENCED TO CAS OR WE, WHICHEVER OCCURS LAST.
7.IRCH IS REFERENCED TO THE TRAILING EDGE OF CAS OR RAS, WHICHEVER OCCURS FIRST.
S.ICRP REOUIREMENT IS ONLY APPLICABLE FOR RAS/CAS CYCLES PRECEEDEDBY A CAS-
ONLY CYCLE Ii .. , FOR SYSTEMS WHERE CAS HAS NOT BEEN DECODED WITH RAS).
7218
2118 FAMILY
D.C. AND A.C. CHARACTERISTICS, PAGE MODE[7.8.11j

TA = OC to 70C, VDD = 5V 10%, Vss = OV, unless otherwise noted.
For Page Mode Operation order 2118-3 56329, 2118-4 56330, or 2118-7 56331.
2118-3 2118-4 2118-7

S6329 S6330 S6331
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit Notes
tpc Page Mode Read or Write Cycle 125 145 190 ns
tpCM Page Mode Read Modify Write Cycle 175 200 280 ns
tcp CAS Precharge Time, Page Cycle 60 70 85 ns
tRPM RAS Pulse Width, Page Mode 115 10000 140 10000 175 10000 ns
1004 Voo Supply Current Page Mode,
Minimum tpc, Minimum tCAS 20 17 15 mA
WAVEFORMS
PAGE MODE READ CYCLE
~------------------------------IR~--------------------------------~I~
__ V'HC
~~--------~------------------------------~~--~,-.~---~~~::-tR-5-H--------~tR'~
RAS
WE V 1HC
V'l _ _ _ +-_J
VOH
DOUT VOl-----------------------~~
NOTES: 1.2. V'H MIN AND V'l MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF INPUT SIGNALS.
3,4. V OH MIN AND Val MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF D oUT '
5. IOFF IS MEASURED TO lOUT IILO I.
6.IReH IS REFERENCED TO THE TRAILING EDGE OF CAS OR RAS, WHICHEVER OCCURS FIRST
7. ALL VOL TAGES REFERENCED TO Vss
8. AC CHARACTERISTIC ASSUME IT = 5n .
9. SEE THE TYPICAL CHARACTERISTICS SECTION FOR VALUES OF THIS PARAMETER
UNDER AL TERNATE CONDITIONS.
10. tCRP REQUIREMENT IS ONLY APPLICABLE FOR RAS/CAS CYCLES PRECEEDED BY A CAS-
ONLY CYCLE (i.e" FOR SYSTEMS WHERE CAS HAS NOT BEEN DECODED WITH RASI.
" ALL PREVIOUSLY SPECIFIED A.C. AND D.C. CHARACTERISTICS ARE APPLICABLE TO THEIR
RESPECTIVE PAGE MODE DEVICE (j.e" 21183, 56329 WILL OPERATE AS A 211831.
7-219
2118 FAMILY
PAGE MODE
WRITE CYCLE ~---------------------------------tRPM--------------------------------~1
,H
ADDRESSES V
V'L--~~T-~~~~~~~------~---~~--~~----~------~~--~~~--~~------+r------------
WE V ,HC
V,L ______ ~----~~~--_+----------~~------_+----------~~--_H~------~------~------------
V ,H
D'N
VIL ______ ~~~~--------~~----~~----------~~--------,~~~----------~~----------------
PAGE MODE READ-MODIFY-WRITE CYCLE

r------------------- ------------------- tRPM - - - - - - - - - - - -
1-------------t pcM ------------.-!

(j)tCRP
t----<o-t------- 'cRW - - - - - - - . I
V'H
CAS
V'L
V'H
ADDRESSES
V'L
V'H
WE
V'L
V 1H
D'N
V'L
VOH HIGH VALID

Dour DATA OUT
VOL IMPEDANCE
NOTES: 1,2. V ,H MIN AND V'l MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF INPUT SIGNALS
3,4. V OH MIN AND VOL MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF DOUT
5. IOFF IS MEASURED TO lOUT' l'lO I.
6. IDS AND IDH ARE REFERENCED TO CAS OR WE, WHICHEVER OCCURS LAST
7. IRCH IS REFERENCED TO THE TRAILING EDGE OF CAS OR RAS, WHICHEVER OCCURS FIRST
8. ICRP REQUIREMENT IS ONLY APPLICABLE FOR RAS/CAS CYCLES PRECEEDED BY A CAS-
ONLY CYCLE (,.e., FOR SYSTEMS WHERE CAS HAS NOT BEEN DECODED WITH RAS)
7-220
2118 FAMILY
TYPICAL SUPPLY CURRENT WAVEFORMS
RAS ONLY REFRESH
60 1\ 1\
1\ 1\
(rnA)
40 n I JI
I\
-""
1\ /1 J\
, Ll
I
M
20 11 11 \ I 11\ I \
~I\J \ 1\ J JJJ 1\ I L \1\1\ II \
J III l;-
"'--J V i'... ) V
""'- '~
100 200 300 400 500 100 200 300
TIME (ns) TIME (ns)
LONG RAS/CAS
60
IDO 40 J\
(rnA) I, 11 1\ JJI1
20
I
LJ /\ 111
j 1M I 1\ 111 [ \
100
J
200
~ 'V 300
\ ,J ' \
400 500
_'I ,
I---
600 700
I'...
800 900
TIME (ns)
Typical power supply waveforms vs. time are shown for temperature on the 100 current are shown in graphs
the RAS/CAS timings of Read/Write, Read/Write (Long included in the Typical Characteristics Section. Each
RAS/CAS), and RAS-only refresh cycles. 100 current family of curves for 1001, 10 02 , and 1003 is related by a
transients at the RAS and CAS edges require adequate common point at V DO = 5.0V and T A = 25 C for two given
decoupling of these supplies. tRAS pulse widths. The typical I DO current for a given
condition of cycle time, V DO and T A can be determi ned by
The effects of cycle time, V DO supply voltage and ambient combining the effects of the appropriate family of curves.
7-221
2118 FAMILY
GR,ll,PH 2
GRAPH 1 TYPICAL ACCESS TIME GRAPH 3
TYPICAL ACCESS TIME tRAG (NORMALIZED) VS. TYPICAL STANDBY CURRENT
tRAG (NORMALIZED) VS. VOO AMBIENT TEMPERATURE 1001 VS. VOO
1.2 1.2 1.4
/
~ 1.1 1.1 /" <"
S 1.2
~
0
V
--
TA = 70 D C f-
on Z
fG
"o
~ 1.0
~
1.0
/ W
II:
II: 1.0
~
:J
/~ ~
()
~ u
~ ~
/!
'0 0.9
<:::
0.9
Q,
Q, 0.8
~
:J TA = ODC
~
Ul
u I
;
u
0.8
; 0.8 _0
Q
0.6
VDO = 4.5V
0.7
1 0.4
0.7
4.0 4.5 5.0 5.5 6.0 20 40 60 80 4.0 4.5 5.0 5.5 6.0
Voo - SUPPL Y VOLTAGE (VOLTS) TA - AMBIENT TEMPERATURE (DC) voo-SUPPLY VOLTAGE (VOLTS)
GRAPH 4 GRAPH 5 GRAPH 6

TYPICAL STANDBY CURRENT TYPICAL OPERATING CURRENT TYPICAL OPERATING CURRENT
IDDl VS. AMBIENT TEMPERATURE 1002 VS. t RC 1002 VS. VOO
1.4 50 50
<"
S
1.2 1.,,,- <"
S
TA 25 DC
40 I---- VOO = 5.0V
J <"
S
40 ~T,."t
,
I- f-
-----------
f- Z
Z Z W
W W
-- --
a: II: II:
30 tRAS = 115ns_
1.0 30 II:
a: II:
:J
t RC = 235ns
:J :J ()
() ()
~ r-- ::; ::;

Q,
Q, 0.8 Q,
20 Q,
20
Q, Q,
:J :J :J
~ '1 t
0
_0 0:6
0.4
.9
g
10
o
I"-...
- ~RAS =,500nS
tRAS = 11 5nS
_
-..;;
Jl 10
o
~
tRAS = 500ns
fRC ~ 750ns
o 20 40 60 80 200 400 600 800 1000 4.0 4.5 5.0 5.5 6.0
TA -AMBIENT TEMPERATURE (DC) tRc-CYCLE TIME (ns) VOD - SUPPLY VOLTAGE (VOLTS)
GRAPH 8 GRAPH 9
GRAPH 7 TYPICAL RAS ONLY TYPICAL RAS ONLY
TYPICAL OPERATING CURRENT REFRESH CURRENT REFRESH CYCLE
1002 VS. AMBIENT TEMPERATURE 1003 VS. tRC ID03 VS. Voo
50 50 50
I
<" 40 f-- VOO
I
5.0V <" TA = 2JC
40 I- Voo = 5.0V
<" 40
TA = 25DC
S
=
S S
f- I-
f- Z
Z Z W
W W
a: II:
30 II: 30 II: 30
a: II: :J
:J tRAS = 115ns :J ()
() ()
t RC = 235ns
~ ::; ::;
Q, Q,
Q,
20 tRAS = 115ns
20 20 Q,
Q, Q,
:J tRC = 235ns
:J :J (j'J
Ul
I
Ul
I I --l
g 0 ....... 0
0 10 r--
_0 _0 10
I_
10
tRAS = 500ns
.............
r-- tRAS =,500 ns
tRAS = 500ns
tRC = 750ns tRAS = 115 ns tRC = 750ns
o o
o 20 40 60 80 200 400 600 800 1000 4.0 4.5 5.0 5.5 6.0
TA -AMBIENT TEMPERATURE (DC) tRC -CYCLE TIME (ns) Voo -SUPPLY VOLTAGE (VOLTS)
7222
2118 FAMILY
GRAPH 10
TYPICAL RAS ONLY GRAPH 11 GRAPH 12
REFRESH CURRENT TYPICAL OUTPUT SOURCE CURRENT TYPICAL OUTPUT SINK CURRENT
1003 VS. AMBIENT TEMPERATURE 10H VS. OUTPUT VOLTAGE VOH 10L VS. OUTPUT VOLTAGE VOL
50 100 100
I ~ ~
voo = 5.0V .s TA 1250C .s I
f- 40 f-
zw 80 r---Voo = 5.0V !z 80 J~;}rO~-
~ a:
w
a:
a: a: a:
a: :::J :::J
:::J ()
() 30 60 () 60
w :.:
~ U z
""
Q. a: iii ~
Q. :::J
:::J 0 f- j
20 I - - - - + - - - + - - - . . . ! . - - - - I ~
(/J
(/J 40 40
~~
/
I IRAS=115ns f-
f-
IRC = 235ns :::J
o Q. :::J
o f- o
:::J I
10 I----l---------je---- IRAS = 500 ns - 0 20 -' 20
~ t---- V
IRC = 750 ns I _0
I
.2
i
20 40 60 80
TA -AMBIENT TEMPERATURE (OC) VOH-OUTPUT VOLTAGE (VOLTS) VOL - OUTPUT VOLTAGE (VOLTS)
DEVICE DESCRIPTION parameters. For example, substituting the device para-

meters of the 2118-3 yields:
The Intel 2118 is produced with HMOS, a high
performance MOS technology which incorporates on 3. tACC = tAAC = 100nsec for 25nsec ~ tACO~ 45nsec
chip substrate bias generation. This process, combined
OR
with new circuit design concepts, allows the 2118 to
operate from a single +5V power supply, eliminating the 4. tACC = tACO + tCAC = tACO + 55nsec for tACO> 45nsec
+12V and -5V requirements. Pins 1 and 9 are not Note that if 25nsec ~ tACO ~ 45nsec device access time is
connected, which allows P.C.B. layout for future higher determined by equation 3 and is equal to tAAC. If tRCO >
density memory generations. 45nsec access time is determined by equation 4. This
The 2118 is functionally compatible with the industry 20nsec interval (shown in the tACO inequality in equation
standard 16-pin 16K dynamic RAMs, except forthe power 3) in which the falling edge of CAS can occur without
supply requirements. Replacing the +12V supply with a affecting access time is provided to allow for system
+5V supply and eliminating the -5V bias altogether, timing skew in the generation of CAS.
allows simple upgrade both in power and performance.
To achieve total speed performance upgrade, however, REFRESH CYCLES
the timing ciruitry must be modified to accommodate the Each of the 128 rows of the 2118 must be refreshed every 2
higher performance. milliseconds to maintain data. Any memory cycle:
1. Read Cycle
READ CYCLE 2. Write Cycle (Early Write, Delayed Write or Read-
A Read cycle is performed by maintaining Write Enable Modify-Write)
(WE) high during a RAS/CAS operation. The output pin of 3. RAS-only Cycle
a selected device will remain in a high impedance state refreshes the selected row as defined by the low order
until valid data appears at the output at access time. (RAS) addresses. Any Write cycle, of course, may change
the state of the selected cell. Using a Read, Write, or Read-
Device access time, tACC, is the longer of the two
Modify-Write cycle for refresh is not recommended for
calculated intervals: systems which utilize "wire-OR" outputs since output bus
OR 2. tAcc = tACO + tCAC contention will occur.
Access time from RAS, tRAC, and access time from CAS, A RAS-only refresh cycle is the recommended technique
tCAC, are device parameters. Row to column address for most applications to provide for data retention. A RAS-
strobe delay time, tRCO, are system dependent timing only refresh cycle maintains the Dour in the high
2118 FAMILY
impedance state with a typical power reduction of 30% This feature allows a refresh cycle to be "hidden" among
over a Read or Write cycle. data cycles without affecting the data availability.
RAS/CAS TIMING
RAS and CAS have minimum pulse widths as defined by
POWER ON
tRAS and teAs respectively. These minimum pulse widths
must be maintained for proper device operation and data After the application of the Voo supply, or after extended
integrity. A cycle, once begun by bringing RAS and/or periods of bias (greater than 2ms) without clocks, the
CAS low must not be ended or aborted prior to fulfilling device must perform a minimum of eight (8) initialization
the minimum clock signal pulse widthls I. A new cycle can cycles (any combination of cycles containing a RAS clock
not begin until the minimum prechargetime, tRP, has been such as RAS-only refresh) prior to normal operation.
met.
DATA OUTPUT OPERATION
The Voo current (100) requirement of the 2118 during
The 211'8 Data Output I DOUT I, which has three-state power on is, however, dependent upon the input levels of
capability, is controlled by CAS. During CAS high state RAS and~. If the input levels of these clocks are at VIH
I CAS at VIH 1 the output is in the high impedance state. The or V oo , whichever is lower, the 100 requirement per device
following table summarizes the DOUT state for various is 1001 (100 standby). If the input levels for these clocks
types of cycles. are lower than V 1H or Voo the 100 requirement will be
greater than 1001, as shown in Figure 2.
Intel 2118 Data Output Operation
for Various Types of Cycles
Type of Cycle DOUT State

Read Cycle Data From Addressed
Memory Cell
Early Write Cycle HI-Z
RAS-Only Refresh Cycle HI-Z
CAS-Only Cycle HI-Z
Read/Modify/Write Cycle Data From Addressed ~
E
Memory Cell To
Delayed Write Cycle Indeterminate o
HIDDEN REFRESH
An optional feature of the 2118 is that refresh cycles may
be performed while maintaining valid data at the output
pin. This feature is referred to as Hidden Refresh. Hid-
den Refresh is performed by holding CAS at VIL and
taking RAS high and after a specified precharge period Voo (VOLTS)
(tRP)' executing a "RAS-Only" refresh cycle, but with CAS
held low (see Figure 1.)
Figure 2. Typical 100 VS Voo during power up.
For large systems, this current requirement for 100 could

be substantially more than that for which the system has
been designed: A system which has been designed,
CAS
assuming the majority of devices to be operating in the
refresh/standby mode, may produce sufficient 100
Dour - - . . .HIGHZ
. ; . . - - - (( DATA
~-------'
>-- loading such that the power supply may current limit. To
assure that the system will not experience such loading
during power on, a pullup resistor for each clock input to .
Voo to maintain the non-selected current level (1001) for
Figure 1. Hidden Refresh Cycle. the power supply is recommended.
7-224
inter 2147H
HIGH SPEED 4096 x 1 BIT STATIC RAM.
2147H1 2147H2 2147H3 2147HL3 2147H 2147HL
Max. Access Time (ns) 35 45 55 55 70 70
Max. Active Current (rnA) 180 180 180 125 160 140
Max. Standby Current (rnA) 30 30 30 15 20 10
Pinout, Function, and Power Com Direct Performance Upgrade for 2147
patible to Industry Standard 2147
HMOS II Technology Automatic PowerDown
Completely Static Memory-No Clock High Density 18Pin Package

or Timing Strobe Required
Directly TTL Compatible-All Inputs
Equal Access and Cycle Times and Output
Single + 5V Supply
Separate Data Input and Output
O.8-2.0V Output Timing Reference
Levels ThreeState Output
The Intel 2147H is a 4096-bit static Random Access Memory organized as 4096 words by 1-bit using
HMOS-II, Intel's next generation high-performance MOS technology. It uses a uniquely innovative design
approach which provides the ease-of-use features associated with non-clocked static memories .and the
reduced stanqby power dissipation associated with clocked static memories. To the user this means low
standby power dissipation without the need for clocks, address setup and hold times,nor reduced data
rates due to cycle times that are longer than access times.
CS controls the power-down feature. In less than a cycle time after CS goes high-deselecting the 2147H
-the part automatically reduces its power requirements and remains in this low power standby mode as
long as CS remains high. This device feature results in system power savings as great as 85% in larger
systems, where the majority of devices are deselected.
The 2147H is placed in an 18-pin package configured with the industry standard 2147 pinout. It is directly
TTL compatible in all respects: inputs, output, and a single + 5V supply. The data is read out nondestruc-
tively and has the same polarity as the input data. A data input and a separate three-state output are used.
PIN CONFIGURATION LOG IC SYMBO L BLOCK DIAGRAM

Ao @
Ao Vee -Vee
A,
A, A6 A2
AJ
~GND
A2 A7
A4
AJ Aa As MEMORY ARRAY
A4 Ag A6 DOUT 64 ROWS
A7 64 COLUMNS
As A,o As
DOUT A" Ag
A,o
WE DIN
A"
DIN WE CS
@
DIN------f DOUT
PIN NAMES
AO-A" ADDRESS INPUTS Vee POWER (+5V)
WE WRITE ENABLE GND GROUND
CS CHIP SELECT
D,N DATA INPUT
DoUT DATA OUTPUT
TRUTH TABLE
B Wl MODE OUTPUT POWER
L L WRITE HIGHZ ACTIVE
Intel. Corporation assumes no responsibility for the use of any circuitry other than cirCUitry embodied In an Intel product. No other CIrCUIt patent licenses are Implied
Intel Corporation. 1979. 1980 April. 1980
7-225
2147H
ABSOLUTE MAXIMUM RATINGS* *COMMENT: Stresses above those listed under "Abso-
lute Maximum Ratings" may cause permanent damage
Temperature Under Bias . . . . . . . . . . . .. - 10 C to 85C to the device. This is a stress rating only and functional
Storage Temperature. . . . . . . . . . . .. - 65C to + 150C operation of the device at these or any other conditions
Voltage on Any Pin above those indicated in the operational sections of this
With Respect to Ground . . . . . . . . . . .. - 3.5V to + 7V specification is not implied. Exposure to absolute maxi-
Power Dissipation ........................... 1.2W mum rating conditions for extended periods may affect
D.C. Output Current ......................... 20 mA device reliability.
D.C. AND OPERATING CHARACTERISTICS[1]

(T A = OC to 70C, Vee = + 5V 10%, unless otherwise noted.)
2147H1, 2, 3 2147HL3 2147H 2147HL
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Unit Min. Typ,l21 Max. Min. Typ,l21 Max.
III Input Load Current 0.01 10 0.01 10 /l- A 0.01 10 0.01 10
(All Input Pins)
ILO Outut Leakage Current 0.1 50 0.1 50 /l- A 0.1 50 0.1 50

Icc Operating Current 120 170 115 mA 100 150 100 135
180 125 mA 160 140
ISB Standby Current 18 30 6 15 mA 12 20 7 10
I po l3] Peak Power-On Current 35 70 25 50 mA 25 50 15 30
V1L Input Low Voltage -3.0 0.8 -3.0 0.8 V -3.0 0.8 -3.0 0.8
V1H Input High Voltage 2.0 6.0 2.0 6.0 V 2.0 6.0 2.0 6.0
VOL Output Low Voltage 0.4 0.4 V 0.4 0.4
VOH Output High Voltage 2.4 2.4 V 2.4 2.4
los Output Short Circuit -150 + 150 -150 + 150 mA -150 + 150 -150 + 150
Current
NOTES:
1. The operating ambient temperature range is guaranteed with transverse air flow exceeding 400 linear feet per minute.
2. Typical limits are at Vcc =5V, TA = + 25C, and specified loading.
3. A pullup resistor to Vcc on the CS input is required to keep the device deselected; otherwise, poweron current approaches Icc
active.
Vee
A.C. TEST CONDITIONS 510U
Input Pulse Levels GND to 3.0V DOUT - - -.......- -...
Input Rise and Fall Times 5 ns 30 pF

300~~
(INCLUDING
Input Timing Reference Levels 1.5V SCOPE AND
JIG)
Output Timing Reference Level (2147H-1) 1.5V
Output Timing Reference Levels
(2147H, H-2, H-3, HL, HL-3) 0.8-2.0V
Output Load See Figure 1 Figure 1. Output Load
Vee
5101!
CAPACITANCE[4] (TA=25C, f= 1.0 MHz)
DOUT - - -.......- -....
5 pF
C IN Input Capacitance 5 pF VIN = OV
COUT Output Capacitance 6 pF VOUT=OV
NOTE:
4. This parameter is sampled and not 100% tested. Figure 2. Output Load for tHZ. tLZ. twz. tow
7-226
2147H
A.C. CHARACTERISTICS (TA =OC to 70C, Vcc = + 5V 10%, unless otherwise noted.)
Read Cycle
2147H3, 2147H,
2147H1 2147H2 HL3 2147HL
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
t [1] Read Cycle Time 35 45 55 70 ns
RC
tAA Address Access Time 35 45 55 70 ns
tACS1[8] Chip Select Access Time 35 45 55 70 ns
tACS2[9] Chip Select Access Time 35 45 65 80 ns
tOH Output Hold from Address Change 5 5 5 5 ns
td2,3,7] Chip Selection to Output in Low Z 5 5 10 10 ns
tHZ[2,3,7] Chip Deselection to Output in High Z 0 30 0 30 0 30 0 40 ns
tpu Chip Selection to Power Up Time 0 0 0 0 ns
t pD Chip Deselection to Power Down Time 20 20 20 30 ns
WAVEFORMS
Read Cycle No. 1[4,5]
tRe
ADDRESS ~(': )\
----./1\
tOH
tAA .
DATA OUT PREVIOUS DATA VALID
XX X ~ DATA VALID
Read Cycle No. 2[4,6]
tRe
~r l
I\.
tACS . -tHZ-
,
tlZ
~XX~
HIGH IMPEDANCE HIGH
DATA OUT DATA VALID
J IMPEDANCE
Vee
SUPPL Y
CURRENT
Ice_-~p~1-~
50%
_ _ _ _r-_tP0==L 50%
158 - - - - -
NOTES:
1. All Read Cycle timings are referenced from the last valid address to the first transitioning address.
2. At any given temperature and voltage condition, tHZ max. is less than tLZ min. both for a given device and from device to device.
3. Transition is measured 500 mV from steady state voltage with specified loading in Figure 2.
5~ Device is continuously selected, CS = V1L .
7. This parameter is sampled and not 100% tested.
8. Chip deselected for greater than 55 ns prior to selection.
9. Chip deselected for a finite time that is less than 55 ns prior to selection. If the deselect time is 0 ns, the chip is by definition
selected and access occurs according to Read Cycle NO.1. Applies to 2147H, 2147HL, 2147H-3, and 2147HL3.
7227
Intel 2147H
A.C. CHARACTERISTICS (Continued)

Write Cycle
I I 2147H3, 2147H,
2147H1 2147H2 HL3 2147HL
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
twe[2] Write Cycle Time 35 45 55 70 ns
tew Chip Selection to End of Write 35 45 45 55 ns
tAW Address Valid to El'ld of Write 35 45 45 55 ns
tAS Address Setup Time 0 0 0 0 ns
twp Write Pulse Width 20 25 25 40 ns
tWR Write Recovery Time 0 0 10 15 ns
tow Data Valid to End of Write 20 25 25 30 ns
tOH Data Hold Time 10 10 10 10 ns
twZ[3] Write Enabled to Output in High Z 0 20 0 25 0 25 0 35 ns
tow[3] Output Active from End of Write 0 0 0 0 ns
----------'we
WAVEFORMS
Write Cycle No. 1 ADDRESS
(WE CONTROLLED)[4) L tew
CSI' I~ ~ t AW - -
II IIII
I----'wo-
tAS----j _twp~
Ii
\\
DATA IN
I
t ---tDW-~
DATA IN VALID
~tOHj
.l
Write Cycle No.2 ~--------twe---------~

I--- twz ----I
~
DATA O U T - - - - - - - D - A - T A - U - N D - E F - I N - E D - - - - -.....
" " ,~,,.~,1-----
-'<>w
(CS CONTROLLED)[4) ADDRESS
~-------~w-------~
~+-----'<>w - - - - - - - . . j -
DATA IN DATA IN VALID
NOTES:
DATA our - - - " ' J:J. .------------
DATA UNDEFINED
1. If CS goes high simultaneously with WE high, the output remains in a high impedance state.
HIGH IMPEDANCE
2. All Write Cycle timings are referenced from the last valid address to the first transitioning address.
3. Transition is measured 500 mV from steady state voltage with specified loading in Figure 2.
4. CS or WE must be high during address transitions.
7228
inter 2716
16K (2K x 8) UV ERASABLE PROM
Fast Access Time Pin Compatible to Intel@ 2732 EPROM

- 350 ns Max. 27161
- 390 ns Max. 27162 Simple Programming Requirements
- 450 ns Max. 2716 Single Location Programming
490 ns Max. 27165 - Programs with One 50 ms Pulse
- 650 ns Max. 27166
Single + 5V Power Supply Inputs and Outputs TTL Compatible

during Read and Program
Low Power Dissipation
525 mW Max. Active Power
- 132 mW Max. Standby Power Completely Static
The Intel 2716 is a 16,384bit ultraviolet erasable and electric;:ally programmable readonly memory (EPROM). The 2716
operates from a single 5volt power supply, has a static standby mode, and features fast single address location program
mingo It makes designing with EPROMs faster, easier and more economical.
The 2716, with its single 5-volt supply and with an access time up to 350 ns, is ideal for use with the newer high performance
+5V microprocessors such as Intel's 8085 and 8086. A selected 2716-5 and 2716-6 is available for slower speed applications.
The 2716 is also the first EPROM with a static standby mode which reduces the power dissipation without increasing access
time. The maximum active power dissipation is 525 mW while the maximum standby power dissipation is only 132 mW, a
75% savings.
The 2716 has the simplest and fastest method yet devised for programming EPROMs - single pulse TTL level programming.
No need for high voltage pulsing because all programming controls are handled by TTL signals. Program any location at any
time-either individually, sequentially or at random, with the 2716's single address location programming. Total prog ramming
time for all 16,384 bits is only 100 seconds.
PIN CONFIGURATION MODE SELECTION

2716
~
Ce/PGM Oe Vpp Vec OUTPUTS
(181 (201 (211 (241 (911,13171
MODE
Read VIL VIL +5 +5 DOUT

Standby VIH Don't Care +5 +5 High Z
Program Pulsed VIL to VIH VIH +25 +5 DIN

Program Verify VIL VIL +25 +5 DOUT
Program Inhibit VIL VIH +25 +5 High Z
BLOCK DIAGRAM
t Refer to 2732 UATAOUTPUTS
data sheet for

specifications
Vcc~
----
00 01
PIN NAMES
ADDRESSES
CHIP ENABLE/PROGRAM
AO-A,O
OUTPUT ENABLE ADDRESS
OUTPUTS INPUTS
7229 AFN-00811A-Ol
2716
PROGRAMMING
The programming specifications are described in the Data Catalog PROM/ROM Programming Instructions Section. ;
Absolute Maximum Ratings*

Temperature Under Bias . . . . . . . . . . . . . -10C to +80C *COMMENT: Stresses above those listed under "Absolute Maxi-
Storage Temperature . . . . . . . . . . . . . . -65C to +125C mum Ratings" may cause permanent damage to the device. This is a
All Input or Output Voltages with stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sec-
Respect to Ground . . . . . . . . . . . . . . . +6V to -0.3V tions of this specification is not implied. Exposure to absolute
Vpp Supply Voltage with Respect maximum rating conditions for extended periods may affect device
to Ground During Program . . . . . . . . +26.5V to -0.3V rei iabi Iity.
DC and AC Operating Conditions During Read

2716 2716-1 2716-2 2716-5 2716-6
Temperature Range OC _ 70C OC _ 70C OC _ 70C OC _ 70C OC _ 70C
VCC Power Supply[1,2) 5V 5% 5V 10% 5V 5% 5V5% 5V5%
Vpp Power Supply [2) VCC VCC VCC VCC VCC
READ OPERATION
Limits
Symbol Parameter Unit Conditions
Min. Typ.[31 Max.
III Input Load Current 10 J1A VIN = 5.25V
ILO Output Leakage Current 10 J1A VOUT = 5.25V
IpP1 [2) Vpp Current 5 mA Vpp = 5.25V
'CC1[2) Vcc Current (Standby) 10 25 mA CE = VIH, OE = VIL
ICC2[21 V CC Current (Active) 57 100 mA OE =cr= VIL
VIH Input High Voltage 2.0 V c c+l V
VO H Output High Voltage 2.4 V IOH = -400 J1A

NOTES: 1. VCC must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
2. Vpp may be connected directly to VCC except during programming. The supply current would then be the sum of ICC and IpP1.
3. Typical values are for T A = 25C and nominal supply voltages.
4. This parameter is only sampled and is not 100% tested.
Typical Characteristics
ICC CURRENT ACCESS TIME ACCESS TIME

VS. VS. vs.
TEMPERATURE CAPACITANCE TEMPERATURE
70 700
700
60 ~
-r--- r-- 600 600
50
r--- r--~
ICC2 ACTIVE CURRENT
500 500
--
~=Vll Vee = 5V
< 40 VCC=5V -r---
--
400 ~ 400
!
-
'-'
--
'-' ~ '-'
-
!:? 30
-
300 ;: 300
f.-- f--- !----
~
20 200 200
ICCI STANDBY CURRENT
~=VIH
10 VCC=5V~
100 100
o
o 10
I
20 30 40 50
1
60 70 80 100 200 300 400 500 600 700 800
o
o 10 20 30 40 50 60 70 80
TEMPERATURE I C) CllpF) TEMPERATURE I'C)
7-230 AFN-OOB11 A-02

2716
Limits (ns)
2716 2716-1 2716-2 2716-5 2716-6 Test

Symbol Parameter Conditions
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
tACC Address to Output Delay 450 350 390 450 450 CE = OE = VI L
tCE CE to Output Delay 450 350 390 490 650 QE=VIL
tOE Output Enable to Output Delay 120 120 120 160 200 CE = V IL
tOF Output Enable High to Output Float 0 100 0 100 0 100 0 100 0 100 CE=VIL
tOH Output Hold from Addresses, CE or 0 0 0 0 0 CE=OE=V IL

OE Whichever Occurred First
Capacitance [4] TA= 25C, f= 1 MHz A.C. Test Conditions:

Symbol Parameter Typ. Max. Unit Conditions Output Load: 1 TTL gate and C L = 100 pF
Input Rise and Fall Times: ~20 ns
CIN Input Capacitance 4 6 pF VIN = OV Input Pulse Levels: 0.8V to 2.2V
COUT Output Capacitance 8 12 pF VOUT = OV Timing Measurement Reference Level:
Inputs 1V and 2V
Outputs 0.8V and 2V
A. C. Waveforms [11
ADDRESSES
ADDRESSES
VALID
CE-----------------+--~
teE
6E----------------~~--------~
'-------+-- . . . . . . . . . .
[6J
tDF
-~""""I"""'II"""'I~-
HIGH Z HIGH Z
OUTPUT-------------------------------+-+-. . . .~~
----........ ~- ...... .
NOTE: 1. Vce must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
3. Typical values are for TA = 25 C and nominal supply voltages.
5. OE may be delayed up to tACC - tOE after the falling edge of CE without impact on tACC.
6. tDF is specified from OE or CE, whichever occurs first.
7-231 AFN-OOB11 A-03

2716
TYPICAL 16K EPROM SYSTEM
A8-15 ....... - - -...- - - - - - - - - - - . . . . . . . ,
ADO-7 t-t--......- . .I
8212
ADDRESS VCC
ALE ~"-_ _ _ _""I LATCH
RD r-r--------------------~
8085
512 X 8
O_C_
PROM
3S04A
.... N CE5
(1)(1)
101M (J(J CES
eE7
This scheme accomplished by using CE (PD) as the primary decode_ OE (CS) is now controlled by previously unused
signal. RD now controls data on and off the bus by way of OE_
A selected 2716 is available for systems which require CE access of less than 450 ns for decode network operation_
The use of a PROM as a decoder allows for:
a) Compatibility with upward (and downward) memory expansion.
b) Easy assignment of ROM memory modules, compatible with PUM modular software concepts.
SK, 16K, 32K, 64K 5V EPROM/ROM FAMILY

PRINTED CIRCUIT BOARD LAYOUT
, D D
A'2 0 A B
D
co . _ a
_._
D_
A,o 0
A9~.
~~
0.-
..:..:... -
..-
A11 00--4IOI-4l, . . . . . - . - . . . _ _ _ _
..
~ .-
~------~
~
~
~
..
~
"'--
~"'--
~
....
o ... '-
:.. ~.... "'--
~
A3 00- - ' "

~ ........
~~
A2 00- - -
A, 0 0 - - -...
Ao -------... - ....
~
~
~
'......
GNDOD-- -. . . .~. . . . . . . . . .-~.~.~c.'Wi
+50D--.........:~. . . .---~. . . . . . . . . . . . . . .- ...
........
~
.................a
:
+
0
COMPONENT SlOE
0 0.
00 0,0203 CEl 04 0 5 0 6 0 7 eE2
7-232
2716
ERASURE CHARACTERISTICS OUTPUT OR-TIEING

The erasure characteristics of the 2716 are such that erasure Because 2716's are usually used in larger memory arrays,
begins to occur when exposed to light with wavelengths Intel has provided a 2 line control function that accomo-
shorter than approximately 4000 Angstroms (A). It should dates this use of multiple memory connections. The two
be noted that sunlight and certain types of fluorescent line control function allows for:
lamps have wavelengths in the 3000-4000A range. Data a) the lowest possible memory power dissipation, and
show that constant exposure to room level fluorescent b) complete assurance that output bus contention will
lighting could erase the typical 2716 in approximately 3
not occur.
years, while it would take approximatley 1 week to cause
erasure when exposed to direct sunlight. If the 2716 is to To most efficiently use these two control lines, it is recom-
be exposed to these types of lighting conditions for ex- mended that CE (pin 18) be decoded and used as the
tended periods of time, opaque labels are available from primary device selecting function, while OE (pin 20) be
Intel which should be placed over the 2716 window to made a common connection to all devices in the array and
prevent unintentional erasure. connected to the READ Iine from the system control bus.
The recommended erasure procedure (see Data Catalog This assures that all deselected memory devices are in their
PROM/ROM Programming Instruction Section) for the low power standby mode and that the output pins are only
2716 is exposure to shortwave ultraviolet light which has active when data is desired from a particular memory
a wavelength of 2537 Angstroms (A). The integrated dose device.
(i.e., UV intensity X exposure time) for erasure should be
PROGRAMMING
a minimum of 15 W-sec/cm 2 . The erasure time with this
dosage is approximately 15 to 20 minutes using an ultra- Initially, and after each erasure, all bits of the 2716 are in
violet lamp with a 12000 f.1W/cm 2 power rating. The 2716 the "1" state. Data is introduced by selectively program-
should be placed within 1 inch of the lamp tubes during ming "a's" into the desired bit locations. Although only
erasure. Some lamps have a filter on their tubes which "a's" will be programmed, both "1 's" and "a's" can be
should be removed before erasure. presented in the data word. The only way to change a "0"
to a "1" is by ultraviolet light erasure.
DEVICE OPERATION
The 2716 is in the programming mode when the Vpp power
The five modes of operation of the 2716 are Iisted in Table supply is at 25V and OE is at VIH. The data to be pro-
I. It should be noted that all inputs for the five modes are at
grammed is applied 8 bits in parallel to the data output
TTL ievels. The power supplies required are a +5V V CC and
pins. The levels required for the address and data inputs are
a Vpp. The Vpp power supply must be at 25V during the
TTL.
three programming modes, and must be at 5V in the other
two modes. When the address and data are stable, a 50 msec, active
high, TTL program pulse is applied to the CE/PGM input.
TABLE I. MODE SELECTION
A program pulse must be applied at each address location
~
CE/PGM DE VPP Vee OUTPUTS to be programmed. You can program any location at any
(18) (20) (21) (24) (911.1317)
MODE
time - either individually, sequentially, or at random.
The program pulse has a maximum width of 55 msec. The
Read VIL VIL +5 +5 DOUT
2716 must not be programmed with a DC signal applied to
Standby VIH Don't Care +5 +5 High Z
+25
the CE/PGM input.
Program Pulsed VIL to VIH VIH +5 DIN
Program Verify VIL VIL +25 +5 DOUT Programming of multiple 2716s in parallel with the same
+25 +5 High Z
Program Inhibit VIL VIH data can be easily accomplished due to the simplicity of
the programming requirements. Like inputs of the paral-
READ MODE
leled 2716s may be connected together when they are pro-
The 2716 has two control functions, both of which must be grammed with the same data. A high level TTL pulse
logically satisfied in order to obtain data at the outputs. applied to the CE/PGM input programs the paralleled
Chip Enable (CE) is the power control and should be used 2716s.
for device selection. Output Enable (OE) is the output
PROGRAM INHIBIT
control and should be used to gate data to the output
pins, independent of device selection. Assuming that Programming of mUltiple 2716s in parallel with different
addresses are stable, address access time hACC) is equal to data is also easily accomplished. Except for CE/PGM, all
the delay from CE to output (tCE). Data is available at like inputs (including OE) of the parallel 2716s may be
the outputs 120 ns (tOE) after the falling edge of OE, common. A TTL level program pulse applied to a 2716's
assuming that CE has been low and addresses have been CE/PGM input with Vpp at 25V will program that 2716.
stable for at least tACC - tOE. A low level CE/PGM input inhibits the other 2716 from
STANDBY MODE being programmed.
The 2716 has a standby mode which reduces the active PROGRAM VERIFY
power dissipation by 75%, from 525 mW to 132 mW. The A verify should be performed on the programmed bits to
2716 is placed in the standby mode by applying a TTL high determine that they were correctly programmed. The verify
signal to the CE input. When in standby mode, the outputs may be performed wth Vpp at 25V. Except during pro-
are in a high impedence state, independent of the OE input. gramming and program verify, Vpp must be at 5V.
7-233 AFN-00911 A-05

2732
32K (4K x 8) UV ERASABLE PROPJI
Fast Access Time: Pin Compatible to Intel 2716 EPROM
- 450 ns Max. 2732
- 550 ns Max. 27326 Completely Static
Single +5V 5% Power Supply
Simple Programming Requirements
Output Enable for MCS-85 and
Single Location Programming
MCS-86 Compatibility
- Programs with One 50ms Pulse
Low Power Dissipation:
150mA Max. Active Current Three-State Output for Direct Bus
30mA Max. Standby Current Interface
The Intel 2732 is a 32,768-bit ultraviolet erasable and electrically programmable read-only memory (EPROM I. The 2732
operates from a single 5-volt power supply, has a standby mode, and features an output enable control. The total program-
ming time for all bits is three and a half minutes. All these features make designing with the 2732 in microcomputer systems
faster, easier, and more economical.
An important 2732 feature is the separate output control, Output Enable (OE) from the Chip Enable control (CE). The
OE control eliminates bus contention in multiple bus microprocessor systems. Intel's Application Note AP-72
describes the microprocessor system implementation of the OE and CE controls on Intel's 2716 and 2732 EPROMs.
AP-72 is available from Intel's Literature Department.
The 2732 has a standby mode which reduces the power dissipation without increasing access time. The maximum active
current is 150mA, while the maximum standby current is only 30mA, an 80% savings. The standby mode is achieved by
applying a TTL-high signal to the CE input.
~
vee
CE OE/Vpp Vcc OUTPUTS
A7
MODE
(18) (20) (24) (911,13-17)
A6 As
Ar, Ag Read VIL V IL +5 DOUT
A4 All Standby VIH Don't Care +5 High Z
A3 OENpp Program V IL Vpp +5 DIN
A2 A 10
Program Verify V IL V IL +5 DOUT
Al CE
Program Inhibit VIH Vpp +5 High Z
Ao ~
00 06
1 Os
2 BLOCK DIAGRAM
GNO 03
DATA OUTPUTS
VCCO--- 00-07
GNDO---
PIN NAMES
YGATING
Ao-A" ADDRESSES AO-All
CE CHIP ENABLE ADDRE$S
INPUTS
OE OUTPUT ENABLE 32.768BIT
OUTPUTS CEll MATRIX
0-7
INTel CORPORATION ASSUMES NO RESPONSIBILITY FOR THE USE OF ANY CIRCUITRY OTHER THAN CIRCUITRY EMBODIED IN AN INTEL PRODUCT. NO OTHER CIRCUIT PATENT LICENSES ARE IMPLIED.
INTEL CORPORATION. 1980 7-234 FEBRUARY 1980
2732
PROGRAMMING
The programming specifications are described in the Data Catalog PROM/ROM Programming Instructions Section.
ABSOLUTE MAXIMUM RATINGS 'COMMENT

Stresses above those listed under Absolute Maximum Ratings may cause
Temperature Under Bias ............ -10C to +80C permanent damage to the device. This is a stress rating only and functional
Storage Temperature .............. -65C to +125C operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied
All Input or Output Voltages with Exposure to absolute maximum rating conditions for extended periods
Respect to Ground ................... +6V to -0.3V may affect device reliability

TA= OC to 70C, VCC = +5V 5%
READ OPERATION
Limits
Symbol Parameter Min. Typ.i 1 1 Max. Unit Conditions
ILl1 Input Load Current (except OE/Vpp) 10 J.l.A VIN = 5.25V
1L12 OE/Vpp Input Load Current 10 J.l.A VIN = 5.25V
ILO Output Leakage Current 10 J.l.A VOUT = 5.25V
ICC1 Vcc Current (StandbYI 15 30 mA CE = VIH, OE = VIL
ICC2 Vce Current (Activel 85 150 mA OE = CE =- VIL
VIH Input High Voltage 2.0 Vec+1 V
VOL Output Low Voltage 0.45 V IOL=2.1mA
VOH Output High Voltage 2.4 V IOH = -400J.l.A
Note: 1. Typical values are for TA = 25C and nominal supply voltages.
Icc CURRENT CE TO OUTPUT DELAY (t CE ) CE TO OUTPUT DELAY (t CE )

VS.TEMPERATURE VS. CAPACITANCE VS. TEMPERATURE
500 500
--
90
~
E
u
80
70
60
50
400
-;:;, 300
I--I--
~
-I--
-u
400
300
~ f.-
...-...- -- ~ ....
u ;:t
40 200
30 I---+--f-- ~~ ~I:ANDBY CURRENT)
200
20 I---+--f-- Vce = 5V 100
10 TA = 25 C Vce = 5V
0 100 1 L I I
0 10 20 30 40 50 60 70 80 o 100 200 300 400 500 600 700 800 00 10 20 30 40 50 60 70 80
TEMPERATURE ( C) CL (pFI
TEMPERATURE ( C)
7-235
2732
5%
TA = OC to 70C, Vee = +5V
2732 Limits 27326 Limits

Test
Symbol Parameter Unit
Min. Max. Min. Max. Conditions
t Ace Address to Output Delay 450 550 ns CE=OE=V 1L
tCE CE to Output Delay 450 550 ns 0E=V 1L
tOE Output Enable to Output Delay 120 120 ns CE= V 1L
tOF Output Enable High to Output Float 0 100 0 100 ns CE=V 1L

Output Hold from Addresses, CE or
tOH 0 0 ns CE=OE=V 1L
OE, Whichever Occurred First
CAPACITANCE [1] TA=25C, f=1MHz A.C. TEST CONDITIONS

Symbol Parameter Typ. Max. Unit Conditions Output Load: 1 TTL gate and CL = 100pF
CIN1 Input Capacitance Input Rise and Fall Times: ::; 20ns
Except OE/Vpp 4 6 pF VIN = OV Input Pulse Levels: 0.8V to 2.2V
Timing Measurement Reference Level:
CIN2 OE/Vpp Input Inputs 1V and 2V
Capacitance 20 pF VIN = OV Outputs O.8V and 2V
COUT Output Capacitance 12 pF VOUT = OV
A.C. WAVEFORMS [2]
ADDRESSES
ADDRESSES
VALID
tDF
[4)
HIGH Z HIGH Z
OUTPUT --------.:;......;;.-----+.f-H~_<
NOTES:
1. THIS PARAMETER IS ONL Y SAMPLED AND IS NOT 100% TESTED.
2. ALL TIMES SHOWN IN PARENTHESES ARE MINIMUM TIMES AND ARE NSEC UNLESS OTHERWISE SPECI FlED.
3. DE MAY BE DELAYED U~O 33~ AFTER THE FALLING EDGE OF CEWITHOUT IMPACT ON tACC.
4. tDF IS SPECI FlED FROM OE OR CEo WHICHEVER OCCURS FIRST.
7236
2732
ERASURE CHARACTERISTICS puts are in a high impedance state, independent of the

OE input.
The erasure characteristics of the 2732 are such that
erasure begins to occur when exposed to light with Output ORTieing
wavelengths shorter than approximately 4000 Angstroms Because EPROMs are usually used in larger memory ar-
(A). It should be noted that sunlight and certain types of rays, Intel has provided a 2 line control function that ac-
fluorescent lamps have wavelengths in the 3000-4000A commodates this use of multiple memory connections.
range. Data show that constant exposure to room level The two line control function allows for:
fluorescent lighting could erase the typical 2732 in a) the lowest possible memory power dissipation, and
approximately 3 years, while it would take approximately 1 b) complete assurance that output bus contention will
week to cause erasure when exposed to direct sunlight. If not occur.
the 2732 is to be exposed to these types of lighting
conditions for extended periods of time, opaque labels are To most efficiently use these two control lines, it is
available from Intel which should be placed over the 2732 recommended that CE (pin 18) be decoded and used as
window to prevent unintentional erasure. the primary device selecting function, while TIE (pin 20)
be made a common connection to all devices in the ar-
ray and connected to the READ line from the system
The recommended erasure procedure (see Data Catalog)
control bus. This assures that all deselected memory
for the 2732 is exposure to shortwave ultraviolet light
devices are in their low power standby mode and that
which has a wavelength of 2537 Angstroms (9)' The inte-
the output pins are only active when data is desired
grated dose (i.e., UV intensity X exposure time) for
from a particular memory device.
erasure should be a minimum of 15 W-sec/cm 2. The
erasure time with this dosage is approximately 15 to 20 Programming
minutes using an ultraviolet lamp with a 12000 I1W/cm2
Initially, and after each erasure, all bits of the 2732 are in
power rating. The 2732 should be placed within 1 inch of
the "1" state. Data is introduced by selectively program-
the lamp tubes during erasure. Some lamps have a filter
ming "O's" into the desired bit locations. Although only
on their tubes which should be removed before erasure.
"O's" will be programmed, both "1's" and "O's" can be
presented in the data word. The only way to change a "0"
DEVICE OPERATION to a "1" is by ultraviolet light erasure.
The five modes of operation of the 2732 are listed in The 2732 is in the programming mode when the OE/Vpp
Table 1. A single 5V power supply is required in the read input is at 25V. It is required that a 0.1 J.lF capacitor be
mode. All inputs are TTL levels except for OElV pp during placed across OE/Vpp and ground to suppress spurious
programming. In the program mode the OElV pp input is voltage transients which may damage the device. The data
pulsed from a TTL level to 25V. to be programmed is applied 8 bits in parallel to the data
output pins. The levels required for the address and data
inputs are TTL.
TABLE 1. Mode Selection
When the address and data are stable, a 50msec, active
low, TTL program pulse is applied to the CE input. A
~
CE OENpp vee OUTPUTS
MODE (18) (20) (24) (911,1317) program pulse must be applied at each address location to
be programmed. You can program any location at any
Read V IL V IL +5 DOUT
time - either individually, sequentially, or at random. The
Standby V IH Don't Care +5 High Z
program pulse has a maximum width of 55msec. The 2732
Program V IL Vpp +5 DIN must not be programmed with a DC signal applied to the
- -
Program Verify V IL V IL +5 DOUT
CE input.
Program Inhibit V IH Vpp +5 High Z Programming of multiple 2732s in parallel with the same
data can be easily accomplished due to the simplicity of
the programming requirements. Like inputs of the
Read Mode paralleled 2732s may be connected together when they
The 2732 has two control functions, both of which must are programmed with the same data. A low level TTL pulse
be logically satisfied in order to obtain data at the out- applied to the CE input programs the paralleled 2732s.
puts. Chip Enable (CE) is the power control and should Program Inhibit
be used for device selection. Output Enable (OE) is the
output control and should be used to gate data to the Programming of multiple 2732s in parallel with different
output pins, independent of device selection. Assuming data is also easily accomplished. Except for CE, all like
inputs (including OE I of the parallel 2732s may be
that addresses are stable, address access time (tAcc) is
common. A TTL level program pulse applied to a 2732's
equal to the delay from CE to output (tCE)' Data is
CE input with OE/Vpp at 25V will program that 2732. A
available at theoutputs 120ns (tOE) after the falling edge
of OE, assuming that CE has been low and addresses high level CE input inhibits the other 2732s from being
programmed.
have been stable for at least tAcc -. tOE,
Standby Mode Program Verify
The 2732 has a standby mode which reduces the active A verify should be performed on the programmed bits to
power current by 80%, from 150mA to 30mA. The 2732 is determine that they were correctly programmed. The
placed i~ the standby mode by applying a TTL high verify is accomplished with OElVpp and CE at VIL. Data
signal to the CE input. When in standby mode, the out- should be verified tDv after the falling edge of CEo
7-237
2732A
32K (4K x 8) UV ERASABLE PROM
200 ns (2732A2) Maximum Access Pin Compatible to 2764 EPROM

Time ... HMOS*E Technology
Compatible to High Speed 8mHz Industry Standard Pinout ... JEDEC

80862 M PU ... Zero WAIT State Approved
Two Line Control Low Standby Current ... 35 mA Max.
The Intel 2732A is a 5V only, 32,384 bit ultraviolet erasable and electrically programmable read-only memory (EPROM). It
is pin compatible to Intel's 450ns 2732. The standard 2732A's access time is 250ns with speed selection (2732A-2)
available at 200ns. The access time is compatible to high performance microprocessors, such as the 8mHz 8086-2. In
these systems, the 2732A allows the microprocessor to operate without the addition of WAIT states.
An important 2732A feature is the separate output control, Output Enable (OE), from the Chip Enable control (CE). The OE
control eliminates bus contention in multiple bus microprocessor systems. Intel's Application Note AP-72 describes the
microprocessor system implementation of the OE and CE controls on Intel's EPROMs. AP-72 is available from Intel's
Literature Department.
The 2732A has a standby mode which reduces the power dissipation without increasing access time. The maximum
active current is 150mA, while the maximum standby current is only 35mA, a 75% saving. The standby mode is achieved
by applying a TIL-high signal to the CE input.
The 2732A is fabricated with HMOS*-E technology, Intel's high speed N-channel MOS Silicon Gate Technology.
2764 MODE SELECTION

PIN CONFIGURATION
~
2732A CE OE/Vpp Vcc OUTPUTS
PIN CONFIGURATION Vpp VCC
MODE
(18) (20) (24) (9-11.1317)
A'2 PGM
A7 N.C.l 11 Read V IL VIL +5 DOUT
A6 AS Standby V IH Don't Care +5 High Z
AS Ag
Program V IL Vpp +5 DIN
A4 An
A3 DE Program Verify VIL VIL +5 DOUT
A2 A,a Program Inhibit V IH Vpp +5 High Z
Al CE
AO
00 06
0, 05
BLOCK DIAGRAM
02 04
GND 03
DATA OUTPUTS
111For total compatibility from VCC~ 00-07
2732A provide a trace to pin 26 GNO~
PIN NAMES
yGATING
Ao-A'l ADDRESSES AO-All
ADDRESS
CE CHIP ENABLE
INPUTS
OE OUTPUT ENABLE 32.7638IT
0 0 -07 OUTPUTS CELL MATRIX
'HMOS is a patented process of Intel Corporation.
7_,)~A
inter
2758
8K (1 K x 8) UV ERASABLE LOW POWER PROM
Single + 5V Power Supply Fast Access Time: 450 ns Max. in
Active and Standby Power Mode.
Simple Programming Requirements
- Single Location Programming
- Programs with One 50 ms Pulse
Inputs and Outputs TTL Compatible
during Read aoo Pr....m
Low Power Dissipation

525 mW Max. Active Power
Completely Static
132 mW Max. Standby Power ThreeState Outputs for OR Ties
The Intel@ 2758 is a 8192-bit ultraviolet erasable and electrically programmable read-only memOfy (~PAOM). The 2758
operates from a single 5-volt power supply, has a static standby mode, and features fast slAgle address location pro-
gramming. It makes designing with EPROMs faster, easier and more economical. The total pr.amming Hme fOf all
8192 bits is 50 seconds.
The 2758 has a static standby mode which reduces the power dissipation without increasj.nQ) aeoess time. TM maxi-
mum active power dissipation is 525mW, while the maximum standby power dissipati.fII is 04'My 132mW, a 75%
savings. Powerd<?wn is achieved by applying a TTL-high signal to the CE input.
A 2758 system may be designed for total upwards compatibility with Intel's 16K 2716 EPFitQM (see Applications Nota
72). The 2758 maintains the simplest and fastest method yet devised for programming EPRQMs - single pulse TTL-
level programming. There is no need for high voltage pulsing because all programming cQntrols are han cUed by TTL
signals. Program any location at any time - either individually, sequentially, or at random, with the single address
location programming.
I~
A7
A6 CE/PGM AJII @I \/pp Vee OUTPUTS
AS (18.) (19) (~ (2t) (34) (911.13.17)
A4 Vpp
MODE
A3 DE
A2
Al Read V IL V IL VIL +5 +5 DOUT
AO 07
Don't
00 06 Standby VIH VIL +5 +5 High Z
Care
Program Pulsed VIL to VIH VIL VIH +25 +5 DIN

Program Veri fy V IL VIL VIL +25 +5 DOUT
Program Inhibit VIL VIL VIH +25 +5 High Z
PIN NAMES BLOCK DIAGRAM

DATA OUTPUTS
AO-Ag ADDRESSES Vcco--- 00-07
CE/PGM CHIP ENABLE/PROGRAM
OE OUTPUT ENABLE
0 0 -0 7 OUTPUTS
SELECT REFERENCE
AR INPUT LEVEL
AO-Ag
ADDRESS
INPUTS
INTEL CORPORATION ASSUMES NO RESPONSIBILITY FOR THE USE OF ANY CIRCUITRY OTHER THAN CIRCUITRY EMBODIED IN AN INTEL PROQUCT. NO OTHER CIRCUIT PATENT LICENSES ARE IMPLIED.
'INTEL CORPORATION. 1979 FESRUARY 1979
7-239
2758
PROGRAMMING
The programming specifications are described in the Data Catalog PROM/ROM Programming Instructions section.
Absolute Maximum Ratings*
Temperature Under Bias . . . . . . . . . . . . . -10C to +80C *COMMENT: Stresses above those listed under "Absolute Maxi-
Storage Temperature. . . . . . . . . . . -65C to +125C mum Ratings" may cause permanent damage to the device. This is a
All Input or Output Voltages with stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sec-
Respect to Ground . . . . . . . . . . . . . . . +6V to -0.3V
tions of this specification is not implied. Exposure to absolute
Vpp Supply Voltage with Respect maximum rating conditions for extended periods may affect device
to Ground During Programming . . . . +26.5V to -0.3V reliability.
READ OPERATION
T A = OC to 70C, Vee[1,2] = +5V 5%, Vpp[2] = Vee
Limits
Symbol Parameter Unit Conditions
Min. Typ,l3J Max.
III Input Load Current 10 /1 A VIN = 5.25V
ILO Output Leakage Current 10 /1A VOUT = 5.25V
IpP1 [2] Vpp Current 5 mA Vpp= 5.25V

lee1 [2] Vee Current (Standby) 10 25 mA CE = VIH, OE = VIL
leC2[21 Vee Current (Active) 57 100 rnA OE=CE=VIL

A [4] Select Reference Input Level -0.1 V liN = 10 /1A
R 0.8
VIH Input High Voltage 2.0 Vee + 1 V
VOH Output High Voltage 2.4 V IOH = -400 /1 A
NOTES: 1. Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
2. Vpp may be connected directly to Vee except during programming. The supply current would then be the sum of lee and IpP1.
3. Typical values are for TA = 25 e and nominal supply voltages.
4. AR is a reference voltage level which requires an input current of only 10 /-IA. The 2758 81865 is also available which has a reference
voltage level of VIH instead of VIL.
Typical Characteristics
ICC CURRENT ACCESS TIME ACCESS TIME

VS. VS. VS.
TEMPERATURE CAPACITANCE TEMPERATURE
70 700 700
~
60
50
~
r-- r--
-- i""- ~
ICC2 ACTIV CURRENT
CE= VIL
vcc = 5V
600
500
600
500
Vcc = 5V
--
40 400 ] 400
!
v v u
1l 30
20 ICC1 STA~BY
CEo VIH
CURR NT
300
200
V I--
u
;: 300
200 - I-- f-- I-- - ~
Vcc = 5V
10 100 100
o o
o 10 20 30 40 50 60 70 80 100 200 300 400 500 600 700 800 o 10 20 30 40 50 60 70 80
TEMPERATURE lOCI CL IpFI TEMPERATURE lOcI
7-240
2758
o
T A = OC to 70 e, VCC[1] = +5V 5%, Vpp[2] = Vee
Limits
Min. Typ.[31 Max.
tAec Address to Output Delay 250 450 ns CE = OE = VIL
tCE CE to Output Delay 280 450 ns OE = VIL
tOE Output Enable to Output Delay 120 ns CE = VIL
tDF Output Enable High to Output Float 0 100 ns CE = VIL
tOH Output Hold From Addresses, CE 0 ns CE=OE=VIL

or OE Whichever Occurred First
Capacitance[4) T A = 25C, f = 1 MHz A.C. Test Conditions:

Symbol Parameter Typ. Max. Unit Conditions Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: :;;;;;20 ns
CIN Input Capacitance 4 6 pF VIN = OV
Input Pulse Levels: 0.8V to 2.2V
COUT Output Capacitance 8 12 pF VOUT= OV Timing Measurement Reference Level:
Inputs 1 V and 2V
NOTE: Please refer to page 2 for notes.
Outputs 0.8V and 2V
A.C. Waveforms[51
ADDRESSES
ADDRESSES
VALID
CE----------------~~~
tCE
1+---(450 MAX.)
6E----------+-----~
\'---------+--. . . . . . . . . . (7)
~
(6)
tOF
tOE
(100 MAX.)
(120 MAX.)
[6)
tOH-
(0)
_-.~~r""'lr""'l....- .
HIGH Z HIGH Z
OUTPUT-------------------------------f-+-~~~~
"-.a..._ _ _.........._
NOTES: 1. Vec must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
3. Typical values are for TA = 25C and nominal supply voltages.
5. All times shown in parentheses are minimum times and are nsec unless otherwise specified.
6. OE may be delayed up to 330 ns after the falling edge of CE without impact on tACC.
7. tDF is specified from DE or CE, whichever occurs first.
7-241
2758
ERASURE CHARACTERISTICS the outputs 120 ns (tOE) after the falling edge of OE,
The erasure characteristics of the 2758 are such that erasure assuming that CE has been low and addresses have been
begins to occur when exposed to light with wavelengths stable for at least tACC - tOE'
shorter than approximately 4000 Angstroms (A). It should
be noted that sunlight and certain types of fluorescent STANDBY MODE
lamps have wavelengths in the 3000-4000A range. Data The 2758 has a standby mode which reduces the active
show that constant exposure to room level fluorescent power dissipation by 75%, from 525 mW to 132 mW. The
lighting could erase the typical 2758 in approximately 3 2758 is placed in the standby mode by applying a TTL high
years, while it would take approximately 1 week to cause signal to CEinput. When in standby mode, the outputs
erasure when exposed to direct sunlight. If the 2758 is to are in a high impedence state, independent of the OE input.
be exposed to these types of lighting conditions for ex-
tended periods of time, opaque labels are available from
Intel which should be placed over the 2758 window to OUTPUT ORTIEING
prevent unintentional erasure. Because EPROMs are usually used in larger memory arrays,
Intel has provided a 2 line control function that accommo-
The recommended erasure procedure (see Data Catalog dates this use of multiple memory connections. The two line
Programming Section) for the 2758 is exposure to short- control function allows for:
wave ultraviolet light which has a wavelength of 2537
a) the lowest possible memory Power dissipation, and
Angstroms (A). The integrated does (i.e., UV intensity X
b) complete assurance that output bus contention will
exposure time) for erasure should be a minimum of 15
not occur.
W-sec/cm 2 . The erasure time with this dosage is approxi-
mately 15 to 20 minutes using an ultraviolet lamp with To most efficiently use these two control lines, it is recom
12,000 p.w /cm 2 power rating. The 2758 should be placed mended that CE (pin 18) be decoded and used as th~
within 1 inch of the lamp tubes during erasure. Some lamps primary device selecting function, while OE (pin 20) be
have a filter on their tubes which should be removed before made a common connection to all devices in the array and
erasure. connected to the READ line from the system control bus.
This assures that all deselected memory devices are in their
DEVICE OPERATION low power standby mode and that the output pins are only
The five modes of operation of the 2758 are listed in Table active when data is desired from a particular memory device.
1. It should be noted that all inputs for the five modes are
at TTL levels. The power supplied required are a +5V Vcc PROGRAMMING
and a Vpp . The Vpp power supply must be at 25V during
Initially, and after each erasure, all bits of the 2758 are in
the two programming modes, and must be at 5V in the
the "1" state. Data is introduced by selectively program-
other three modes. In all operational modes, AR must be
ming "O's" into the desired bit locations. Although only
at V I L (except for the 2758 S 1865 which has AR at V I H).
"O's" will be programmed, both "1 's" and "O's" can be
presented in the data word. The only way to change a "0"
TABLE I. MODE SELECTION to a "1" is by ultraviolet light erasure.
I~
The 2758 is in the programming mode when the Vpp
CE/PGM AR DE Vpp Vee OUTPUTS power supply is at 25V and OE is at V IH. The data to be
(18) (19) (20) (21) (24) (911,1317) programmed is applied 8 bits in parallel to the data output
MODE pins. The levels required for the address and data inputs are
TTL.
Read V IL VIL VIL +5 +5 DOUT
When the address and data are stable, a 50 msec,
Don't
Standby VIH VIL +5 +5 High Z active high, TTL program pulse is applied to the CE/PGM
Care
input. A program pulse must be applied at each address
Program Pulsed VIL to VIH VIL VIH +25 +5 DIN
location to be programmed. You can program any location
Program Verify VIL VIL VIL +25 +5 DOUT
at any time - either individually, sequentially, or at ran-
Program Inhibit VIL VIL VIH +25 +5 High Z
dom. The program pulse has a maximum width of 55 msec.
READ MODE The 2758 must be programmed with a DC signal applied

to the CE/PGM input.
The 2758 has two control functions, both of which must be
logically satisfied in order to obtain data at the outputs. Programming of multiple 2758s in parallel with the same
Chip Enable (CE) is the power control and should be used data can be easily accomplished due to the simplicity of
for device selection. Output Enable (DE) is the output the programming requirements. Like inputs of the paral
control and should be used to gate data to the output lelled 2758s may be connected together when they are
pins, independent of device selection. Assuming that programmed with the same data. A high level TTL pulse
addresses are stable, address access time (tACC) is equal to applied to the cr/PGM input programs the paralleled
the delay from CE to output (tCE)' Data is available at 2758s.
7242
2758
PROGRAM INHIBIT PROGRAM VERIFY
Programming of multiple 2758s in parallel with different A verify should be performed on the programmed bits to
data is also easily accomplished. Except for CE/PGM, all determine that they were correctly programmed. The verify
like inputs (including DE) of the parallel 2758s may be may be performed with Vpp at 25V. Except during pro-
common. A TTL level program pulse applied to a 2758's gramming and program verify, V pp must be at 5V.
CE/PGM input with Vpp at 25V will program that 2758.
A low level CE/PGM input inhibits the other 2758 from
being programmed.
7-243
I
CHAPTER 8
DEVELOPMENT SUPPORT TOOLS
INTELLEC SERIES 11185 MODEL 235
Complete 8051 application development support is

based on the Intellec Model 235 development system. A
Model 235 system is configured from a Model 225
system and Model 720 Flexible Disk Subsystem, de-
scribed in the following pages. The Model 235 provides
the ISIS-II operating system, supported by integral CRT
and keyboard, 1.25M bytes of flexible disk storage and
64K bytes of RAM.
The Model 225 system without the additional disk drives

can support limited 8051 development tasks which re-
quire only a single drive and 250K bytes of storage.
inter MODEL225
INTELLEC@SERIES 11/85
MICROCOMPUTER DEVELOPMENT SYSTEM
Complete microcomputer development Integral 250K byte floppy disk drive

system for MCS86, MCS85, with total storage capacity expandable
MCS80, MCS48, and MCS51 to over 2M bytes of floppy disk storage
microprocessor families and 7.3M bytes of hard disk storage
Powerful ISIS-II Disk Operating System

High performance 8085A-2 CPU, with relocating macroassembler,
64K bytes RAM memory, and linker, locater, and CRT based editor
4K bytes ROM memory CREDIT
Self-test diagnostic capability Supports PL/M, FORTRAN, BASIC,

PASCAL and COBOL high level
languages
Built-in interfaces for high speed paper
tape reader/punch, printer, and univer- Software compatible with previous
sal PROM programmer Intellec ~ systems
The Intellec Series 11/85 Model 225 Microcomputer Development System is a performance enhanced, com-
plete microcomputer development system integrated into one compact package. The Model 225 includes
a CPU with 64K bytes of RAM, 4K bytes of ROM, a 2000-character CRT, detachable full ASCII keyboard
with cursor controls and upperllower case capability, and a 250K-byte floppy disk drive. Powerful ISIS-II
Disk Operating System software allows the Model 225 to be used quickly and efficiently for assembling
and debugging programs for Intel's MCS-86, MCS-85, MCS-80, MCS-48, or MCq:51 microprocessor
families. ISIS-II performs all file handling operations for the user, leaving him free to concentrate on the
details of his own application. When used with an optional in-circuit emulator (ICETM) module, the Model
225 provides all of the hardware and software development tools necessary for the rapid development of a
microcomputer-based product. Optional storage peripherals provide over 2 million bytes of floppy disk,
and 7.3 million of hard disk storage capacity.
The following are trademarks of Intel Corporation and may be used only to identify Intel products: BXP. Intellec. Multibus. i. iSBC. Multimodule. ICE. iSBX. PROMPT. iCS. Library
Manager. Promware. Insite. MCS. RMX. Intel. Megachassis. UPI. Intelevision. Micromap. ~Scope and the combination of ICE. iCS. iSBC. iSBX. MCS. or RMX and a numerical
suffix.
Intel Corporation 1980 121599-001 Rev. A
MODEL 225
FUNCTIONAL DESCRIPTION high technology LSI components. Known as the

integrated processor card (lPC), it occupies the
Hardware Components first slot in the cardcage. A second slave CPU card
is responsible for all remaining 1/0 control
The Intellec Series 11/85 Model 225 is a highly- including the CRT and keyboard interface. This
integrated microcomputer development system card, mounted on the rear panel, also contains its
consisting of a CRT chassis with a 6-slot cardcage, own microprocessor, RAM and ROM memory, and
power supply, fans, cables, single floppy disk 1/0 interface logic, thus, in effect, creating a dual
drive, and two printed circuit cards. A separate, processor environment. Known as the 1/0 con-
full ASCII keyboard is connected with a cable. troller (IOC), the slave CPU card communicates
A block diagram of the Model 225 is shown in with the IPC over an 8-bit bidirectional data bus.
Figure 1.
Expansion - Five remaining slots in the cardcage

CPU Cards - The master CPU card contains its are available for system expansion. Additional
own microprocessor, memory, 1/0, interrupt and expansion of 4 slots can be achieved through the
bus interface circuitry implemented with Intel's addition of an Intellec Series II expansion chassis.
!
8-LEVEL BAUD RATE
64K BYTES 4K BYTES SERIAL SERIAL
PRIORITY GENERATOR &
RAM ROM CHANNELO CHANNEL1
INTERRUPT REAL-TIME CLOCK
8251A 8251A
8259A 8253A
BUS
CONTROLLER PRIORITY SYSTEM 8080A-2 8085A-2 BIDIRECTIONAL
8219 RESOLUTION CLOCKS CPU CPU DRIVER
CABLE BUS
8228 . 8253
8K ROM SYSTEM INTERVAL
CONTROLLER TIMER
8041A
CPU
8271 8275
TAPE TAPE
FLOPPY CRT KEYBOARD PRINTER
PUNCH READER
CONTROLLER CONTROLLER
Figure 1. Intellec Series 11/85 Model 225 Microcomputer Development System Block Diagram
AFN-014?4R
MODEL225
System Components troller. The master processor on the IPC transfers

a character for display to the 10C, where it is
The heart of the IPC is an Intel NMOS 8-bit micro- stored in RAM. The CRT controller reads a line at a
processor, the 8085A-2, running at 4.0 MHz. 64K time into its line buffer through an Intel 8257 DMA
bytes of RAM memory are provided on the board controller and then feeds one character at a time
using 16K RAMs. 4K of ROM is provided, pre- to the character generator to produce the video
programmed with system bootstrap "self-test" signal. Timing for the CRT control is provided by
diagnostics and the Intellec Series 11/85 System an Intel 8253 interval timer. The screen display is
Monitor. The eight-level vectored priority inter- formatted as 25 rows of 80 characters. The full set
rupt system allows interrupts to be individually of ASCII characters is displayed, including lower
masked. Using Intel's versatile 8259A interrupt case alphas.
controller, the interrupt system may be user pro-
grammed to respond to individual needs. Keyboard - The keyboard interfaces directly to
the 10C processor via an 8-bit data bus. The
Input/Output keyboard contains an Intel UPI-41 Universal
Peripheral Interface, which scans the keyboard,
IPC Serial Channels - The I/O subsystem in the encodes the characters, and buffers the
Model 225 consists of two parts: the 10C card and characters to provide N-key rollover. The
two serial channels on the IPC itself. Each serial keyboard itself is a high quality typewriter style
channel is RS232 compatible and is capable of run- keyboard containing the full ASCII character set.
ning asynchronously from 110 to 9600 baud or syn- An upperllower case switch allows the system to
chronously from 150 to 56K baud. Both may be be used for document preparation. Cursor control
connected to a user defined data set or terminal. keys are also provided.
One channel contains current loop adapters. Both
channels are implemented using Intel's 8251 A Peripheral Interface
USART. They can be programmed to perform a
variety of I/O functions. Baud rate selection is A UPI-41 Universal Peripheral Interface on the 10C
accomplished through an Intel 8253 interval timer. board provides interface for other standard
The 8253 also serves as a real-time clock for the Intellec peripherals including a printer, high
entire system. I/O activity through both serial speed paper tape reader, high speed paper tape
channels is signaled to the system through a punch, and universal PROM programmer. Com-
second 8259A interrupt controller, operating in a munication between the IPC and 10C is maintained
polled mode nested to the primary 8259A. over a separate 8-bit bidirectional data bus. Con-
nectors for the four devices named above, as weli
IOC Interface - The remainder of system I/O as the two serial channels, are mounted directly
activity takes place in the 10C. The 10C provides on the 10C itself.
interface for the CRT, keyboard, and standard
Intellec peripherals including printer, high speed
Control
paper tape reader/punch, and universal PROM User control is maintained through a front panel,
programmer. The 10C contains its own independ- consisting of a power switch and indicator,
ent microprocessor, an 8080A-2. The CPU controls reset/boot switch, run/halt light, and eight inter-
all I/O operations as well as supervising rupt switches and indicators. The front panel cir-
communications with the IPC. 8K bytes of ROM cuit board is attached directly to the IPC, allowing
contain all I/O control firmware. 8K bytes of RAM the eight interrupt switches to connect to the
are used for CRT screen refresh storage. These primary 8259A, as well as to the Intellec Series II
do not occupy space in Intellec Series II main bus.
memory since the 10C is a totally independent
microcomputer subsystem. Integral Floppy Disk Drive
Integral CRT The integral floppy disk is controlled by an Intel
8271 single chip, programmable floppy disk con-
Display - The CRT is a 12-inch raster scan type troller. It transfers data via an Intel 8257 DMA con-
monitor with a 50/60 Hz vertical scan rate and troller between an 10C RAM buffer and the
15.5kHz horizontal scan rate. Controls are pro- diskette. The 8271 handles reading and writing of
vided for brightness and contrast adjustments. data, formatting diskettes, and reading status, all
The interface to the CRT is provided through an upon appropriate commands from the 10C
Intel 8275 single-chip programmable CRT con- microprocessor.
Q A
inter MODEL225
MULTIBUS Interface Capability and memory by operating at different priority

levels. Resolution of bus exchanges is syn-
chronized by a bus clock signal derived
All Intellec Series 11/85 models implement the independently from processor clocks. Read /write
industry standard MUL TIBUS protocol. The transfers may take place at rates up to 5 MHz. The
MULTIBUS protocol enables several bus masters, bus structure is suitable for use with any Intel
such as CPU and DMA devices, to share the bus microcomputer family.
SPECI FICATIONS Memory Access Time
RAM - 470 ns max

Host Processor (I PC) PROM - 540 ns max
8085A-2 based, operating at 4.0 MHz.

RAM - 64K on the CPU card
ROM - 4K (2K in monitor, 2K in boot/diagnostic)
Bus - MUL TIBUS bus, maximum transfer rate
of 5 MHz Integral Floppy Disk Drive
Clocks - Host processor, crystal controlled at
4.0 MHz, bus clock, crystal controlled at 9.8304 Floppy Disk System Capacity -
MHz 250K bytes (formatted)
Floppy Disk System Transfer Rate-
160K bits/sec
Floppy Disk System Access Time -
I/O Interfaces Track to Track: 10 ms max
Average Random Positioning: 260 ms
Two Serial 110 Channels, RS232C, at 110-9600 baud Rotational Speed: 360 rpm
(asynchronous) or 150-56K baud (synchronous). Average Rotational Latency: 83 ms
Baud rates and serial format fully programmable Recording Mode: FM
using Intel 8251 A USARTs. Serial Channel 1 addi-
tionally provided with 20 mA current loop. Parallel
I/O interfaces provided for paper tape punch,
paper tape reader, printer, and UPP-103 Universal
PROM Programmer.
Physical Characteristics
Interrupts CHASSIS
8-level, maskable, nested priority interrupt net- Width -17.37 in. (44.12 cm)
work initiated from front panel or user selected Height -15.81 in. (40.16 cm)
devices. Depth -19.13 in. (48.59 cm)
Weight - 73 lb. (33 kg)
Direct Memory Access (DMA) KEYBOARD
Standard capability on MULTIBUS interface; Width -17.37 in. (44.12 cm)

implemented for user selected DMA devices Height - 3.0 in. (7.62 cm)
through optional DMA module-maximum transfer Depth - 9.0 in. (22.86 cm)
rate of 5 MHz. Weight - 61b. (3 kg)
fVi AFN-014248
intJ MODEL225
Eiectricai Characteristics Equipment Suppiied

Model 225 Chassis including:
Integrated Processor Card (lPC)
DC POWER SUPPLY
1/0 Controller Board (laC)
CRT
Typical
ROM-Resident System Monitor
Volts Amps System
Detachable keyboard
Supplied Supplied Requirements
ISIS-II System Diskette with MCS-80/MCS-85
Macroassembler
+ 55% 30.0 17.0
+125% 2.5 1.1 ISIS-II CREDIT Diskette CRT-Based Text Editor
-125% 0.3 0.1
-10 5% 1.0 0.08
+ 15 5%* 1.5 1.5 Documentation Supplied
+ 24 5%* 1.7 1.7
A Guide to Microcomputer Development Systems,
*Not available on bus. 9800558
Intel/ec Series 1/ Model 22X /23X Installation
Manual, 9800559
ISIS-II System User's Guide, 9800306
Intel/ec Series /I Hardware Reference Manual,
9800556
AC REQUIREMENTS FOR MAINFRAME
8080/8085 Assembly Language Programming
110V, 60 Hz - 5.9 Amp Manual, 9800301
220V, 50 Hz - 3.0 Amp ISIS-II 8080/8085 Assembler Operator's Manual,
9800292
Intel/ec Series II Systems Monitor Source
Listing, 9800605
Intellec Series II Schematic Drawings, 9800554
ISIS-II CREDIT (CRT-Based Text Editor) User's
Guide, 9800902
Environmental Characteristics
Additional manuals may be ordered from any Intel
Operating Temperature -16C to 32C sales representative or distributor office, or from
(61F to 90F) Intel Literature Department, 3065 Bowers Avenue,
Humidity - 20% to 80% Santa Clara, California 95051.
ORDERING INFORMATION
Part
Number Description
MDS-225* Intellec(~ Series 11/85 Model 225

Microcomputer
Development System (110V 160 Hz)
MDS-226* Intellec"J Series 11/85 Model 226
Microcomputer
Development System (220V 150 Hz)
*HMDS" is an ordering code only, aOid is not used as a product

name or trademark. MDS is a registered trademark of
Mohawk Data SCiences Corp.
8-n AFN-014248
INTELLEC SINGLE/DOUBLE DENSITY
FLEXIBLE DISK SYSTEM
Flexible Disk System Providing High Data Recorded on Double Density

Speed Input/Output and Data Storage Flexible Disk is in Soft-Sectored Format
for Intellec Microcomputer Which Allows Y2 Million Byte Data
Development Systems Capacity with Up to 200 Files Per
Flexible Disk
Available in Both Single Density and Associated Software Supports Up to
Double Density Systems Four Double Density Drives and Two
Single Density Drives, Providing Up to
2.5 Megabytes of Storage in One
Data Recorded on Single Density
System
Flexible Disk Is in IBM Soft-Sectored
Format Which Allows Y4 Million Byte Dynamic Allocation and Deallocation of
Data Capacity with Up to 200 Files Per Flexible Disk Sectors for Variable
Flexible Disk Length Files
The Intellec Flexible Disk System is a sophisticated, general purpose, bulk storage peripheral for use with the
Intellec Microcomputer Development System. The use of a flexible disk operating system significantly re-
duces program development time. The software system known as ISIS-11 (Intel System Implementation
Supervisor), provides the ability to edit, assemble, compile, link, relocate, execute and debug programs, and
performs all file management tasks for the user.
The following are trademarks of Intel Corporation and may be used only to identify Intel products: i. Intel. INTEL, INTELLEC, MCS, 1m , ICS. ICE, UPI, BXP. iSBC, iSBX, iNSITE, iRMX,
CREDIT, RMXl80, ILScope, Multibus, PROMPT, Promware, Megachassis, Library Manager, MAIN MULTI MODULE, and the combination of MCS, ICE, SBC, RMX or iCS and a numerical
suffix; e.g., iSBC-80.
Intel Corporation 1980
8-7
HARDWARE puter Set. This 8-bit processor includes four 3002 Cen-
tral Processing Elements (2-bit slice per CPE), a 3001
The Intellec@ flexible disk system provides direct Microprogram Control Unit, and 512 x 32 bits of 3604
access bulk storage, intelligent controller, and two flex- programmable-read-only-memory (PROM) which stores
ible disk drives. Each single density drive provides 1/4 the microprogram. It is the execution of the micro-
million bytes of storage with a data transfer rate of program by the microcomputer set which actually
250,000 bits/second. The double density drive provides effects the control capability of the Channel Board.
1/2 million bytes of storage with a data transfer rate of
500,000 bits/second. The controllers are implemented This board is the same for either single or double den-
with Intel's powerful Series 3000 Bipolar Microcomputer sity drives, except that the Series 3000 microcode is dif-
Set. The controllers provide interface to the Intellec ferent.
System bus. Each single density controller will support
two drives. Each double density controller will support INTERFACE BOARD
up to four drives. The flexible disk system records all The Interface Board provides the flexible disk controller
data in soft sector format. with a means of communication with the flexible disk
The single/double density flexible disk controllers each drives, as well as with the .lntellec system bus. Under
consists of two boards, the Channel Board and the Inter- control of the microprogram being executed on the
face Board. These two printed circuit boards reside in Channel Board, the Interface Board generates those
the Intellec System chaSSis. The boards are shown in signals which ca~se the read/write head on the selected
the photograph, and are described in more detail in the drive to be loaded (i.e., to come in contact with the flex-
following paragraphs. ible disk platter), cause the head to move to the proper
track and verify successllli operation. The Interface
Board accepts the data beirlg read off the flexible disk,
interprets synchronizing bii:patterns, checks the valid-
ity of the data using a cyclic redundancy check (CRC)
polynomial, and then transfers the data to the Channel
Board.
During write operations, the Interface Board outputs the
data and clock bits to the selected drive at the proper
times, and generates the CRC characters which are then
appended to the data.
When the flexible disk controller requires access to
SINGLEIDOUBLE DENSITY CHANNEL BOARD Intellec system memory, the Interface Board requests
the DMA master control of the system bus, and gener-
ates the appropriate memory command. The Interface
Board also acknowledges 'I/O commands as required by
the Intellec bus.
The Flexible Disk System is capable of performing
seven different operations: recalibrate, seek, format
track, write data, write deleted data, read data, and verify
CRC.
The channel board is different for single and double den-
sity drives, due to the different recording techniques
used. The single density controller boards support one
DOUBLE DENSITY INTERFACE BOARD
set of dual single density drives. The double density
(SINGLE DENSITY INTERFACE BOARD controller boards support up to two sets of dual double
IS SIMILAR TO THE ONE SHOWN ABOVE) density drives (four drives total).
The double density controller may co-reside with the
Intel single density controller to allow conversion of
CHANNEL BOARD
single density flexible disk to double denSity format,
The Channel Board is the primary control module within and provide up to 2.5M bytes of storage.
the flexible disk system. The Channel Board receives,
decodes, and responds to channel commands from the FLEXIBLE DISK DRIVE MODULES
Central Processor Unit (CPU) in the Intellec system. The
Each flexible disk drive consists of read/write and con-
Channel Board can access a block of Intellec system
memory to determine the particular flexible disk opera- trol electronics, drive mechanisms, read/write head,
tions to be performed and fetch the parameters required track positioning mechanism, and the removable flex-
for the successful completion of the specified opera- ible disk platter. These components interact to perform
tion. the following functions:
The control functions of the Channel Board have been Interpret and generate control signals
achieved with an 8-bit microprogrammed processor, Move read/write head to selected track
designed with Intel's Series 3000 Bipolar Microcom- Read and write data
8-8
ASSOCIATED SOFTWARE - INTEL library management, run-time supports, and utility

management.
SYSTEMS IMPLEMENTATION
SU PERVISOR (ISIS-II) ISIS-II provides automatic implementation of random ac-
cess disk files. Up to 200 files may be stored on each 1/4
million byte flexible disk for single density system or on
The Flexible Disk Drive System is to be used in con- each 1/2 million byte flexible disk for double density
junction with the ISIS-II Operating System_ ISIS-II pro- system. For more information, see the ISIS-II data speci-
vides total file management capabilities, file editing, fication sheet.
ISISII OPERATIONAL ENVIRONMENTAL FLEXIBLE DISK DRIVE PERFORMANCE

ISIS II SPECIFICATION
32K bytes RAM memory
48K bytes when using Assembler Macro feature
Single Double
64K bytes when using PUM or Fortran
Density Density
System Console
Single or Double density Flexible Disk Drive Capacity (Unformatted):
Per Disk 3.1 megabits 6.2 megabits
HARDWARE SPECIFICATIONS Per Track 41 kilobits 82 kilobits
MEDIA Capacity (Formatted):
Single Density Double Density Per Disk 2.05M bits 4.10 megabi ts
Per Track 26.6K bits 53.2 kilobits
Flexible Disk Double Density Specified
Data Transfer Rate 250 kilobits/ 500 kilobits/
Flexible Disk
sec sec
One Recording Surface One Recording Surface
Access Time:
IBM Soft Sector Format Soft Sector Format Trackto-Track 10 ms 10 ms
77 Tracks/Diskette 77 TrackslDiskette Head Settling Time 10 ms 10 ms
26 Sectors/Track 52 Sectors/Track Average Random
128 Bytes/Sector 128 Bytes/Sector Positioning Time 260 ms 260 ms
Rotational Speed 360 rpm 360 rpm
PHYSICAL CHARACTERISTICS
Average Latency 83 ms 83 ms
CHASSIS AND DRIVES Recording Mode Frequency M2FM
Mounting: Table-Top Modulation
Height: S.7 in. (14.S cm)
Width: 17.6 in. (44.7 cm)
Depth: 19.4 in. (49.3 cm)
Weight: 43.0 lb. (19.S kg) ENVIRONMENTAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS MEDIA
CHASSIS Temperature:
DC Power Supplies Operating: 15.6C to 51.rC
Supplied Internal to the Cabinet NonOperating: 5C to 55C
AC Power Requirements Humidity:
3-wire input with center conductor (earth ground) tied Operating: 8 to 80% (Wet bulb 29.4 0c)
to chassis NonOperating: 8 to 90%
Singlephase, 115 VAC; 60 Hz; 1.2 Amp Maximum (For DRIVES AND CHASSIS
a Typical Unit) Temperature:
230 VAC; 50 Hz; 0.7 Amp Maximum (For Operating: 10C to 38C
a Typical Un)t) NonOperating: - 35C to 65C
FLEXIBLE DISK OPERATING SYSTEM CONTROLLER Humidity:
DC Power Requirements (All power supplied by Intellec Operating: 20% to 80% (Wet bulb 26.rC)
Development System) NonOperating: 5% to 9S%
CHANNEL BOARD CONTROLLER BOARDS
Single Density Double Density Temperature:
SV @ 3.7SA (typ), SA (max) SV @ 3.7SA (typ), SA (max) Operating: o to 55C
NonOperati ng: - SsoC to 8SoC
INTERFACE BOARD
Humidity:
Single Density Double Density
Operating: Up to 9S% relative humidity without
SV @ 1.SA (typ), 2.SA (max) SV @ 1.SA (typ), 2.SA (max) condensation
- 10V @ 0."1A (typ), NonOperati ng: All conditions without condensa
0.2A (max) tion of water or frost
89
EQUIPMENT SUPPLIED
SINGLE DENSITY DOUBLE DENSITY
Cabinet, Power Supplies, Line Cord, Two Drives Cabinet, Power Supplies, Line Cord, Two Drives
Single Density FDC Channel Board Double Density FDC Channel Board
Single Density FDC Interface Board Double Density FDC Interface Board
Dual Auxiliary Board Connector Dual Auxiliary Board Connector
Flexible Disk Controller Cable Flexible Disk Controller Cable
Flexible Disk Peripheral Cable Flexible Disk Peripheral Cable
Hardware Reference Manual Hardware Reference Manual
Reference Schematics\ Reference Schematics
ISIS-II Single Density System Disk ISIS-II Double Density System Disk
ISIS-II System User's Guide ISIS-II System User's Guide
OPTIONAL EQUIPMENT
MDS-BLD* 10 Blank Flexible Disks
MDS-730/731 * Second Drive Cabinet with two addi-
tional drives
Part Number Description
MDS-710/110V* Flexible Disk drive unit with two
711/220V drives, single density drive con-
troller, software, and cables.
M DS-720-11 OV* Flexible Disk drive unit with two
721/220V drives, double density drive con-
troller, software, and cables.
MDS-730/110V* Add-on drive unit with two drives
731/220V and double density cable, without
controller and software. Can be
used with double density con
troller.
MDS is an ordering cude 01J1y and is not used as a product name or trademark. MDS is a registered trademark of Mohawk Data Sciences
Corporation.
810
8051 SOFTWARE DEVELOPMENT PACKAGE
Symbolic assembly language program- CONV51 Converter for translation of

ming for 8051 microcontrollers 8048 assembly language source code to
8051 assembly language source code
Extends Intellec Microcomputer
Development System to support 8051
program development Provides upward compability from the
MCS-48 family of single-chip
Provides assembler output in standard microcontrollers
Intel hex format
Macro Assembler features conditional Supports conversion of ASM48 source
assembly and macro capabilities code macro definitions
The 8051 software development package provides development system support for the powerful 8051 family of single
chip microcomputers. The package contains a symbolic macro assembler and MCS-48 source code converter.
The assembler produces absolute machine code from 8051 macro assembly language instructions. This object code
may be used to program the 8751 EPROM version of the chip. The assembler output may also be debugged using the
ICE-51TM in-circuit emulator.
The converter translates 8048 assembly language instructions into 8051 source instructions to provide software com-
patibility between the two families of microcontrollers.
This diskette-based software package runs under ISIS-II on an Intellec Microcomputer Development System with 64K
bytes of memory.
AFN01739A
8-11
8051 MACRO ASSEMBLER

Supports 8051 family program develop- Provides software support for many
ment on Intellec Microcomputer Devel- addressing and data allocation
opment Systems capabilities
Gives symbolic access to powerful 8051
hardware features
Symbolic Assembler supports symbol
Produces object file, listing file and table, cross-reference, macro
error diagnostics capabilities, and conditional assembly
The 8051 Macro Assembler (ASM51) translates symbolic 8051 macro assembly language instructions into machine
executable object code. These assembly language mnemonics are easier to program and are more readable than
binary or hexadecimal machine instructions. Also, by allowing the programmer to give symbolic names to memory
locations rather than absolute addresses, software design and debug are performed more quickly and reliably.
The assembler supports macro definitions and calls. This is a convenient way to program a frequently used code
sequence only once. The assembler also provides conditional assembly capabilities.
Cross referencing is provided in the symbol table listing, showing the user the lines in which each symbol was
defined and referenced.
ASM51 provides symbolic access to the many useful addressing features of the 8051 architecture. These features
include referencing for bit and byte locations, and for providing 4-bit operations for BCD arithmetic. The assembler
also provides symbolic access to hardware registers, 1/0 ports, control bits, and RAM addresses.
Math routines are enhanced by the MUltiply and DIVide instructions.
If an 8051 program contains errors, the assembler provides a comprehensive set of error diagnostics, which are
included in the assembly listing or on another file. Program testing may be performed by using the Universal PROM
Programmer and 8751 personality card to program the 8751 EPROM version of the chip, or by using the ICE-51 in-circuit
emulator.
ISI$-II I'tCS-'l "ACRO ASSE"9LER

OBJECT "DDULE PLAC[O IN !FI:CONVRT HEX
ASSEI'tBLER INVOkED BY: : Fl; ASI'I51 ; Fl: COHVRT 51 SVI'tBOlS XREF
..,,,
4 ; Th . .., rout,nQo conI/torts BCD to b,nary and b,no.ry to BCD
BIBB
BIBB 7
BIB17SFB8A
81844BSA
I.
11
12
8186S4FB 13 ,HIL wuraH ; 'lQ:ok out low vrd~r d, 9 I t
a: IJ~
Dilhl Ci'
BIBB 54BF
1-14 I.
I'
IS
17
IS
:
SWAP A
,",,,,! t" P ~~L d ~~' t
::c H
'HIL
I R I
~1.
A.IOFH
by lIJ
,"'Olle h'Qn digIt ,nto low order
;
,
;
l'Iult,ply digIt by 13
n,bble of o,ccu .. ulo.tor
Stoll'", ,ntel'I'Ied, Q til' I'';'$ul t (Ina get

flQsk O;Jt h'gh order d'glt
nl'w cop~ of BeD
DIBD l? :9 ; ~~~I':',~:s~~~er <j,gd 'lnd low ordel' digit

BIB[ F7 ~B f10V@RI,A
aUF 22 21 RET
OliO 84 22 ! D1 'I' de b~ 1B
Bill C-1
811245F8
8114 F;'
,." P;.}:~\:~::;,::~ :~ ~l~~\~~:;r n7~:~!e
"2.
ffOV 9Pl ....
811 ~ 22 RET
27
)(REF SVNBOL TABLE lIST JHG
TYPE VALUE AHI> REFERENCES
B H ()SEC IBFBH 1124

BCOBIH l eSEC IIIGH 131
SINSCI> L CSEC IIIBH 12221
COHVRT l CSEC BIBBH lBl
Sample ASM51 Listing
8-12 AFN01739A
CONV51
8048 TO 8051 ASSEMBLY LANGUAGE
CONVERTER UTILITY PROGRAM
Enables software written for the Preserves comments; translates 8048
MCS-48 family to be upgraded to macro definitions and calls
run on the 8051
Provides diagnostic information and
Maps each 8048 instruction to a warning messages embedded in the
corresponding 8051 instruction output listing
The 8048 to 8051 Assembly Language Converter is a utility to help users of the MCS-48 family of microcomputers
upgrade their designs with the high performance 8051 architecture. By converting 8048 source code to 8051 source
code, the software investment developed for the 8048 is maintained when the system is upgraded.
The goal of the converter (CONV51) is to attain functional equivalence with the 8048 code by mapping each 8048
instruction to a corresponding 8051 instruction. In some cases a different instruction is produced because of the
enhanced instruction set (e.g., bit CLR instead of ANL).
Although CONV51 tries to attain functional equivalence with each instruction, certain 8048 code sequences cannot be
automatically converted. For example, a delay routine which depends on 8048 execution speed would require manual
adjustment. A few instructions, in fact. have no 8051 equivalent (such as those involving P4-P7). Finally, there are a few
areas of possible intervention such as PSW manipulation and interrupt processing, which at least require the user to
confirm proper translation. The converter always warns the user when it cannot guarantee complete conversion.
CONV51 produces two files. The output file contains the ASM51 source program produced from the 8048 instructions.
The listing file produces correlated listings of the input and output files, with warning messages in the output file to
point out areas that may require users' intervention in the conversion.
SPECIFICATIONS Optional Hardware:

Universal PROM Programmer
OPERATING ENVIRONMENT Line Printer
ICE-51 In-Circuit Emulator
Required Hardware: Required Software:
Intellec Microcomputer Development System with ISIS-II Diskette Operating System (V3.4 or later)
Documentation Package:
64K Bytes of RAM
MCS-51 Macro Assembler User's Guide
Flexible Disk Drive(s)
MCS-51 Macro Assembly Language Pocket Reference
System Console
MCS-51 8048-to-8051 Assembly Language Converter
-CRT or hard copy device Operating Instructions for ISIS-II Users
MCI-51-ASM 8051 Software Development
Package
8-13 AFN01739A
inter ICE51
8051 INCIRCUIT EMULATOR
Precise, full-speed, real-time emulation Full symbolic debugging

- Load, drive, timing characteristics
- Full-speed program RAM Single-line assembly and disassembly
- Serial and parallel ports for program instruction changes
User-specified breakpoints Macro commands and conditional

blo~k constructs for automated
Execution trace debugging sessions
- User-specified qualifier registers
- Conditional trigger HELP facility: ICE-51 command syntax
- Symbolic groupings and display reference at the console
- Instruction and frame modes
User confidence test of ICE-51
Emulation timer hardware
The ICE-51 module resides in the Intellec Microcomputer Development System and interfaces to any
. user-designed 8051 system through a cable terminating in an 8051 emulator microprocessor and a pin-
compatible plug. The emulator processor, together with 8K bytes of user program RAM located in the
ICE-51 buffer box, replaces the 8051 device in the user system while maintaining the 8051 electrical and
timing characteristics. Powerful Intellec debugging functions are thus extended into the user system.
Using the ICE-51 module, the designer can emulate the system's 8051 in real-time or single-step mode.
Breakpoints allow the user to stop emulation on user-specified conditions, and a trace qualifier feature
allows the conditional collection of 1000 frames of trace data. Using the single-line 8051 assembler the
user may alter program memory using ASM51 mnemonics and symbolic references, without leaving the
emulator environment. Frequently used command sequences can be combined into compound com-
mands and identified as macros with user-defined names.
The following are trademarks of Intel Corporation and may be used only to describe Intel products: Intel, Intellec, MCS and ICE, and the combination of MCS or ICE and a
numerical suffix. Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are
implied.
c INTEL CORPORATION, 1980 8-14 October 1980

ICE51
FUNCTIONAL DESCRIPTION Symbolic Debugging

The ICE-51 emulator permits the user to define
Integrated Hardware and Software and use symbolic, rather than absolute, refer-
Development ences to program and data memory addresses; ad-
The . ICE-51 emulator allows hardware and soft- ditional symbols are predefined by the ICE-51 soft-
ware development to proceed interactively. This ware for referencing registers, flags, and input!
approach is more effective than the traditional output ports. Thus, the user need not recall or look
method of independent hardware and software up the addresses of key locations in his program
development followed by system integration. With as they change with each assembly, or become
the ICE-51 module, prototype hardware can be involved with machine code.
added to the system as it is designed. Software When a symbol is used for memory reference in an
and hardware integration occurs while the prod- ICE-51 emulator command, the emulator supplies
uct is being developed. the corresponding location as stored in the ICE-51
The ICE-51 emulator assists four stages of devel- emulator symbol table. This table can be loaded
opment: with the symbol table produced by the assembler
during application program assembly. The user
can obtain the symbol table during software prep-
SOFTWARE DEBUGGING
aration simply by using the "DEBUG" switch in
It can be operated without being connected to the the ASM51 macroassembler. Furthermore, the
user's system before any of the user's hardware is user can interactively modify the emulator symbol
available. In this stage ICE-51 debugging capabili- table by adding new symbols or changing or delet-
ties can be used in conjunction with the Intellec ing old ones. This feature provides great flexibility
text editor and 8051 macroassembler to facilitate in debugging and minimizes the need to work with
program development. hexadecimal values.
Through symbolic references in combination with
HARDWARE DEVELOPMENT other features of the emulator, the user can easily:
The ICE-51 module's precise emulation character- Interpret the results of emulation activity col-
istics and full-speed program RAM make it a valu- lected during trace.
able tool for debugging hardware, including time-
Disassemble program memory to mnemonics,
critical serial port, parallel port, and timer inter-
or assemble mnemonic instructions to execut-
faces.
able code.
Examine or modify 8051 internal registers, data
SYSTEM INTEGRATION
memory, or port contents.
Integration of software and hardware can begin Reference labels or addresses defined in a user
when any functional element of the user system program.
hardware is connected to the 8051 socket. As
each section of the user's hardware is completed,
it is added to the prototype. Thus, each section of
the hardware and software is "system" tested in Automated Debugging and Testing
real-time operation as it becomes available.
MACRO COMMAND
SYSTEM TEST A macro is a set of commands which is given a
When the user's prototype is complete, it is tested name. A group of commands which is executed
with the final version of the user system software. frequently can be defined as a macro. The user
The ICE-51 module is then used for real-time emu- can execute the group of commands by typing a
lation of the 8051 to debug the system as a com- colon followed by the macro name. Up to ten
pleted unit. parameters may be passed to the macro.
The final product verification test may be per- Macro commands can be defined at the beginning
formed using the 8751 EPROM version of the 8051 of a debug session and then used throughout the
microcomputer. Thus, the ICE-51 module provides whole session. The user can save one or more
the user with the ability to debug a prototype or macro definitions on diskette for later use. The
production system at any stage in its develop- Intellec text editor may be used to edit the macro
ment without introducing extraneous hardware or file. The macro definitions are easy to include in
software test tools. any later emulation session.
815 AFN.n17Q1A
ICE51
The power of the development system can be ap- tinuously compares the values stored in the break-
plied to manufacturing testing as well as develop- point registers with the status of specified ad-
ment by writing test sequences as macros. The dress, opcode, operand, or port values, and halts
macros are stored on diskettes for use during emulation when this comparison is satisfied.
system test. When an instruction initiates a break, that instruc-
tion is executed completely before the break
COMPOUND COMMAND takes place. The ICE-51 emulator then regains
Compound commands provide conditional execu- control of the console and enters the Interroga-
tion of commands (IF command) and execution of tion Mode. With the breakpoint feature, the user
commands repeatedly until certain conditions are can request an emulation break when his pro-
met (COUNT, REPEAT commands). gram:
Compound commands may be nested any number Executes an instruction at a specific address or
of times, and may be used in macro commands. within a range of addresses.
Example: Executes a particular opcode.
* DEFINE .1 = a ; Define symbol .1 to a Receives a specific Signal on a port pin.
*COUNT 100H ; Repeat the following
Fetches a particular operand from the user pro-
commands 100H times.
gram memory.
.*IF.I AND 1 THEN ; Check if .1 is odd
,,*BYTE .1=.1 ; Fill the memory at location .1 Fetches an operand from a specific address in
to value .1 program memory.
,,*END
. *.1 =.1+ 1 ; Increment .1 by 1. Table 1. Major Emulation Commands
.*END ; Command executes upon
carriage-return after END Command Description
(The characters *, . *, and" * shown in this exam-
GO Begins real-time emulation and op-
ple are system prompts which include an indica- tionally specifies break conditions.
tion of the nesting level of compound commands.)
BRO, BR1, BR Sets or displays either or both
Breakpoint Registers used for stop-
Operating Modes ping real-time emulation.
The ICE-51 software is an Intellec RAM-based pro- STEP Performs Single-step emulation.
gram that provides the user with easy-to-use com- QRO, QR1 Specifies match conditions for qual-
mands for initiating emulation, defining break- ified trace.
points, controlling trace data collection, and dis- TR Specifies or displays trace-data col-
playing and controlling system parameters. lection conditions and optionally
sets Qualifier Register (ORO, OR1).
ICE-51 commands are configured with a broad
range of modifiers which provide the user with Synchroniza- Set and display status of synchroni-
tion Line zation line outputs or latched in-
maximum flexibility in describing the operation to
Commands puts. Used to allow real-time emula-
be performed. tion or trace to start and stop syn-
chronously with external events.
EMULATION
The ICE-51 module can emulate the operation of a
prototype 8051 system, at real-time speed (1.2 to Trace and Tracepoints
12 MHz) or in Single steps. Emulation commands Tracing is used with both real-time and single-
to the ICE-51 module control the process of set- step emulation to record diagnostic information in
ting up, running, and halting an emulation of the the trace buffer as a program is executed. The in-
user's 8051-based system. Breakpoints and trace- formation collected includes opcodes executed,
points enable the ICE-51 emulator to halt emula- port values, and memory addresses. The ICE-51
tion and provide a detailed trace of execution in emulator collects 1000 frames of trace data.
any part of the user's program. A summary of the
emulation commands is shown in Table 1. This information can be displayed as assembler
instruction mnemonics, if desired, for analysis
Breakpoints during interrogation or single-step mode. The
The ICE-51 hardware includes two breakpoint reg- trace-collection facility may be set to run condi-
isters that allow the user to halt emulation when tionally or unconditionally. Two unique trace qual-
specified conditions are met. The emulator con- ifier registers, specified in the same way as break-
8-16 A~N.n17Q1l1..
ICE51
point registers, govern conditional trace activity. Changes can be made in memory and in the 8051
The qualifiers can be used to condition trace data registers, flags, and port values. Commands are
collection to take place as follows: also provided for various utility operations such
as loading and saving program files, defining sym-
Under all conditions (forever). bols, displaying trace data, controlling system
Only while the trace qualifier is satisfied. synchronization and returning control to ISIS-II. A
For the frames or instructions preceding the summary of the basic interrogation and utility
time when a trace qualifier is first satisfied (pre- commands is shown in Table 3. Two time-saving
trigger trace). emulator features are discussed below.
For the frames or instructions after a trace qual-
ifier is first satisfied (post-triggered trace).
SINGLE-LINE ASSEMBLER/DISASSEMBLER -
Table 2 shows an example of a trace display. The single-line assembler/disassembler (ASM and
DASM commands) permits the designer to exam-
Table 2. Trace Display (Instruction Mode) ine and alter program memory using assembly
*r P[ l
language mnemonics, without leaving the emu-
FF~n I rc ep.l J~'~Trt'rT I('~' rJ F7 Fr Trl'F
lator environment or requiring time-consuming
rrrr: rrrn; Fe ,...('vy prrTF, f rrp F'Pf-1 IFf' r
r rr": rrrJII H r-'rv pr, r rr~ r'lPp fFf
program reassembly. When assembling new
PrJ I: rrr7P Ft eFl ~ rpp ~Pfl fFf
rrj': rrr31
rrJ c: rrrtp
1
"
"'r::('C'""
PlC
r-"(,V
f-
.r], ' . . n'
rrl'
prrl
PPII
prf 1
FFf'
FFI'
mnemonic instructions into program memory, pre-
P r 77: rr r7P r'
co
erp r reI' rPfl F FI' viously defined symbolic references (from the
rr'1: rrrn' ~l'" f l,Fr t'1'}1 f'pp FF I'
rr? r::.: rrrq: rrrr POF rrl' I'/P f'!'"Jf.' FF I original program assembly, or subsequently de-
('('1": r('rl-! ..., r ") /' (' ~
~rv ?t P, :/I. f T,.~~ ttf' ?,Pfl HI
rr'J: rn'n ('11:f"- f,'~r (,(rrfl
" t~ prl' III fined during the emulation session) may be used
in the instruction operand field. The emulator will
supply the absolute address or data values as
INTERROGATION AND UTILITY stored in the emulator symbol table. These fea-
Interrogation and utility commands give the user tures eliminate user time spent translating to and
convenient access to detailed information about from machine code and searching for absolute ad~
the user program and the state of the 8051 that is dresses, with a corresponding reduction in trans-
useful in debugging hardware and software. cription errors.
Table 3. Major Interrogation and Utility Commands
Command Description
HELP Displays help messages for ICE-51 emulator command-entry assistance.
LOAD Loads user object program (8051 code) into user program memory, and user symbols into
ICE-51 emulator symbol table.
SAVE Saves ICE-51 emulator symbol table andlor user object program in ISIS-II hexadecimal file.
LIST Copies all emulator console input and output to ISIS-II file.
EXIT Terminates ICE-51 emulator operation.
DEFINE Defines ICE-51 emulator symbol or macro.
REMOVE Removes ICE-51 emulator symbol or macro.
ASM Assembles mnemonic instructions into user program memory.
DASM Disassembles and displays user program memory contents.
ChangelDisplay Change or display value of symbolic reference in ICE-51 emulator symbol table, contents of
Commands key-word references (including registers, 1/0 ports, and status flags), or memory references.
EVALUATE Evaluates expression and displays resulting value.
MACRO Displays ICE-51 macro or macros.
INTERRUPT Displays serial, external, or timer interrupt register settings.
SECONDS Displays contents of emulation timer, in microseconds.
Trace Commands Position trace buffer pointer and select format for trace display.
PRINT Displays trace data pointed to by trace buffer pointer.
8-17 AI=I\.I_n17Q111
ICE51
HELP - The HELP fiie aiiows the user to dispiay Emulation Accuiacy
ICE-51 command syntax information at the Intel- The speed and interface demands of a high-
lee console. By typing "HELP", a listing of all performance single-chip microcomputer require
items for which help messages are available is extremely accurate emulation, including full-
displayed; typing "HELP < Item>" then displays speed, real-time operation with the full function of
relevant information about the item requested, in- the microcomputer. The ICE-51 emulator achieves
cluding typical usage examples. Table 4 shows accurate emulation with an 8051 bond-out chip, a
some sample HELP messages. special configuration of the 8051 microcomputer
family, as its emulation processor.
Each of the 40 pins on the user plug is connected

directly to the corresponding 8051 pin on the
bond-out chip. Thus the user system sees the
emulator as an 8051 microcomputer at the 8051
socket. The resulting characteristics provide ex-
tremely accurate emulation of the 8051, including
speed, timing characteristics, load and drive
values, and crystal operation. The emulator may
draw more power from the user system than a
standard 8051 family device.
Additional bond-out pins provide signals such as

internal address, data, clock, and control lines to
the emulator buffer box. These signals let static
RAM in the buffer box substitute for on-Chip pro-
gram ROM or EPROM or external program mem-
ory. The 8K bytes of full-speed RAM in the buffer
box can be mapped in 4K blocks to anywhere with-
Figure 1. A Typical 8051 Development Configu- in the 64K program memory space of the 8051. The
ration. The host system is an Intellec bond-out chip also gives the emulator "back-
Model 225, plus 1 megabyte dual double- door" access to internal chip operation, so that
density flexible disk storage. The ICE-51 the emulator can break and trace execution with-
module is connected to an SDK-51 sys- out interfering with the values on the user-system
tem design kit. pins.
Table 4. HELP Command
-HELP -HELP IF
Helo is aVC'lilf'ble for trf> follov.!rlo itE'l"1s. TyOfl Pflf' follo\o,'f'\."i ny IF - The .:onditiorlCll COrnfTIa!l~-t .allows ...:onditio!lel ex(>.:'ut i 0.""1 of onE:"
the itelTl rl?mt>. Tt"lE" t'elo items =Cl~I~lot te flb["lrE"vi('ltp ..i . (For fT'Iorf' or more C'ommClnds t-ased on the vi'lues of I:')oolean ..:onditiorlSa
i~tformCltio:l, tyoe t:F.lP PF[P or l'fLF rNFC".) IF (E"XDr> fTHF.f..'l <cr> <tru~~list'>: :=r<.:omlflond> <c!">lfl
Fl'lulc-tion: Trr':E' ('ollf>.:t!o~l: r-"is..:-: <a:d,-irf>ss'> <true!"list> <false!"list)::=r<corr.ffla!ld> <cr'>lP
CO en syr TR C'P C'pr (,P1 ~YJ RPf-F <(,PU~kf>y"ord> rOPIF <exer> <.:r> <.:ommand>: :=/lrl ICF-~l .... omlT'a~ld.
BR BRr PRJ f'lfPPLf <exec) (truetlist>l r
STEF Tril..:'p ['isol?y: FNAPLE <rCE~l~lq:'yword) r!'LSE <cr)
TRAC'r. ~(,"F' PRINi FRP0P <idf>~ltifif>r'> <fal se~ list> 1
OLrF~T' NEWEf;T FVAL.tt/'.1F <instruct ~Ofl'> ENV
tlFLP <rni'skf>d~":O~lstMlt> The <exor>s ere pVcluated in o:-der as Jr.-hit u'lsianed integprs.
Ch."ge/fli solay/[.e f i ~e/P.mov~: JNFC' <1"('It.:t-~=o~hi' If one is rf'acr.ed \o,'hos' vf'lue hi'S lO\o."-or.:Jer nit J (TRUE), all
<C~PNCE> RFN'VF CPYTF PPIT <LH~HTS> commands in ttE' <trueSlist,> follo .... i:lo that <E'XOr) Cl!'"E' thE'~1
<!'ISPLAY> SY~B(,L f'~YTE r".E~ I r~T <cart i t i.O!) executed and ~ll .:omma!lds in tt-~ otrer <true~list>s arid in thf'
RECISTER RFSE'T PEYTE PE'" l.CPC . <str ina) <fals(>~l!st> arc skiDoed. rf all <ext:'r>S ;'('"\'e value wit.h lo\..-
SFCCNDS I<RITF. PPYTE ~A~ SAVE < st!" i nq~ ':O~lstc! ~I t) order hit r (FJ'LSE), thE'fI elll coml1'C'~his irl ('"II <truetlist>s arp
DEF INE STPC XBYTF. EY SUFF'lX <~ymbol i.=~ rf' f> skipeed cHid, if FLSF is rrpSE'~lt, <,,11 commands i~1 t.hp <fil1se~list'>
SYl"fCLI(' (system~ sYlflhols> are exe.:utE'd.
fli'acro: C"omoouud < traceS re fe!" en..:e> (EX: IF. I00P=< T~f~'
VEF JNE DlR CommC"rlds: <unl im i ted~rr<?t.:'hS' cond> STEP
['ISABLE FNAPLE CrUl'IT <usf>rs$symnols,> EL!=F
INCLUDE PUT IF G0
<~ACRC"~DISPLP y> RFPEPT ENro)
<"PCRCf! "'VOC" TIC~'>
-
8-18 AFNQ1791A
ICE51
SPECIFICATIONS Physical Characteristics

Printed Circuit Boards
ICE51 Operating Requirements
Width: 12.00 in. (30.48 cm)
Intellec Microcomputer Development System Height: 6.75 in. (17.15 cm)
(64K RAM required) Depth: 0.50 in. (1.27 cm)
System console Buffer Box
Intellec Diskette Operating System (single or Width: 8.00 in. (20.32 cm)
double density) ISIS-II v. 3.4 or later Length: 12.00 in. (30.48 cm)
Depth: 1.75 in. (4.44 cm)
Equipment Supplied
Weight: 4.0 Ib (1.81 kg)
Printed circuit boards (2)
Emulation buffer box, Intellec interface cables,
and user-interface cable with 8051 emulation Electrical Characteristics
processor DC Power Requirements (from Intellec system)
Crystal power accessory Vee= + 5V, + 5%, -1%
Operating instructions manual lee = 13.2A max; 11.0A typical
Diskette-based ICE-51 software (single and dou- Voo= + 12V, 5%
ble density) 100 = 0.1A max; 0.05A typical
VaB = - 10V, 5%
Emulation Clock IBB = 0.05A max; 0.01A typical
User's system clock (1.2 to 12 MHz) or ICE-51
crystal power accessory (12 MHz)
User plug characteristics at 8051 socket
Environmental Characteristics Same as 8031, 8051, or 8751, except that the user
Operating Temperature: 0 to 40C system will see an added load of 25 pF capaci-
Operating Humidity: Up to 95% relative humidity tance and 50/LA leakage from the ICE-51 emulator
without condensation. user plug at ports 0, 1, and 2.
MCI-51-ICE 8051 Microcontroller In-Circuit
Emulator, cable assembly and
interactive diskette software
8-19 AFN-01791A
UPP-103*
UNIVERSAL PROM PROGRAMMER
*Replaces UPP101, UPP102 Universal PROM Programmers
Intellec development system peripheral Universal PROM mapper software pro

for PROM programming and verification vides powerful data manipulation and
programming commands
Provides flexible power source for

Provides personality cards for program
system logic and programming pulse
ming all Intel PROM families
generation
Holds two personality cards to facilitate

Provides zero insertion force sockets for programming operations using several
both 16pin and 24pin PROMs PROM types
The UPP103 Universal PROM Programmer is an Intellec system peripheral capable of programming and verifying all of
the Intel programmable ROMs (PROMs). In addition, the UPP-103 programs the PROM memory portions of the 8748
microcomputer,8741 UPI, the 8755 PROM and 1/0 chip and the 2920 signal processor. Programming and verification
operations are initiated from the Intellec development system console and are controlled by the universal PROM map-
per (UPM) program.
8-20
UPP103
FUNCTIONAL DESCRIPTION Universal PROM Mapper

Universal PROM Programmer The Universal PROM Mapper (UPM) is the software pro-
The basic Universal PROM Programmer (UPP) consists gram used to control data transfer between paper tape
of a controller module, two personality card sockets, a or diskette files and a PROM plugged into the Universal
front panel, power supplies, a chassis, and an Intellec PROM Programmer. It uses Intellec system memory for
development system intert;onnection cable. An Intel intermediate storage. The UPM transfers data in 8-bit
4040-based intelligent controller monitors the com- HEX, BNPF, or binary object format between paper tape
mands from the Intellec System and controls the data or diskette files and the Intellec system memory. While
transfer interface between the selected PROM persona- the data is in Intellec system memory, it can be dis-
lity card and the Intellec memory. A unique personality played and changed. In addition, word length, bit posi-
card contains the appropriate pulse generation function, and data sense can be adjusted as required for the
tions for each Intel PROM family. Programming and veri- PROM to be programmed. PROMs may also be dupli-
fying any Intel PROM may be accomplished by selecting cated or altered by copying the PROM contents into the
and plugging in the appropriate personality card. The Intellec system memory. Easy to use program and com-
front panel contains a power-on switch and indicator, a pare commands give the user complete control over pro-
reset switch, and two zero-force insertion sockets (one gramming and verification operations. The UPM elimi-
16-pin and one 24-pin or two 24-pin). A central power nates the need for a variety of personalized PROM pro-
supply provides power for system logic and for PROM gramming routines because it contains the program-
programming pulse generation. The Universal PROM ming algorithms for all Intel PROM families. The UPM
Programmer may be used as a table top unit or mounted (diskette based version) is included with the Universal
in a standard 19-inch RETMA cabinet. PROM Programmer.
SPECIFICATIONS
Hardware Interface UPP-955: 8755A personality card with 40-pin adaptor
Data - Two 8-bit unidirectional buses socket
Commands - 3 write commands, 2 read commands, PROM Programming Sockets
one initiate command UPP-501: 16-pin/24-pin socket pair
Physical Characteristics UPP-502: 24-pin/24-pin socket pair
Width - 6 in. (14.7 cm) UPP-562: Socket adaptor for 3621, 3602, 3622, 3602A,
Height - 7 in. (17.2 cm) 3622A
Depth - 17 in. (41.7 cm) UPP-555: Socket adaptor for 3604AL, 36046-6, 3608,
3628, 3636
Weight - 18 Ib (8.2 kg)
UPP-566: Socket adaptor for 3605, 3625, 3605A, 3625A
Electrical Characteristics
AC Power Requirements - 50-60 Hz; 115/230V AC: 80W
Equipment Supplied
Environmental Characteristics
Operating Temperature - OC to 55C Cabinet
Power supplies
Optional Equipment
4040 intelligent controller module
Personality Cards
Specified zero insertion force socket pair
UPP-816: 2716 personality card Intellec development system interface cable
UPP-832: 2732 personality card
Universal PROM Mapper program (diskette-based ver-
UPP-848: 8748,8741 personality card with 40-pin adaptor sion)
socket
UPP-865: 3602, 3622, 3602A, 3622A, 3621, 3604, 3624,
3604A, 3624A, 3604AL, 36046-6, 3605, 3605A, 3625,
3625A, 3608, 3628, 3636 Reference Manuals
UPP-872: 8702A/1702A personality card 9800819 - Universal PROM Programmer User's Manual
UPP-878: 8708/8704/2708/2704 personality card (SUPPLIED)
UPP-103 Universal PROM programmer with
16-pin/24-pin socket pair and
24-pin/24-pin socket pair.
8-21
SDK-51
MeS-51 SYSTEM DESIGN KIT
Complete singleboard microcomputer Extensive system software in ROM:

kit: - Singleline assembler and
disassembler
- Intel 8031 CPU - System debugging commands
Go
- ASCII keyboard and 24character Step
alphanumeric display Breakpoints
- Wirewrap area for custom Interface software:

circuitry - Serial port
- Audio cassette
-Userconfigurable RAM - Intellec system
User's guide, assembly manual, and
- Serial and parallel interfaces MCS51 design manuals
The SDK-51 MCS-51 System Design Kit contains all of the components required to assemble a complete
single-board microcomputer based on Intel's high-performance 8051 single-chip microcomputer. SDK-51
uses the external ROM version of the 8051 (8031). Once you have assembled the kit and supplied + 5V
power, you can enter programs in MCS-51 assembly language mnemonics, translate them into MCS-51 ob-
ject code, and run them under control of the system monitor. The kit supports optional memory and inter-
face configurations, including a serial terminal link, audio cassette storage, EPROM program memory,
and Intellec development system upload and download capability.
The following are trademarks of Intel Corporation and may be used only to describe Intel products: intel, Intellec, MCS and ICE, and the combination of MCS or ICE and a
numerical suffix, Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are
implied.
, INTEL CORPORATION, 1980 November 1980

AFN01792A 8-22 162549
SDK-51
FUNCTIONAL DESCRIPTION The 8031, 8051, and 8751 CPUS

The SDK-51 is a kit which includes hardware and The 8031, 8051, and 8751 CPUs each combine, on
software components to assemble a complete a single chip, a 128 x 8 data RAM; 32 input/output
MCS-51 family single-board microcomputer. Only lines; two 16-bit timer/event counters; a five-
common laboratory tools and test equipment are source, two-level nested interrupt structure; a
required to assemble the kit. Assembly generally serial 110 port; and on-chip oscillator and clock cir-
requires 5 to 10 hours, depending on the experi- cuits. An 8051 block diagram is shown in Figure 1.
ence of the user. The 8031, the SDK-51's CPU, is a CPU without on-
chip program memory. The 8031 can address 64K
bytes of external program memory in addition to
The MCS-51 Microcomputer Series 64K bytes of external data memory. For systems
requiring extra capability, each member of the
MCS-51 is a series of high-performance single- 8051 family can be expanded using standard mem-
chip microcomputers for use in sophisticated ories and the byte-oriented MCS-80 and MCS-85
real-time applications such as instrumentation, peripherals. The 8051 is an 8031 with the lower 4K
industrial control and intelligent computer periph- bytes of program memory filled with on-chip
erals. The 8031, 8051, and 8751 microcomputers mask-programmable ROM while the 8751 has 4K
belong to the 8051 family, which is the first family bytes of ultraviolet light-erasable, electrically pro-
in the MCS-51 series. grammable ROM (EPROM).
The 8031 CPU operates at a 12 MHz clock rate,
In addition to their advanced features for control
resulting in 4 Ils multiply and divide and other in-
applications, MCS-51 family devices have a micro-
processor bus and arithmetic capability such as structions of 1 Ils and 2 Ils.
hardware multipy and divide instructions, which For additional information on the 8051 family, see
make the SDK-51 a versatile stand-alone micro- the 8051 User's Manual or MCS-51 Macroassem-
computer board. bier User's Guide.
REFERENCE COUNTERS
I-
I
-t------------------ --l
I
I OSCILLATOR
4096 BYTES
PROGRAM 128 BYTES
TWO 16BIT I
& TIMER/EVENT
I TIMING
MEMORY
(8051 & 8751)
DATA MEMORY
COUNTERS I
I I
I I
I I
8051
I CPU
I I
I I
I PROGRAMMABLE I
SERIAL PORT
I 1 64KBYTE BUS
EXPANSION
PROGRAMMABLE FULL DUPLEX I
f_____
I/O USART
I SYNCHRONOUS I
SHIFTER I
I CON'""'
L __ ~ ____ J
INTERRUPTS
CONTROL PARALLEL PORTS, SERIAL SERIAL
ADDRESS/DATA BUS, IN OUT
& I/O PINS
Figure 1. 8051 Block Diagram
8-23 AFN01792A
SDK51
System Softwaie Table 1. SDK-51 Commands

A compact but powerful system monitor is con-
Command Operation
tained in 8K bytes of pre-programmed ROM. The
monitor includes system utilities such as com- Set breakpoint Define addresses for breaking
mand interpretation, user program debugging, execution.
and interface controls. Table 1 summarizes the Display cause Ask the system why execution
SDK-51 monitor commands. stopped.
The ROM devices also include a single-line as- Upload, download Transfer files to and from Intel-
sembler and disassembler. The assembler lets lec@ development system.
you enter programs in MCS-51 assembly language Save, load Transfer files to and from op-
mnemonics directly from the ASCII keyboard. The tional cassette interface.
disassembler supports debugging by letting you Set top of Define partition between pro-
look at MCS-51 instructions in mnemonic form program memory gram memory and data mem-
during system interrogation. ory.
Set baud Define baud rate value of serial
Memory port.
The two 64K external memo'ry spaces are com- Display memory Examine and change program
bined into a single memory space which you can memory or data locations.
configure between program memory and data Assemble Translate an MCS-51 assembly
memory. The kit includes 1K-byte of static RAM. mnemonic into object code.
The board has space and printed circuitry for an Disassemble Translate program memory into
additional 15K bytes of RAM and 8K bytes of MCS-51 assembly language
ROM. mnemonics.
Go Start execution between a se-
lected pair of addresses.
User Interface
Step Execute a specified number of
The kit includes a typewriter-format, ASCII-subset instructions.
keyboard and a 24-character, alpha-numeric LED
USER
CONFIGURABLE
MEMORY
ADDRESS
& DATA BUSES
UPI
BUS
Figure 2_ Block Diagram of SDK-51 System Design Kit
8-24 AFN01792A
SDK-51
display. The standard keyboard and display pro- Debugging

vide full access to all of the SDK-51's capabilities. Hardware breakpoint logic in the SDK-51 checks
All of the SDK-51 interfaces are controlled by a the address of a program or external data-memory
pre-programmed Intel 8041 Universal Peripheral access against values defined by the user and
Interface. stops execution when it sees a "break" condition.
A 3 x 4 matrix keyboard can be jumpered to port 1 After a breakpoint, you can examine and modify
of the 8031. registers, memory locations, and other points in
the system. A step command lets you execute in-
structions in a single-step mode.
Optional Interfaces
TERMINAL Assembly and Test
An RS-232-compatible CRT or printing terminal or The SDK-51 assembly manual describes hardware
a current-loop-interface terminal may be used as a assembly in a step-by-step process that includes
listing device by connecting it to the board's checking each hardware subsystem as it is in-
serial interface connector and supplying + 12 and stalled. Building the system requires only a few
- 12 volts to the board. common tools and standard laboratory instru-
ments.
AUDIO CASSETTE
The kit includes hardware, software, and user's
guide instructions to connect and operate an
audio cassette tape recorder for low-cost program
and data storage.
INTELLEC SYTSTEM
An SDK-51 and an Intellec Model 800 or Series II
development system with ISIS-II can upload and
download files through the serial interface with-
out adding any software to the Intellec system.
Parallel 1/0
The kit includes an Intel 8155 parallel 1/0 device
which expands the 8031 1/0 capability by provid-
ing 22 dedicated parallel lines. Three 40-pin head-
ers between the 8031 and 8155 devices and the
wire-wrap area facilitate interconnections with the Figure 3. SDK-51 Assembled with Additional RAM
user's custom circuitry. and ROM Devices Installed
SPECIFICATIONS
Control Processor Interfaces

Intel 8031 microcomputer Keyboard - 51-key, ASCII subset, typewriter for-
12 MHz clock rate mat, 12-key (3 x 4) matrix
Memory Display - 24-character, alpha-numeric
RAM - 1K-byte static, expandable in 1K seg- Serial - RS-232 with user-selectable baud rate.
ments to 16K-byte with 2114 RAM devices; user- Printed circuitry for 110 baud 20 rnA current loop
configurable as program or data memory. interface. 8031 serial port.
ROM - Printed circuitry for 8K bytes of program Parallel - 22 lines, TTL compatible
memory in 4K segments using 2732A EPROM de-
vices. Cassette - Audio cassette tape storage interface
8-25 "1=1\1.n17Q?,,
SDK51
Eieciricai Characterisiics
System monitor preprogrammed in on-board ROM DC Power Requirement (supplied by user, cable
MCS-51 assembler and disassembler prepro- included with kit)
grammed in on-board ROM Voltage Current
Interface control software preprogrammed in + 5V 5% 3A
8041's on-chip ROM + 12V 5% * 100 mA
-12V 5% * 100 mA
Assembly and Test Equipment Required
12 volts required only for operation with serial interface.
Needle-nose pliers
Small Phillips screwdriver
Small diagonal wire cutters Environmental Characteristics
Soldering pencil, :::;30 watts, 1116" diameter tip
Operating Temperature - 0 to 40C
Rosin-core, 60-40 solder, 0.05" diameter
Relative Humidity - 10% to 90%, non-condens-
Volt-Ohm-Milliammeter, 1 meg-ohm input imped- ing
ance
Oscilloscope, 1 volt/division vertical sensitivity,
200 p.s/division sweep rate, single trace, internal Reference Manuals
and external triggering
SDK-51 User's Manual
Physical Characteristics SDK-51 Assembly Manual
Length - 13.5 in. (34.29 cm) SDK-51 Monitor Listing
Width - 12 in. (30.48 cm) MCS-51 Macro Assembler User's Guide
Height - 4 in. (10.16 cm) MCS-51 Macro Assembly Language Pocket Refer-
Weight - 3 Ib (1.36 kg) ence

MCI-51-SDK MCS-51 System Design Kit
8-26 AFN01792A
PL/M-80 COMPILER 8051 INSTRUCTION SET SIMULATOR
ISIS-II PL/M-80 VJ. 1 COMPILA1ION OF MODULE SIM51

OBJECT MODULE PLACED IN SIM31. ODJ
COMPILER INVOKED BY: .F1 PLM80 SIM51. PLM PRINT(:Fl:SIM51 LST) XREF DATE(302)
$TITLE( '8051 INSTRUCTION SET SIMULATOR / )
1* THE FOLLOWING IS A PLM-80 PROGRAM TO SIMULATE THE

OPERATION OF THE INTEL BOSl INSTRUCTION SET
1\10 ATTEMPT HAS BEEI'~ I"IADE TO ~; It1UL.ATE THE IIO PORTE; OR
SPECIAL FUNCTION REGISTEHS, THOUGH THERE ARE 'HOOv..S' TO
ACCESS EXTERNALLY-DEFINED PROCEDURES WHENEVER PO-P3 OR
SaUF ARE READ OR WRITTEN.
RELEVANT ENTRY POINTS:
'INITIALIZE' - SIMULATE HARDWARE RESET;

SUBROUTINE WITH NO INPUT PARAMETERS.
'STEP' - SIMULATE EXECUTION OF ONE INSTRUCTION

INPUT PARAMETER = STARTING ADDRESS;
VALUE RE"l UHNED .:: UPDATED PC.
'FETCH$SIM' - FETCH DATA FROM VARIOUS ADDRESS SPACES

(SEE ROUTINE DEFINITION FOR PARAMETER DEFINITION).
'STORE$SIM ' - STORE DATA INTO VARIOUS ADDRESS SPACES

(SEE ROUTINE DEFINITION FOR PARAMETER DEFINITION).
ALL PARAMETERS PASSED TO AND FROM ALL ROU1INES ARE SIXTEEN-BIT.
AFN01739A
A1
i SIM5i;
DO;
1* DEFINITIONS OF GLOBAL VARIABLES USED BY INDIVIDUAL
INSTRUCTION SIMULATION PROCEDURES; *1
2 1 DECLARE ROM$SIZE LITERALLY '4096 ~; 1* 4K ROf\l SUPPORTED */

3 1 DECLARE INT$RAM(128) BYTE;
4 1 DECL.ARE HARD$REG(128) BYTE;
5 1 DECLARE USER$CODE(ROM$SIZE) BYTE PUBLICi
6 1 DECLARE EXTERN$RAM(256) BYTEi
7 1 DECLARE REG$ADDR BYTEi
8 1 DECLARE DIR$ADDR BYTE;
9 1 DECL.ARE SOURCE$ADDR BYTE;
10 1 DECLARE DEST$ADDR BYTEi
11 1 DECL.ARE BIT$ADDR BYTE;
12 1 DECLARE CODE$ADDR ADDRESS;
13 1 DECLARE PAGED$EXTERNAL$ADDR BYTEi
14 1 DECL/\RE REG$DATA BYTE;
15 1 DECL.ARE DIR$DATA BYTEi
16 1 DECL.ARE IND$DATA BYTEj
17 1 DECLARE IMM$DATA BYTE;
18 1 DECL.ARE BIT$DATA BYTE;
19 1 DECLARE STACK$DATA BYTE;
20 1 DECL.ARE PAGE$CODE BYTE;
21 1 DECLARE PAGE$OFFSET BYTE;
22 1 DECL.ARE DISPLACEMENT BYTE;
23 1 DECLARE LINK$BIT BYTEi
24 1. DECLARE L.OW$NIB BYTE;
25 1 DECLARE HIGH$NIB BYTE;
26 1 DECL.ARE L.OW$SOURCE$NIB BYTE;
27 DECLARE ADD$TEMP ADDRESS;
28 1 DECL.ARE SUB$TEMP BYTE;
29 1 DECLARE MUL$TEMP ADDRESS;
30 1 DECLARE DIV$TEMP BYTE;
31 1 DECLARE PC ADDRESS;
32 1 DECL.AHE OPCODE BYTE;
33 1 DECLARE i'1f\CH$CYC ADDRESS PUBLICi
34 1 DECL.ARE BIT$REG$ADDR BYTE;
35 1 DECLARE BIT$PATTERN BYTE;
36 1. DECLARE BIT$MASK BYTE;
AFN01739A
A-2
$EJECT
1* PREDEFINED SPECIAL SYMBOLS FOR HARDWARE REGISTERS

( NOTE: VALUES OFFSET BY 80H TO CORRESPOND TO INDEX INTO
HARD$REG ARRAY(0-127). -H. I
37 1 DECLARE PO LITERALLY 'HARD$REG (OOH) 'i

38 1 DECLARE SP LITERALLY 'HARD$REG(OlH)' ;
39 1 DECLARE DPL LITERALLY 'HARD$REG (02H) ';
40 1 DECLARE DPH LITERALLY 'HARD$REG (03H) ';
41 1 DECLARE TCON LITERALLY 'HARD$REG (08H) 'i
42 1 DECLARE TMOD LITERALLY 'HARD$REG (09H) 'i
43 1 DECLARE TLO LITERALLY 'HARD$REG ( OAH) , i
44 1 DECLARE TLl LITERALLY 'HARD$REG (OBH) 'i
45 1 DECLARE THO LITERALLY 'HARD$REG (OCH) j I
46 1 DECLARE THl LITERALLY 'HARD$REG (ODH) 'i

47 1 DECLARE P1 LITERALLY 'HARD$REG( 10H)' i
48 1 DECLARE SCON LITERALLY 'HARD$REG ( 18H) 'i
49 1 DECLARE SBUF L I TER,6,LL Y 'HARD$REG ( 19H) ' j
50 1 DECLARE P2 LITERALLY 'HARD$REG ( 20H) , i
51 1 DECLARE IE LITERALLY IHARDSREG ( 28H) , i
52 1 DECLARE P3 LITERAL.LY 'HARD$REG ( 30H) , i
53 1 DECL.ARE IP LITERALLY 'HARD$REG (38H) , ;
54 1 DECL.ARE PSW LITERALLY 'HARDSREG (SOH) 'i
55 1 DECLARE ACC LITERALLY 'HARD$REG (60H) , ;
56 1 DECLARE B LITERAL.LY 'HARD$REG(70H) ' i
1* HARDWARE REGISTER TYPE CODES ARE ASSIGNED AS FOL.L.OWS:

o - REGISTER UNDEFINED OR BEYOND SCOPE OF SIMULATOR;
1 REGISTER WRITTEN OR READ SIMPLY BY DIRECT ADDRESSING;
2 110 PORTi
3 (RESERVED FOR EXPANSION) *1
57 1 DECLARE HARD$REG$ATTRIB(128) BYTE DATA

(2, L L L 0.0,0,0, 1, L 1, L L L 0,0,
2,0,0,0, 0,0,0,0, 1,2,0,0, 0,0, (L 0,
2,0,0,0, 0.0,0,0, 1,0,0,0, 0,0,0,01
2,0,0,0, 0,0 . 0, 0, 1, 0, 0, 0, 0,0 .. 0,01
0,0,0,0, 0,0,0,0 . 0,0,0,0, 0,0,0,0,
1,0,0,0. 0, 0, 0, 0, 0,0,0,0, 0,0,010,
1,0,0.0, 0,0,0 . 0, 0,0,0,0 . 0,0,010,
1,0,0,0. 0.0,0,0, 0,0,0,0, 0,0,0,0) i
58 DECL.ARE BITSREGSMAP(32) BYTE DATA

( 20H.. 21H, 22H, 23H. 24H, 25H, 26H, 27H.
28H.. 29H, 2AH, 2BH. 2CH, 2DH, 2EHI 2FH.
BOH, B8H. 90H. 98H, OAOHIOA8H,OBOH,OB8H,
OCOH,OC8H,ODOH,OD8H, OEOH,OE8H.OFOH.OF8H);
59 1 DECLARE MASK$TABLE(S) BYTE DATA

(OOOOOOOlB. 00000010B, 00000100D. 00001000B,
0001 OOOOH, 00 1 OOOOOB, 01 OOOOOOD, 10000000D ) i
AFN-01739A
A-3
$EJECT
1* HOOKS FOR EXTERNAL 110 PORT AND ERROR

HANDLING ROUTINES: *1
60 1 PORT$OUTPUT: PROCEDURE(PORT$NOIPORT$DATA) EXTERNAL;

61 2 DECLARE (PORT$NOIPORT$DATA) BYTE;
62 2 END PORT$OUTPUT;
63 1 PORT$INPUT: PROCEDURE(PORT$NO) BYTE EXTERNAL;

64 2 DECLARE PORT$NO BYT~;
65 2 END PORT$INPUT;
66 1 DIR$ADDR$ERR: PROCEDURE(HARD$REG$CODE) EXTERNAL;

67 2 DECLARE HARD$REG$CODE BYTE;
68 2 END DIR$ADDR$ERR;
69 1 IND$ADDR$ERR: PROCEDURE(ILLEGAL$IND$ADDR) EXTERNAL;

70 2 DECLARE ILLEGAL$IND$ADDR BYTE;
71 2 END IND$ADDR$ERR;
72 STACK$ERR: PROCEDURE(ILLEGAL$STACK$ADDR) EXTERNAL;

73 2 DECLARE ILLEGAL$STACK$ADDR BYTE;
74 2 END ST,.,\CK$ERR;
75 1 FETCH$PROG$ERR: PROCEDURE(ILLEGAL$CODE$ADDR) EXTERNAL;

76 2 DECLARE ILLEGALSCODE$ADDR ADDRESS;
77 2 END FETCH$PROG$ERR;
AFN-01739A
A-4
$EdECT
1* VARIOUS MEMORY SPACE ACCESS ROUTINES: *1
78 FETCHSPROGRAM: PROCEDURE (CODESADDR) BYTE;

79 2 DECLARE (CODE$ADDR) ADDRESS;
80 2 IF CODESADDR ( ROM$SIZE
THEN RETURN USERSCODE(CODESADDR);
82 2 EL.SE DO;
83 3 CALL FETCH$PROGSERR(CODESADDR);
84 3 RETURN OOHi
85 3 END;
86 :2 END FETCHSPROGRAM;
87 1 FETCHSREG: PROCEDURE (REGSNO) BYTE;

88 2 DECLARE (REGSNO,REGSADDR) BYTE;
89 ..,
t::._ REGSADDR=(PSW AND 00011000B) + REGSNO;
90 2 RETURN INT$RAM(REGSADDR);
91 2 END FETCHSREG;
92 STORESREG: PROCEDURE (REGSNO,DATA$VALUE);

93 2 DECLARE (REGSNO,REGSADDR,DATASVALUE) BYTE;
94 2 REGSADDR=(PSW AND 00011000B) + REG$NO;
95 2 INTSRAMCREGSADDR)=DATA$VALUE;
96 2 END STORESREG;
97 FETCHSDIR- PROCEDURECDIRSADDR$NO) BYTE;

98 2 DECLARE(DIRSADDRSNO,HARD$REGSINDEX,HARD$REGSTYPE) BYTE;
99 2 IF DIR$ADDRSNO (= 7FH THEN
100 2 RETURN INTSRAM(DIRSADDRSNO);
101 .)
c. EL.SE DOi
102 3 HARDSREGSINDEX=DIR$ADDRSNO - 80H;
103 3 HARDSREG$TYPE=HARDSREG$ATTRIB(HARDSREGSINDEXl;
104 :~ DO CASE HARD$REGSTYPE;
105 4 DO;
106 5 CALL DIR$ADDRSERR(DIR$ADDRSNO);
107 :5 RETUHN OOHi
lOB ~.1 END;
109 4 RETURN HARD$REG(HARD$REG$INDEX);
110 4 RETURN PORT$INPUTCDIRSADDRSNO);
1J 1 4 END;
11.2 3 END;
11 :3 2 END FFfCI-!$D I I~.;
114 1 FETCH$DIR$INT: PROCEDURECDIR$AODRSNO> ByrE;

115 ...
c.
)
DECLARE(DIRSADDRSNO,HARDSREGSINDEX,HARDSREGSTVPE) By-rEi
116 2 I~ DIRSADDRSNO (= 7FH THEN
117 2 RETURN INT$RAM<DIRSADDRSNO);
11.8 '"i
r.:.. ELSE DO;
AFN01739A
A5
119 3 HARD$REG$INDEX~DIRSADDR$NO - BOH;

120 3 HARD$REG$TVPE=HARDSREG$ATTRIBCHARD$REGSINDEX);
121 3 DO CASE HARD$REGSTYPE;
1. ;,..!;.? 4 DO;
1 ;2:3 5 CALL DIRSADDRSERR(DIRSADDR$NO);
1 ;:'~4 ~j RETURN' OOH;
.1.;]5 :5 END;
1.26 4 RETURN HARDSREG(HARDSREGSINDEX);
127 ,q. RETURN HARDSREG(HARD$REG$lNDEX);
.1 ~2B '+ END;
1;}9 :J END;
l ~10 ;2 END FETCH$DIRSINT;
1~] :t STORESDIR: PROCEDURE(DIRSADDRSNO,DATASVALUE);

1 :-j;2 2 DECLARE(DIRSADDRSNO,HARDSREGSINDEX,HARDSREGSTYPE,DATA$VALUE)
1:.33 2 IF DIR.ADDR$NO <= 7FH THEN
1 ~34 2 INTSRAM(DIRSADDR$NO)=DATASVAlUE;
1 :J~j '"i
r... EL.SE DO;
136 :3 HARDSREGSINDEX=DIR$ADDR$NO - BOH;
137 3 HARDSREGSTVPE=HARDSREGSATTRI8CHARDSREGSINDEX);
1.]f-] 3 DO CASE HARDSREG$TYPE;
139 4 CALL DIRSADDR$ERRCDIR$ADDR$NO);
140 4- HARDSREGCHARD$REGSINDEX)=DATA$VALUE;
141 IJ. DO;
142 5 HARDSREG(HARD$REGSINDEX)=DATA$VALUE;
143 5 CALL PORT$OUTPUT(OIR$ADDR$NO,DATASVALUE);
.l44 5 END;
145 4 END;
1'1-6 :3 END;
147 ;'2 END STORE$DIR .
148 FETCH$IND: PROCEDURECREGSNO) BYTE;

149 2 DECLARE (REG$NO, REG$ADDR, RAMSADDR) BYTE;
150 ;;l REG$ADDR=(PSW AND 000110008) + REG$NO;
1 ~j1 ~)
"::. RAM$ADDR=INT$RAMCREG$ADDR);
1 :52 :.~~ IF RAM$ADDR (= 7FH
THEN RETURN INT$RAM(RAM$ADDR);
1 ~)/.j. 2 ELSE DO;
155 :3 CALL INDSADDR$ERR(RAMSADDR);
1G6 ;-] RETURN OOH;
1 ~:?} :] END;
138 rl
r.:.. END FETCH$IND;
159 STORESIND: PROCEDURECREGSNO,DATASVALUE);

160 r)
t:.. DECLARE (REGSNO,REGSADDR,RAMSADDR,DATA$VALUE) By'rEi
161 2 REGSADDR=(PSW AND 000110008) + REG$NO;
162 2 RAM$ADDR=INT$RAM(REG$ADDR);
:16:3 2 IF RAM$AVDR <= 7FH
THEN INT$RAM(RAMSADDR)=DATA$VALUE;
165 -)
r._ ELSE CALL INDSADDRSERR(RAMSADDR);
1.66 ;:~ END STORESIND;
AFN01739A
A-6
167 1 FETCH$BIT~ PROCEDURE(BIT$ADDR) BYTE;

168 2 DECLARE BITSADDR BYTE;
161",> 2 BIT$REG$ADDR=BITSREGSMAPCBIT$ADDR / 8);
110 2 BITSPAtTERN=FETCHSDIR(BITSREG$ADDR)i
171 2 BIT$MASK=MASKSTABLE(BITSADDR AND 000001118);
112 2 IF (BIT$PA1TERN AND BIT$MASK) = 0
THEN RETURN OOH;
114 2 EL SE RETURN L
115 2 END FETCHSBIT;
176 1 FETCH$Bll$INT: PROCEDURECBIT$ADDR) BYTE;

1ll 2 DECLARE BIT$ADDR BYTE;
178 2 BIT$REGSADDR=BIT$REG$MAPCBITSADDR ! 8);
179 ...
r-
)
BIT$PATTERN=FETCH$DIR$INTC8IT$REG$ADDR);
180 '")
r- BIT$MASK=MASK$TABLE(BIT$ADDR AND 00000111B);
Ul1 2 IF (BITSPATTERN AND BIT$MASK) = 0
THEN RETURN OOH;
18:3 2 ELSE RETURN 1;
HJ4 2 END FETCHSBIT$INT;
185 STORE$BIT: PROCEDURE(BIT$ADDR,BIT$DATA);

186 2 DECLARE (BITSADDR,BIT$DATA) BYTE;
187 2 BITSREGSADDR=BIT$REGSMAPC8ITSADDR / 8);
188 2 BIT$PATTERN=FETCHSDIR$INT(BITSREGSADDR);
189 2 BITSMASK=MASK$TABLE(BITSADDR AND 000001110);
190 2 IF BITSDATA = 0
THEN BITSPATTERN=BITSPATTERN AND (NOT BIT$MASK);
192 2 ELSE BIT$PATTERN~(BIT$PATTERN OR BIT$MASK);
193 2 CALL STORE$DIRCBIT$REG$ADDR,BIT$PATTERN);
194 2 END STORE$B IT;
195 1 PUSH$STACK: PROCEDURE CDATASVALUE);

196 2 DECLARE (DATASVALUE) BYTE;
1 (.77 2 SP";:SP+l j
198 2 IF SP (::: '7FH

THEN INT$RAM(SP)=DATA$VAlUE;
200 2 ELSE CALL STACK$ERR(SP);
201 2 END PUSHSSTACK;
;;~O2 1 POP$STACK: PROCEDURE BYTE;

203 ;')
c. DECLARE (DATA$VALUE) BYTE;
~:O4 ~2 IF SP (= '7FH
THEN DATA$VALUE=INT$RAM(SP);
206 ;;~ ELSE DO;
;207 :3 CALL STACK$ERR(SP);
208 3 DATA$VALUE=OOHi
209 3 END;
21.0 2 SP=SP-'l ;
21.1 2 RETURN DATASVALUE;
21.2 2 END POP$STAC!I,j
A-7
AFN01739A
213 FETCHSPAGEDSEXTERNAL: PROCEDURE (PAGEDSEXTERN$ADDR) BYTE;

214 2 DECLARE (PAGEDSEXTERNSADDR) BYTE;
215 2 RETURN EXTERNSRAM(PAGEDSEXTERN$ADDR);
216 2 END FETCHSPAGEDSEXTERNAL;
217 1 STORESPAGEDSEXTERNAL: PROCEDURE (PAGEDSEXTERN$ADDR,DATASBYTE);

218 2 DECLARE (PAGED.EXTERNSADDR) BYTE;
219 2 DECLARE DATA$BYTE BYTE;
220 2 EXTERNSRAM(PAGED$EXTERNSADDR) = DATA$BYTE;
221 2 END STORESPAGEDSEXTERNAL;
222 FETCH$LONG$EXTERNAL: PROCEDURE (LONG$EXTERN$ADDR) BYTE;

223 2 DECLARE (LONG$EXTERN$ADDR) ADDRESS;
224 2 RETURN EXTERN$RAM(LONGSEXTERN.ADDR);
225 2 END FETCH$LONG$EXTERNAL;
226 1 STORE$LONGSEXTERNAL: PROCEDURE (LONGSEXTERN$ADDR,DATASBYTE"

227 2 DECLARE (LONGSEXTERN.ADDR) ADDRESS;
229 2 EXTERN$RAMCLONGSEXTERN$AbDR) = DATA$BYTE;
2:'"'.)0 2 END STORESLONGSEXTERNAL;
231 1 SIGN.EXTENDED: PROCEDURE (SIGNED$BYTE) ADDRESS;

232 ...,
1::.. DECLARE SIGNEDSBYTE BYTE;
233
, 2 IF (SIGNED$BYTE AND 10000000B) = 0
THEN RETURN SIGNEDSBYTE;
235 2 ELSE RETURN (SIGNED$BYTE + OFFOOH);
236 2 END SIGNSEXTENDED;
237 1 PARITY$STATE: PROCEDURE (DATA$BYTE) BYTE;

238 '")
1:_ DECLARE (DATASBYTE,PARITY$BIT) BYTE;
239 2 PARITYSBIT=O;
240 2 IF (DATA$BYTE AND 00000001B) (> 0
THEN PARITY$BIT=PARITY$BIT XOR 000000018;
242 2 IF (DATA$BYTE AND 000000108) <> 0
THEN PARITY$BIT=PARITY$BIT XOR Ob000001D;
244 2 IF (DATA$BYTE AND 00000100B) <> 0
THEN PARITYSBIT=PARITYSBIT XOR 0000000lB;
246 ...,
c. IF (DATA$BYTE AND 00001000B) <) 0
THEN PARITYSBIT=PARITYSBIT XOR 00000001D;
248 2 IF (DATA$BYTE AND 00010000B) () 0
THEN PARITYSBIT=PARITY$BIT XOR 00000001B;
250 2 IF (DATA$BYTE AND 00100000B) () 0
THEN PARITY$BIT=PARITYSBIT XOR 000000018;
AFN01739A
A-a
252 ;2 IF (DATA$BYTE (.>.ND 01000000B) (;

THEN PARI1YSBIT=PARITY$BIT XOR 00000001 B.;
...
254 2 IF (DATA$BYTE !<\ND 10000000B) .-.... . 0
'
;
THEN PARITY$BIT=PARITY$BIT lOR OOOOOOOlD;

256 ~2 RETURN PARITY$I3ITi
2~7 2 END PAR I TY1iE) rATE;
AFN-01739A
A-9
$EJECT
1* THE FOLLOWING CODE PROVIDES A SINGLE ENTRY POINT FOR
AN EXTERNAL ROUTINE TO READ DATA FROM ALL SIMULATOR ADDRESS SF
THE FIRST CALLING PARAMETER GIVES UP TO 16 BITS OF ADDRESS;
THE SECOND SPECIFIES WHICH LOGICAL ADDRESS SPACE TO
READ, USING THE SCHEME:
0 = PROGRAM MEMORY
1 = WORKING REGISTER
2 = DIRECT ADDRESS (INPUTS FOR PORTS)
3 INDIRECT THROUGH REGISTER SPECIFIED
4 = DIRECT BIT ADDRESS (DATA RIGHT-JUSTIFIED)
5 = PAGED EXTERNAL MEMORY
6 = 64K EXTERNAL MEMORY (ALL WRITES CURRENTLY TO PAGE 0)
7 = TOP-OF-STACK (SP UPDATED)
THE FUNCTION CALL RETURNS THE BYTE SO ADDRESSED.
258 FETCH$SIM: PROCEDURE (DATA$ADDR,DATA$TYPE) ADDRESS PUBLIC;

259 2 DECLARE (RETURN$DATA,DATA$ADDR,DATA$TYPE) ADDRESS;
260 2 DECLARE DATA$ADDR$BYTE BYTE;
261 2 DATA$ADDR$BYTE=DATA$ADDRi
262 2 DO CASE DATA$TYPE;
263 3 RETURN$DATA=FETCH$PROGRAM(DATA$ADDR);
264 3 RETURN$DATA=FETCH$REG(DATA$ADDR$BYTE);
265 3 RETURN$DATA=FETCH$DIR$INT(DATA$ADDR$BYTE);
266 3 RETURN$DATA=FETCH$IND(DATA$ADDR$BYTE);
267 3 RETURN$DATA=FETCH$BIT$INT(DATA$ADDR$BYTE);
268 3 RETURN$DATA=FETCH$PAGED$EXTERNAL(DATA$ADDR$BYTE);
269 3 RETURN$DATA=FETCH$LONG$EXTERNAL(DATA$ADDR);
270 3 RETURN$DATA=POP$STACK;
271 3 END;
272 2 RETURN RETURN$DATA;
273 2 END FETCH$S I M;
1* THE FOLLOWING CODE PROVIDES A SINGLE ENTRY POINT FOR

AN EXTERNAL ROUTINE TO WRITE DATA INTO ALL SIMULATOR ADDRESS
THE FIRST CALLING PARAMETER GIVES UP TO 16 BITS OF ADDRESS;
THE SECOND SPECIFIES WHICH LOGICAL ADDRESa SPACE TO
READ, USING THE SCHEME:
o PROGRAM MEMORY
1 - WORKING REGISTER
2 - DIRECT ADDRESS (OUTPUT LATCHES FOR PORTS)
3 INDIRECT THROUGH REGISTER SPECIFIED
4 = DIRECT BIT ADDRESS (DATA RIGHT-JUSTIFIED)
5 - PAGED EXTERNAL MEMORY
6 64K EXTERNAL MEMORY CALL WRITTEN CURRENTLY TO PAGE 0)
7 TOP-OF-STACK (SP UPDATED)
THE THIRD PARAMETER HOLDS THE BYTE VALUE TO BE WRITTEN. *1
274 STORE$SIM: PROCEDURE (DATA$ADDR,DATA$TYPE,DATA$VALUE) PUBLIC;

275 2 DECLARE (DATA$ADDR,DATA$TYPE,DATASVALUE) ADDRESS;
276 2 DECLARE (DATA$ADDR$BYTE,DATA$VALUE$BYTE) BYTE;
AFN01739A
A10
277 2 DATA$ADDR$BYTE=DATA$ADDRl
278 2 DATA$VALUE$BYTE=DATA$VALUEi
279 2 DO CASE DATA$TYPEi
280 3 USER$CODECDATA$ADDR MOD ROM$SIZE)=DATA$VALUE$BYTEi
281 3 CALL STORE$REG(DATA$ADDR$BYTE,DATA$VALUE$BYTE)l
282 3 CALL STORE$DIR(DATA$ADDR$BYTE,DATA$VALUE$BYTE)i
283 3 CALL STORE$IND(DATA$ADDR$BYTE,DATA$VALUE$BYTE);
284 3 CALL STORE$BIT(DATA$ADDR$BYTE,DATA$VALUE$BYTE);
285 3 CALL STORE$PAGED$EXTERNALCDATA$ADDR$BYTE,DATA$VALUE$BYTE);
286 3 CALL STORE$LONG$EXTERNALCDATA$ADDR,DATA$VALUE$BYTE)i
287 3 CALL PUSH$STACKCDATA$VALUE$BYTE);
288 3 END;
289 2 END STORE$SIM;
AFN-01739A
A-11
$EJE:CT
$INCLUDE (ISET~51. PLM)
= 1* INDIVIDUAL INSTRUCTION PROCEDURES: *1
=
= 1* "ACALL ad dr 16" INSTRUCT ION: *1
.-
290 1 = ACALLtADDR11: PROCEDURE;
291 2 = PAGEtCODE==(OPCODE AND 11100000B) I 32;
292 2 = PAGEtOFFSET=FETCHtPROGRAM(PC+1);
293 2 PC=PC+2i
294 2 CALL PUSHtSTACK(LOW(PC;
295 2 == CALL PUSHtSTACK(HIGH(PC;
296 2 ;:: PC=(PC AND OF800H) + (PAGE$CODE * 100H) + PAGE$OFFSET;
297 2 END ACALL$ADDR11;
1* "ADD A, (src-byte)11 FUNCTION: *1

-
298 1 ADD$A: PROCEDURE(DATAtBYTE);
300 2 = IF ( (ACC AND OFH)+(DATA$BYTE AND OFH) ) ). OFH
- THEN PSW=PSW OR 01000000Bi
302 2 - ELSE PSW=PSW AND 10111111Bi
303 2 = IF ( (ACC AND 7FH)+(DATA$BYTE AND 7FH) ) :> 7FH
THEN PSW=PSW OR 0OOOO100B;
305 2 == ELSE PSW=PSW AND 11111011Bi
306 2 ADD$TEMP = (ACC) j
307 2 == ADD$TEMP = (ADD$TEMP+DATA$BYTE);
308 2 == IF ADD$TEMP :> OFFH
::: THEN PSW==(PSW OR 10000000B) XOR 000OO100Bi
310 2 ELSE PSW=(PSW AND 01111111B);
311 2 - ACC=LOW(ADD$TEMP);
312 2 = END ADDtAi
--
1* "ADD A/Rn" INSTRUCTION: *1
31.3 ADD$A$REG: PROCEDUREi

314 2 REG$ADDR=OPCODE AND 00000111Bi
315 2 REG$DATA==FETCH$REG(REGtADDR)i
316 2 CALL ADD$A (REG$DATA);
31.7 2 PC::::PC+1;
318 2 END ADD$A$REG;
/* "ADD A, direc"t;1I INSTRUCTION: */
319 1 ADD$A$DIR: PROCEDURE;

320 2 == DIR$ADDR=FETCH$PROGRAM(PC+l);
321 2 DIR$DATA=FETCH$DIR(DIR$ADDR);
322 2 CALL ADD$A (OIR$DATA);
3;'23 2 == PC=PC+2i
324 2 END ADD$A$DIR;
--
1* "ADD A,@Ri" INSTRUCTION: */
AFN01739A
A-12
325 1 ADD$A$IND: PROCEDURE;

327 2 IND$DATA=FETCH$INDCREG$ADDR)i
328 2 == CALL ADD$A ( IND$DATA) i
:3;'29 2 - PC=PC+1 i
330 2 END ADD$A$IND;
1* "ADD A, #data" INSTRUCTION: *1
331 1 ADD$A$IMM: PROCEDUREi

332 2 IMMSDATA=FETCHSPROGRAM(PC+1);
333 2 CALL ADD$A(IMMSDATA);
3~34 2 PC=PC+2;
335 2 END ADD$A$IMM;
1* "ADDC A, (src-byte)" FUNCTION: 1f1
336 1 ADDC$A: PROCEDURECDATA$BYTE)i

338 2 LINK$BIT = (PSW AND 10000000B) I 128;
339 2 IF (CACC AND OFH)+(OATA$BYTE AND OFH)+LINK$BIT) > OFH
THEN PSW=PSW OR 01000000B;
341 2 ELSE PSW=PSW AND 10111111Bi
342 2 IF (CACC AND 7FH)+(DATA$BYTE AND 7FH)+LINKSBJT) > 7FH
344 2 ELSE PSW=PSW AND 11111011B;
345 2 ADD$TEMP (ACC);
346 2 ADD$TEMP :::: (ADD$TEMP+DATA$BYTE);
347 2 ADD$TEMP :::: (ADDSTEMP+LINK$BIT)i
348 2 IF ADDS TEMP > OFFH
THEN PSW=(PSW OR 10000000B) XOR 000001000;
351 2 ACC=LOW(ADD$TEMP);
352 2 END ADDCS,...,,;
I'I!- "ADDC A, Rn" INSTRUCTION: tt/
353 1 ADDC$A$REG: PROCEDURE;

354 ':1
e. REGSADDR=OPCODE AND 00000111H;
355 2 REGSDATA=FETCH$REGCREG$ADDR);
3~j6 2 CALL ADDC$A(REG$DAfA);
:J~7 2 PC::::PC-I'l ;
358 '".,
t:.. END I~DDC$A$REG.;
1* "f.\DDC A,direct" INSTRUC'TION: .I(.!,
359 1 ADDC$A$DIR: PROCEDURE;

360 2 DIR$ADDR=FETCHSPROGRAMCPC+l);
361 2 DIRSDATA=FETCH$DIR(DIRSADDR);
362 2 CALL ADDC$A(DIRSDATA);
363 2 PC~:=PC-t"2i
:361.1- 2 END ADDC$ASDIR;
AFN01739A
A-13
- llf "ADDC A,@Ri." INSTRUCT ION: 11-/

..-
365 1 _. ADDC$A$IND: PROCEDURE;
366 2 REG$ADDR=OPCODE AND OOOOOOOlBi
367 2 IND$DATA=FETCH$IND(REG$ADDR);
368 2 .. CALL ADDC$A(IND$DATA)i
369 2 .- PC""PC+1 ;
370 2 END ADDC$A$IND;
'-
l* "ADDe A,#data" INSTRUCTION: it!
371 1 .- ADDC$A$II'1M: PROCEDURE;

3"72 2 IMM$DATA=FETCH$PROGRAM(PC+l),
373 2 CALL ADDC$A(IMMSDATA);
374 2 PC::.::PC+;'~;
375 2 = END ADDC$A$JI'1M;

.-
/* "AJMP addT'11" IN::lTRUCTIONllj
:376 1 ::::: AJMP$ADDR11: PROCEDURE;

377 2 PAGE$CODE=(OPCODE AND 11100000B) I J2;
378 '')
1:.. - PAGE$OFFSET=FETCH$PROGRAM(PC+l);
379 2 PC:=PG+2;
380 2 PC=(PC AND OF800H) + (PAGE$CODE * IOOH) + PAGE.OFFSET;
381 2 E.ND AJMP $f'\DDR 11 i
/* "ANL. A,Rn" INSTHUCTIDN: .1$-/

--
382 ANL$A$REG: PROCEDURE;
383 2 -. REG$ADDR=OPCODE AND 00OOO111B .
384 2 = REG$DATA=FETCH$REG(REG$ADDR);
3f:35 2 ACC=ACC AND REG$DA"r Ai
:3B6 2 PC:::::PC+l ;
387 ...,
1:"_ END ANL.$A$REGi
1* "ANL A, direct" INSTRUCTION: .y,./

-
388 1 ANL.$A$DIR: PROCEDlIREi
389 2 DIR$ADDR=FETCH$PROGRAM(PC+l);
390 2 - DIR$DATA=FETCH$DIR(DIR$ADDR);
ACC::.~ACC AND DIR$DATAi
391 2
392 2 - PC:;::PC+2;
393 2 - END ANL$A$DIR;
11t- ",~NL A,@Ri" II\ISTr~IJCT ION: *1
394 1 -_. ANL$A$IND: PROCEDURE;

395 2 REG$ADDR=OPCODE AND 00000001 Ii.:
3 C)6 2 = IND$DATA=FETCH$IND(REGSADDR);
397 2 ACC=ACC AND IND$DATAi
AFN01739A
A14
398 PC::;:PC-f'l ;
399 END ANL$ASIND;
11t- "ANL AI #deta" INSTRUCTION: *1
400 1 ANL$A$IMM: PROCEDURE;

401 2 IMM$DATA=FETCH$PROGRAM(PC+1);
402 2 ACC=ACC AND IMM$DATA;
403 2 ::::: PC=PC+2;
404 2 END ANL$A$IMMi
- lit "ANL direct,AJI I NSTRUCT I ON: i1:1
405 1 ANL$DIR$A: PROCEDUI~Ei

406 2 DIRSADDR=FETCH$PROGRAMCPC+1);
407 2 = DIR$DATA=FETCH$DIR$INT(DIR$ADDR),
408 2 CALL STORE$DIR(DIR$ADDR,ACC AND DIR$J)ATA) j
409 2 ::;: PC;:-.:;PC+2;

410 2
_. END ANL$DIR$Ai
:::::
1* "ANL direct . #data" INSTRUCTION: .;;./

,,-
411 1 ANL$DIR$IMM: PROCEDURE;
414 ...,
/:. ::::: DIR$DATA=FETCH$DIR$INTCDIR$ADDR);
415 2 CALL STORE$DIR(DIRSADDR,IMMSDATA AND DIR~iDATA).;
416 2 PC:::::PC+3;
417 2 END ANL$D I R$ I MM;
1* "ANL C, bit" INSTRUCTION:
418 ANL$C$BIT: PROCEDURE;

419 2 BIT$ADDR=FETCHSPROGRAM(PC+l);
420 2 BIT$DATA=FETCH$BIT(BIT$ADDR);
421 2 IF BIT$DATA -. 0 THEN PSW=PSW AND 01111111D;
4;23 2 :::: PC=PC+2;
424 2 END ANLSC$BIT;
1* "ANL C. Ibit" INSTRUCTION: *1
425 ANL$C$COMPSB IT: PROCEDURE;

426 2 BIT$ADDR=FETCHSPROGRAM(PC+l);
427 2 BITSDATA=FETCH$BIT(BITSADDR);
428 2 :::: IF BIT$DATA -. 1 THEN PSW=PSW AND 01111111B;
4::10 2 - PC=PC+2;
431 2 END ANL$C$COl"IP$B IT;
-
..
lit "CJNE A, direct, T'ElI" INSTRUCTION: '1:-/
432 CJNE$A$DIR$REL: PROCEDURE;

AFN-01739A
A-15
433 2 DIR$ADDR=FETCHSPROGRAMCPC+l);
434 2 DIRSDATA=FETCH$DIR(DIR$ADDR);
435 2 - DISPLACEMENT=FETCHSPROGRAMCPC+2);
436 '"'
1':- IF Ace < DIR$DATA
THEN PSW=(PSW OR 100000000);
4~J8 2 ELSE PSW=(PSW AND 01111111B);
4:39 2 PC::::PC+3;
440 ...'"-' _. IF ACC () DIRSDATA
THEN PC=PC+SIGN$EXTENDEDCDISPLACEMENT);
442 '"I
t::. END C,)NE$ASD I R$REL;
1* "CJNE A, #data, re I" INSTRUCTION:It-!
443 CJNESA$!MM$REL: PROCEDURE;

44-4 2 IMM$DATA=FETCHSPROQRAM(PC+l);
44~5 2 DISPLACEMENT=FETCH$PROGRAMCPC+2);
":~46
'"'
r... IF Ace < IMMSOATA
448 2 ELSE PSW=CPSW AND 01111111B);
44<;> ;2 PC::::PC+3;
450 ;,;2 IF Ace <> IMMSDATA
THEN PC=PC+SIGNSEXTENDEDCDISPLACEMENT);
4~}2 2 END CJNE$A$IMM$REL;
1* "CJNE RTlI #data, reI" INSTRUCTION: *1
453 1 CJNESREGSIMMSREL: PROCEDURE;

454 ,..,
c:. REG$ADDR=OPCOOE AND 00000111B;
455 2 REGSDATA=FETCHSREGCREG$ADDR);
456 2 IMM$DATA=FETCHSPROGRAM(PC+l);
457 2 DISPLACEMENT=FETCHSPROGRAMCPC+2);
458 ':J
I"- -- IF REGSDATA < IMM$DATA
460 2 ELSE PSW=(PSW AND 011111110);
461 2 - PC::;PC+3i
IF REG$DATA () IMM$DATA
462 '"I
r.;.
THEN PC=PC+SIGN$EXTENDED(DISPLACEMENT);
464 2 END CJNE$REGSIMM$REL;
1* "CJNE @RL #data, rel" INSTRUCTION: n-I
465 1 CJNE$IND$IMM$REL: PROCEDURE;

467 2 :: IND$DATA~FETCH$IND(REG$ADDR)i
468 2 IMM$DATA=FETCH$PROGRAMCPC+l);
469 2 DISPLACEMENT=FETCH$PROGRAMCPC+2);
470 '"'
1"- IF INDSDATA < IMMSDATA
THEN PSW=(PSW OR 10000000D);
,::> .-.
472 r.:. ELSE PSW=(PSW AND 01111111B);
473 ~.,
r-_ P(>::PC+3;
474 2 IF IND$DATA <> IMM$DATA
THEN PC=PC+SIGN$EXTENDEDCDISPLACEMENT);
476 2 END CJNE$IND$IMMSREL;
AFN-01739A
A16
".
::: 1* "CLR A" INSTRUCTION: *1

-
477 CLR$A: PROCEDURE;
478 2 ACC=O;
47q 2 - PC=PC+l ;
480 2 END CLR$A;
'.
--
/.* "CLR C" INSTRUCTION: '11-/
-.
481 CLR$C: PROCEDURE;
PSW=PSW AND 01111111B;
482
483 ..,
2
c.. :;:: PC=PC+1 i
484 2 END CLR$Ci
/.1$,. "CLR bit" INSTRUCTION: *1
485 1 CL.R$B IT: PROCEDURE;

486 2 BIT$ADDR=FETCH$PROGRAM(PC+l);
487 2 CALL STORE$BIT(BIT$ADDR,O);
488 2 :;:: PC::::PC+2;
489 2 END CLR$BITi
..-
1* I'CPL A" INSTRUCTION: *.1

'-
490 1 :=: CPL$A: PROCEDURE;
491 2 ACC=ACC XOR 11111111B;
492 2 :=: PC::::PC+l j
493 2 END CPL$A;
/.* "CPL C" INSTRUCTION: *1

--
494 1 CPL.$C: PROCEDUREi
41.75 2 PSW=PSW XOR 10000000B;
4(.76 2 PC=PC+1 ;
497 2 END CPL$C;
:;::
1* "CPL bit" INSTRUCTION: *1
498 1 CPL$B IT: PROCEDURE;

500 2 BIT$DATA=FETCH$BIT$INT(BIT$ADDR);
501 2 BIT$DATA=BIT$DATA XOR 00000001Bi
502 2 CALL STORE$BIT~BIT$ADDR/BIT$DATA);
503 2 := PC=PC+2i
504 2 END CPL$BIT;
1* "DA A" INSTRUCTION: *1

505 1 DA$A: PROCEDUREi
506 2 IF ( (ACe AND OFH) :> 09H) OR ( (PSW AND 01000000B) <::::. 0)
AFN01739A
A17
= THEN DO;
508 3 IF ACC >= OFAH THEN PSW=PSW OR 10000000B;
511 3 ACC=AeC+6;
512 3 == END;
513 2 IF ACC AND OFOH) > 90H) OR PSW AND 100000008) <> 0)
THEN DO)
515 3 == IF ACC >= OAOH THEN PSW=PSW OR 10000000B;
ACC=ACC+60H)
518 3 END;
519 2 PC=PC+l;
520 2 END DASA;
-
1* "DEC A" INSTRUCTION: *1
::::
521 DEC$A: PROCEDURE;

522 2 == ACC=ACC-1;
523 2 PC=PC+1 )
524 2 END DECSAi
1* "DEC Rn" INSTRUCTION; *1
525 1 DECSREG: PROCEDURE;

526 2 REGSADDR==OPCODE AND 000001118;
527 2 REG$DATA=FETCHSREG(REGSADDR);
528 2 REGSDATA==REG$DATA-1;
529 2 == CALL STORE$REG(REGSADDR,REGSDATA);
5:~0 2 PC==PC+li
531 2 END DECSREG;
1* "DEC direct" INSTRUCTION: *1
532 1 DECSDIR: PROCEDURE;

534 2 DIR$DATA=FETCH$DIR$INTCDIRSADDR);
535 2 :::: DIRSDATA=DIRSDATA-1i
536 2 CALL STORESDIR(DIR$ADDR,DIRSDATA);
5:~7 2 P(>::PC+2i
538 2 END DECSDIR;
1-1l- "DEC @Ri" INSTRUCTION: *1
539 DEC$IND~ PROCEDURE;

540 2 REGSADDR=OPCODE AND 000000018;
541 2 INDSDATA=FETCH$INDCREGSADDR);
542 2 INDSDATA=INDSDATA-1;
543 2 CALL STORESIND(REG$ADDR, INDSDATA);
5 /+4 2 PC::"PC+l ;
545 2 END DECSIND;
l* "DIV AB" INSTRUCTION: *1
AFN-01739A
A-18
546 1 = DIV$AB: PROCEDURE;

547 2 = IF B = 0 THEN PSW=PSW OR 00000100B;
549 2 = ELSE DO;
550 3 :::: PSW=PSW AND 11111011B;
551 3 DIVSTEMP=ACC I B;
552 3 = B=ACC MOD B;
553 3 ACC=DIV$TEMP;
554 3 END;
555 2 = PSW=PSW AND 01111111B;
556 2 = PC=PC+1;
557 2 =
::::
END DIVSABi
= 1* "DJNZ Rn,rel" INSTRUCTION: *1

=
558 1 DJNZSREG$REL: PROCEDUREi
559 2 = REG$ADDR=OPCODE AND 00000111B;
560 2 = DISPLACEMENT=FETCH$PROGRAM(PC+1);
561 2 = REG$DATA=FETCHSREG(REG$ADDR);
562 2 = REG$DATA=REG$DATA-1;
563 2 = CALL STORE$REG(REG$ADDR,REG$DATA);
564 2 = PC=PC+2;
565 2 = IF REGSDATA <> 0
= THEN PC=PC+SIGN$EXTENDED(DISPLACEMENT);
567 2 = END DJNZ$REGSREL;
1* "DJNZ direct,rel" INSTRUCTION: *1

=
568 1 = DJNZSDIR$REL: PROCEDURE;
569 2 = DIR$ADDR=FETCHSPROGRAM(PC+l);
571 2 = DIRSDATA=FETCHSDIRSINT(DIRSADDR);
572 2 = DIR$DATA=DIRSDATA-1i
573 2 = CALL STORESDIR(DIR$ADDR,DIR$DATA);
5'74 2 = PC=PC+3i
575 2 IF DIR$DATA <> 0
= THEN PC=PC+SIGN$EXTENDEDCDISPLACEMENT);
577 2 = END DJNZ$DIRSREL;
::::
:::: 1* "INC A" INSTRUCTION: *1
578 1 = INC$A: PROCEDURE;

5'79 2 ACC=ACC+l;
580 2 = PC::::PC+l ;
581 2 = END INGSAi
:::: 1* "INC Rn" INSTRUCTION: *1
582 1 :::: INC$REG: PROCEDURE;

584 2 = REGSDATA=FETCH$REG(REG$ADDR);
585 2 = REG$DATA=REG$DATA+1i
586 2 = CALL STORESREG(REGSADDR,REG$DATA);
587 2 = PC::::PC+l ;
AFN,01739A
A19
588 2 END INCSREG;
= 1* "INC direct" INSTRUCTION: *1

=
589 1 = INCSDIR: PROCEDURE;
590 2 = DIRSADDR=FETCHSPROGRAM(PC+l);
591 2 = DIRSDATA=FETCHSDIRSINT(DIRSADDR);
592 2 = DIR$DATA=DIR$DATA+1;
593 2 CALL STORESDIR(DIRSADDR,DIRSDATA);
594 2 PC=PC+2;
595 2 END INCSDIR;
= 1* "INC @Ri" INSTRUCTION: *1

:=
596 1 = INC$IND: PROCEDURE;

598 2 = INDSDATA=FETCHSIND(REGSADDR);
599 2 = INDSDATA=INDSDATA+l;
600 2 CALL STORESIND(REGSADDR, INDSDATA);
601 2 = PC=PC+1;
602 2 = END INCSIND;
1* "INC DPTR II
INSTRUCTION: *1
603 1 INC$DPTR: PROCEDURE;

604 2 DPL=DPL+i;
605 2 := IF DPL=O THEN DPH=DPH+i;
607 2 = PC=PC+1;
608 2 END INCSDPTR;
1* ",)B b i t, re 111 INSTRUCTION: *1
609 1 JB$BITSREL: PROCEDURE;

610 2 = BITSADDR=FETCH$PROGRAM(PC+l);
611 2 BITSDATA=FETCH$BITCBITSADDR);
612 2 DISPLACEMENT=FETCHSPROGRAM(PC+2};
61.:3 2 PC~::PC+3;
614 2 IF BITSDATA=1
THEN PC=PC+SIGNSEXTENDEDCDISPLACEMENT);
616 2 END JB$BIT$REl;
1* "JBC b i t, re 111 INSTRUCTION: *1
617 1 JBC$BITSREL: PROCEDURE;

618 2 BIT$ADDR=FETCH$PROGRAMCPC+l);
61.9 2 BITSDATA=FETCH$BITSINT(BITSADDR);
621 2 PC=PC+3;
622 2 CALL STORESBIT(BITSADDR,O);
6;23 2 IF BIT$DATA=i
THEN PC=PC+SIGNSEXTENDED(DISPLACEMENT);
625 2 = END JBC$BIT$REL;
AFN-01739A
A-20
1* IIJC reI" INSTRUCTION: *1
626 1 JC$REL: PROCEDURE;

627 2 = DISPLACEMENT=FETCH$PROGRAM(PC+l);
628 2 = PC::::PC+2;
629 2 = IF (PSW AND 10000000B) <> 0
631 2 END JC$REL;
== l* "J/"lP @A+DPTR" INSTRUCTION: *1
632 1 JMP$ADPTR: PROCEDURE;

633 2 CODE$ADDR=(DPH*256)+DPL+ACC;
6:34 2 PC=CODE$ADDR;
635 2 END JMP$ADPTR;
1* "JNB bit, re 1" INSTRUCTION: *1
636 1 = JNB$BIT$REL: PROCEDURE;

638 2 DISPLACEMENT=FETCH$PROGRAM(PC+2);
639 2 BIT$DATA=FETCH$BIT(BIT$ADDR);
640 2 PC=PC+3;
641 2 IF BIT$DATA=O
643 2 = END JNB$B IT$REL;
l* "JNC reI" INSTRUCTION: *1
64-4 1 JNC$REL: PROCEDURE;

645 2 :::: DISPLACEMENT=FETCH$PROGRAM(PC+l);
646 .,r.:.. PC"=PC+2;
647 2 IF (PSW AND 10000000B) - 0
649 2 END ,JNC$REL;
1* "JNZ reI" INSTRUCTION: *1
650 1 :::: JNZSREL: PROCEDURE;

651 2 DISPLACEMENT=FETCH$PROGRAM(PC+l);
652 2 PC:::;PC+2;
6~)3 2 IF ACC <> 0
655 2 END JNZ$REL;
1* ",)l reI" INSTRUCTION: *1
656 . JZ$REL: PROCEDURE;

657 2:::: DISPLACEMENT==FETCH$PROGRAM(PC+l);
6~;8 2 PC:::::PC+2;
AFN01739A
A21
6!59 2 IF Ace _. 0
661 2 END JZ$REl.i
1* "LCALL addr16" INSTRUCTION: *1
662 1 LCALL$ADDR16: PROCEDURE;

663 2 PAGE$CODE=FETCH$PROGRAM(PC+l)i
664 2 PAGE$OFFSET=FETCH$PROGRAM(PC+2);
665 2 PC~-::PC+3;
666 2 CALL PUSH$STACK(LOW(PC;
667 2 CALL PUSH$STACK(HIGHCPC;
668 2 PC=(PAGE$CODE * IOOH) + PAGESOFFSET;
669 2 END LCALL$ADDR16;
1* "LJMP addr16" INSTRUCTION: *1
670 1 LJMP$ADDR16: PROCEDURE;

671 2 PAGE$CODE=FETCH$PROGRAM(PC+l);
672 2 PAGESOFFSET=FETCH$PROGRAM(PC+2);
673 2 PC=(PAGE$CODE * lOOH) + PAGE$OFFSET;
674 2 END LJMPSADDR16i
1* "MCJV A,Rn" INSTRUCTION: *1
675 1 MOV$ASREG: PROCEDUREi

676 2 REGSADDR=OPCODE AND OOOOOl11D;
677 2 ACC=FETCH$REG(REG$ADDR);
678 2 PC:==PC+li
679 2 END MOV$ASREG;
1* "MOV A, direct" INSTRUCTION: *1
680 I MOV$A$DIR: PROCEDURE;

681 DIR$ADDR=FETCH$PROGRAM(PC+l)i
682 ...,
2
t::.. ACC=FETCHSDIRCDIRSADDR)i
6B3 2 PC:::::PC+2i
684 2 END MOV$ASDIR;
1* "MOV A,@Ri" INSTRUCTION: *1
685 1 MOV'A$IND: PROCEDUREi

686 2 = REGSADDR=OPCODE AND 0000000lBi
687 2 ACC=FETCHSIND(REG$ADDR)i
688 2 PC::::PC+li
689 2 END MOVSA$lNDi
1* "I"IOV A, #data" INSTRUCTION: '~I
6'-70 I = MOV$ASIMM: PROCEDUREi

691 2 ACC=FETCH$PROGRAM(PC+l);
AFN-01739A
A-22
692 2 = PC~.::PC+2;
693 2 END MOV$A$IMM;
1* "JVIOV RTl, A" INSTRUCTION: *1
694 = MOV$REG$A: PROCEDURE;

695 "")
c. REG$ADDR=OPCODE AND 00000111Bi
696 2 CALL STORE$REG(REG$ADDR,ACC);
697 2 PC::::PC+1 i
698 2 END MOV$REG$Ai
::: 1* "MOV Rn, direct" INSTRUCTION: '11.-1
699 MOV$REG$DIR: PROCEDURE;

700 2 REG$ADDR=OPCODE AND 00000111B;
701 2 DIR$ADDR=FETCH$PROGRAMCPC+l);
703 2 CALL STORE$REG(REG$ADDR,DIR$DATA);
704 2 PC;:.PC+2,.
705 2 END MOV$REG$DIR;
1* II 1"10 V Rn,:>.ta" INSTRUCTION: *1
706 MOV$REG$IMM: PROCEDUREi

708 2 = IMM$DATA=FETCH$PROGRAM(PC+1);
709 2 = CALL STORE$REG(REG$ADDR, IMM$DATA);
7:1.0 2 PC=PC+2i
711 2 = END MOV$REG$IMM;
1* "MOV ,direct, All INSTRUCTION: *1
712 1 MOV$DIR$A: PROCEDUREi

713 2 = DIR$ADDR=FETCH$PROGRAM(PC+l);
714 2 CALL STORE$DIR(DIR$ADDR,ACC);
715 2 PC;::PC+2;
716 2 END MOV$DIR$A;
1* "MOV d i rec t, Rn II INSTRUCTION: *1
7:1.7 1 MOV$DIR$REG: PROCEDURE;

718 2 :; REG$ADDR=OPCODE AND 00000111Bi
719 2 REG$DATA=FETCH$REGCREG$ADDR);
720 2 = DIR$ADDR=FETCH$PROGRAMCPC+l);
721 2 = CALL STORE$DIR(OIR$ADOR,REG$DATA);
'7;:12 2 PC=PC+2;
723 2 = END' 1'10V$DIR$REG;
= 1* "MOV d ire c t, d ire c t II I NSTR UC T I ON : *I

:::
724 1 = MOV$DIR$DIR: PROCEDURE;
AFN01739A
A-23
725 2 = SOURCE$ADDR=FETCH$PROGRAM(PC+l)i
726 2 = DEST$ADDR=FETCH$PROGRAM(PC+2);
727 2 = DIR$DATA=FETCH$DIR(SOURCE$ADDR);
728 2 = CALL STORE$DIR(DEST$ADDR,DIR$DATA);
729 2 = PC::::PC+3;
730 2 = END MOV$DIR$DIR;
1* IIMOV d i rec t, @Ri /I INSTRUCTION: *1
731 1 MOV$DIR$IND: PROCEDURE;

732 2 = AND 0000000lB;
REG$ADDR~OPCODE
733 2 = IND$DATA=FETCH$IND(REG$ADDR);
734 2 DIR$ADDR=FETCH$PROGRAM(PC+1);
735 2 CALL STORE$DIR(DIR$ADDR, IND$DATA);
7~36 2 PC::::PC+2i
73'7 2 :: END MOV$DIR$INDi
=: I ,If "MOV direct, #data" INSTRUCTION: *1
738 1 MOV$DIR$IMM: PROCEDUREi

740 2 IMM$DATA=FETCH$PROGRAM(PC+2)i
741 2 CALL STORE$DIR(DIR$ADDRI IMM$DATA);
742 2 PC==PC+3i
743 2 = END MOV$DIR$IMM;
1* "MOV @Ril All INSTRUCTION: *1

=
744 1 MOV$IND$A: PROCEDURE;
74,6 2 = CALL STORE$IND(REG$ADDR,ACC);
747 2 PC=PC+1 i
748 2 :: END MOV$IND$A;
= l* "MOV @Ri, d i rec t /I INSTRUCTION: *1
749 1 :: MOV$IND$DIR: PROCEDURE;

751 2 = DIR$OATA=FETCH$OIR(DIR$ADDR);
753 2 = CALL STORE$IND(REG$ADDR,DIR$DATA);
7~i4 2 PC=PC+2;
755 2 END MOV$IND$DIR;
1* "1lOV @Ril#data ll INSTRUCTION: *1
756 1 :: MOV$IND$IMM: PROCEDURE;

757 2 = IMM$DATA=FETCH$PROGRAM(PC+l);
759 2 = CALL STORE$IND(REG$ADDR, IMM$DATA);
760 2 PCr.::PC+2i
761 2 END MOV$IND$IMM;
AFN01739A
A-24
1* "rHJV C, bit" INSTRUCTION: '~I
762 1 MOVSCSBIT: PROCEDURE;

764 2 BITSDATA=FETCHSBITCBIT$ADDR);
765 2 IF BIT$DATA=O
THEN PSW=(PSW AND 01111111B);
767 2 ELSE PSW=(PSW OR 10000000B);
768 2 PC::::PC+2i
769 2 END MOVSCSB IT j
1* "MOV b i t, C" INSTRUCTION: -j!-/
Tl0 MOVSBITSC: PROCEDURE;

771 2 BITSADDR=FETCHSPROGRAM(PC+l);
772 '-I
c:.. BITSDATA=PSW AND 10000000B) I 128);
773 2 CALL STORESBIT(BIT$ADDR.BIT$DATA);
7'/4 2 PC;;::;PC -1-2;
7'15 2 END MOV$BIT'flC;
1* "I"IOV DPTR, #data16" INSTr~UCTION: i!;'/
776 1 MOVSDPTR$IMM16. PROCEDURE;

7'77 2 DPH=FETCHSPROGRAM(PC+l);
7'78 2 DPL=FETCH$PROGRAM(PC+2);
7'79 '"1
r._ PC:::::PC+3;
780 2 END MOV$DPTRSIMM16;
/* "1"lOVe A, @A+DPTR" INSTRUCTION: .!t. .!
781 MOVC$ASADPTR: PROCEDURE;

782 2 CODESADDR=(DPH*256)+DPL+ACC;
78~3 2 ACC=FETCH$PROGRAM(CODE$ADDR);
7B4 2 PC:=PC+:L ;
785 2 END MOVC$ASADPTR;
1* "Move A, @At,PC" INSTRUCTION: It-I
786 MOVC$A$APC: PROCEDURE;

7U7 2 PC::=pC+l i
788 "1
c:.. CODESADDR=(PC+ACC);
789 2 = ACC=FETCH$PROGRAMCCODESADDR);
790 "c:.. END MOVCSA$APC;
1* "I"IOVX A, @Ri II INSTRUCTION: *1
791 MOVX$ASIND: PROCEDURE;

793 2 PAGEDSEXTERNALSADDR=FETCH$REG(REG$ADDR)I
794 2 ACC=FETCH$PAGED$EXTERNAL(PAGED$EXTERNALSADDR);
AFN01739A
A-25
PL/M-BO COMPILER 8051 INSTRUCTION SET SIMULATOR
795 2 = PC=PC+i;
796 2 = END MOVX$A$IND;
= 1* "MOVX @Ri. A" INSTRUCTION: *1
791 = MOVX$IND$A: PROCEDUREj

798 2 = REG$ADDR=OPCODE AND 0000000lBi
799 2 = PAGED$EXTERNAL$ADDR==FETCH$REG(REG$ADDR);
800 2 = CALL STORE$PAGED$EXTERNALCPAGED$EXTERNAL$ADDR,ACC);
801 2 = PC=PC+li
802 2 = END MOVX$IND$Ai
= 1* "MOVX A,@DPTR" INSTRUCTION: *1
e03 1 ::::: MOVX$A$DPTR: PROCEDURE;

804 2 = ACC=FETCH$LONG$EXTERNAL(CDPH*256)+DPL)i
805 2 = PC=PC+li
806 2 = END MOVX$A$DPTRi
:::
= 1* "MOVX @DPTR,A" INSTRUCTION: *1

:::
907 1 = MOVX$DPTR$A: PROCEDUREi

808 2 = CALL STORE$LONG$EXTERNAL(CDPH*256)+DPL,ACC)j
809 2 ::: PC::::PC+li
810 2 == END MOVX$DPTR$Ai
:=
:= 1* "MUL AB" INSTRUCTION: *1

:::
811 1 = MUL$AB: PROCEDUREi

812 2 MUL$TEMP=ACC * Bi
913 2 = B=HIGHCMUL$TEMP);
814 2 = ACC=LOW(MUL$TEMP)i
815 2 == PSW=PSW AND 01111111B;
816 2 IF B :co:: 0
::: THEN PSW==PSW AND 11111011B;
818 2 ::: ELSE PSW=PSW OR 00000I00B;
8:1.9 2 ::: PC:;::PC+li
8~~O 2 = END MUL$ABi
1* IINOP " INSTRUCTION: 'Ifol

--
821 1 ::: NOP: PROCEDUREi
8~12 2 - Pco:::pC+:I. i
823 2 :;:: END NOP;
-
::::: 1* "ORL A,Rn" INSTRUCTION: 'Ifol
.. -
824 1 ::: ORL$A$REG: PROCEDUREi
825 2 ::: REG$ADDR=OPCODE AND 000OO111Bi
826 2 = REG$DATA=FETCH$REGCREG$ADDR);
827 2 == ACC=ACC OR REG$DATA,
AFN-01739A
A-26
828 2 :::: PC=PC+1i

829 2 = END ORL$A$REGi
=
= 1* "ORL A,direct" INSTRUCTION: *1
::::
830 1 ORL$A$DIR: PROCEDUREi

831 2 :::: DIR$ADDR==FETCH$PROGRAM(PC+1)i
832 2 DIR$DATA=FETCH$DIR(DIR$ADDR)i
833 2 = ACC=ACC OR DIR$DATAi
834 2 PC=PC+2;
835 2 :::: END ORL$A$DIRi
1* "ORL A,@Ri" INSTRUCTION: *1

=
836 1 = ORL$A$IND: PROCEDUREi
837 2 = REG$ADDR=OPCODE AND 0000000lB;
839 2 ACC=ACC OR IND$DATAi
840 2 PC=PC+1;
841 2 :::: END ORL$A$INDi
== 1* "ORL A,#data" INSTRUCTION: *1

=
842 :::: ORL$A$IMM: PROCEDURE;
844 2 :::: ACC=ACC OR IMM$DATAi
845 2 :::: PC=PC+2i
846 2 END ORL$A$IMMi
== 1* "ORL d i rec t, A" INSTRUCTION: *1
847 1 ORL$DIR$A: PROCEDURE;

848 2 = DIR$ADDR=FETCH$PROGRAM(PC+1)i
849 2 = DIR$DATA=FETCH$DIR$INT(DIR$ADDR);
850 2 = CALL STORE$DIRCDIR$ADDR,ACC OR DIR$DATA)i
851 2 == PC:::,pC+2i
852 2 END ORL$DIR$l\;
= 1* 1I0RL direct, #data" INSTRUCTION: *1
853 1 ORL$DIR$IMM: PROCEDUREi

856 2 = DIR$DATA=FETCH$DIR$INT(DIR$ADDR)i
857 2 = CALL STORE$DIR(DIR$ADDR, IMM$DATA OR DIR$DATA)i
858 2 == PC=PC+3i
859 2 == END ORL$DIR$IMMi
1* "ORL C, bit" INSTRUCTION: *1
860 1 ORL$C$BIT: PROCEDURE;
AFN01739A
A-27
861 2 = BIT$ADDR=FETCH$PROGRAM(PC+1);
862 2 = BIT$DATA=FETCH$BIT(BIT$ADDR)i
863 2 = IF BIT$DATA = 1 THEN PSW=PSW OR 10000000B;
865 2 = PC=PC+2i
866 2 END ORL$C$BITi
:::
=
::: 1* IIORL C,/bit ll
INSTRUCTION: *1
=
867 1 = ORL$C$COMP$BIT: PROCEDUREi
869 2 = BIT$DATA=FETCH$BIT(BIT$ADDR)i
870 2 = IF BIT$DATA = 0 THEN PSW=PSW OR lOOOOOOOBi
872 2 = PC=PC+2i
873 2 = END ORL$C$COMP$BITi
= 1* IIPOP d i -rec t II INSTRUCTION: *1

874 1 == POP$DIR: PROCEDURE;
876 2 = STACK$DATA=POP$STACKi
877 2 = CALL STORE$DIR(DIR$ADDR,STACK$DATA);
878 2 PC=PC+2;
879 2 = END POP$DIR;
:::
1* IIPUSH d i -rec t II INSTRUCTION: *1

=
880 1 ::: PUSH$DIR: PROCEDURE;
882 2 = DIR$DATA=FETCH$DIR(DIR$ADDR)i
883 2 CALL PUSH$STACK(DIR$DATA)i
884 2 PC=PC+2i
885 2 END PUSH$DIRi
:::
= 1* "RET II INSTRUCTION: *1
886 1 RET: PROCEDURE;

887 2 = PAGE$CODE=POP$STACKi
888 2 PAGE$OFFSET=POP$STACK;
889 2 = PC=(PAGE$CODE * lOOH) + PAGE$OFFSETi
890 2 = END RETi
:::
1* "RETIII INSTRUCTION: *1
891 ::: RETI: PROCEDURE;

892 2 PAGE$CODE=POP$STACK;
893 2 PAGE$OFFSET=POP$STACKi
8(74 2 = PC=(PAGE$CODE * lOOH) + PAGE$OFFSETi
1* RESTORE INTERRUPT SYSTEM TO LEVEL IN EFFECT
::: BEFORE LAST INTERRUPT RECEIVED *1
895 2 ::: END RETIi
AFN-01739A
A-28
::::
1* "RL A" INSTRUCTION: *1

==
896 1 = RL$A: PROCEDUREi
897 2 LINK$BIT=(ACC AND 10000000B) 1 128i
898 2 ACC==(ACC * 2) + LINK$BITi
899 2 = PC==PC+1i
900 2 == END RL$Ai
::::
1* "RLC All INSTRUCTION: *1
901 1 = RLC$A: PROCEDUREi

902 2 LINK$BIT=(ACC AND 10000000B) 1 128;
903 2 ACC=(ACC * 2) + PSW AND 10000000B) 1 128);
904 2 = PSW=(PSW AND 01111111B) + (LINK$BIT * 128)i
905 2 PC=PC+1 i
906 2 = END RLC$Ai
::::
1* "RR A" INSTRUCTION: *1
907 1 == RR$A: PROCEDURE;

908 2 == LINK$BIT=ACC AND 00000001Bi
909 2 == ACC=(ACC 1 2) + (LINK$BIT * 128)i
910 2 PC=PC+1i
911 2 END RR$Ai
1* "RRC All INSTRUCTION: *1
912 1 RRC$A: PROCEDURE;

913 2 LINK$BIT=ACC AND 00000001B;
'914 2 ACC=(ACC I 2) + (PSW AND 10000000B)i
915 2 PSW=(PSW AND 01111111B)+(LINK$BIT * 128)i
916 2 == PC=PC+1i
917 2 == END RRC$Ai
1* IISETB C" INSTRUCTION: *1
918 1 = SETB$C: PROCEDURE;

919 2 PSW=PSW OR 10000000B;
920 2 PC:.::PC+l ;
921 2 END SETB$Ci
1* "SETB bit" INSTRUCTION: *1
922 1 == SETB$BIT: PROCEDURE;

923 2 :::: BIT$ADDR=FETCH$PROGRAM(PC+1);
924 2 :::: CALL STORE$BIT(BIT$ADDR, 1);
9~25 2 :::: PC!.::PC+2;
926 2 END SETB$B IT;
AFN-01739A
A29
= l* IIS,)MP reI Ii
INSTRUCTION: *1
92'7 == SJMP$REL: PROCEDURE;

929 2 PC=PC+2;
930 2 PC=PC+SIGN$EXTENDED(DISPLACEMENT);
931 2 END SJMP$RELi
1* "SUBD A, (sT'c-byte:>" FUNCTION: -lI.1
932 SUBB$A: PROCEDURE(DATA$BYTE)i

9:33 2 DECLARE DATA$BYTE BYTE;
934 ;2 = LINK$BIT=(PSW AND 100000000) 1 128;
935 2 SUB$TEMP=DATA$BYTE;
936 2 = SUB$TEMP=SUB$TEMP+LINK$BIT;
937 2 IF (ACC AND OFH) ~ (SUB$TEMP AND OFH)
939 2 ELSE PSW=PSW AND 101111110;
940 2 IF (ACC AND 7FH) ~ (SUB$TEMP AND 7FH)
942 2 ELSE PSW=PSW AND 11111011B;
943 2 IF Ace < SUB$TEMP
THEN PSW=(PSW OR 10000000B) XOR 00000100B;
<7'46 2 ACC~ACC-SUB$TEMP;
947 2 = END SUBB$A;
1* "SUBB A, Rn" INSTRUCTION: *1
948 = SUBB$A$REG: PROCEDURE;

950 2 == REG$DATA=FETCH$REG(REG$ADDR);
951 2 CALL SUBB$A(REG$DATA);
9~J2 2 PC::::PC+l ;
953 2 END SU13B$A$REG;
1* "SUBB A, direct" INSTRUCTION: -lI.1
954 SUBB$A$DIR: PROCEDURE;

955 2 :::: DIR$ADDR=FETCH$PROGRAM(PC+l);
9'57 2 Cf'\LL SUBB$A.( DIR$DATA);
958 2 PC::::PC+2;
959 2 .- END SUBB$A$DIRi
::::
= 1* "SUBB A,@Ri" INSTRUCTION: *1

..-
960 SUBB$A$IND: PROCEDURE;
961 2 = REG$ADDR=OPCODE AND 000000010;
963 2 CALL SUBB$A(IND$DATA);
964 2 PC:::::PC+l ;
965 2 END SUBB$A$INDi
AFN01739A
A-30
::: 1* "SUBB Al#data" INSTRUCTION: *1
966 SUBB$A$IMM: PROCEDURE;

967 2 ::: IMM$DATA==FETCH$PROGRAM(PC+1);
968 2 == CALL SUBB$A(IMM$DATA);
969 2 PC;::PC+2;
9-'0 2 END SUBB$f\$IMMi
== 1* "SWAP A" INSTRUCTION: *1
971 1 == SWAP$A: PROCEDURE;

972 2 LOW$NIB=ACC AND 000011118;
973 2 HIGH$NIB==ACC AND 11110000B;
974 2 ::: ACC==(LOW$NIB * 16) + (HIGH$NIB I 16);
975 2 == PC==PC+1;
976 2 == END SWAP$A;
1* "XCH A,Rn" INSTRUCTION: *1
977 1 XCH$A$REG: PROCEDURE;

979 2 == REG$DATA=FETCH$REG(REG$ADDR};
980 2 = CALL STORE$REG(REG$ADDR,ACC);
981 2 ACC=REG$DATA;
982 2 PC:.::PC+l ;
983 2 END XCH$A$REG;
== 1* "XCH A, direct" INSTRUCTION: *1

==
984 1 ::: XCH$A$DIR: PROCEDURE;
987 2 ::: CALL STORE$DIR(DIR$ADDR,ACC);
988 2 ACC=DIR$DATA;
989 2 PC=PC+2;
990 2 :::: END XCH$A$DIR;
:::
1* "XCH Al @Ri" INSTRUCTION: ltl
991 ::: XCH$A$IND: PROCEDURE;

992 2 = REG$ADDR=OPCODEAND 00000001B;
994 2 CALL STORE$IND(REG$ADDRlACC);
995 2 = ACC=IND$DATA;
996 2 == PC=PC+l;
997 2 == END XCH$A$IND;
== 1* "XCHD Al@Ri" INSTRUCTION: *1

:::::
998 1 XCHD$A$IND: PROCEDURE;

AFN01739A
A-31
999 2 = REG$ADDR=OPCODE AND 00000001Bi

1000 2 = IND$DATA=FETCH$INDCREG$ADDR)i
1001 2 ::;;: LOW$SOURCE$NIB=IND$DATA AND 000011110i
t002 2 IND$DATA=(IND$DATA AND 111100000) + CACC AND 000011110)i
1003 2 ::;;: CALL STORE$INDCREG$ADDR, IND$DATA)i
1004 2 ::;;: ACC=CACC AND 111100000) + LOW$SOURCE$NIBi
1005 2 ::;;: PC=PC+1;
1006 2 = END XCHD$A$INDi
1* "XRL A, Rn" INSTRUCTION: *1
1007 1 XRL$A$REG: PROCEDUREi

1008 2 = REG$ADDR=OPCODE AND 000001110i
1009 2 = REG$DATA=FETCH$REGCREG$ADDR)i
1010 2 := ACC=ACC XOR REG$DATAi
1011 2 PC=PC+1i
1012 2 ::;;: END XRL$A$REGi
1* "XRL A, direct" INSTRUCTION: *1
1013 XRL$A$DIR: PROCEDUREi

1014 2 DIR$ADDR=FETCH$PROGRAMCPC+1);
1015 2 = DIR$DATA=FETCH$DIRCDIR$ADDR)i
1016 2 ::;;: ACC=ACC XOR DIR$DATAi
1017 2 = PC==PC-f'2i
1018 2 END XRL.$A$DIRi
1* IIXRL A,@Ri ll INSTRUCTION: *1
1019 XRL$A$IND: PROCEDURE;

1020 2 = REG$ADDR=OPCODE AND 00000001Bi
1021 2 IND$DATA=FETCH$INDCREG$ADDR)
1022 2 = ACC=ACC XOR IND$DATAi
1023 2 PC=PC+l i
1024 2 = END XRL$A$INDi
1* "XRL A,#data" INSTRUCTION: *1
1025 XRL$A$IMM: PROCEDURE)

1026 2 = IMM$DATA=FETCH$PROGRAM(PC+l)i
1027 2 := ACC=ACC XOR IMM$DATAi
1028 2 = PC=PC+2i
1029 2 END XRL$A$IMM;
= 1* "XRL diT'ect,A II INSTRUCTION: *1
1030 XRL$DIR$A: PROCEDUREi

1031 2 ::;;: DIR$ADDR=FETCH$PROGRAMCPC+1)
1032 2 DIR$DATA=FETCH$DIR$INTCDIR$ADDR)i
1033 2 = CALL STORE$DIRCDIR$ADDR,ACC XOR DIR$DATA);
1034 2 PC=PC+2i
1035 2 = END XRL$DIR$Ai
AFN01739A
A-32
11t- "XRL direct, #data" INSTRUCTION: *1
1036 1 _. XRLSDIR$IMM: PROCEDURE;

1037 2 .- DIR$ADDR=FETCHSPROGRAM(PC+l);
1038 2 IMMSDATA=FETCH$PROGRAM(PC+2};
1039 2 := DIRSDATA=FETCHSDIRSINT(DIRSADDR);
1040 2 - CALL STORESDIRCDIRSADDR.IMMSDATA XDR DIR$DATA) ;
1041 2 PC::::;PC+3;
1042 2 END XRLSDIRSIMMi
AFN01739A
A-33
$E,,}ECT
1043 1 INITIALIZE: PROCEDURE PUBLICi

1044 2 PC=OOOOHi
1045 2 PO=OFFHi
1046 2 Pl::::0FFHi
1047 2 P2=OFFHi
1048 2 P3=OFFHi
1049 2 PSW=OOHi
1050 2 SP=07Hi
1051 2 DPL=OOHi
1052 2 DPH=OOHi
1053 2 ACC=OOHi
1054 2 B=OOHi
1055 2 TLO=OOHi
1056 2 THO=OOHi
1057 2 TL1=OOHi
1058 2 TH1=OOHi
1059 2 TCON=OOHi
1060 2 TMOD=OOHi
1061 2 SCON=OOHi
1062 2 IE==OOHi
1063 2 IP=OOHi
1064 2 MACH$CYC=OOOOHi 1* SIMULATION ELAPSED TIME REGISTER. *1
1065 2 END INITIALIZEi
1066 1 DECLARE EXECUTION$TIME(256) BYTE DATA

(1, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, I,
2, 2, 2, 1, 1, 1, 1, L I, 1, 1, 1, 1,
2, 2, 2, 1, 1, I, 1, 1, 1, 1, 1, 1, 1,
2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2, 2, 1, 2, I, 1, 1, 1, 1, L 1, 1, 1, 1, 1, L
2, 2, L 2, L 1, 1, 1, L L 1, 1, 1, L L 1,
2, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, I, 1, 1, 1,
2, 2, 2, 2, 1, 2, 1, 1, 1, 1, I, 1, L L 1, L
2, 2, 2, 2, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1, L L 1, 1, L L L 1, 1, L
2, 2, I, 2, 4, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2" 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 1, 1, 1, 1, I. 1, 1, 1, 1, L 1, 1,
2, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 1, 1, 1; 1, 1, 1, 1, I, I, 1, 1, L
2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, L 1, 1, 1, 1)i
AFN01739A
A34
$EJECT
1067 1 STEP: PROCEDURE (NEXT$INSTRUCTION) ADDRESS PUBLIC;

J,068 2 DECLARE NEXT$INSTRUCTION ADDRESSi
1069 2 PC=NEXT$INSTRUCTION;
1070 2 OPCODE=USER$CODE(PC);
1071 2 DO CASE OPCODEi
1* INSTRUCTIONS CORRESPONDING TO ROW 0 OF OrCaDE MAP

(FORM OXH): *1
1072 3 CALL NOPi
1073 3 CALL AJMP$ADDR 11 ;
1074 3 CALL LJMP$ADDR 16i
1075 3 CALL RR$Ai
1076 3 CALL INC$A;
1077 3 CALL INC$DIRi
1078 3 CALL INC$INDi
1079 3 CALL INC$INDi
1080 3 CALL INC$REGi
1* INSTRUCTIONS CORRESPONDING TO ROW 1 OF OrCaDE MAP

(FORM lXH): *1
1088 3 CALL JBC$BIT$RELi
1089 3 CALL ACALL$ADDR11i
1090 3 CALL LCALL$ADDR16i
1091 3 CALL RRC$Ai
1092 3 CALL DEC$Ai
1093 3 CALL DEC$DIRi
1094 3 CALL DEC$INDi
1095 3 CALL DEC$INDi
1096 3 CALl. DEC$REGi
1097 3 CALL DEC$REGi
1101 3 CALL DEC$REG;
1102 3 C,t\LL DEC$REGi
1103 3 CI\LL DEC$REG;
.lL ':1 I=; AFN01739A

$EJECT
1* INSTRUCTIONS CORRESPONDING TO ROW 2 OF OPCODE MAP

(FORM 2XH): *1
1104 3 CALL JB$BIT$REL;
1105 3 CALL AJMP$ADDR11;
1106 3 CALL RET;
1107 3 CALL RL$A;
1108 3 CALL ADD$A$IMMi
1109 3 CALL ADD$A$DIR;
1110 3 CALL ADD$A$IND;
1111 3 CALL ADD$A$IND;
1112 3 CALL ADD$A$REG;
1119 3 CALL ADD$A$REGi

(FORM 3XH): *1
1120 3 CALL JNB$BIT$REL;
1121 3 CALL ACALL$ADDRlli
1122 3 CALL RETI;
1123 3 CALL RLC$Ai
1124 3 CALL ADDC$A$ I MMi
1125 3 CALL ADDC$A$D I R;
1126 3 CALL ADDC$A$IND;
1127 3 CALL ADDC$A$IND;
1128 3 CALL ADDC$A$REG;
1129 3 CALL ADDC$A$REGi
1133 3 CALL ADDC$A$REG;
AFN01739A
A36
$EJECT

(FORM 4XH): *1
1136 3 CALL JC$REL;
1137 3 CALL AJMP$ADDR11i
1138 3 CALL ORL$DIR$A;
1139 3 CALL ORL$DIR$IMM;
1140 3 CALL ORL$A$ I MM;
1141 3 CALL ORL$A$DIRi
1142 3 CALL ORL$A$IND;
1143 3 CALL ORL$A$IND;
1144 3 CALL ORL$A$REGi
1146 3 CALL ORL$A$REG;

(FORM 5XH): *1
1152 3 CALL JNC$REL;
1153 3 CALL ACALL$ADDR 11 .
1154 3 CALL ANL$DIR$A;
1.155 3 CALL ANL$DIR$IMM;
1156 3 CALL ANL$A$IMM;
1157 3 CALL ANL$A$DIRi
1158 3 C,\LL ANL$A$IND;
1139 3 CALL ANL$A$IND;
1160 3 CALL. ANL$A$REG;
1161 3 CALL ANL$A$REG;
1162 :3 C~LL ANL$A$REG;
1163 3 C,\LL ANL$A$REG;
1164 3 CALL ANL$A$REGi
1166 3 CALL ANL$A$REGi
AFN01739A
A-37
$EJECT

(FORM 6XH): *1
1168 3 CALL JZ$RELi
1169 3 CALL AJMP$ADDRlli
1170 3 CALL XRL$DIR$Ai
1171 3 CALL XRL$DIR$IMM;
1172 3 CALL XRL$A$IMM;
1173 3 ClltLL XRL$A$DIR;
1114 3 CALL XRL$A$ I ND;
1175 3 Cf~LL XRL$A$INDi
1176 3 CALL XRL$A$REGi
I1T7 :3 C/~LL XRL$A$REG;
1178 3 CALL XRL$A$REG;
1179 3 Cf\LL XRL$A$REGi

(FORM 7XH): *1
1184 3 CALL JNZ$REli
1185 3 CALL ACALL$ADDRlli
1186 3 CALL ClRL$C$B I T;
t 187 3 CALL JMP$ADPTRi
1188 3 CALL MOV$A$IMM;
1189 3 CALL MOV$DIR$IMM;
1190 3 CALL MOV$IND$IMM;
1191 3 CALL MOV$IND$IMMi
1192 3 CALL MOV$REG$IMM;
1193 3 CALL MOV$REG$IMMi
AFN-01739A
A-38
$EJECT

(FDRM BXH): *1
1200 3 CALL S.JMP$RELi
1201 3 CALL AJMP$ADDR 11 i
1202 3 CALL ANL$C$BITi
1203 3 CALL MOVC$A$APC;
1204 3 CALL DIV$AB;
1205 3 CALL MOV$DIR$DIRi
1206 3 CALL MOV$DIR$INDi
1207 3 CALL MOV$DIR$INDi
1208 3 CALL MOV$DIR$REGi
1213 3 CALL MOV$D I R$REGi

(FORM 9XH): *1
1216 3 CALL MOV$DPTR$IMM16;
1217 3 CALL ACALL$ADDR11;
1;;!18 3 CALL MOV$BIT$C;
'.219 3 CALL MOVC$A$ADPTRi
1220 3 CALL SUBB$A$IMMi
1221 3 CALL SUBB$A$DIR;
1222 3 CALL SUBB$A$IND;
1223 3 CALL SUBB$A$INDi
1224 3 CALL SUBB$A$REGi
1225 3 CALL SUBB$A$REG;
AFN01739A
A-39
$EdECT
lit- INSTRUCTIONS CORRESPONDING TO ROW A OF OPCODE MAP

(FORM AXH): *1
1232 3 CALL ORL$C$COMP$BIT;
1234 3 CALL MOV$C$BITi
1235 3 CALL INC$DPTRi
12~J6 3 CALL MUL$AB;
1237 3 C/\LL NOP;
1238 3 CALL MOV$IND$DIRi
1239 3 CAL.L MOV$IND$DIRi
1240 3 CALL MOV$REG$DIR;
1241 3 CALL MOV$REG$DIRi
1246 3 CAL.L MOV$REG$DIRi
124'7 3 CALL MOV$REG$D I R;
1* INSTRUCTIONS CORRESPONDING TO ROW D OF OPCODE MAP

(FORM BXH): *1
1248 3 CALL ANL$C$COMP$BIT;
12~iO 3 CALL CPL$BIT;
1251 3 CALL CPL$C;
1252 3 CALL CJNE$A$IMM$REL;
1253 3 CALL CJNE$A$DIR$REL;
1254 3 CALL CJNE$IND$IMM$RELj
12~j5 3 CALL CJNE$IND$IMM$REL;
1256 3 CALL CJNE$REG$IMM$REL;
1257 3 Cf~LL CJNE$REG$IMM$REL;
1260 3 CALL CJNE$REG$IMM$RELi
1261 3 CALL CJNE$REG$IMM$RELi
1263 3 CALL. CJNE$REG$IMM$RELi
AFN01739A
A40
$EdECT
1* INSTRUCTIONS CORRESPONDING TO ROW C OF OPCODE MAP

(FORM CXH): *1
1264 3 CALL PUSH$DIRi
1265 3 CALL AJMP$ADDR 11 i
1266 3 CALL CLR$BITi
1267 3 Cf\LL CLR$Ci
1268 3 CALL SWAP$A;
1269 3 CALL XCH$A$DIR;
1270 3 Cf\LL XCH$A$INDi
1271 3 CALL XCH$A$IND;
1272 3 CALL XCH$A$REG;
1273 3 CALL XCH$A$REGi
1'11: INSTRUCTIONS CORRESPONDING TO ROW D OF OPCODE MAP

(FORM DXH): *1
1280 3 CALL POP$DIR;
1282 3 CALL SETB$B IT;
1.283 3 CALL SETB$C;
1284 3 CALL DA$A;
1285 3 CALL DJNZ$D I R$REL
1286 3 CALL XCHD$A$INDi
1287 3 CALL XCHD$A$IND;
1288 3 CALL DJNZ$REG$REL;
1292 3 CALL DJNZ$REG$REL
AFN-01739A
A-41
$EJECT
1* INSTRUCTIONS CORRESPONDING TO ROW E OF OPCODE MAP

(FORM EXH): *1
1296 3 CALL MOVX$A$DPTR;
1298 3 CALL MOVX$A$IND;
1299 3 CALL MOVX$A$ I NO;
1300 3 CALL CLR$A;
1301 3 CALL MOV$A$DIR;
1302 3 CALL MOV$A$IND;
1303 3 CALL MOV$A$INDi
1304 3 CALL MOV$A$REG;
1305 3 CALL MOV$A$REGi
1* INSTRUCTIONS CORRESPONDING TO ROW F OF OPCODE MAP

(FORM FXH): *1
1312 3 CALL MOVX$DPTR$Ai
1314 3 CALL MOVX$IND$Ai
1315 3 CALL MOVX$IND$Ai
1316 3 CALL CPL$Ai
1317 3 CALL MOV$DIR$A;
1318 3 CALL MOV$IND$Ai
1319 3 CALL MOV$IND$A;
1320 3 CALL MOV$REG$Ai
1321 3 CALL. MOV$REG$A;
1322 3 CALL MOV$REG$A;
1324 3 CALL MOV$REG$Ai.
1325 3 CALL MOV$REG$Ai
1328 3 END;
1329 2 PSW=(PSW AND 11111110B) + PARITY$STATE(ACC);
1330 2 MACH$CYC=MACH$CYC + EXECUTION$TIMECOPCODE)i
1331 ? RETURN PCi
1332 2 END STEP;
1333 1 END SIMS1;
A42 AFN01739A
I
APPLICATIONS
vss vee RSTIVPD
P1.0 vee
P1.1 po.o
P1.2 PO.1
P1.3 PO.2
P1.4 PO.3
P1.S PO.4
P1.& PO.S
P1.7 PO.&
VPD/RST PO.7
P3.0/RXD VDD/EA
P3.1/TXD PROG/ALE
P3.2/INTO PSEN
P3.3.1NT1 P2.7 RXD
P3.4/TO P2.6
I
TXD
P3.S/T1 P2.S INTO
P3.6/WR P2.4 001
P3.7/RD P2.3 PORT 3 TO
XTAL2 P2.2 T1
XTAL1 P2.1 WR
VSS P2.0
Ro
Figure 1a. 8051 Microcomputer Pinout Diagram Figure 1b. 8051 Microcomputer Logic Symbol
1. INTRODUCTION some microprocessor (preferably Intel's, of course) or

In 1976 Intel introduced/the' MCS-48 family, consisting have a background in computer programming and digital
of the 8048, 8748, and 8035 microcomputers. These parts logic.
marked the first time a complete microcomputer system,
including an eight-bit CPU, 1024 8-bit words of ROM Family Overview
or EPROM program memory, 64 words of data memory,
Pinout diagrams for the 8051, 8751, and 8031 are shown
I/O ports and an eight-bit timer/counter could be inte-
in Figure I. The devices include the following features:
grated onto a single silicon chip. Depending only on the
program memory contents, one chip could control a Single-supply 5 volt operation using HMOS tech-
limitless variety of products, ranging from appliances or nology.
automobile engines to text or data processing equipment. 4096 bytes program memory on-chip (not on 8031).
Follow-on products stretched the MCS-48 architecture 128 bytes data memory on-chip.
in several directions: the 8049 and 8039 doubled the Four register banks.
amount of on-chip memory and ran 83% faster; the 8021 128 User-defined software flags.
reduced costs by executing a subset of the 8048 instruc- 64 Kilobytes each program and external RAM
tions with a somewhat slower clock; and the 8022 put a addressability.
unique two-channel 8-bit analog-to-digital converter on One microsecond instruction cycle with 12 MHz
the same NMOS chip as the computer, letting the chip crystal.
interface directly with analog transducers. 32 bidirectional I/O lines organized as four 8-bit
ports (16 lines on 8031).
Now three new high-performance single-chip microcom- Multiple mode, high-speed programmable Serial
puters-the Intel 8051, 8751, and 8031-extend the Port.
advantages of Integrated Electronics to whole new prod- Two mUltiple mode, 16-bit Timer/Counters.
uct areas. Thanks to Intel's new HMOS technology, the Two-level prioritized interrupt structure.
MCS-5ITM family provides four times the program Full depth stack for subroutine return linkage and
memory and twice the data memory as the 8048 on a data storage.
single chip. New I/O and peripheral capabilities both Augmented MCS-48 instruction set.
increase the range of applicability and reduce total system Direct Byte and Bit addressability.
cost. Depending on the use, processing throughput Binary or Decimal arithmetic.
increases by two and one-half to ten times. Signed-overflow detection and parity computation.
This Application Note is intended to introduce the reader Hardware Multiple and Divide in 4 usec.
to the M CS-51 architecture and features. While it does Integrated Boolean Processor for control applica-
not assume intimacy with the MCS-48 product line on tions.
the part of the reader, he/she should be familiar with Upwardly compatible with existing 8048 software.
AFN-01502A
B-1
APPLICATIONS
All three devices come in a standard 40-pin Dual In- ware application examples illustrate many of the concepts.
Line Package, vlith the same pin-out, the same timing, Several, isolated tasks (rather than one complete system
and the same electrical characteristics. The primary design example) are presented in the hope that some of
difference between the three is the on-chip program them will apply to the reader's experiences or needs.
memory-different types are offered to satisfy differing
A document this short cannot detail all of a computer
user requirements.
system's capabilities. By no means will all the 8051 instruc-
The 8751 provides 4K bytes of ultraviolet-Erasable, tions be demonstrated; the intent is to stress new or
Programmable Read Only Memory (EPROM) for unique MCS_5ITM operations and instructions generally
program development, prototyping, and limited pro- used in conjunction with each other. For additional hard-
duction runs. (By convention, 1K means 210 = 1024. ware information refer to the Intel MCS-5rM Family
lk-with a lower case "k"-equals 103 = 1000.) This part User's Manual, publication number 121517. The assembly
may be individually programmed for a specific applica- language and use of ASM51, the MCS_5ITM assembler,
tion using Intel's Universal PROM Programmer (UPP). are further described in the MCS-5J Macro Assembler
If software bugs are detected or design specifications User's Guide, publication number 9800937.
change the same part may be "erased" in a matter of The next section reviews some of the basic concepts
minutes by exposure to ultraviolet light and repro- of microcomputer design and use. Readers familiar
grammed with the modified code. This cycle may be with the 8048 may wish to skim through this section
repeated indefinitely during the design and development or skip directly to the next, "ARCHITECTURE AND
phase.
ORGANIZATION."
The final version of the software must be programmed
into a large number of production parts. The 8051 has Microcomputer Background Concepts
4K bytes of ROM which are mask-programmed with the Most digital computers use the binary (base 2) number
customer's order when the chip is built. This part is con- system internally. All variables. constants, alphanumeric
siderably less expensive, but cannot be erased or altered characters, program statements, etc., are represented by
after fabrication. groups of binary digits ("bits"), each of which has the
The 8031 does not have any program memory on-chip, value 0 or I. Computers are classified by how many bits
but may be used with up to 64K bytes of external standard they can move or process at a time.
or multiplexed ROMs, PROMs, or EPROMs. The 8031
fits well in applications requiring significantly larger or The MCS-5ITM microcomputers contain an eight-bit
smaller amounts of memory than the 4K bytes provided central processing unit (CPU). Most operations process
by its two siblings. variables eight bits wide. All internal RAM and ROM,
and virtually all other registers are also eight bits wide.
(The 8051 and 8751 automatically access external pro- An eight-bit ("byte") variable (shown in Figure 2) may
gram memory for all addresses greater than the 4096 bytes assume one of 28 = 256 distinct values, which usually
on-chip. The External Access input is an override for represent integers between 0 and 255. Other types of
all internal program memory-the 8051 and 8751 will numbers, instructions, and so forth are represented by
each emulate an 8031 when pin 31 is low.) one or more bytes using certain conventions.
Throughout this Note, "8051" is used as a generic term.
For example, to represent positive and negative values,
Unless specifically stated otherwise, the point applies
the most significant bit (07) indicates the sign of the other
equally to all three components. Table 1 summarizes the
seven bits-O if positive, I if negative-allowing integer
quantitative differences between the members of the
variables between -128 and +127. For integers with
MCS-48 and MCS-51TM families.
extremely large magnitudes, several bytes are manipu-
The remaind~r of this Note discusses the various M CS-51 lated together as "multiple precision" signed or unsigned
features and how they can be used. Software and/or hard- integers-16, 24, or more bits wide.
Table 1. Features of Intel's Single-Chip Microcomputers
EPROM ROM External Program Data Instr. Input!

Program Program Program Memory Memory Cycle Output Interrupt Reg.
Memory Memory Memory (Int!Max) (Bytes) Time Pins Sources Banks
- 8021 - IK/IK 64 8.4pSec 21 0 I
- 8022 - 2K/2K 64 8.4fiSec 28 2 I
8748 8048 8035 .IK/4K 64 2.5 pSec 27 2 2
- 8049 8039 2K/4K 128 1.36 fiSec 27 2 2
8751 8051 8031 4K/64K 128 1. 0 IJ Sec 32 5 4
AFN-01502A
B2
APPLICATIONS
a single character, and a word or sequence of letters may

The letters "MCS" have traditionally indicated be represented by a series (or "string") of bytes. Since the
a system or family of compatible Intel micro- ASCII code only uses 128 characters, the most significant
computer components, including CPUs, mem- bit of the byte is not needed to distinguish between char-
ories, clock generators, I/O expanders, and so acters. Often D7 is set to 0 for all characters. In some
forth. The numerical suffix indicates the micro- coding schemes, D7 is used to indicate the "parity" of the
processor or microcomputer which serves as other seven bits-set or cleared as necessary to ensure
the cornerstone of the family. Microcomputers that the total number of "I" bits in the eight-bit code is
in the MCS-48T11 family currently include the even ("even parity") or odd ("odd parity"). The 8051
8048-series (8035, 8048, & 8748), the 8049-series includes hardware to compute parity when it is needed.
(8039 & 8049), and the 8021 and 8022; the
A computer program consists of an ordered sequence of
family also includes the 8243, an I/O expander
specific, simple steps to be executed by the CPU one-at-
compatible with each of the microcomputers.
a-time. The method or sequence of steps used collectively
Each computer's CPU is derived from the 8048,
to solve the user's application is called an "algorithm."
with essentially the same architecture, address-
ing modes, and instruction set, and a single The program is stored inside the computer as a sequence
assembler (ASM48) serves each. of binary numbers, where each number corresponds to
one of the basic operations ("opcodes") which the CPU
The first members of the MCS-51T11 family are is capable of executing. In the 8051, each program
the 8051, 8751, and 8031. The architecture of memory location is one byte. A complete instruction
the 8051-series, while derived from the 8048, consists of a sequence of one or more bytes, where the
is not strictly compatible; there are more first defines rhe operation to be executed and additional
addressing modes, more instructions, larger bytes (if needed) hold additional information, such as
address spaces, and a few other hardware dif- data values or variable addresses. No instruction is longer
ferences. In this Application Note the letters than three bytes.
"MCS-51" are used when referring to archi-
tectural features of the 8051-'series-features The way in which binary opcodes and modifier bytes are
which would be included on possible future assigned to the CPU's operations is called the computer's
microcomputers based on the 8051 CPU. Such "machine language." Writing a program directly in
products could have different amounts of machine language is time-consuming and tedious. Human
memory (as in the 8048/8049) or different beings think in words and concepts rather than encoded
peripheral functions (as in the 8021 and 8022) numbers, so each CPU operation and resource is given a
while leaving the CPU and instruction set name and standard abbreviation ("mnemonic"). Programs
intact. ASM51 is the assembler used by all are more easily discussed using these standard mnemonics,
microcomputers in the 8051 family. or "assembly language," and may be typed into an Intel
Intellec 800 or Series II microcomputer development
system in this form. The development system can mechan-
ically translate the program from assembly language
"source" form to machine language "object" code using a
Two digit decimal numbers may be "packed" in an eight- program called an "assembler." The MCS_5ITM assembler
bit value, using four bits for the binary code of each digit.
is called AS M51.
This is called Binary-Coded Decimal (BCD) representa-
tion, and is often used internally in programs which There are several important differences between a com-
interact heavily with human beings. puter's machine language and the assembly language used
as a tool to represent it. The machine language or instruc-
Alphanumeric characters (letters, numbers, punctuation tion set is the set of operations which the CPU can
marks, etc.) are often represented using the American perform while a program is executing ("at run-time"), and
Standard Code for Information Interchange (ASCII)
is strictly determined by the microcomputer hardware
convention. Each character is associated with a unique
design.
seven-bit binary number. Thus one byte may represent
The assembly language is a standard (though more-or-
less arbitrary) set of symbols including the instruction set
mnemonics, but with additional features which further
07 06 05 04 03 02 01 DO simplify the program design process. For example,
ASM51 has controls for creating and formatting a pro-
Figure 2. Representation of Bits Within an Eight-Bit gram listing, and a number of directives for allocating
"Byte" (Value shown = 01010001 Binary = variable storage and inserting arbitrary bytes of data into
81 decimal). the object code for creating tables of constants.
AFN-01S02A
B3
APPLICATIONS
In addition, ASM51 can perform sophisticated mathe- assembly language by a series of ones and zeros
matical operations, computing addresses or evaluating (naiuraiiy), foHowed by the ietter "B" (for Binary); octal
arithmetic expressions to relieve the programmer from numbers as a series of octal digits (0-7) followed by the
this drudgery. However, these calculations can only use letter "0" (for Octal) or "Q" (which doesn't stand for any-
information known at "assembly time." thing, but looks sort of like an "0" and is less likely
to be confused with a zero).
For example, the 8051 performs arithmetic calculations
at run-time, eight bits at a time. ASM51 can do similar Hexadecimal numbers are represented by a series of hexa-
operations 16 bits at a time. The 8051 can only do one decimal digits (0-9,A-F), followed by (you guessed it) the
simple step per instruction, while ASM51 can perform letter "H." A "hex" number must begin with a decimal
complex calculations in each line of source code. How- digit; otherwise it would look like a user-defined symbol
ever, the operations performed by the assembler may only (to be discussed later). A "dummy" leading zero may be
use parameter values fixed at assembly-time, not variables inserted before the first digit to meet this constraint. The
whose values are unknown until program execution character string "BACH" could be a legal label for a
begins. Baroque music synthesis routine; the string "OBACH" is
the hexadecimal constant BAC I6 This is a case where
For example, when the assembly language source line,
adding 0 makes a big difference.
ADD A,#(LOOP_COUNT + I) *3
Decimal numbers are represented by a sequence of decimal
is assembled, AS M51 will find the value of the pre- digits, optionally followed by a "D." If a number has no
viously-defined constant "LOOP_COUNT" in an internal suffix, it is assumed to be decimal-so it had better not
symbol table, increment the value, multiply the sum by contain any non-decimal digits. "OBAC" is not a legal
three, and (assuming it is between -256 and 255 inclusive) representation for anything.
truncate the product to eight bits. When this instruction
When an ASCII code is needed in a program, enclose the
is executed, the 8051 ALU will just add that resulting
constant to the accumulator. desired character between two apostrophes (as in '#') and
the assembler will convert it to the appropriate code (in
Some similar differences exist to distinguish number this case 23H). A string of characters between apos-
system ("radix") specifications. The 8051 does all com- trophes is translated into a series of constants; 'BACH'
putations in binary (though there are provisions for then becomes 42H, 41 H, 43H, 48H.
converting the result to decimal form). In the course of
These same conventions are used throughout the asso-
writing a program, though, it may be more convenient
ciated Intel documentation. Table 2 illustrates some of the
to specify constants using some other radix, such as base
different number formats.
Hr. On other occasions, it is desirable to specify the ASCII
code for some character or string of characters without 2. ARCHITECTURE AND ORGANIZATION
refering to tables. ASM51 allows several representations Figure 3 blocks out the MCS_5ITM internal organization.
for constants, which are converted to binary as each
Each microcomputer combines a Central Processing
instruction is assembled.
Unit, two kinds of memory (data RAM plus program
For example, binary numbers are represented in the ROM or EPROM), Input/ Output ports, and the mode,
Table 2. Notations Used to Represent Numbers
Hexa- Signed
Bit Pattern Binary Octal Decimal Decimal Decimal
00000000 OB OQ OOH 0 0
o0 0
0 000 1 IB IQ OIH I +1
............... .. . .. . .. ., ....
00000111 IIIB 7Q 07H 7 +7
o0 0 0 1 000 1000B IOQ 08H 8 +8
o000 100 1 lOOIB llQ 09H 9 +9
o0 0 0 1 0 1 0 10 lOB 12Q OAH 10 +10
............... .. . .. ... .. . ...
o0 0
0 1 1 1 1 I11IB 17Q OFH 15 +15
00010000 lOOOOB 20Q IOH 16 +16
........ ......
~ .. . .. ... .. . ...
o1111111 IIIIIIIB 177Q 7FH 127 +127
10000000 10000000B 200Q 80H 128 -128
10000001 1000000lB 20lQ 81H 129 -127
............... ........ ... . .. .. , '0'
1 1 1 1 1 1 1 0 1IIIll1OB 376Q OFEH 254 -2

1 1 1 1 1 1 1 1 IIIIIIIIB 377Q OFFH 255 -I
AFN01502A
8-4
APPLICATIONS
TL1
TH1
TIMER
CONTROL
Figure 3. Block Diagram of 8051 Internal Structure
status, and data registers and random logic needed for

a variety of peripheral functions. These elements com-
municate through an eight-bit data bus which runs
throughout the chip, somewhat akin to indoor plumbing.
This bus is buffered to the outside world through an I/O
port when memory or I/O expansion is desired.
Let's summarize what each block does; later chapters dig
into the CPU's instruction set and the peripheral registers
in much greater detail.
Central Processing Unit

The CPU is the "brains" of the microcomputer, reading
the user's program and executing the instructions stored
therein. Its primary elements are an eight-bit Arithmetic/
Logic Unit with associated registers A, B, PSW, and SP,
and the sixteen-bit Program Counter and "Data Pointer"
registers.
AFN-01502A
8-5
APPLICATIONS
Arithmetic Logic Unit Arithmetic Operations

The ALU can perform (as the name implies) arithmetic Logical Oper~tions for Byte Variables
and logic functions on eight-bit variables. The former Data Transfer Instructions
include basic addition, subtraction, multiplication, and Boolean Variable Manipulation
division; the latter include the logical operations AND, Program Branching and Machine Control
OR, and Exclusive-OR, as well as rotate, clear, comple-
MCS:''48 programmers perusing Table 4 will notice the
ment, and so forth. The ALU also makes conditional
absence of special categories for Input/Output, Timer/
branching decisions, and provides data paths and tem-
Counter, or Control instructions. These functions are all
porary registers used for data transfers within the system.
still provided (and indeed many new functions are added),
Other instructions are built up from these primitive func-
but as special cases of more generalized operations in
tions: the addition capability can increment registers or
other categories. To explicitly list all the useful instruc-
automatically compute program destination addresses;
tions involving I/O and peripheral registers would require
subtraction is also used in decrementing or comparing the
a table approximately four times as long.
magnitude of two variables.
Observant readers will also notice that all of the 8048's
These primitive operations are automatically cascaded
page-oriented instructions (conditional jumps, JMPP,
and combined with dedicated logic to build complex
MOVP, MOVP3) have been replaced with corresponding
instructions such as incrementing a sixteen-bit register
but non-paged instructions. The 8051 instruction set is
pair. To execute one form of the compare instruction, for
entirely non-page-oriented. The MCS-48 "MOVP"
example, the 8051 increments the program counter three
instruction replacement and all conditional jump instruc-
times, reads three bytes of program memory, computes a
tions operate relative to the program counter, with the
register address with logical operations, reads internal
actual jump address computed by the CPU during instruc-
data memory twice, makes an arithmetic comparison of
tion execution. The "MOVP3" and "JMPP" replacements
two variables, computes a sixteen-bit destination address,
are now made relative to another sixteen-bit register,
and decides whether or not to make a branch-all in two
which allows the effective destination to be anywhere in
microseconds!
the program memory space, regardless of where the
An important and unique feature of the MCS-51 archi- instruction itself is located. There are even three-byte
tecture is that the ALU can also manipulate one-bit as jump and call instructions allowing the destination to be
well as eight-bit data types. Individual bits may be set, anywhere in the 64K program address space.
cleared, or complemented, moved, tested, and used in
logic computations. While support for a more primitive The instruction set is designed to make programs efficient
data type may initially seem a step backwards in an era both in terms of code size and execution speed. No
of increasing word length, it makes the 8051 especially instruction requires more than three bytes of program
well suited for controller-type applications. Such algo- memory, with the majority requiring only one or two
rithms inherently involve Boolean (true/false) input bytes. Virtually all instructions execute in either one or
and output variables, which were heretofore difficult to two instruction cycles-one or two microseconds. with
implement with standard microprocessors. These features a 12-MHz crystal-with the sole exceptions (multiply
are collectively referred to as the MCS-51 "Boolean and divide) completing in four cycles.
Processor," and are described in the so-named chapter Many instructions such as arithmetic and logical func-
to come. tions or program control, provide both a short and a long
Thanks to this powerful ALU, the 8051 instruction set form for the same operation, allowing the programmer
fares well at both real-time control and data intensive to optimize the code produced for a specific application.
algorithms. A total of 51 separate operations move and The 8051 usually fetches two instruction bytes per instruc-
manipulate three data types: Boolean (I-bit), byte (8-bit), tion cycle, so using a shorter form can lead to faster
and address (l6-bit). All told, there are eleven addressing execution as well.
modes-seven for data, four for program -;equence con- For example, any byte of RAM may be loaded with a
trol (though only eight are used by more than just a few constant with a three-byte, two-cycle instruction, but the
specialized instructions). Most operations allow several commonly used "working registers" in RAM may be
addressing modes, bringing the total number of instruc- initialized in one cycle with fl two-byte form. Any bit
tions (operation/addressing mode combinations) to Ill, anywhere on the chip may be set, cleared, or comple-
encompassing 255 of the 256 possible eight-bit instruc- mented by a single three-byte logical instruction using
tion opcodes. two cycles. But critical control bits, I/O pins, and soft-
ware flags may be controlled by two-byte, single cycle
Instruction Set Overview instructions. While three-byte jumps and calls can "go
Table 4 lists these III instructions classified into five anywhere" in program memory, nearby sections of code
groups: may be reached by shorter relative or absolute versions.
AFN-01S02A
8-6
APPLICATIONS
(MSB) (LSB)
Symbol Position Name and Significance
I I
CY AC FO RS1 RSO OV
I Ip
OV PSW.2 Overflow flag.
Set/cleared by hardware during arith-
Symbol Position Name and Significance metic instructions to indicate overflow
CY PSW.7 Carry flag. conditions.
Set/cleared by hardware or software
during certain arithmetic and logical PSW.I (reserved)
instructions.
P PSW.O Parity flag.
AC PSW.6 Auxiliary Carry flag. Set/cleared by hardware each instruc-
Set/cleared by hardware during addition tion cycle to indicate an odd/even
or subtraction instructions to indicate number of "one" bits in the accumu-
carry or borrow out of bit 3. lator, i.e., even parity.
FO PSW.5 Flag 0 Note- the contents of (RSI, RSO) enable the

Set / cleared / tested by software as a working register banks as follows:
user-defined status flag.
(O,O)-Bank 0 (DOH-07H)
RSI PSW.4 Register bank Select control bits I & O. (O,I)-Bank I (OSH-OFH)
Set/cleared by software to determine (I ,D)-Bank 2 (IOH-I7H)
RS PSW.3 working register bank (see Note). (I,I)-Bank 3 (ISH-IFH)
Figure 4. PSW-Program Status Word' Organization
A significant side benefit of an instruction set more and rotates. The carry also serves as a "Boolean accumu-
powerful than those of previous single-chip microcom- lator" for one-bit logical operations anp bit manipulation
puters is that it is easier to generate applications-oriented instructions. The overflow flag (OV) detects when arith-
software. Generalized addressing modes for byte and bit metic overflow occurs on signed integer operands, making
instructions reduce the number of source code lines two's complement arithmetic possible. The parity flag
written and debugged for a given application. This leads (P) is updated after every instruction cycle with the even-
in turn to proportionately lower software costs, greater parity ()f the accumulator contents.
reliability, and faster design cycles.
The CPU does not control the two register-bank select
bits, RS I and RSO. Rather, they are manipulated by
Accumulator and PSW software to enable one of the four register banks. The
The 8051, like its 8048 predecessor, is primarily an usage of the PS W flags is demonstrated in the Instruc-
accumulator-based architecture: an eight-bit register tion Set chapter of this Note.
called the accumulator ("A") holds a source operand and Even though the architecture is accumulator-based, pro-
receives the result of the arithmetic instructions (addition, visions have been made to bypass the accumulator in
subtraction, multiplication, and division). The accumula- common instruction situations. Data may be moved from
tor can be the source or destination for logical operations any location on-chip to any register, address, or indirect
and a number of special data movement instructions, address (and vice versa), any register may be loaded with
including table look-ups and external RAM expansion. a constant, etc., all without affecting the accumulator.
Several functions apply exclusively to the accumulator: Logical operations may be performed against registers or
rotates, parity computation, testing for zero, and so on. variables to alter fields of bits-without using or affecting
Many instructions implicitly or explicitly affect (or are the accumulator. Variables may be incremented, decre-
affected by) several status flags, which are grouped mented, or tested without using the accumulator. Flags
together to form the Program Status Word shown in and control bits may be manipulated and tested without
FIgure 4. affecting anything else.
(The period within entries under the Position column is

called the "dot operator," and indicates a particular bit Other CPU Registers
position within an eight-bit byte. "PSW.5" specifies bit 5 A special eight-bit register ("B")'serves in the execution of
of the PSW. Both the documentation and ASM51 use the multiply and divide instructions. This register is used
this notation.) in conjunction with the accumulator as the second input
The most "active" status bit is called the carry flag (abbre- operand and to return eight-bits of the result.
viated "C"). This bit makes possible multiple precision The MCS-51 family processors include a hardware stack
arithmetic operations including addition, subtraction, within internal RAM, useful' for subroutine linkage,
AFN-01502A
8-7
APPLICATIONS
passing parameters between routines, temporary variable are addressed using the Program Counter or instructions
storage, or saving status during interrupt service routines. which generate a sixit:t::n-bit address.
The Stack Pointer (SP) is an eight-bit pointer register
To stretch our analogy just a bit, data memory is like a
which indicates the address of the last byte pushed onto
mouse: it is smaller and therefore quicker than program
the stack. The stack pointer is automatically incremented
memory, and it goes into a random state when electrical
or decremented on all push or pop instructions and all
power is applied. On-chip data RAM is used for variables
subroutine calls and returns. In theory, the stack in the
which are determined or may change while the program
8051 may be up to a full 128 bytes deep. (In practice, even
is running.
simple programs would use a handful of RAM locations
for pointers, variables, and so forth-reducing the stack A computer spends most of its time manipulating vari-
depth by that number.) The stack pointer defaults to 7 on ables, not constants, and a relatively small number of
reset, so that the stack will start growing up from location variables at that. Since eight-bits is more than sufficient
8, just like in the 8048. By altering the pointer contents the to uniquely address 128 RAM locations, the on-chip
stack may be relocated anywhere within internal RAM. RAM address register is only one byte wide. In contrast
to the program memory, data memory accesses need a
Finally, a 16-bit register called the data pointer (DPTR) single eight-bit value-a constant or another variable-
serves as a base register in indirect jumps, table look-up to specify a unique location. Since this is the basic width
instructions, and external data transfers. The high- and of the ALU and the different memory types, those
low-order halves of the data pointer may be manipulated resources can be used by the addressing mechanisms,
as separate registers (DPH and DPL, respectively) or contributing greatly to the computer's operating efficiency.
together using special instructions to load or increment
all sixteen bits. Unlike the 8048, look-up tables can there- The partitioning of program and data memory is extended
fore start anywhere in program memory and be of to off-chip memory expansion. Each may be added
arbitrary length. independently, and each uses the same address and data
busses, but with different control signals. External pro-
gram memory is gated onto the external data bus by the
PSEN (Program Store Enable) control output, pin 29.
External data memory is read onto the bus by the RD
output, pin 17, and written with data supplied from the
microcomputer by the WR output, pin 16. (There is no
control pin to write external program ROM, which is by
definition Read Only.) While both types may be expanded
to up to 64K bytes, the external data memory may
optionally be expanded in 256 byte "pages" to preserve
the use of P2 as an I/O port. This is useful with a relatively
small expansion RAM (such as the Intel 8155) or for
addressing external peripherals.
Single-chip controller programs are finalized during the
project design cycle, and are not modified after produc-
tion. Intel's single-chip microcomputers are not "von
Neumann" architectures common among main-frame
and mini-computer systems: the MCS-5ITM processor
data memory-on-chip and external-may not be used
for program code. Just as there is no write-control signal
Memory Spaces for program memory, there is no way for the CPU to
Program memory is separate and distinct from data execute instructions out of RAM. In return, this con-
memory. Each memory type has a different addressing cession allows an architecture optimized for efficient
mechanism, different control signals, and a different controller applications: a large, fixed program located in
function. ROM, a hundred or so variables in RAM, and different
methods for efficiently addressing each.
The program memory array (ROM or EPROM), like an
elephant, is extremely large and never forgets informa- (Von Neumann machines are helpful for software develop-
tion, even when power is removed. Program memory is ment and debug. An 8051 system could be modified to
used for information needed each time power is applied: have a single off-chip memory space by gating together
initialization values, calibration constants, keyboard the two memory-read controls (PSEN and RD) with a
layout tables, etc., as well as the program itself. The pro- two-input AND gate (Figure 5). The CPU could then
gram memory has a sixteen-bit address bus; its elements write data into the common memory array using WR and
AFN-01S02A
8-8
APPLICATIONS
8051 WI! ~ J.fE'MWR} TO

MEMORY
L..-_ _ _I5"'EliI_Im...... MEM RD ARRAY
Figure 5. Combining External Program and Data

Memory Arrays
external data transfer instructions, and read instructions

or data with the AND gate output and data transfer or
program memory look-up instructions.)
In addition to the memory arrays, there is (yet) another
(albeit sparsely populated) physical address space. Con-
nected to the internal data bus are a score of special-
purpose eight-bit registers scattered throughout the chip.
Some of these-B, SP, PSW, DPH, and DPL-have
been discussed above. Others-I/O ports and peripheral
function registers-will be introduced in the following
sections. Collectively, these registers are designated as the
"special-function register" address space. Even the accu-
mulator is assigned a spot in the special-function register
Input/Output Ports
address space for additional flexibility and uniformity.
The MCS-51'M I/O port structure is extremely versatile.
Thus, the MCS-5I architecture supports several distinct The 8051 and 8751 each have 32 I/O pins configured as
"physical" address spaces, functionally separated at the four eight-bit parallel ports (PO, PI, P2, and P3). Each pin
hardware level by different addressing mechanisms, read will input or output data (or both) under software con-
and write control signals, or both: trol, and each may be referenced by a wide repertoire of
On-chip program memory; byte and bit operations.
On-chip data memory;
Off-chip program memory; In various operating or expansion modes, some of these
Off-chip data memory; I/O pins are also used for special input or output func-
On-chip special-function registers. tions. Instructions which access external memory use
Port 0 as a multiplexed address/data bus: at the beginning
What the programmer sees, though, are "logical" address of an external memory cycle eight bits of the address are
spaces. For example, as far as the programmer is output on PO; later data is transferred on the same eight
concerned, there is only one type of program memory, pins. External data transfer instructions which supply
64K bytes in length. The fact that it is formed by com- a sixteen-bit address, and any instruction accessing
bining on- and off-chip arrays (split 4K/60K on the 8051 external program memory, output the high-order eight
and 8751) is "invisible" to the programmer; the CPU bits on P2 during the access cycle. (The 8031 always uses
automatically fetches each byte from the appropriate the pins of PO and P2 for external addressing, but PI and
array, based on its address. P3 are available for standard I/O.)
(Presumably, future microcomputers based on the The eight pins of Port 3 (P3) each have a special function.
MCS_5ITM architecture may have a different physical split, Two external interrupts, two counter inputs, two serial
with more or less of the 64K total implemented on-chip. data lines, and two timing control strobes use pins of P3
Using the MCS-48 family as a precedent, the 8048's 4K as described in Figure 6. Port 3 pins corresponding to
potential program address space was split I K/ 3K between functions not used are available for conventional I/O.
on- and off-chip arrays; the 8049's was split 2K/2K.)
Even within a single port, I/O functions may be combined
Why go into such tedious details about address spaces? in many ways: input and output may be performed using
The logical addressing modes are described in the Instruc- different pins at the same time, or the same pins at different
tion Set chapter in terms of physical address spaces. times; in parallel in some cases, and in serial in others; as
Understanding their differences now will payoff in under- test pins, or (in the case of Port 3) as additional special
standing and using the chips later. functio"ns.
AFN-01502A
B-9
APPLICATIONS
(MSB) (LSB)
I RD I WR T1 TO IINT1 I INTO I TXD I RXD I

Symbol Position Name and Significance Symbol Position Name and Significance
RD P3.7 Read data control output. Active low INTI P3.3 Interrupt I input pin. Low-level or
pulse generated by hardware when falling-edge triggered.
external data memory is read.
INTO P3.2 Interrupt 0 input pin. Low-level or
WR P3.6 Write data control output. Active low faUing-edge triggered.
pulse generated by hardware when
external data memory is written. TXD P3.1 Transmit Data pin for serial port in
UART mode. Clock output in shift
Tl P3.5 Timer/counter I external input or test register mode.
pin.
RXD P3.0 Receive Data pin for serial port in
TO P3.4 Timer/counter 0 external input or test UART mode. Data I/O pin in shift
pin. register mode. .
Figure 6. P3-Alternate Special Functions of Port 3
software-accessible). These registers are called, naturally

enough, THO, TLO, THI, and TLl. Each pair may be
independently software programmed to any of a dozen
modes with a mode register designated TMOD (Figure
7), and controlled with register TCON (Figure 8).
The timer modes can be used to measure time intervals,
determine pulse widths, or initiate events, with one-micro-
second resolution, up to a maximum interval of 65,536
instruction cycles (over 65 milliseconds). Longer delays
may easily be accumulated through software. Configured
as a counter, the same hardware will accumulate external
events at frequencies from D.C. to 500 KHz, with up to
sixteen bits of precision.
Serial Port Interface

Each microcomputer contains a high-speed, full-duplex,
serial port which is software programmable to function
in four basic modes: shift-register I/O expander, 8-bit
Special Peripheral Functions UART, 9-bit UART, or interprocessor communications
There are a few special needs common among control- link. The UART modes will interface with standard I/O
oriented computer systems: devices (e.g. CRTs, teletypewriters, or modems) at data
keeping track of elapsed real-time; rates from 122 baud to 31 kilobaud. Replacing the
maintaining a count of signal transitions; standard 12 MHz crystal with a 10.7 MHz crystal allows
measuring the precise width of input pulses; 110 baud. Even or odd parity (if desired) can be included
communicating with other systems or people; with simple bit-handling software routines. Inter-processor
closely monitoring asynchronous external events. communications in distributed systems takes place at 187
kilobaud with hardware for automatic address/data
Until now, microprocessor systems needed peripheral message recognition. Simple TTL or CMOS shift registers
chips such as timer/counters, USARTs, or interrupt con- provide low-cost I/O expansion at a super-fast I Mega-
trollers to meet these needs. The 8051 integrates all of baud. The serial port operating modes are controlled by
these capabilities on-chip! the contents of register SCON (Figure 9).
Timer/Counters Interrupt Capability and Control

There are two sixteen-bit multiple-mode Timer/Counters '(Interrupt capability is generally considered a CPU
on the 8051, each consisting of a "High" byte (correspond- function. It is being introduced here since, from an appli-
ing to the 8048 "T" register) and a low byte (similar to the cations point of view, interrupts relate more closely to
8048 prescaler, with the additional flexibility of being peripheral and system interfacing.)
AFN-01502A
8-10
APPLICATIONS
M1 MO Operating Mode
I I I
GATE CIT M1 MO I I I
GATE CIT M1 MO I o o MCS-48 Timer. "TLx" serves as five-
\~------., ~----"I\~---.. ~_ _----") bit prescaler.
TIMER 1 TIMER 0
o 16-bit timer/counter. "THx" and "TLx"

are cascaded; there is no prescaler.
o 8-bit auto-reload timer/counter. "THx"

holds a value which is to be reloaded
GATE Gating control. When set, Timer/counter into "TLx" each time it overflows.
"x" is enabled only while "INTx" pin is
high and "TRx" control bit is set. When (Timer 0) TLO is an eight-bit timer/
cleared, timer/counter is enabled counter controlled by the
whenever "TRx" control bit is set. standard Timer 0 control
bits.
CiT Timer or Counter Selector. Cleared for THO is an eight-bit timer
Timer operation (input from internal only controlled by Timer I
system clock). Set for Counter opera- control bits.
tion (input from "Tx" input pin).
(Timer I) Timer/counter I stopped.
Figure 7. TMOD-Timer/Counter Mode Register
(MSB) (lSB)
I TF1 I TR1 I TFO TRO IE1 IT1 lEO I ITO
Symbol Position Name and Significance

Symbol Position Name and Significance lEI TCON.3 Interrupt I Edge flag. Set by hardware
TFI TCON.7 Timer I overflow Flag. Set by hardware when external interrupt edge detected.
on timer/counter overflow. Cleared Cleared when interrupt processed.
when interrupt processed.
ITI TCON.2 Interrupt I Type control bit. Set/cleared
TRI TCON.6 Timer I Run control bit. Set/cleared by software to specify falling edge/low
by software to turn timer/counter level triggered external interrupts.
on/off.
lEO TCON.I Interrupt 0 Edge flag. Set by hardware
TFO TCON.5 Timer 0 overflow Flag. Set by hardware when external interrupt edge detected.
on timer/counter overflow. Cleared Cleared when interrupt processed.
when interrupt processed.
ITO TCON.O Interrupt 0 Type control bit. Set/cleared
TRO TCON.4 Timer 0 Run control bit. Set/cleared by by software to specify falling edge/low
software to turn timer/counter on/off. level triggered external interrupts.
Figure 8. TCON-Timer/Counter Control/Status Register
AFN01502A
8-11
APflLlCATIONS
(MSB) (LSB)
I I I I I I I I I
SMO SM1 SM2 REN TBB RBB TI RI
SMO SCON.7 Serial port Mode control bit O. RB8 SCON.2 Receive Bit 8. Set/cleared by hardware
Set/cleared by software (see note). to indicate state of ninth data bit
received.
SMI SCON.6 Serial port Mode control bit I.
Set/cleared by software (see note). TI SCON.I Transmit Interrupt flag. Set by hard-
ware when byte transmitted. Cleared
SM2 SCON.S Serial poft Mode control bit 2. Set by by software after servicing.
software to disable reception of frames
for which bit 8 is zero. RI SCON.O Received Interrupt flag. Set by hard-
ware when byte received. Cleared by
REN SCON.4 Receiver Enable control bit. Set/cleared software after servicing.
by software to enable/disable serial
data reception. Note- the state of (SMO,SM I) selects:
(O,O)-Shift register I/O expansion.
TB8 SCON.3 Transmit Bit 8. Set/cleared by hard- (0,1)-8 bit VART, variable data rate.
ware to determine state of ninth data (1,0)-9 bit VART, fixed data rate.
bit transmitted in 9-bit UART mode. (1,1)-9 bit VART, variable data rate.
Figure 9. SCON-~erial Port Control/Status Register
These peripheral functions allow special hardware to background task long enough to handle the appropriate
monitor real-time signal interfacing without bothering device, then return to the point where it left off.
the CPU. For example, imagine serial data is arriying from This is the basis of the third and generally optimal solu-
one CRT while being transmitted to another, and one tion, hardware interrupts. The 8051 has five interrupt
timer/counter is tallying high-speed input transitions sources: one from the serial port when a transmission or
while the other measures input pulse widths. During all reception is complete, two from the timers when over-
of this the CPU is thinking about something else. flows occur, and two from input pins INTO and INTI.
But how does the CPU know when a reception, transmis- Each source may be independently enabled or disabled
sion, count, or pulse is finished? The 8051 programmer to allow polling on some sources or at some times, and
can choose from three approaches. each may be. classified as high or low priority. A high
priority source can interrupt a low priority service
TCON and SCON contain status bits set by the hardware routine; the manager's boss can interrupt conferences
when a timer overflows or a serial port operation is com- with subordinates. These options are selected by the inter-
pleted. The first technique reads the control register into rupt enable and priority control registers, IE and IP
the accumulator, tests the appropriate bit, and does a (Figures 10 and II).
conditional branch based on the result. This "polling"
Each source has a particular program memory address
scheme (typically a three-instruction sequence though
associated with it (Table 3), starting at 0003H (as in the
additional instructions to save and restore the accu-
8048) and continuing at eight-byte intervals. When an
mulator may sometimes be needed) will surely be
event enabled for interrupts occurs the CPU automatically
familiar to programmers used to multi-chip microcom-
executes an internal subroutine call to the corresponding
puter systems and peripheral controller chips. This
process is rather cumbersome, especially when monitoring address. A user 'subroutine starting at this location (or
jumped to from this location) then performs the instruc-
multiple peripherals.
tions to service that particular source. After completing
As a second approach, the 8051 can perform conditional a the interrupt service routine, execution returns to the
branch based on the state of any control or status bit or background program.
input pin in a single instruction; a four instruction
sequence could poll the four simultaneous happenings Table 3. 8051 Interrupt Sources and Service Vectors
mentioned above in just eight microseconds.
Interrupt Service Routine
Unfortunately, the CPU must still drop what it's doing Source Starting Address
to test these bits. A manager cannot do his own work
(Reset) OOOOH
well if he is continuously monitoring his subordinates; External 0 0OO3H
they should interrupt him (or her) only when they need Timer/ Counter 0 OOOBH
attention or guidance. So it is with machines: ideally, the External I OOl3H
CPU would not have to worry about the peripherals until Timer/ Counter I OOIBH
Serial Port 0023H
they require servicing. At that time, it would postpone the
AFN01502A
8-12
APPLICATIONS
(MSB) (LSB)
I EA I ES ET1 EX1 ETO I I

EXO
EA IE.7 Enable All control bit. Cleared by EXI IE.2 Enable External interrupt I control bit.
software to disable all interrupts, Set/cleared by software to enable/
independent of the state of IEA-IE.O. disable interrupts from INTI.
IE.6 (reserved) ETO lE.I Enable Timer 0 control bit. Set/cleared

IE.5 (reserved) by software to enable/disable interrupts
from timer/counter 0
ES lEA Enable Serial port control bit.
Set/cleared by software to enable/ EXO IE.O Enable External interrupt 0 control bit.
disable interrupts from TI or RI flags. Set/cleared by software to enable/
disable interrupts from INTO.
ETI IE.3 Enable Timer I control bit. Set/cleared
by software to enable/disable interrupts
from timer/counter I.
Figure 10. IE-Interrupt Enable Register
(MSB) (LSB)
I- I PS PT1 PX1 PTO I I

PXO
IP.7 (reserved) PX I IP.2 External interrupt I Priority control
IP.6 (reserved) bit. Set/cleared by software to specify
IP.5 (reserved) high/ low priority interrupts for INTI.
PS IPA Serial port Priority control bit. PTO IP.I Timer 0 Priority control bit.
Set/cleared by software to specify Set/cleared by software to specify
high/ low priority interrupts for Serial high/low priority interrupts for
port. timer/counter O.
PTI IP.3 Timer I Priority control bit. PXO IP.O External interrupt 0 Priority control
Set/cleared by software to specify bit. Set/cleared by software to specify
highjlow priority interrupts for highjlow priority interrupts for INTO.
timer/counter I.
Figure 11. IP-Interrupt Priority Control Register
AFN-01502A
B-13
APPLICATIONS
Table 4. MCS-S1TM Instruction Set Description
ARITHMETIC OPERATIONS DATA TRANSFER (cont.)

Mnemonic Description Byte Cyc Mnemonic Description Byte Cyc
ADD A.Rn Add register to Accumulator I I MOVC A.@A+DPTR Move Code byte relative to DPTR to A I 2
ADD A.direct Add direct byte to Accumulator 2 I MOVC A.@A+PC Move Code byte relative to PC to A I 2
ADD A.@Ri Add indirect RAM to Accumulator I I MOVX A.@Ri Move External RAM (8-bit addr) to A I 2
ADD A.#data Add immediate data to Accumulator 2 I MOVX A.@DPTR Move External RAM (16-bit addr) to A I 2
ADDC A.Rn Add register to Accumulator with Carry I I MOVX @Ri.A Move A to External RAM (8-bit addr) I 2
ADDC A.direct Add direct byte to A with Carry flag 2 I MOVX @DPTR.A Move A to External RAM (16-bit addr) I 2
ADDC A.@Ri Add indirect RAM to A with Carry flag I I PUSH direct Push direct byte onto stack 2 2
ADDC A.#data Add immediate data to A with Carry flag 2 I POP direct Pop direct byte from stack 2 2
SUBB A.Rn Subtract register from A with Borrow I I XCH A.Rn Exchange register with Accumulator I I
SUBB A.direct Subtract direct byte from A with Borrow 2 I XCH A.direct Exchange direct byte with Accumulator 2 I
SUBB A.@Ri Subtract indirect RAM from A w/Borrow I I XCH A.@Ri Exchange indirect RAM with A I I
SUBB A.#data Subtract immed. data from A w/ Borrow 2 I XCHD A.@Ri Exchange low-order Digit indo RAM w/ A I I
INC A Increment Accumulator I I
INC Rn Increment register I I BOOLEAN VARIABLE MANIPULATION
INC direct I ncrement direct byte 2 I
INC @Ri Increment indirect RAM I I Mnemonic Description Byte Cyc
DEC A Decrement Accumulator I I CLR C Clear Carry flag I I
DEC Rn Decrement register I I CLR bit Clear direct bit 2 I
DEC direct Decrement direct byte 2 I SETB C Set Carry flag I I
DEC @Ri Decrement indirect RAM I I SETB bit Set direct Bit 2 I
INC DPTR Increment Data Pointer I 2 CPL C Complement Carry flag I I
MUL AB Multiply A & B I 4 CPL bit Complement direct bit 2 I
DIV AB Divide A by B I 4 ANL C.bit AND direct bit to Carry flag 2 2
DA A Decimal Adjust Accumulator I I ANL C./bit AND complement of direct bit to Carry 2 2
ORL C.bit OR direct bit to Carry flag 2 2
LOGICAL OPERATIONS ORL C./bit OR complement of direct bit to Carry 2 2
MOV C.bit Move direct bit to Carry flag 2 I
Mnemonic Destination Byte Cyc MOV bit.C Move Carry flag to direct bit 2 2
ANL A.Rn AND register to Accumulator I I
ANL A.direct AND direct byte to Accumulator 2 I PROGRAM AND MACHINE CONTROL
ANL A.@Ri AND indirect RAM to Accumulator I I
ANL A.#data AND immediate data to Accumulator 2 I Mnemonic Description Byte Cyc
ANL direct.A AND Accumulator to direct byte 2 I ACALL addrll Absolute Subroutine Call 2 2
ANL direct.#data AND immediate data to direct byte 3 2 LCALL addrl6 Long Subroutine Call 3 2
ORL A.Rn OR register to Accumulator I I RET Return from subroutine I 2
ORL A.direct OR direct byte to Accumulator 2 I RET! Return from interrupt I 2
ORL A.@Ri OR indirect RAM to Accumulator I I AJMP addrll Absolute Jump 2 2
ORL A.#data OR immediate data to Accumulator 2 I LJMP addrl6 Long Jump 3 2
ORL direct.A OR Accumulator to direct byte 2 I SJMP rei Short Jump (relative addr) 2 2
ORL direct.#data OR immediate data to direct byte 3 2 JMP @A+DPTR Jump indirect relative to the DPTR I 2
XRL A.Rn Exclusive-OR register to Accumulator I I JZ rei Jump if Accumulator is Zero 2 2
XRL A.direct Exclusive-OR direct byte to Accumulator 2 I JNZ rei Jump if Accumulator is Not Zero 2 2
XRL A.@Ri Exclusive-OR indirect RAM to A I I JC rei Jump if Carry flag is set 2 2
XRL A.#data Exclusive-OR immediate data to A 2 I JNC rei Jump if No Carry flag 2 2
XRL direct.A Exclusive-OR Accumulator to direct byte 2 I JB bit.rel Jump if direct Bit set 3 2
XRL direct.#data Exclusive-OR immediate data to direct 3 2 JNB bit.rel Jump if direct Bit Not set 3 2
CLR A Clear Accumulator I I JBC bit.rel Jump if direct Bit is set & Clear bit 3 2
CPL A Complement Accumulator I I CJNE A.direct.rel Compare direct to A & Jump if Not I;:qual 3 2
RL A Rotate Accumulator Left I I CJNE A.#data.rel Compo immed. to A & Jump if Not Equal 3 2
RLC A Rotate A Left through the Carry flag I I CJNE Rn.#data.rel Compo immed. to reg. & Jump if Not Equal 3 2
RR A Rotate Accumulator Right I I CJNE @Ri.#data.rel Compo immed. to indo & Jump if Not Equal 3 2
RRC A Rotate A Right through Carry flag I I DJNZ Rn.rel Decrement register & Jump if Not Zero 2 2
SWAP A Swap nibbles within the Accumulator I I DJNZ direct.rel Decrement direct & Jump if Not Zero 3 2
NOP No operation I I
DATA TRANSFER
Notes on data addressing modes:
Mnemonic Description Byte Cyc Rn -Working register RO-R7
MOV A.Rn Move register to Accumulator I I direct -128 internal RAM locations. any I/O port. control or status register
MOV A.direct Move direct byte to Accumulator 2 I @Ri --Indirect internal RAM location addressed by register RO or RI
MOV A.@Ri Move indirect RAM to Accumulator I I #data -8-bit constant included in instruction
MOV A.#data Move immediate data to Accumulator 2 I #data 16 -16-bit constant included as bytes 2 & 3 of instruction
MOV Rn.A Move Accumulator to register I I bit -128 software flags. any I/O pin. control or status bit
MOV Rn.direct Move direct byte to register 2 2
MOV Rn.#data Move immediate data to register 2 I Notes on program addressing modes:
MOV direct.A Move Accumulator to direct byte 2 I addrl6 -Destination address for LCALL & LJMP may be anywhere within
MOV direct.Rn Move register to direct byte 2 2 the 64-Kilobyte program memory address space.
MOV direct.direct Move direct byte to direct 3 2 addrll -Destination address for ACALL & AJMP will be within the same
MOV direct.@Ri Move indirect RAM to direct byte 2 2 2-Kilobyte page of program memory as the first byte of the following
MOV direct.#data Move immediate data to direct byte 3 2 instruction.
MOV @Ri.A Move Accumulator to indirect RAM I I rei -SJ M P and all conditional jumps include an 8-bit offset byte. Range is
MOV @Ri.direct Move direct byte to indirect RAM 2 2 +127 / -128 bytes relative to first byte of the following instruction.
MOV @Ri.#data Move immediate data to indirect RAM 2 I
MOV DPTR.#data 16 Load Data Pointer with a 16-bit constant 3 2 All mnemonics copyrighted Intel Corporation 1979
3. INSTRUCTION SET AND ADDRESSING MODES group, this chapter starts with the addressing mode
The 805 I instruction set is extremely regular, in the sense classes and builds to include the related instructions.
that most instructions can operate with variables from
several different physical or logical address spaces. Before Data Addressing Modes
getting deeply enmeshed in the instruction set proper, it MCS-51 assembly language instructions consist of an
is important to understand the details of the most operation mnemonic and zero to three operands separated
common data addressing modes. Whereas Table 4 sum- by commas. In two operand instructions the destination
marizes the instructions set broken down by functional is. specified first, then the source. Many byte-wide data
AFN-01502A
8-14
APPLICATIONS
operations (such as ADD or MOY) inherently use the hardware reset enables register bank 0; to select a
accumulator as a source operand and/or to receive the different bank the programmer modifies PSW bits 4 and
result. For the sake of clarity the letter "A" is specified in 3 accordingly.
the source or destination field in all such instructions.
Example 2 - Selecting Alternate Memory Banks
For example, the instruction,
MOV PSW.II00010000B SELECT BANK 2
ADD A,<source>
will add the variable<source>to the accumulator, leaving Register addressing in the 8051 is the same as in the 8048
the sum in the accumulator. family, with two enhancements: there are four banks
rather than one or two, and 16 instructions (rather than
The operand designated '~source>" above may use any
12) can access them.
of four common logical addressing modes:
Register-one of the working registers in the cur-
rently enabled bank. Direct Byte Addressing
Direct-an internal RAM location, I/O port, or Direct addressing can access anyon-chip variable or
special-function register. hardware register. An additional byte appended to the
Register-indirect-an internal RAM location, opcode specifies the location to be used (Figure 12.b).
pointed to by a working register.
Depending on the highest order bit of the direct address
Immediate data-an eight-bit constant incorporated
byte, one of two physical memory spaces is selected.
into the instruction.
When the direct address is between 0 and 127 (00H-7FH)
The first three modes provide access to the internal RAM one of the 128 low-order on-chip RAM locations is used.
and Hardware Register address spaces, and may therefore (Future microcomputers based on the MCS_5ITM archi-
be used as source or destination operands; the last mode tecture may incorporate more than 128 bytes of on-chip
accesses program memory and may be a source operand RAM. Even if this is the case, only the low-order 128
only. bytes will be directly addressable. The remainder would
(It is hard to show a "typical application" of any instruc- be accessed indirectly or via the stack pointer.)
tion without involving instructions not yet described. The Example 3 -Adding RAM Location Contents
following descriptions use only the self-explanatory ADD
and MOY instructions to demonstrate how the four ; DIRADR ADD CONTENTS OF RAM LOCATION 41H
TO CONTENTS OF RAM LOCATION 40H
addressing modes are specified and used. Subsequent DIRADR MOV A,40H
examples will become increasingly complex.) ADD
MOV
A,41H
40H, A
All I/O ports and special function, control, or status

Register Addressing registers are assigned addresses between 128 and 255
The 8051 programmer has access to eight "working regis- (80H-OFFH). When the direct address byte is between
ters," numbered RO-R7. The least-significant three-bits of these limits the corresponding hardware register is
the instruction opcode indicate one register within this accessed. For example, Ports 0 and I are assigned direct
logical address space. Thus, a function code and operand addresses 80H and 90H, respectively. A complete list is
address can be combined to form a short (one byte) presented in Table 5. Don't waste your time trying to
instruction (Figure 12.a). memorize the addresses in Table 5. Since programs using
absolute addresses for function registers would be difficult
The 8051 assembly language indicates register addressing to write or understand, ASM51 allows and understands
with the symbol Rn (where n is from 0 to 7) or with a the abbreviations listed instead.
symbolic name previously defined as a register by the
EQUate or SET directives. (For more information on Example 4-Adding Input Port Data to Output Port
assembler directives see the Macro Assembler Reference Data
; PRTADR ADD DATA INPUT ON PORT 1
Manual.) TO DATA PREVIOUSLY OUTPUT
ON PORT 0
Example I-Adding Two Registers Together PRTADR MOV A, PO'

ADD A, PI
MOV PO, A
; REGADR ADD CONTENTS OF REG I STER 1
TO CONTENTS OF REGISTER 0
Direct addressing allows all special-function registers in
REGADR MOV A, RO
ADD A, Rl the 8051 to be read, written, or used as instruction
MOV RO. A
operands. In general, this is the only method used for
There are four such banks of working registers, only one accessing I/O ports and special-function registers. If direct
of which is active at a time. Physically, they occupy the addressing is used with special-function register addresses
first 32 bytes of on-chip data RAM (addresses O-IFH). other than those listed, the result of the instruction is
PSW bits 4 and 3 determine which bank is active. A undefined.
AFN01502A
8-15
APPLICATIONS
The 8048 does not have or need any generalized direct Indirect addressing on the 8051 is the same as in the
addressing mode, since there are only five special registers 8048 family, except that all eight bits of the pointer register
(BUS, PI, P2, PSW, & T) rather than twenty. Instead, 16 contents are significant; if the contents point to a non-
special 8048 opcodes control output bits or read or write existent memory location (i.e., an address greater than
each register to the accumulator. These functions are all 7FH on the 8051) the result of the instruction is undefined.
subsumed by four of the 27 direct addressing instructions (Future microcomputers based on the MCS-5I archi-
of the 8051. tecture could implement additional memory in the
on-chip RAM logical address space at locations above
Table 5. 8051 Hardware Register Direct Addresses 7FH.) The 8051 uses register-indirect addressing for five
new instructions plus the 13 on the 8048.
Register Address Function
PO 80H* Port 0
SP 81H Stack Pointer
Immediate AddreSSing
DPL 82H Data Pointer (Low) When a source operand is a constant rather than a vari-
DPH 83H Data Pointer (High) able (i.e.-the instruction uses a value known at assembly
TCON 88H* Timer register
TMOD 89H Timer Mode register time), then the constant can be incorporated into the
TLO 8AH Timer 0 Low byte instruction. An additional instruction byte specifies the
TLI 8BH Timer I Low byte value used (Figure l2.d).
THO 8CH Timer 0 High byte
THI 8DH Timer I High byte The value used is fixed at the time of ROM manufacture
PI 90H* Port I or EPROM programming and may not be altered during
SCON 98H* Serial Port Control register program execution. In the assembly language immediate
SBUF 99H Serial Port data Buffer operands are preceded by a number sign ("#"). The
P2 OAOH* Port 2
operand may be either a numeric string, a symbolic
IE OA8H* Interrupt Enable register
P3 OBOH* Port 3 variable, or an arithmetic expression using constants.
IP OB8H* Interrupt Priority register
PSW ODOH* Program Status Word Example 6-Adding Constants Using Immediate
ACe OEOH* Accumulator (direct address) Addressing
B OFOH* B register i IMMADR ADD THE CONSTANT 12 (DECIMAL)
TO THE CONSTANT 34 (DECIMAL)
LEAVE SUM IN ACCUMULATOR
= bit addressable register.
IMMADR MOV A.1I12
ADD A.1I34
Register-Indirect AddreSSing The preceding example was included for consistency; it

has little practical value. Instead, ASM51 could compute
How can you handle variables whose locations in RAM
are determined, computed, or modified while the program the sum of two constants at assembly time.
is running? This situation arises when manipulating Example 7 -Adding Constants Using ASM51
sequential memory locations, indexed entries within tables Capabilities
in RAM, and multiple precision or string operations. i ASMSUM LOAD ACC WITH THE SUM OF
Register or Direct addressing cannot be used, since their THE CONSTANT 12 (DEC IMAL)
THE CONSTANT 34 <DECIMAL)
AND
operand addresses are fixed at assembly time. ASMSUM: MOV A. II( 12+34)
The 8051 solution is "register-indirect RAM addressing."

RO and R I of each register bank may operate as index a.) Register Addressing:
or pointer registers, their contents iridicating an address

into RAM. The internal RAM location so addressed is
ADD A,R
the actual operand used. The least significant bit of the
b.) Direct Addressing:
instruction opcode determines which register is used as
the "pointer" (Figure 12.c).
ADD A, direct
In the 8051 assembly language, register-indirect addressing
is represented by a commercial "at" sign ("@") preceding c.) Register-indirect Addressing:
RO, R I, or a symbol defined by the user to be equal to

RO or R1. I : : +co+
ADD
: :
A,@R
II
i
Example 5 - Indirect Addressing d.) Immediate Addressing:

INDADR ADD CONTENTS OF MEMORY LOCATION
ADDRESSED BY REG I STER 1
TO CONTENTS OF RAM LOCATION
ADDRESSED BY REG I STER 0
ADD A,# data
NDADR MOV A.l!RO
ADD A.l!Rl
MOV l!RO. A Figure 12. Data Addressing Machine Code Formats
AFN-01502A
8-16
APPLICATIONS
Addressing Mode Combinations. Notice from Table 4 that the MCS-SITM instruction set has
relatively few instruction mnemonics (abbreviations) for
The above examples all demonstrated the use of the four
the programmer to memorize. Different data types or
data-addressing modes in two-operand instructions
addressing modes are determined by the operands
(MOV, ADD) which use the accumulator as one
specified, rather than variations on the mnemonic. For
operand. The operations ADDC, SUBB, ANL, ORL,
example, the mnemonic "MOV" is used by 18 different
and XRL (all to be discussed later) could be substituted
instructions to operate on three data types (bit, byte, and
for ADD in each example. The first three modes may be
address). The fifteen versions which move byte variables
also be used for the XCH operation or, in combination
between the logical address spaces are diagrammed in
with the Immediate Addressing mode (and an additional
Figure 13. Each arrow shows the direction of transfer
byte), loaded with a constant. The one-operand
from source to destination.
instructions INC and DEC, DJNZ, and C~NE may all
operate on the accumulator, or may specify the Register, Notice also that for most instructions allowing register
Direct, and Register-indirect addressing modes. addressing there is a corresponding direct addressing
Exception: as in the 8048, DJNZ cannot use the instruction and vice versa. This lets the programmer
accumulator or indirect addressing. (The PUSH and begin writing 80S I programs as if (s)he has access to 128
PO P operations cannot inherently address the different registers. When the program has evolved to the
accumulator as a special register either. However, all point where the programmer has a fairly accurate idea
three can directzv address the accumulator as one of the how often each variable is used, he / she may allocate th'e
twenty special-function registers by putting the symbol working registers in each bank to the most "popular"
"ACe" in the operand field.) variables. (The assembly cross-reference option will show
exactly how often- and where each symbol is referenced.)
If symbolic addressing is used in writing the source
Advantages of Symbolic Addressing program only the lines containing the symbol definition
Like most assembly or higher-level programming will need to be changed; the assembler will produce the
languages, ASMSI allows instructions or variables to be appropriate instructions even though the rest of the
given appropriate, user-defined symbolic names. This is program is left untouched. Editing only the first two lines
done for instruction lines by putting a label followed by a of Example 8 will shrink the six-byte code segment
colon (":") before the instruction proper, as in the above produced in half.
examples. Such symbols must start with an alphabetic
character (remember what distinguished BACH from How are instruction sets "counted"? There is
OBACH?), and may include any combination of letters, no standard practice; different people assess-
numbers, question marks ("T) and underscores ("_"). For ing the same CPU using differentconventions
very long names only the first 31 characters are relevant. may arrive at different totals.
Assembly language programs may intermix upper- and Each operation is then broken down according
lower-case letters arbitrarily, but AS M SI converts both to the different addressing modes (or com-
to upper-case. For example, ASMSI will internally binations of addressing modes) it can accom-
process an "I" for an "i" and, of course, "A_TOOTH" for modate. The "CLR" mnemonic is used by two
"a_tooth." instructions with respect to bit variables ("CLR
The underscore character makes symbols easier to read C" and "CLR bit") and once ("CLR A") with
and can eliminate potential ambiguity (as in the label for regards to bytes. This expansion yields the 111
a subroutine to switch two entires on a stack, separate instructions of Table 4.
"S_EXCHANGE"). The underscore is significant, and The method used for the MCS-51 instruction
would distinguish between otherwise-identical character set first breaks it down into "operations": a
strings. basic function applied to a single data type. For
AS M 51 allows all variables (registers, ports, internal or example, the four versions of the ADD instruc-
external RA M add resses, constants, etc;) to be assigned tion are grouped to form one operation -
labels according to these rules with the EQUate or SET addition of eight-bit variables. The six forms of
directives. the ANL instruction for byte variables make up
a different operation; the two forms of ANL
Example 8-Symbolic Addressing of Variables which operate on bits are considered still
Defined as RAM Locations another. The MOV mnemonic is used by three
VAR 0 SET 20H
VAR=I SET 21H different operation classes, depending on
i SYt1B_I ADD CONTENTS OF VAR I whether bit, byte; or 16-bit values are affected.
TO CONTENTS OF VAR. O'
Using this terminology the 8051 can perform
SYMB_I' MOV
ADD
A. VAR
A. VAR=I 51 different operations.
MOV VAR_O. A
AFN-01502A
B-17
APPLICATIONS
The MCS-51 processors detect whetht:r these situations

occur and indicate such errors with the OV flag. (OV may
be tested with the conditional jump instructions JB and
JNB, described under the Boolean Processor chapter.)
At a hardware level, OV is set if there is a carry out of bit 6
but not out of bit 7, or a carry out of bit 7 but not out of
bit 6. When adding signed integers this indicates a
negative number produced as the sum of two positive
operands, or a positive sum from two negative operands;
on S UBB this indicates a negative result after subtracting
a negative number from a positive number, or a positive
Figure 13. Road map for moving data bytes
result when a positive number is subtracted from a
negative number.
Example 9-Redeclaring Example 8 Symbols as
Registers The ADDC and SUBB instructions incorporate the
previous state of the carry (borrow) flag to allow multiple
VAR 0 SET RO
VAR:::1 SET Rl precision calculations by repeating the operation with
;
; SYMB_2 ADD CONTENTS OF VAR_l successively higher-order operand bytes. In either case,
TO CONTENTS OF VAR_O
; the carry must be cleared before the first iteration.
SYMB_2: MOV A. VAR_O
ADD A. VAR_l
MOV VAR_O. A If the input data for a multiple precision operation is an
unsigned string of integers, upon completion the carry
flag will be set if an overflow (for ADDC) or underflow
Arithmetic Instruction Usage - ADD, ADDC, SUBB (for SUBB) occurs. With two's complement signed data
and DA (i.e., if the most significant bit of the original input data
The ADD instruction adds a byte variable with the indicates the sign of the string), the overflow flag will be
accumulator, leaving the result in the accumulator. The set if overflow or underflow occurred.
carry flag is set if there is an overflow from bit 7 and
cleared otherwise. The AC flag is set to the carry-out Example 10 - String Subtraction with Signed Overflow
from bit 3 for use by the DA instruction described later. Detection
ADDC adds the previous contents of the carry flag with ; SUBSTR SUBTRACT STRING INDICATED BY Rl
FROM STRING INDICATED BY RO TO
the two byte variables, but otherwise is the same as ADD. PRECISION INDICATED BY R2.
CHECK FOR SIGNED UNDERFL.OW WHEN DONE.
The SUBB (subtract with borrow) instruction subtracts SUBSTR' CL.R C ; BORROW= O.
SUBSl : MOV A.IRO
the byte variable indicated and the contents of the carry SUBB A. IR 1 ; SUBTRACT NEXT PL.ACE
MOV @RO.A
flag together from the accumulator, and puts the result INC RO ; BUMP POINTERS
INC Rl
back in the accumulator. The carry flag serves as a OJNZ R2. SUBSI ; L.OOP AS NEEDED
WHEN DONE. TEST IF OVERFLOW OCCURED
"Borrow Required" flag during subtraction operations; ON LAST ITERATION OF LOOP
JNB OV.OV OK
when a greater value is subtracted from a lesser value (as ; - (OVERFLOW RECOVERY ROUTINE>
OV_OK: RET ; RETURN
in subtracting 5 from I) requiring a borrow into the
highest order bit, the carry flag is set; otherwise it is
cleared.
Decimal addition is possible by using the DA instruction
When performing signed binary arithmetic, certain in conjunction with ADD and/or ADDC. The eight-bit
combinations of input variables can produce results binary value in the accumulator resulting from an earlier
which seem to violate the Laws of Mathematics. For addition of two variables (each a packed BCD digit-pair)
example, adding 7FH (127) to itself produces a sum of is adjusted to form two BCD digits of four bits each. If the
OFEH, which is the two's complement representation of contents of accumulator bits 3-0 are greater than nine
-2 (refer back to Table 2)! In "normal" arithmetic, two (xxxx 10 IO-xxxx 1111), or ifthe AC flag had been set, six
.positive values can't have a negative sum. Similarly, it js is added to the accumulator producing the proper BCD
normally impossible to subtract a positive value from a digit in the low-order nibble. (This addition might itself
negative value and leave a positive result - but in two's set - but would not clear - the carry flag.) Ifthe carry
complement there are instances where this too may flag is set, or if the four high-order bits now exceed nine
happen. Fundamentally, such anomolies occur when the (10 IOxxxx-IIII xxxx), these bits are incremented by six.
magnitude of the resulting value is too great to "fit" into The carry flag is left set if originally set or if either
the seven bits allowed for it; there is no one-byte two's addition of six produces a carry out of the highest-order
complement representation for 254, the true sum of 127 bit, indicating the sum of the original two BCD variables
and 127. is greater than or equal to decimal 100.
AFN-01S02A
R.1A
APPLICATIONS
Example II - Two Byte Decimal Add with Registers digits in the accumulator and returns the product of the
and Constants two individual digits in packed BCD format in the
; BCDADD ADD THE CONSTANT 1.234 (DECIMAl) TO THE accumulator.
CONTENTS OF REGISTER PAIR ':R3><R2>
(ALREADY A 4 BCD-DIGIT VARIABLE)
Example 13 -Implementing a BCD Multiply Using
BCDADD MOV A. R2
ADD A.4I34H MPYand DIV
DA A
MOV R2. A ; MULBCD UNPACK TWO BCD DIGITS RECEIVED IN ACC.
MOV A. R3 FIND THEIR PRODUCT. AND RETURN PRODUCT
ADDC A.4I12H IN PACKED BCD FORMAT IN ACC
DA A
MOV R3. A MULBCD' MOV B.III0H; DIVIDE INPUT 8Y 16
RET DIV AB ; A 8< B HOLD SEPARATED IiIGITS
; (EACH RIGHT JUSTIFIED IN REGISTER)
MUL ; A HOLDS PRODUCT IN BINARY FORMAT (0 -
; 99(DECIMAU = 0 - 63H)
MOV B.III0; DIVIDE PRODUCT BY 10
Multiplication and Division DIV
SWAP
AB
A
; A HOLDS II OF TENS. B HOLDS REMAINDER
ORL A. B ; PACK DIGITS

The instruction "MUL AB" multiplies the unsigned RET
eight-bit integer values held in the accumulator and B-

registers. The low-order byte of the sixteen-bit product is
logical Byte Operations - ANL, ORl, XRl
left in the accumulator, the higher-order byte in B. If the
high-order eight-bits of the product are all zero the The instructions ANL, ORL, and XRL perform the
overflow flag is cleared; otherwise it is set. The logical functions AND, OR, and! or Exclusive-OR on the
programmer can poll OV to determine when the B two byte variables indicated, leaving the results in the
register is non-zero and must be processed. first. No flags are affected. (A word to the wise - do not
vocalize the first two mnemonics in mixed company.)
"DIV AB" divides the unsigned eight-bit integer in the
accumulator by the unsigned eight-bit integer in the B- These operations may use all the same addressing modes
register. The integer part of the quotient is returned in the as the arithmetics (ADD, etc.) but unlike the arithmetics,
accumulator; the remainder in the B-register. If the B- they are not restricted to operating on the accumulator.
register originally contained OOH then the overflow flag Directly addressed bytes may be used as the destination
will be set to indicate a division error, and the values with either the accumulator or a constant as the source.
returned will be undefined. Otherwise OV is cleared. These instructions are useful for clearing (ANL), setting
(ORL), or complementing (XRL) one or more bits in a
The divide instruction is also useful for purposes such as
RAM, output ports, or control registers. The pattern of
radix conversion or separating bit fields of the
bits to be affected is indicated by a suitable mask byte.
accumulator. A short subroutine can convert an eight-bit
Use immediate addressing when the pattern to be affected
unsigned binary integer in the accumulator (between 0 &
is known at assembly time (Figure 14); use the
255) to a three-digit (two byte) BCD representation. The
accumulator versions when the pattern is computed at
hundred's digit is returned in one register (HUND) and
the ten's and one's digits returned as packed BCD in run-time.
another (TENONE). I! 0 ports are often used for parallel data in formats other
than simple eight-bit bytes. For example, the low-order
Example 12- Use of DIV Instruction for Radix five bits of port I may output an alphabetic character
Conversion code (hopefully) without disturbing bits 7-5. This can be a
; BINBCD CONVERT 8-BIT BINARY VARIABLE IN ACC simple two-step process. First, clear the low-order five
TO 3-DIGIT PACKED BCD FORMAT
HUNDREDS' PLACE LEFT IN VARIABLE HUND'. pins with an ANL instruction; then set those pins corres-
TENS' AND ONES' PLACES IN 'TENONE'
ponding to ones in the accumulator. (This example
HUND E<lU 21H
TENONE EQU 22H assumes the three high-order bits of the accumulator are
BINBCD MOV B.II100 ; DIVIDE BY 100 TO originally zero.)
DIV AB ; DETERM I NE NUMBER OF HUNDREDS
MOV HUND. A
MOV A,4IIO ; DIVIDE REMAINDER BY 10 TO Example l4-Reconfiguring Port Size with Logical
XCH A. B ; DETERMINE II OF TENS LEFT
DIV AB ; TENS DIGIT IN ACC. REMAINDER 15 ONES Byte Instructions
; DIGIT
SWAP A
OUT _px ANL PI. 4I11100000B ; CLEAR BITS PI. 4 - PI. 0
ADD A. B ; PACK BCD DIGITS IN ACC
ORL PI.A ;SET PI PINS CORRESONDING TO SET ACC
MOV TENONE. A
; BITS.
RET
RET
The divide instruction can also separate eight bits of data

in the accumulator into sub-fields. For example, packed
BCD data may be separated into two nibbles by dividing oP_c_od_e_---'11
L..-_ _ direct address I L.1_ _m_a_s_k_ - - - '
the data by 16, leaving the high-nibble in the accumulator ANL P1. #data
and the low-order nibble (remainder) in B. The two digits

may then be operated on individually or in conjunction Figure 14. Instruction Pattern for logical Operation
with each other. This example receives two packed BCD Special Addressing Modes
AFN-OI502A
8-19
APPLICATIONS
In this example, low-order bits remaining high may destination at run-time by adding the signed eight-bit
"glitch" low for one machine cycle. If this is undesirabh:, dispiacemeni vaiue io ihe incremented P.c. Negative
use a slightly different approach. First, set all pins offset values will cause jumps up to 128 bytes backwards;
corresponding to accumulator one bits, then clear the positive values up to 127 bytes forwards. (SJ M P with
pins corresponding to zeroes in low-order accumulator OOH in the machine code offset byte will proceed with the
bits. Not all bits will change from original to final state at following instruction).
the same instant, but no bit makes an intermediate
transition. In keeping with the 8051 assembly language goal of
minimizing the number of instruction mnemonics, there
Example 15 - Reconfiguring I/O Port Size without is a "generic" form of the three jump instructions.
Glitching ASM51 recognizes the mnemonic JMP as a "pseudo-
ALT]X' ORL PI. A instruction," translating it into the machine instructions
ORL A 111000008
ANL PI. A LJMP, AJMP, or SJMP, depending on the destination
RET
address.
Like SJ M P, all conditional jump instructions use relative

Program Control - Jumps, Calls, Returns
addressing. JZ (Jump if Zero) and JNZ (Jump if Not
Whereas the 8048 only has a single form of the simple Zero) monitor the state of the accumulator as implied by
jump instruction, the 805! has three. Each causes the their names, while JC (Jump on Carry) and JNC (Jump
program to unconditionally jump to some other address. on No Carry) test whether or not the carry flag is set. All
They differ in how the machine code represents the four are two-byte instructions, with the same format as
destination address. Figure 15.c. JB (Jump on Bit), JNB (Jump on No Bit) and
JBC (Jump on Bit then Clear Bit) can test any status bit
LJMP (Long Jump) encodes a sixteen-bit address in the
or input pin with a three byte instruction; the second byte
second and third instruction bytes (Figure 15.a); the
specifies which bit to test and the third gives the relative
destination may be anywhere in the 64 Kilobyte program
offset value.
memory address space.
There are two subroutine-call instructions, LCALL
The two-byte AJMP (Absolute Jump) instruction
(Long Call) and ACALL (Absolute Call). Each
encodes its destination using the same format as the 8048:
increments the P.c. to the first byte of the following
address bits 10 through 8 form a three bit field in the
opcode and address bits 7 through 0 form the second byte instruction, then pushes it onto the stack (low byte first).
Saving both bytes increments the stack pointer by two.
(Figure 15. b). Address bits 15-12 are unchanged from the
The subroutine's starting address is encoded in the same
(incremented) contents of the P.C., so AJMP can only be
ways as LJMP and AJMP. The generic form of the call
used when the destination is known to be within the same
2K memory block. (Otherwise ASM51 will point out the operation is the mnemonic CALL, which ASM51 will
translate into LCALL or ACALL as appropriate.
error.)
A different two-byte jump instruction is legal with any The return instruction RET pops the high- and low-order
nearby destination, regardless of memory block bytes of the program counter successively from the stack,
boundaries or "pages." SJMP (Short Jump) encodes the decrementing the stack pointer by two. Program
destination with a program counter-relative address in execution continues at the address previously pushed: the
the second byte (Figure 15.c). The CPU calculates the first byte of the instruction immediately following the
call.
When an interrupt request is recognized by the 8051
a.) Long Jump (LJMP addr16): hardware, two things happen. Program control is
opcode "r--- a-dd-'l-s-_-a-d""'d'-S---W,, add,7 - addrO automatically "vectored" to one of the interrupt service
routine starting addresses by, in effect, forcing the CPU
to process an LCALL instead of the next instruction.
b.) Absolute Jump (AJMP add,ll):
This automatically stores the return address on the stack.
(Unlike the 8048, no status information is automatically
saved.)
c.) Short Jump (SJMP rei): Secondly, the interrupt logic is disabled from accepting
I:: ;oP+d< : : III---r_elative_ollset------l

any other interrupts from the same or lower priority.
After completing the interrupt service routine, executing
an RETI (Return from Interrupt) instruction will return
execution to the point where the background program
Figure 15. Jump Instruction Machine Code was interrupted - just like RET - while restoring the
Formats interrupt logic to its previous state.
AFN-01S02A
8-20
APPLICATIONS
Operate-and-branch instructions - CJNE, DJNZ The dollar sign in this example is a special character
Two groups of instructions combine a byte operation meaning "the address of this instruction." It is useful in
with a conditional jump based on the results. eliminating instruction labels on the same or adjacent
source lines. CJNE and DJNZ (like all conditional
CJNE (Compare and Jump if Not Equal) compares two
jumps) use program-counter relative addressing for the
byte operands and executes a jump if they disagree. The
destination address.
carry flag is set following the rules for subtraction: if the
unsigned integer value of the first operand is less than
Stack Operations - PUSH, POP
that of the second it is set; otherwise, it is cleared.
However, neither operand is modified. The PUSH instruction increments the stack pointer by
one, then transfers the contents of the single byte variable
The CJNE instruction provides, in effect, a one-
indicated (direct addressing only) into the internal RAM
instruction "case" statement. This instruction may be
location addressed by the stack pointer. Conversely,
executed repeatedly, comparing the code variable to a list
POP copies the contents of the internal RAM location
of "special case" value: the code segment following the
addressed by the stack pointer to the byte variable
instruction (up to the destination label) will be executed
indicated, then decrements the stack pointer by one.
only if the operands match. Comparing the accumulator
or a register to a series of constants is a convenient way to (Stack Addressing follows the same rules, and addresses
check for special handling or error conditions; if none of the same locations as Register-indirect. Future micro-
the cases match the program will continue with "normal" computers based on the MCS-5ITM CPU could have up to
processing. 256 bytes of RA M for the stack.)
A typical example might be a word processing device Interrupt service routines must not change any variable
which receives ASCII characters through the serial port or hardware registers modified by the main program, or
and drives a thermal hard-copy printer. A standard else the program may not resume correctly. (Such a
routine translates "printing" characters to bit patterns, change might look like a spontaneous random error.)
but control characters DEL>, <CR>, <LF>, <BEL>, Resources used or altered by the service routine
<ESC>, or<SP must invoke corresponding special (Accumulator, PSW, etc.) must be saved and restored to
routines. Any other character with an ASCII code less their previous value before returning from the service
than 20H should be translated into the<NUL>value, routine. PUSH and POP provide an efficient and
OOH, and processed with the printing characters. convenient way to save register states on the stack.
Example 16-Case Statements Using CJNE Example 18 - Use of the Stack for Status Saving on
CHAR
;
E<lU R7 ; CHARACTER CODE VAR IABLE Interrupts
INTERP' CJNE CHAR, 117FH, INTP 1 LoC_TMP E<lU ; REMEMBER LoCAT I ON COUNTER
(SPECIAL ROUTINE FOR RUBOUT CODE)
RET oRG 0003H ; STARTING ADDRESS FOR INTERRUPT ROUTINE
INTP I CJNE CHAR, 1I07H, INTP 2 LJMP SERVER ; JUMP TO ACTUAL SERVICE ROUTINE LOCATED
- (SPEC I AL RoUTI NE FOR BELL CODE) ; ELSEWHERE
RET
INTP _2' CJNE CHAR, IIOAH, INTP 3 oRG LoC TMP ; RESTORE LoCAT ION COUNTER
(SPECIAL ROUTINE FOR LFEED CODE) SERVER PUSH PSW-
RET PUSH ACC ; SAVE ACCUMULATOR (NOTE DIRECT ADDRESSING
INTP _3: CJNE CHAR, IIODH, INTP 4 ; NOTATION)
(SPEC IAL ROUTINE FOR RETURN CODE) PUSH B ; SAVE B REGISTER
RET PUSH DPL ; SAVE DATA POINTER
INTP 4 CJNE CHAR, IIIBH, INTP ~ PUSH DPH ,
- (SPECIAL ROUTINE FOR ESCAPE CODE) MoV PSW, 110000 I OOOB SELEC T REG I STER BANK I
RET
INTP
-~ CJNE CHAR, 1120H, INTP 6
(SPECIAL ROUTINE FOR SPACE CODE) PDP DPH RESTORE REGISTERS IN REVERSE ORDER
RET PDP DPL
INTP _6' Jr. PRINTC ; JUMP IF CODE )0 20H PDP B
MoV CHAR. 110 ; REPLACE CONTROL CHARACTERS WITH PDP ACC
; NULL CODE PDP PSW ; RESTORE PSW AND RE-SELECT OR IGINAL
PRINTC ; PROCESS STANDARD PRINTING ; REG I STER BANK
; CHARACTER RETI ; RETURN TO MAIN PROGRAM AND RESTORE
RET ; INTERRUPT LOGIC
DJNZ (Decrement and Jump if Not Zero) decrements If the SP register held I FH when the interrupt was
the register or direct address indicated and jumps if the detected, then while the service routine was in progress
result is not zero, without affecting any flags. This the stack would hold the registers shown in Figure 16; SP
provides a simple means for executing a program loop a would contain 26H.
given number of times, or for adding a moderate time The example shows the most general situation; if the
delay (from 2 to 512 machine cycles) with a single service routine doesn't alter the B-register and data
instruction. For example, a 99-usec. software delay loop
pointer, for example, the instructions saving and
can be added to code forcing an I I 0 pin low with only restoring those registers would not be necessary.
two instructions.
The stack may also pass parameters to and from
Example 17 -Inserting a Software Delay with DJNZ subroutines. The subroutine can indirectly address the
CLR WR
MOV R2,1I49 parameters derived from the contents of the stack
DJNZ R2, S
SETB WR pointer.
AFN-01502A
8-21
APPLICATIONS
If the position of the motor is determined by the contents

RAM
ADDR of variable POSM I (a byte in internal RAM) and the
7FH position of a second motor on Port 2 is determined by the
data input to the low-order nibble of Port 2, a six-
instruction sequence could update them both.
26H DPH _(SP) Example 21 -Loading and Unloading Stack Direct
25H DPL from I/O Ports
24H B POSMI E(JU 51
23H ACC PUSH POSMI

CALL NXTPOS
POP PI
22H PSW
PUSH P2
CALL NXTPOS
21H PC (HIGH) PDP P2
20H PC (LOW)
lFH
Data Pointer and Table look-up instructions -
MOV, INC, MOVC, JMP
OOH
The data pointer can be loaded with a 16-bit value using
the instruction MOV DPTR, #dataI6. The data used is
Figure 16. Stack contents during interrupt stored in the second and third instruction bytes, high-
order byte first. The data pointer is incremented by INC
DPTR. A 16-bit increment is performed; an overflow
One advantage here is simplicity. Variables need not be
from the low byte will carry into the high-order byte.
allocated for specific parameters, a potentially large
Neither instruction affects any flags.
number of parameters may be passed, and different
calling programs may use different techniques for The MOVC (Move Constant) instructions (MOVC
determining or handling the variables. A,@A+DPTR and MOVC A,@A+PC) read into the
For example, the following subroutine reads out a accumulator bytes of data from the program memory
parameter stored on the stack by the calling program, logical address space. Both use a form of indexed
uses the low order bits to access a local look-up table addressing: the former adds the unsigned eight-bit
holding bit patterns for driving the coils of a four phase accumulator contents with the sixteen-bit data pointer
stepper motor, and stores the appropriate bit pattern register, and uses the resulting sum as the address from
back in the same position on the stack before returning. which the byte is fetched. A sixteen-bit addition is
The accumulator contents are left unchanged. performed; a carry-out from the low-order eight bits may
propagate through higher-order bits, but the contents of
Example 19 - Passing Variable Parameters to Sub- the DPTR are not altered. The latter form uses the incre-
routines Using the Stack mented program counter as the "base" value instead of
NXTPOS MOV RO. SP the D PTR (figure 17). Again, neither version affects the
DEC RO ; ACCESS LOCATION PARAMETER PUSHED INTO
DEC RO flags.
XCH A. @RO ; READ I NPUT PARAMETER AND SAVE
; ACCUMULATOR
ANL A. 1I03H; MASK ALL BUT LO~-ORDER T~O BITS
ADD A. 112 ; ALLD~ FOR OFFSET FROM MoVC TO TABLE
MOVC
XCH
A.
A.
@A+PC
@RO
; READ LOOK-UP TABLE ENTRY
; PASS 8ACK TRANSLATED VALUE AND RESTORE
a.) MOVC A. @ A + PC
(LOCAL TABLE IS-BIT I P.C.
; ACC LOOK-UP)
STPTBL
RET
DB
; RETURN TO BACKGROUND PROGRAM
01101 I liB ; POSITION 0
~ACC
DB 0101 I 1118 ; POSITION 1
DB 100111118 POSITION 2
DB 10101111B ; POSITION 3
L -_ _ _l_6_-_B_
IT....J1 ~~~g~I~~RESS
The background program may reach this subroutine with
several different calling sequences, all of which PUSH a
b.) MOVC A.@ A+ DPTR
(GLOBAL TABLE
lS-BIT I DPTR
LOOK-UP)
value before calling the routine and POP the result after. ~ACC
A motor on Port I may be initialized by placing the
desired position (zero) on the stack before calling the L -_ _ _l_6_-_B_IT...j1 ~~~g~~~RESS
subroutine and outputing the results directly to a port
afterwards. c.) JMP @ A+ DPTR
(GLOBAL INDIRECT lS-BIT I DPTR
JUMP)
Example 20-Sending and Receiving Data Parameters ~ACC
Via the Stack
'--_ _ _l_S_-_B_IT...IILOADED INTO P.C.
CLR A
PUSH ACC
CALL NXTPOS
POP PI Figure 17. Operation of MOVC instructions
AFN-01502A
8-22
APPLICATIONS
Each can be part of a three step sequence to access look- There are several different means for branching to
up tables in ROM. To use the DPTR-relative version, sections of code determined or selected at run time. (The
load the Data Pointer with the starting address of a look- single destination addresses incorporated into
up table; load the accumulator with (or compute) the conditional and unconditional jumps are, of course,
index of the entry desired; and execute MOVC determined at assembly time). Each has advantages for
A,@A+DPTR. Unlike the similar MOVP3 instructions different applications.
in the 8048, the table may be located anywhere in The most common is an N-way conditional jump based
program memory. The data pointer may be loaded with a on some variable, with all of the potential destinations
constant for short tables. Or to allow more complicated known at assembly time. One of a number of small
data structures, or tables with more than 256 entries, the
routines is selected according to the value of an index
values for DPH and DPL may be computed or modified
variable determined while the program is running. The
with the standard arithmetic instruction set.
most efficient way to solve this problem is with the
The PC-relative version has the advantage of not MOVC and an indirect jump instruction, using a short
affecting the data pointer. Again, a look-up sequence table of one byte offset values in ROM to indicate the
takes three steps: load the accumulator with the index; relative starting addresses of the several routines.
compensate for the offset from the look-up instruction to
the start of the table by adding the number of bytes JMP @A+DPTR is an instruction which performs an
separating them to the accumulator; then execute the indirect jump to an address determined during program
MOVC A,@A+PC instruction. execution. The instruction adds the eight-bit unsigned
accumulator contents with the contents of the sixteen-bit
Let's look at a non-trivial situation where this instruction data pointer, just like MOVC A,@A+DPTR. The
would be used. Some applications store large multi- resulting sum is loaded into the program counter and is
dimensional look-up tables of dot matrix patterns, non- used as the address for subsequent instruction fetches.
linear calibration parameters, and so on in a linear (one- Again, a sixteen-bit addition is performed; a carry out
dimensional i) vector in program memory. To retrieve from the low-order eight bits may propagate through the
data from the tables, variables representing matrix higher-order bits. In this case, neither the accumulator
indices must be converted to the desired entry's memory contents nor the data pointer is altered.
address. For a matrix of dimensions (MDIMEN x
NDIMEN) starting at address BASE and respective The example subroutine below reads a byte of RAM into
indices INDEXI and INDEXJ, the address of element the accumulator from one of four alternate address
(lNDEXI, INDEXJ) is determined by the formula, spaces, as selected by the contents of the variable
MEMSEL. The address of the byte to be read is
Entry Address = BASE + (NDIMEN x INDEXI) +
determined by the contents of RO (and optionally R I). It
INDEXJ
might find use in a printing terminal application, where
The code shown below can access any array with less than
four different model printers all use the same ROM code
255 entries (i.e., an II x21 array with 231 elements). The
but use different types and sizes of buffer memory for
table entries are defined using the Data Byte ("DB")
different speeds and options.
dire~tive, and will be contained in the assembly object
code as part of the accessing subroutine itself. Example 23 -N-Way Branch and Computed Jump
Example 22 - Use of MPY and Data Pointer Instruc- Instructions via JMP @ ADPTR
tions to Access Entries from a Multi- MEMSEL EQU R3
dimensional Look-Up Table in ROM ,)UMP _4 MOV A, MEMSEL

MOV DPTR,II')MPTBL
; MATRXI LOAD CONSTANT READ FROM TWO DIMENSIONAL LOOK-UP MOVC A, @A+DPTR
TABLE IN PROGRAM MEMORY INTO ACCUMULATOR ')MP @A+DPTR
USING LOCAL TABLE LOOK-UP INSTRUCT ION. 'MOVC A. @A+PC ')MPTBL DB MEMSPO-')MPTBL
THE TOTAL NUMBER OF TABLE ENTRIES IS ASSUMED TO DB MEMSP I-')MPTBL
BE SMALL. I. E. LESS THAN ABOUT 250 ENTR IES. ) DB MEMSP2-')MPTBL
TABLE USED IN THIS EXAMPLE IS ( I I X 21 ) DB MEMSP3-')MPTBL
DESIRED ENTRY ADDRESS IS GIVEN BY THE FORMULA. MEM5PO' MOV A, (!RO ,READ FROM INTERNAL RAM
[ (BASE ADDRESS) + (21 X INDEXI) + (INDEX') J RET
MEMSPI MOVX A, @RO ; READ FROM 2:56 BYTES OF EXTERNAL RAM
INDEXI EQU Rio ,FIRST COORDINATE OF ENTRY (0-10) RET
INDEX') EQU 23H SECOND C'OORDINATE OF ENTRY (0-20) MEMSP2 MOV DPL, RO
MOV DPH, RI
MATRXI MOV A,INDEXI MOVX A, @DPTR ,READ FROM b4K BYTES OF EXTERNAL RAM
MOV B.1I21 RET
MUL AB MEMSP3' MOV A, R I
ADD A, INDEX,) ANL A,1I07H
ALLOW FOR INSTRUCTION BYTE BETWEEN "MOVC" AND ANL PI,IIIIIIIOOOB
ENTRY (0,0) ORL PI, A
INC A MOVX A, @RO ,READ FROM 4K BYTES OF EXTERNAL RAM
MOVC A, (!A+PC RET
RET
BASEl DB ; (.ntry 0.0)
DB ; (entry O. I) Note that this approach is suitable whenever the size of
DB 21 ; (.ntry 0.20) jump table plus the length of the alternate routines is less
DB 22 ; (entrl:' 1.0)
than 256 bytes. The jump table and routines may be
DB 42 ,(.ntry 1,20)
located anywhere in program memory, independent of
DB 231 ; (entry 10.20) 256-byte program memory pages.
AFN-01502A
8-23
APPLICATIONS
For applications where up to 128 destinations mustbe Prior to the introduction of the MCS-5I'M family, nice
selected, all of which reside in the same 2K pagt: of number-crunchers made bad bit-bangers and vice versa.
program memory which may be reached by the two-byte The 8051 is the industry's first single-chip' micro-
absolute jump instructions, the following technique may computer designed to crunch and bang. (In some circles,
be used. In the above mentioned printing terminal the latter technique is also referred to as "bit-twiddling".
example, this sequence could "parse" 128 different codes Either is correct.)
for ASCII characters arriving via the 8051 serial port.
Direct Bit AddreSSing
Example 24~N-Way Branch with 128 Optional
Destinations A number of instruction~ operate on Boolean (one-bit)
variables, using a direct bit addressing mode comparable
OPTION EQU R3
to direct byte addressing. An additional byte appended to
JMP 128 MDV A. OPTION the opcode specifies the Boolean variable, I/O pin, or
RL A i MULTIPLY BY 2 FOR 2 BYTE JUMP TAIiLE
MDV DPTR.IIINSTBL FIRST ENTRY IN JUMP TABI.E control bit used. The state of any of these bits may be
JMP @A+DPTR JUMP INTO JUMP TABLE
tested for "true" or "false" with the conditional branch
, INSTBL AJMP PROCOO i 128 CONSECUTI VE
AJMP PROCOI ; AJMP INSTRUCTIONS instructions JB (Jump on Bit) and JNB (Jump on Not
AJMP PROC02
Bit). The JBC (Jump on Bit and Clear) instruction
AJMP PROC7E combines a test-for-true with an unconditional clear.
AJMP PROC7F
The destinations in the jump table (PROCOO- As in direct byte addressing, bit 7 of the address byte
PROC7F) are not all necessarily unique routines. A large switches between two physical address spaces. Values
number of special control codes couldeach be processed between 0 and 127 (00H-7FH) define bits in internal
with their own unique routine, with the remaining RA M locations 20H to 7FH (Figure 18a); address bytes
printing characters all causing a branch to a common between 128 a,nd 255 (80H-OFFH) define bits in the 2 x
routine for entering the character into the output queue. "special-func'tion" register address space (Figure 18b). If
no 2 x "special-function" register corresponds to the
In those rare situations where even 128 options are direct bit address used the result of the instruction is
insufficient, or where the destination routines may cross a
undefined.
2K page boundary, the above approach may be modified
slightly as shown below. Bits so addressed have many wondrous properties. They
may be set, cleared, or complemented with the two byte
Example 25 -256-Way Branch Using Address Look- instructions SETB, CLR, or CPL. Bits may be moved to
Up Tables and from the carry flag with MOV. The logical ANL and
RTEMP EGU R7 ORL functions may be performed between the carry and
.JMP256 MOV
MOV
DPTR.IIADRTBL
A. OPTION
; FIRST ENTRY IN TABLE OF ADDRESSES either the addressed bit or its complement.
CLR C
RLC A MULTIPLY BY 2 FOR 2 BYTE JUMP TABLE
JNC LOWI28
INC DPH Bit Manipulation Instructions - MOV
LOWI28 MOV RTEMP. A ; SAVE ACC FOR HIGH BYTE READ
MOVC A. @A+DPTR ; READ LOW BYTE FROM JUMP TABLE
XCH. A. RTEMP The "MOV" mnemonic can be used to load an
INC A
MOVC A. @A+DPTR ; GET LOW-ORDER BYTE FROM TABLE addressable bit into the carry flag ("MOV C, bit") or to
PUSH ACC
MOV A. RTEMP copy the state of the carry to such a bit ("MOV bit, C").
MOVC A. @A+DPTR ; GET HIGH-ORDER BYTE FROM TABLE
PUSH ACC These instructions are often used for implementing serial
THE TWO ACC PUSHES HAVE PRODUCED
A "RETURN ADDRESS" ON THE STACK WHICH CORRESPONDS I/O algorithms via software or to adapt the standard I/O
TO THE DESIRED STARTING ADDRESS
IT MAY BE REACHED BY POPP ING THE STACK port structure.
INTO THE PC
RET
ADRTBL DW PROCOO ; UP TO 256 CONSECUTIVE DATA It is sometimes desirable to "re-arrange" the order of I/O
DW PROCOI ; WORDS INDICATING STARTING ADDRESSES
pins because of considerations in laying out printed
OW PROCFF
circuit boards. When interfacing the 8051 to an
DUMMY CODE ADDRESS DEFINITIONS NEEDED BY ABOVE immediately adjacent device with "weighted" input pins,
TWO EXAMPLES:
such as keyboard column decoder, the corresponding
PROCOO NOP
PROCOI NOP pins are likely to be not aligned (Figure 19).
PROC02 NOP
PROC7E NOP
PROC7F NOP There is a trade-off in "scrambling" the interconnections
PROCFF NOP
with either interwoven circuit board traces or through
software. This is extremely cumbersome (if not
4. BOOLEAN PROCESSING INSTRUCTIONS impossible) to do with. byte-oriented computer
The commonly accepted terms for tasks at either end of architectures. The 8051'5 unique set of Boolean
the computational vs. control application spectrum are, instructions makes it simple to move individual bits
respectively, "number-crunching" and "bit-banging". between arbitrary locations.
AFN-01502A
8-24
APPLICATIONS
a.) RAM Bit Addresses. b.) Hardware Register Bit Addresses.
RAM Direct Hardware

Bit Addresses
:~~eress
BYTE (MSB) (LSB) (LSB) Register
(MSB) Symbol
7FH
1 I"'
1
.
OFFH
OFOH F7 1 F6 1 F5 1 F41F31F21 F1
1
FO B
2FH 7F 7E 70 7C 7B 7A 79 78 OEOH E7 1 E6 1 E5 E4 1 E3 1 E2 1 E1 EO ACC

1 1
2EH 77 76 75 74 73 72 71 70
20H 6F 6E 60 6C 6B 6A 69 68 OOOH 07 1 06 1 05 1 04 1 03 1 02 1 01 1 DO PSW
2CH 67 66 65 64 63 62 61 60
2BH 5F 5E 50 5C 5B 5A 59 58
2AH 57 56 55 54 53 52 51 50 OB8H - 1 - 1 - 1 BC 1 BB 1 BA 1 B9 B8 IP
1
29H 4F 4E 40 4C 4B 4A 49 48
28H 47 46 45 44 43 42 41 40 OBOH B7 1 B6 1 B51B41B31B21 B1 BO P3

1
27H 3F 3E 3D 3C 3B 3A 39 38
26H 37 36 35 34 33 32 31 30 OA8H AF I- 1 - 1 AC 1 AB I AA I A9 I A8 IE
25H 2F 2E 20 2C 2B 2A 29 28
24H 27 26 25 24 23 22 21 20 OAOH A7 I A6 I A5 I A4 I A3 I A2 I A1 I AO P2
23H 1F 1E 10 1C 1B 1A 19 18
22H 17 16 15 14 13 12 11 10 98H 9FI9EI9019CI 9B I 9A I 99 I 98 SCON
21H OF OE 00 OC OB OA 09 08
20H 07 06 05 04 03 02 01 00 90H 97 1961951941 93 92 I 91 I 90 P1

I
1FH
Bank 3
18H 88H 8F J 8 E J 8 0 J 8 C J 8B 8A 1 89 1 88 TCON
J
17H
Bank 2
80H 87 1861851841 83 82 1 81 I 80 PO
10H I
OFH
Bank 1
08H
07H
Bank 0
OOH
Figure 18. Bit Address Maps
Example 26-Re-ordering I/O Port Configuration

ALE OUT _PZ RRC A ; MOVE ORIGINAL ACC.O INTO CY
MOV P2. 6, C ; STORE CARRY TO PIN P26
RRC A ; MOVE ORIGINAL ACC. I INTO CY
PSEN MOV P2. 5, C ; STORE CARRY TO PIN P25
RRC A ; MOVE ORIGINAL ACC.2 INTO CY
P2.7 RRC A ; MOVE ORIGINAL ACC.3 INTC! CY
RRC ; MOVE ORIGINAL ACC.4 INTO CY
P2.6 AO MOV P2. 2, C ; STORE CARRY TO PIN P22
RET
8351 P2.5 A1
8751
P2.4 A2
DECODER
Solving Combinatorial Logic Equations - ANL, ORL
P2.3 A3
Virtually all hardware designers are familiar with the

P2.2 A4
problem of solving complex functions using
P2.1 combinatorial logic. The technologies involved may vary
greatly, from multiple contact relay logic, vacuum tubes,
P2.0
TTL, or CM OS to more esoteric approaches like fluidics,
but in each case the goal is the same: a Boolean
Figure 19. "Mismatch" Between I/O port and (true/false) function is computed on a number of
. Decoder Boolean variables .
AFN-01502A
8-25
APPLICATIONS
b.) Relay logic.
a.) TTL
CR1
Q = (U (V+W) + (X. V) + Z
z
Figure 20. Implementations of Boolean functions
Figure 20 shows the logic diagram for an arbitrary INPUT, OUTPUT, LOAD, STORE, etc., instead of the
function of six variables named U through Z using universal MOV.
standard logic and relay logic symbols. Each is a solution
of the equation,
Q = (U (V + W + (X Y) + Z
(While this equation could be reduced using Karnaugh
Maps or algebraic techniques, that is not the purpose of
this example. Even a minor change to the function
equation would require re-reducing from scratch.)
Most digital computers can solve equations of this type
with standard word-wide logical instructions and
conditional jumps. Still, such software solutions seem
somewhat sloppy because of the many paths through the
program the computation can take.
Assume U and V are input pins being read by different

input ports; Wand X are status bits for two peripheral
controllers (read as I/O ports), and Y and Z are software
flags set or cleared earlier in the program. The end result
must be written to an output pin on some third port.
For the sake of comparison we will implement this

function with software drawn from three proper subsets
of the MCS-5I'M instruction set. The first two
implementations follow the flow chart shown in Figure
21. Program flow would embark on a route down a test-
and-branch tree and leaves either the "True" or "Not
True" exit ASAP. These exits then write the output port
with the data previously written to the same port with the
result bit respectively one or zero.
In the first case, we assume there are no instructions for
addressing individual bits other than special flags like the
carry. This is typical of many older microprocessors and
(CONTINUE)
mainframe computers designed for number-crunching.
MCS-5I'M mnemonics are used here, though for most
other machines the issue would be even further clouded Figure 21. Flow chart for tree-branching logic
by their use of operation-specific mnemonics like implementation
AFN-01S02A
8-26
APPLICATIONS
Example 27 - Software Solution to Logic Function of These instructions may be "strung together" to simulate a
Figure 20, Using only Byte-Wide Logical multiple input logic gate. When finished, the carry flag
Instructions contains the result, which may be moved directly to the
; BFUNCI SOLVE A RANDOM LOGIC FUNCTION OF 6 destination or output pin. No flow chart is needed - it is
VARIABLES BY LOADING AND MASKING THE APPROPRIATE
BITS IN THE ACCUMULATOR. THEN EXECUTING CONDITIONAL simple to code directly from the logic diagrams in Figure
JUMPS BASED ON ZERO CONDITION
(APPROACH USED BY BYTE-ORIENTED ARCHITECTURES ) 20.
BYTE AND MASK VALUES CORRESPOND TO RESPECTIVE
BYTE ADDRESS AND BIT POS IT I ON
Example 29-Scftware Solution to Logic Function of
OUTBUF EGU 22H ; OUTPUT PIN STATE MAP
;
Figure 20, Using the MCS-5l (TM)
TESTV MOV A. P2
ANL A.IIOOOOOIOOO Unique Logical Instructions on Boolean
JNZ TESTU
MOV A. TCON
Variables
ANL A.IIOOIOOOOOU ; OFUNC3 SOLVE A RANDOM LOGIC FUNCTION OF 6
JZ TEST X VARIABLES USING STRAIGHT-LINE LOGICAL INSTRUCTIONS
TESTU: MOV A. PI ON MCS-51 BOOLEAN VAR I ABLES
ANL A.IIOOOOO0100
JNZ SETG MOV C. V
TESTX: MOV A. TCON ORL C. W ; OUTPUT OF OR GATE
ANL A.IIOOOOIOOOO ANL C. U i OUTPUT OF TOP AND GATE
JZ TESTZ MOV FO. C i SAVE INTERMEDIATE STATE
MOV A.20H MOV C. X
ANL A.IIOOOOOOOIO ANL C./Y i OUTPUT OF BOTTOM AND GATE
JZ SETG ORL C. FO i I NCLUDE VALUE SAVED ABOVE
TESTZ: MOV A.2IH ORL C./Z i INCLUDE LAST INPUT VARIABLE
ANL A. 11000000100 MOV G. C i OUTPUT COMPUTED RESULT
JZ SETG
CLRG MOV A.OUTBUF
ANL A.llllll01110
JMP OUTG Simplicity itself. Fast, flexible, reliable, easy to design,
SETG MOV A.OUTOUF
ORL A.IIOOO010000 and easy to debug.
OUTG MOV OUTBUF. A
MOV P3. A
The Boolean features are useful and unique enough to
Cumbersome, to say the least, and error pron_ ,t would warrant a complete Application Note of their own.
be hard to prove the above example worked. ,11 cases Additional uses and ideas are presented in Application
without an exhaustive test. Note AP-70, Using the Intel MCS-Sl Boolean
Processing Capabilities, publication number 121519.
Each move/mask/conditional jump instruction
sequence may be replaced by a single bit-test instruction
thanks to direct bit addressing. But the algorithm would 5. ON-CHIP PERIPHERAL FUNCTION
be equally convoluted. OPERATION AND INTERFACING
Example 28 - Software Solution to Logic Function of 1/0 Ports

Figure 20, Using only Bit-Test The I/O port versatility results from the "quasi-
Instructions bidirectional" output structure depicted in Figure 22.
(This is effectively the structure of ports I, 2, and 3 for
; BFUNC2 SOLVE A RANDOM LOGIC FUNCTION OF 6
VARIAOLES BY DIRECTLY POLLING EACH OIT
(APPROACH USING MCS-51 UNIGUE BIT-TEST
INSTRUCTION CAPABILITY. )

normal I/O operations. On port resistor R2 is disabled
except during multiplexed bus operations, providing
SYMBOLS USED IN LOGIC DIAGRAM ASSIGNED TO
CORRESPONDING B051 OIT ADDRESSES
BIT PI. 1
BIT P2.2 READ/MODIFY/
BIT TFO WRITE
BIT lEI
OIT 20H.0
OIT 21H. I
OIT P3.3
+5V +5V
TEST _v JO v. TEST_U
JNB W. TEST X
TEST_U JB U. SET 0
TEST_X' JNB x. TEST Z Q
JNB Y. SET_O INTERNAL
TEST _z JNB z. SET_G D
CLR - G' CLR G
BUS
JMP NXTTST
SET G SETB G D
NXTTST ; (CONTINUATION OF PROGRAM) FLIP
FLOP
A more elegant and efficient 8051 implementation uses

the Boolean ANL and ORL functions to generate the
ClK
output function using straight-line code. These WRITE
PUlSE-i_ _ ~
instructions perform the corresponding logical BUS

operations between the carry flag ("Boolean CYCLE
TIMING
Accumulator") and the addressed bit, leaving the result in
INPUT
the carry. Alternate forms of each instruction (specified BUFFER
in the assembly language by placing a slash before the bit READ
name) use the complement of the bit's state as the input
operand. Figure 22. Pseudo-bidirectional 1/0 port circuitry
AFN-01502A
8-27
APPLICATIONS
essentially open-collector outputs, For full electrical Example 30 - Mixing Parallel Output, Input, and
characteristics see the User's Manual.) Control Strobes on Port 2
; IN8243 INPUT DI\TA FROM AN 8243 I' 10 EXPANDER
CoNNECTElJ TO P23-P20
An output latch bit associated with each pin is updated by P25 ~{ P24 MIMIC CS
A
~: PROG
,/
P27-P26 USED AS INPt)TS

direct addressing instructions when that port is the POR T TO BE READ I N Ace
destination. The latch state is buffered to the outside IN8243 ORI,. 1\, III l010000B
M(lV P;l. A ; OUTPUT INSTRUCTION CODE
world by R I and Q I, which may drive a standard TTL CLR p;, 4 ; FALLING EDGE OF PROG
orlL P2.1100001111B ; SET FOR INPUT
input., (In TTL terms, Q I and R I resemble an open- ~IOV (~, P2 ,READ INPUT DATA
SETH p;~ 4 RETURN PROG HIGH
collector output with a pull-up resistor to Vcc.) SETB P:1 5 ; DE-SELECT CHIP
R2 and Q2 represent an "active pull-up" device enabled Serial Port and Timer applications
momentarily when a 0 previously output changes to a I. Configuring the 8051's Serial Port for a given data rate
This "jerks" the output pin to a I level more quickly than and protocol requires essentially three short sections of
the passive pull-up, improving rise-time significantly if
software. On power-up or hardware reset the serial port
the pin is driving a capacitive load. Note that the active
and timer control words must be initialized to the
pull-up is only activated on O-to-I transitions at the
appropriate values. Additional software is also needed in
output latch (unlike the 8048, in which Q2 is activated
the transmit routine to load the serial port data register
whenever a I is written out).
and in the receive routine to unload the data as it arrives.
Operations using an input port or pin as the source This is best illustrated through an arbitrary example.
operand use the logic level ofthe pin itself, rather than the Assume the 8051 will communicate with a CRT
output latch contents. This level is affected by both the operating at 2400 baud (bits per second). Each character
microcomputer itself and whatever device the pin is is transmitted as seven data bits, odd parity, and one stop
connected to externally. The value read is essentially the bit. This results in a character rate of 2400/ 10=240
"0 R-tied" function of Q I and the external device. If the characters per second.
external device is high-impedence, such as a logic gate For the sake of clarity, the transmit and receive
input or a three state output in the third state, then subroutines are driven by simple-minded software status
reading a pin will reflect the logic level previously output. polling code rather than interrupts. (It might help to refer
To use a pin for input, the corresponding output latch back to Figures 7-9 showing the control word formats.)
must be set. The external device may then drive the pin The serial port must be initialized to 8-bit UART mode
with either a high or low logic signal. Thus the same port (MO, M 1=01), enabled to receive all messages (M2=0,
may be used as both input and output by writing ones to REN= I). The flag indicating that the transmit register is
all pins used as inputs on output operations, and ignoring free for more data will be artificially set in order to let the
all pins used as output on an input operation. output software know the output register is available.
This can all be set up with one instruction.
In one operand instructions (INC, DEC, DJNZ and the
Boolean CPL) the output latch rather than the input pin Example 31 - Serial Port Mode and Control Bits
level is used as the source data. Similarly, two operand ; SPINIT INITIALIZE SERIAL PORT
FOR 8-B IT UART MODE
instructions using the port as both one source and the 8< SET TRANSMIT READY FLAG
destination (ANL, ORL, XRL) use the output latches. SPINIT: MOil SCON.1I01010010B
This ensures that latch bits corresponding to pins used as

inputs will not be cleared in the process of executing these
instructions.
8351
8751
The Boolean operation JBC tests the output latch bit, 8243
P4
rather than the input pin, in deciding whether or not to P2.7
} INPUTS
jump. Like the byte-wise logical operations, Boolean P2.6
P2.S CS P5
operations which modify individual pins of a port leave P2.4 PROG
the other bits of the output latch unchanged.
P2.3 P23 P6
P2.2 P22
A good example of how these modes may play together
P2.1 P21
may be taken from the host-processor interface expected P2.0 P20 P7
by an 8243 I/O expander. Even though the 8051 does not
include 8048-type instructions for interfacing with an
8243, the parts can be interconnected (Figure 23) and the Figure 23. Connecting an 8051 with an 8243
protocol may be emulated with simple software. 1/0 Expander
AFN-01S02A
B-28
APPLICATIONS
Timer I will be used in auto-reload mode as a data rate 6. SUMMARY

generator. To achieve a data rate of 2400 baud, the timer
This Application Note has described the architecture,
must divide the I M Hz internal clock by 32 x (desired instruction set, and on-chip peripheral features of the
data rate): first three members of the MCS-SI'M microcomputer
family. The examples used throughout were admittedly
I X 106 (and necessarily) very simple. Additional examples and
(32) (2400) techniques may be found in the MCS-SI User's Manual
and other application notes written for the M CS-48 n .. and
which equals 13.02 rounded down to 13 instruction MCS-SITM families,
cycles. The timer must reload the value -13, or OF3H.
(ASMSI will accept both the signed decimal or hexa- Since its introduction in 1977, the MCS-48 family has
decimal representations.) become the industry standard single-chip
microcomputer. The M CS-SI architecture expands the
Example 32 - Initializing Timer Mode and Control Bits addressing capabilities and instruction set of its
; TI INIT INITIALIZE TIMER I FOR predecessor while ensuring flexibility for the future, and
AUTO-RELOAD AT 32*2400 HZ
(TO USED AS GATED 16-B IT COUNTER ) maintaining basic software compatability with the past.
TIINIT MOV TCON,IIIIOIOOIOB
MOV THI,II-13 Designers already familiar with the 8048 or 8049 will be.
SETB TRI
able to take with them the education and experience
gained from past designs as ever-increasing system
A simple subroutine to transmit the character passed to it
performance demands force them to move on to state-of-
in the accumulator must first compute the parity bit,
the-art products. Newcomers will find the power and
insert it into the data byte, wait until the transmitter is
regularity of the 80S I instruction set an advantage in
available, output the character, and return. This is nearly
streamlining both the learning and design processes.
as easy said as done.
Microcomputer system designers will appreciate the 80S I
Example 33 -Code for UART Output, Adding Parity, as basically a single-chip solution to many problems
Transmitter Loading which previously required board-level computers.
; SP OUT ADD ODD PAR ITY TO ACC AND Designers of real-time control systems will find the high
- TRANSMIT WHEN SERIAL PORT READY
execution speed, on-chip peripherals, and interrupt
SP _OUT MOV C, P
CPL C capabilities vital in meeting the timing constraints of
MOV ACC.7,C
JNB TJ. $ products previously requiring discrete logic designs. And
CLR TI
MOV SBUF, A designers of industrial controllers will be able to convert
RET
ladder diagrams directly from tested-and-true TTL or
relay-logic designs to microcomputer software, thanks to
A simple minded routine to wait until a character is
the unique Boolean processing capabilities.
received, set the carry flag if there is afr odd-parity error,
and return the masked seven-bit code in the accumulator It has not been the intent of this note to gloss over the
is equally short. difficulty of designing microcomputer-based systems. To
be sure, the hardware and software design aspects of any
Example 34-Code for UART Reception and Parity
new computer system are nontrivial tasks. However, the
Verification
system speed and level of integration of the M CS-SI
; SP _IN INPUT NEXT CHARACTER FROM SERIAL PORT
SET CARRY I FF ODD-PAR lTY ERROR microcomputers, the power and flexibility of the
SP - IN JNB RI, $ instruction set, and the sophisticated assembler aI1d other
CLR RI
MOV A, SBUF support products combine to give both the hardware and
MOV C, P
CPL C
software designer as much of a head start on the problem
ANL A,1I7FH
RET as possible.
AFN-01S02A
8-29
,
;111
1. INTRODUCTION The CPU in each microcomputer is one of the industry's
The Intel microcontroller family now has three new fastest and most efficient for numerical calculations on
me~bers - the lntel 8031, 8051, and 8751 single-chip
byte operands. But controllers often deal with bits, not
microcomputers. These devices, shown in Figure I, will bytes: in the real world, switch contacts can only be open
allow whole new classes of products to benefit from recent or closed, indicators should be either lit or dark, motors
advances in Integrated Electronics. Thanks to Intel's new are either turned on or off, and so forth. For such control
H MOS technology, they provide larger program and situations the most significant aspect of the M CS-5 pM
data memory spaces, more flexible 110 and peripheral architecture is its complete hardware support for one-bit,
capabilities, greater speed, and lower system cost than any or Boolean variables (named in honor of Mathematician
previous-generation single-chip microcomputer. George Boole) as a separate data type.
The 8051 incorporates a number of special features which

-vee support the direct manipulation and testing of individual
- po.o bits and allow the use of single-bit variables in performing
- PO.1
logical operations. Taken together, these features are
- PO.2
referred to as the M CS-5l Boolean Processor. While the
- PO.3
- PO.4
bit-processing capabilities alone would be adequate to
- po.s solve many control applications, their true power comes
- PO.6 when they are used in conjunction with the microcompu-
- PO.7 ter's byte-processing and numerical capabilities.
- VDD/EA
Many concepts embodied by the Boolean Processor will

- PSEN
certainly be new even to experienced microcomputer sys-
- P2.7
tem designers. The purpose of this Application Note is to
- P2.6
explain these concepts and show how they are used. It is
- P2.S
- P2.4
assumed the reader has read Application Note AP-69, An
- P2.3
Introduction to the Intel MCS-SrM Single-Chip Micro-
computer Family, publication number 121518, or has
- P2.1 been exposed to Intel's single-chip microcomputer pro-
- P2.0 duct lines.
Figure 1. 8051 Family Pinout Diagram. For detailed information on these parts refer to the Intel
MCS-SrM Family User's Manual, publication number
Table 1 summarizes the quantitative differences between 121517. The instruction set, assembly language, and use of
the members of the MCS-48 and 8051 families. The 8751 the 8051 assembler (ASM51) are further described in the
contains 4K bytes of EPROM program memory fabri- MCS-SrM Macro Assembler User's Guide, publication
cated on-chip, while the 8051 replaces the EPROM with number 9800937.
4K bytes of lower-cost mask-programmed ROM. The
8031 has no program memory on-chip; instead, it accesses
up to 64K bytes of program memory from external 2. BOOLEAN PROCESSOR OPERATION
memory. Otherwise, the three new family members are The Boolean Processing capabilities of the 8051 are based
identical. Throughout this Note, the term "8051" will on concepts which have been around for some time. Dig-
represent all members of the 8051 Family, unless specifi- ital computer systems of widely varying designs all have
cally stated otherwise. four functional elements in common (Figure 2):
Table 1. Features of Intel's Single-chip Microcomputers.
EPROM ROM External Program Data Instr. Inputl Interrupt Reg.

Program Program Program Memory Memory Cycle Output Sources Banks
Memory Memory Memory (Int/Max) (Bytes) Time Pins
- 8021 - IK/IK 64 10 fASec 21 0 I

- 8022 - 2K/2K 64 10 fASec 28 2 I
8748 8048 8035 IK/4K 64 2.5 fASec 27 2 2
- 8049 8039 2K/4K 128 1.36fASec 27 2 2
8751 8051 8031 4K/64K 128 1.0 IlSec 32 5 4
01489A
C-1
a central processor (CPU) with the control, timing, processors might first re-create Shakespeare's classics
and logic circuits needed to execute stored and this Application Note)! This fact offers little consola-
instructions; tion to product designers who want programs to run as
quickly as possible. By definition, a real-time control algo-
a memory to store the sequence of instructions rithm must proceed quickly enough to meet the preor-
making up a program or algorithm; dained speed constraints of other equipment.
data memory to store variables used by the program; One of the factors determining how long it will take a
and microcomputer to complete a given chore is the number of
instructions it must execute. What makes a given compu-
some means of communicating with the outside ter architecture particularly well-or poorly-suited for a
world. class of problems is how well its instruction set matches
the tasks to be performed. The better the "primative"
operations correspond to the steps taken by the control
algorithm, the lower the number of instructions needed,
and the quicker the program will run. All else being equal,
PROGRAM
a CPU supporting 64-bit arithmetic directly could clearly
L
MEMORY
perform floating-point math faster than a machine

bogged-down by multiple-precision subroutines. In the
INPUT/
same way, direct support for bit manipulation naturally
~~~
OUTPUT
PORTS
leads to more efficient programs handling the binary in put
and output conditions inherent in digital control problems.
Processing Elements
The introduction stated that the 8051 's bit-handling capa-
Figure 2. Block Diagram for Abstract Digital bilities alone would be sufficient to solve some control
Computer. applications. Let's see how the four basic elements of a
The CPU usually includes one or more accumulators or digital computer - a CPU with associated registers, pro-
special registers for computing or storing values during gram memory, addressable data RAM, and I/O capabil-
program execution. The instruction set of such a proces- ity - relate to Boolean variables.
sor generally includes, at a minimum, operation classes to
perform arithmetic or logical functions on program vari- cpu. The 8051 CPU incorporates special logic devoted to
ables, move variables from one place to another, cause executing several bit-wide operations. All told, there are
program execution to jump or conditionally branch based 17 such instructions, all listed in Table 2. Not shown are 94
on register or variable states, and instructions to call and other (mostly byte-oriented) 8051 instructions.
return from subroutines. The program and data memory
functions sometimes share a single memory space, but this Program Memory. Bit-processing instructions are fetched
is not always the case. When the address spaces are separ- from the same program memory as other arithmetic and
ated, program and data memory need not even have the logical operations. In addition to the instructions of Table
same basic word width. 2, several sophisticated program control features like mul-
tiple addressing modes, subroutine nesting, and a two-
A digital computer's flexibility comes in part from com- level interrupt structure are useful in structuring Boolean
bining simple fast operations to produce more complex Processor-based programs.
(albeit slower) ones, which in turn link together eventually
solving the problem at hand. A four-bit CPU executing Boolean instructions are one, two, or three bytes long,
multiple precision subroutines can, for example, perform depending on what function they perform. Those involv-
64-bit addition and subtraction. The subroutines could in ing only the carry flag have either a single-byte opcode or
turn be building blocks for floating-point mUltiplication an opcode followed by a conditional-branch destination
and division routines. Eventually, the four-bit CPU can byte (Figure 3.a). The more general instructions add a
simulate a far more complex "virtual" machine. "direct address" byte after the opcode to specify the bit
affected, yielding two or three byte encodings (Figure 3.b).
In fact, any digital computer with the above four func- Though this format allows potentially 256 directly addres-
tional elements can (given time) complete any algorithm sable bit locations, not all of them are implemented in the
(though the proverbial room full of chimpanzees at word 8051 family.
01489A
C-2
At"t"LI\,;A IIUN::
Table 2. MCS-S1TM Boolean Processing Instruction

Subset.
opcode
Mnemonic Description Byte Cyc

SETB C
SETB C Set Carry flag I CLR C
SETB bit Set direct Bit 2 CPL C
CLR C Clear Carry flag I
CLR bit Clear direct bit 2
CPL C Complement Carry flag I
CPL bit Complement direct bit 2 ,-_o_p_c_o_d_e_...J displacement
11
MOV C,bit Move direct bit to Carry flag 2 I JC rei

MOV bit,C Move Carry flag to direct bit 2 2
JNC rei
ANL C,bit AND direct bit to Carry flag 2 2
ANL C,/bit AND complement of direct bit to 2 2 a.) Carry Control and Test Instructions.
Carry flag
ORL C,bit OR direct bit to Carry flag 2 2
ORL C,/bit OR complement of direct bit to
Carry flag
2 2 opcode
II bit address
JC reI Jump if Carry is flag is set 2 2 SETB bit

JNC rei Jump if No Carry flag 2 2
JB bit,rel Jump if direct Bit set 3 2 CLR bit
JNB bit,rel Jump if direct Bit Not set 3 2 CPL bit
JBC bit,rei Jump if direct Bit is set & Clear bit 3 2 ANLC, bit
ANL C,I bit
Address mode abbreviations: ORLC, bit
ORL C,I bit
C Carry flag. MOVC, bit
MOV bit,C
bit 128 software flags, any I/O pin, control or status
bit
opcode bit address displacement
reI - All conditional jumps include an 8-bit offset byte.
II
Range is + 127/ -128 bytes relative to first byte of JB bit, rei
the following instruction. JNB bit, rei
JBC bit. rei
b.) Bit Manipulation and Test Instructions.
Figure 3. Bit Addressing Instruction Formats.
Data Memory. The instructions in Figure 3.b can operate Direct Bit Addressing
directly upon 144 general purpose bits forming the Boo- The most significant bit of the direct address byte selects
lean processor "RAM." These bits can be used as sofware one of two groups of bits. Values between 0 and 127 (00 H
flags or to store program variables. Two operand instruc- and 7FH) define bits in a block of 32 bytes of on-chip
tions use the CPU's carry flag ("C") as a special one-bit RAM, between RAM addresses 20H and 2FH (Figure
register; in a sense, the carry is a "Boolean accumulator" 4.a). They are numbered consecutively from the lowest-
for logical operations and data transfers. order byte's lowest-order bit through the highest-order
byte'S highest-order bit.
Input/ Output. All 32 I/O pins can be addressed as indi-
vidual inputs, outputs, or both, in any combination. Any Bit addresses between 128 and 255(80H and OFFH) cor-
pin can be a control strobe output, status (Test) input, or respond to bits in a number of special registers, mostly
serial I/O link implemented via software. An additional used for I/O or peripheral control. These positions are
33 individually addressable bits reconfigure, control, and numbered with a different scheme than RAM: the five
monitor the status of the CPU and all on-chip peripheral high-order address bits match those of the register's own
functions (timer/counters, serial port modes, interrupt address, while the three low-order bits identify the bit
logic, and so forth). position within that register (Figure 4.b).
01489A
C-3
,",r r "'1"''"'1 1"' .... 0.1
Direct Bit Addresses Hardware

RAM Byte Register
Byte (MS8) (LSB) Addre!! (MSB) (lSB) Symbo!
7FH~ 1--";:"" 1--

OFFH
OFOH F7 FO B
2FH 7F 7E 70 7C 7B 7A 79 78
2EH 77 76 75 74 73 72 71 70 OEOH E7 EO ACC
20H 6F 6E 60 6C 68 6A 69 68
2CH 67 66 65 64 63 62 61 60 OOOH 07 DO PSW
2BH SF 5E 50 5C 5B SA 59 58
2AH 57 56 55 54 53 52 51 50 OB8H B8 IP
29H 4F 4E 40 4C 4B 4A 49 48
28H 47 46 45 44 43 42 41 40 OBOH B7 BO P3
27H 3F 3E 3D 3C 3B 3A 39 38
26H 37 36 35 34 33 32 31 30 OA8H AF A8 IE
25H 2F 2E 20 2C 2B 2A 29 28
24H 27 26 25 24 23 22 21 20 OAOH A7 AO P2
23H 1F 1E 10 1C 1B 1A 19 18
22H 17 16 15 14 13 12 11 10 98H 9F 98 SCON
21H OF OE 00 OC OB OA 09 08
20H 07 06 05 04 03 02 01 00 90H 97 90 P1
1FH
18H Bank 3
17H
88H 8F 88 TCON
10H Bank 2
OFH
08H Bank 1
07H
80H 87 80 PO
Bank 0
00
a.) RAM Bit Addresses. b.) Special Function Register Bit Addresses.
Figure 4. Bit Address Maps.
Notice the column labeled "Symbol"in Figure 5. Bits with Figure 7 shows the last four bit addressable registers.
special meanings in the PSW and other registers have TCON (Timer Control) and SCON (Serial port Control)
corresponding symbolic names. General-purpose (as control and monitor the corresponding peripherals, while
opposed to carry-specific) instructions may access the IE (Interrupt Enable) and IP (Interrupt Priority) enable
carry like any other bit by using the mnemonic CY in place and prioritize the five hardware interrupt sources. Like the
of C, PO, PI, P2, and P3 are the 8051 's four I 10 ports; reserved hardware register addresses, the five bits not
secondary functions assigned to each of the eight pins of implemented in I E and I P should not be accessed; they can
P3 are shown in Figure 6. not be used as software flags.
01489A
C-4
At"'t"'LI "'''' I IVI"'~
(MSB) (LSB)
I I I I I I
Cy AC FO RSl RSO OV P
OV PSW.2 Overflow flag.
Symbol Position Name and significance Set/cleared by hardware during
CY PSW.7 Carry flag. arithmetic instructions to indicate
Set/cleared by hardware or soft- overflow conditions.
ware during certain arithmetic and
logical instructions. PSW.1 (reserved)
AC PSW.6 Auxiliary Carry flag. P PSW.O Parity flag.

Set/cleared by hardware during Set/cleared by hardware each in-
addition or subtraction instruc- struction cycle to indicate an odd/-
tions to indicate carry or borrow even number of "one" bits in the
out of bit 3. accumulator, i.e., even parity.
FO PSW.5 Flag O. Note - the contents of (RS1 , RSO) enable

Set/cleared/tested by software as the working register banks as
a user-defined status flag. follows:
RS1 PSW.4 Register bank Select control bits (0,0) - Bank 0 (00H-07H)
RSO PSW.3 1 & O. Set/cleared by software to (0,1) - Bank 1 (OBH-OFH)
determine working register bank (1,0) - Bank 2 (10H-17H)
(see Note). (1,1)-Bank3 (1BH-1 FH)
Figure 5. PSW - Program Status Word organization.
(MSB) (LSB)
I I I T1
RO WR TO IINnllNTO I TXO I I
RXD
Symbol Position Name and significance

RD P3.7 Read data control output. INT1 P3.3 Interrupt 1 input pin.
Active low pulse generated by Low-level or falling-edge
hardware when external data triggered.
memory is read.
INTO P3.2 Interrupt 0 input pin.
WR P3.6 Write data control output. Low-level or falling-edge
Active low pulse generated by triggered.
hardware when external data
memory is written. TXD P3.1 Transmit Data pin for serial port
in UART mode. Clock output in
T1 P3.5 Timer/counter 1 external input or shift register mode.
test pin.
RXD P3.0 Receive Data pin for serial port in
TO P3.4 Timer/counter 0 external input or UART mode. Data 110 pin in shift
test pin. register mode.
Figure 6. P3 - Alternate I/O Functions of Port 3.

01489A
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(MSB) (lSB)
!T1 !EO II ITO II iEi TCON.3 Interrupt 1 Edge flag.

Set by hardware when external
Symbol Position Name and significance interrupt edge detected. Cleared
TF1 TCON.? Timer 1 overflow Flag. when interrupt processed.
Set by hardware on
timer/counter overflow. Cleared IT1 TCON.2 Interrupt 1 Type control bit.
when interrupt processed. Set/cleared by software to
specify falling edge/low level
TR1 TCON.6 Timer 1 Run control bit. triggered external interrupts.
Set/cleared by software to turn
timer/counter on/off. lEO TCON.1 Interrupt a Edge flag.
Set by hardware when external
TFO TCON.5 Timer a overflow Flag. interrupt edge detected. Cleared
Set by hardware on when interrupt processed.
timer/counter overflow. Cleared
when interrupt processed. ITO TCON.O Interrupt a Type control bit.
Set/cleared by softrware to
TRO TCON.4 Timer a Run control bit. specify falling edge/low level
Set/cleared by software to turn triggered external interrupts.
timer/counter on/off.
a.) TCON - Timer/Counter Control/status register.
(MSB) (lSB)
I I
SMO SMl SM21 I REN ITBBI RBBI TI
SMa SCON.? Serial port Mode control bit O.
RB8 SCON.2 Receive Bit 8.
Set/cleared by software (see
Set/cleared by hardware to indi-
note).
cate state of ninth data bit
received.
SM1 SCON.6 Serial port Mode control bit 1.
Set/cleared by software (see
TI SCON.1 Transmit Interrupt flag.
note).
Set by hardware when byte
transmitted. Cleared by software
SM2 SCON.5 Serial port Mode control bit 2.
after servicing.
Set by software to disable recep-
tion of frames for which bit 8 is
RI SCON.O Receive Interrupt flag.
zero.
Set by hardware when byte re-
ceived. Cleared by software after
REN SCON.4 Receiver Enable control bit.
servicing.
Set/cleared by software to
enable/disable serial data
Note - the state of (SMO,SM1) selects:
reception.
(O,O) - Shift register 110 expansion.
(0,1) - 8 bit UART, variable data rate.
TB8 SCON.3 Transmit Bit 8.
(1,0) - 9 bit UART, fixed data rate.
Set/cleared by hardware to deter-
(1,1) - 9 bit UART, variable data rate.
mine state of ninth data bit trans-
mitted in 9-bit UART mode.
b.) SCON - Serial Port Control/status register.
Figure 7. Peripheral Configuration Registers.
01489A
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APPLICATIONS
(MSB) (LSB)
ES [ ET1 [ EX1 [ ET1 [ EXO [

EA IE.? Enable All control bit. EX1 IE.2 Enable External interrupt 1
Cleared by software to disable all control bit. Set/cleared by
interrupts, independent of the software to enable/disable
state of IE.4 - IE.O. interrupts from INT1.
IE.6 (reserved) ETO IE.1 Enable Timer 0 control bit.

IE.5 Set/cleared by software to
enable/ disable interrupts from
ES IE.4 Enable Serial port control bit. timer/counter O.
enable/ disable interrupts from EXO IE.O Enable External interrupt 0
TI or RI flags. control bit. Set/cleared by
software to enable/disable
ET1 IE.3 Enable Timer 1 control bit. interrupts from INTO.
enable/ disable interrupts from
timer/counter 1.
c.) IE - Interrupt Enable Register.
(MSB) (LSB)
[ - [ PS PT1 [ PX1 [ PTO [ PXO [
Symbol Position Name and significance PX1 IP.2 External interrupt 1 Priority
IP.? (reserved) control bit. Set/cleared by
IP.6 (reserved) software to specify high/low
IP.5 (reserved) priority interrupts for INT1.
PS IP.4 Serial port Priority control bit. PTO IP.1 Timer 0 Priority control bit.
Set/cleared by software to Set/cleared by software to
specify high/low priority specify high/lolt/ priority
interrupts for Serial port. interrupts for tirndr/counter O.
PT1 IP.3 Timer 1 Priority control bit. PXO IP.O External interrupt 0 Priority
Set/cleared by software to control bit. Set/cleared by
specify high/low priority software to specify high/low
interrupts for timer/counter 1. priority interrupts for INTO.
d.) IP - Interrupt Priority Control Register.
Figure 7. (continued)
Addressable Register Set. There are 20 special function
registers in the 8051, but the advantages of bit addressing
only relate to the II described below. Five potentially The accumulator and B registers (A and B) are normally
bit-addressable register addresses (OCOH, OC8H, OD8H, involved in byte-wide arithmetic, but their individual bits
OE8H, & OF8H) are being reserved for possible future can also be used as 16 general software flags. Added with
expansion in microcomputers based on the MCS-5 I'M the 128 flags in RAM, this gives 144 general purpose
architecture. Reading or writing non-existent registers in variables for bit-intensive programs. The program status
the 8051 series is pointless, and may cause unpredictable word (PSW) in Figure 5 is a collection of flags and
results. Byte-wide logical operations can be used to machine status bits including the carry flag itself. Byte
manipulate bits in all non-bit addressable registers and operations acting on the PSW can therefore affect the
RAM. carry.
01489A
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At't'LI\,;A IIUN~
Instruction Set
Having looked at the bit variables available to the Boolean
Processor, we wiii now iook at the four classes of instructions
that manipulate these bits. It may be helpful to refer back to
Table 2 while reading this section.
State Control. Addressable bits or flags may be set, cleared,

or logically complemented in one instruction cycle with the
two-byte instructions SETB, CLR, and CPL. (The "B"
affixed to SETB distinguishes it from the assembler "SET"
directive used for symbol definition.) SETB and CLR are
analogous to loading a bit with a constant: I or O. Single
byte versions perform the same three operations on the
carry.
The M CS-5 I'M assembly language specifies a bit address in

any of three ways:
bya number or expression corresponding to the direct

bit address (0-255);
Figure 8. Bit Transfer Instruction Operation.
by the name or address of the register containing the
bit, the dot operator symbol (a period: ". "), and the slash mark ("j") before the source operand indicates whether
bit's position in the register (7-0); to use the positive-logic value or the logical complement of
the addressed bit. (The source operand itself is never
in the case of control and status registers, by the prede- affected.)
fined assembler symbols listed in the first columns
of Figures 5-7. Bit-test Instructions. The conditional jump instructions "JC
rei" (Jump on Carry) and "JNC rei" (Jump on Not Carry)
Bits mayalso be given user-defined names with the assembler test the state of the carry flag, branching if it is a one or zero,
"BIT" directive and any of the above techniques. For exam- respectively. (The letters "rei" denote relative code address-
ple, bit 5 of the PSW may be cleared by any of the four ing.) The three-byte instructions "JB bit, rei" and "JNB
instructi ons, bit,rel" (Jump on Bit and Jump on Not Bit) test the state of
any addressable bit in a similar manner. A fifth instruction.
USR_FLG BIT PSW.5 User Symbol Definition combines the Jump on Bit and Clear operations. "JBC
bit,rel" conditionally branches to the indicated address, then
CLR OD5H Absolute Addressing clears the bit in the same two cycle instruction. This opera-
CLR PSW.5 Use of Dot Operator tion is the same as the MCS-48 "JTF" instructions.
CLR FO Pre-Defined Assembler
Symbol All 8051 conditional jump instructions use program
CLR USILFLG User-Defined Symbol counter-relative addressing, and all execute in two cycles.
The last instruction byte encodes a signed displacement
Data Transfers. The two-byte MOV instructions can trans- ranging from -128 to + 127. During execution, the CPU adds
port any addressable bit to the carry in one cycle, or copy the this value to the incremented program counter to produce
carry to the bit in two cycles. A bit can be moved between the jump destination. Put another way, a conditional jump
two arbitrary locations via the carry by combining the two to the immediately following instruction would encode OOH
instructions. (If necessary, push and pop the PS W to preserve in the offset byte.
the previous contents of the carry.) These instructions can
replace the multi-instruction sequence of Figure 8, a program A se~tion of program or subroutine written using only rela-
structure appearing in controller applications whenever flags tive jumps to nearby addresses will have the same machine
or outputs are conditionally switched on or off. code independent of the code's location. An assembled rou-
tine may be repositioned anywhere in memory, even crossing
Logical Operations. Four instructions perform the logical- memory page boundaries, without having to modify the
AND and logical-OR operations between the carry and program or recompute destination addresses. To facilitate
another bit, and leave the results in the carry. The instruction this flexibility, there is an unconditional "Short Jump"
mnemonics are ANL and ORL; the absence or presence ofa (SJ M P) which uses relative addressing as well. Since a pro-
01489A
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APPLICATIONS
grammer would have quite a chore trying to compute rela- Table 3. Other Instructions Affecting the Carry
tive offset values from one instruction to another, AS M 51 Flag.
automatically computes the displacement needed given only
the destination address or label. An error message will alert Mnemonic Description Byte Cyc
the programmer if the destination is "out of range."
ADD A.Rn Add register to
Accumulator
(The so-called "Bit Test" instructions implemented on many ADD A.direct Add direct byte to
other microprocessors simply perform the logical-AND Accumulator
operation between a byte variable and a constant mask, and ADD A.@Ri Add indirect RAM to
set or clear a zero flag depending on the result. This is Accumulator
ADD A.#data Add immediate data to
essentially equivalent to the 8051 "MOY Cbit" instruction. Accumulator
A second instruction is then needed to conditionally branch ADDC A.Rn Add register to
based on the state of the zero flag. This does not constitute Accumulator with Carry
abstract bit-addressing in the MCS-5 I'M sense. A flag exists flag
only as a field within a register~ to reference a bit the pro- ADDC A. direct Add direct byte to
Accumulator with Carry
grammer must know and specify both the encompassing flag
register and the bit's position therein. This constraint ADDC A.@Ri Add indirect RAM to
severely limits the flexibility of symbolic bit addressing and Accumulator with Carry
reduces the machine's code-efficiency and speed.) flag
ADDC A.#data Add immediate data to
Acc with Carry flag
Interaction with Other Instructions. The carry flag is also
SUBB A.Rn Subtract register from
affected by the instructions listed in Table 3. It can be rotated Accumulator with
through the accumulator, and altered as a side effect of borrow
arithmetic instructions. Refer to the User's Manual for SUBB A.direct Subtract direct byte
details on how these instructions operate. from Acc with borrow
SUBB A.@Ri Subtract indirect RAM
from Acc with borrow
Simple Instruction Combinations SUBB A.#data Subtract immediate data
By combining general purpose bit operations with certain from Acc with borrow 1
MUL AB Multiply A & B 4
addressa ble bits, one can "custom build" several hundred
DIY AB Divide A by B 4
useful instructions. All eight bits of the PSW can be tested DA A Decimal Adjust
directly with conditional jump instructions to monitor Accumulator
(among other things) parity and overflow status. Pro-
grammers can take advantage of 128 software flags to keep RLC A Rotate Accumulator
Left through the Carry
track of operating modes, resource usage, and so forth.
flag
RRC A Rotate Accumulator
The Boolean instructions are also the most efficient way to Right through Carry flag
control or reconfigure peripheral and I/O registers. All 32
I/O lines become "test pins," for example, tested by condi- . CINE A.direct.relCompare direct byte to
Acc & Jump if Not
tional jump instructions. Any output pin can be toggled
Equal 2
(complemented) in a single instruction cycle. Setting or clear- CINE A.#data.rel Compare immediate to
ing the Timer Run flags (TRO and TR I) turn the timer- Acc & Jump if Not
/ counters on or off~ polling the same flags elsewhere lets the Equal
program determine if a timer is running. The respective CINE Rn.#data.rel Compare immed to
register & Jump if Not
overflow flags (TFO and TFI) can be tested to determine
Equal 2
when the desired period orcount has elapsed, then cleared in CINE @Ri.#data.reICompare immed to
preparation for the next repetition. (For the record, these indirect & Jump if Not
bits are all part of the TCON register, Figure 7.a. Thanks to Equal
symbolic bit addressing, the programmer only needs to
remember the mnemonic associated with each function. In
other words, don't bother memorizing control word layouts.)
I n the M CS-48 family, instructions corresponding to some

of the above functions require specific opcodes. Ten different
opcodes serve to clear I complement the software flags FO
and Fl, enable I disable each interrupt, and start/ stop the
timer. In the 8051 instruction set, just three opcodes (SETB, All mnemonics copyrighted Intel Corporation 1980
01489A
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AI-'I-'LI\,;A IIUN:)
CLR, CPL) with a direct bit address appended perform the using awkward sequences of other basic operations. As
same functions. Two test instructions (JB and JNB) can be mentioned earlier, any CPU can solve any problem given
combined with bit addresses to test the sofnvare flags, the enough time.
8048 110 pins TO, Tl, and INT, and the eight accumulator Quantitatively, the differences between a solution allowed
bits, replacing 15 more different instructions. by the 8051 and those required by previous architectures
are numerous. What the 8051 Family buys you is a faster,
Table 4.a shows how 8051 programs implement software cleaner, lower-cost solution to microcontroller
flag and machine control functions associated with special applications.
The opcode space freed by condensing many specific 8048
Table 4.a. Contrasting 8048 and 8051 Bit Control and Testing Instructions.
8048 8x51
Instruction Bytes Cycles uSec Instruction Bytes Cycles & uSec
Flag Control
CLR C I I 2.5 CLR C I I
CPL FO I I 2.5 CPL FO 2 I
Flag Testing
JNC offset 2 2 5.0 JNC reI 2 2
JFO offset 2 2 5.0 JB FO,rel 3 2
JB7 offset 2 2 5.0 JB ACC.7,rel 3 2
Peripheral Polling
JTO offset 2 2 5.0 JB TO,rel 3 2
JNI offset 2 2 5.0 JNB INTO,rel 3 2
JTF offset 2 2 5.0 JBC TFO,rel 3 2
Machine and Peripheral Control

STRT T I I 2.5 SETB TRO 2 I
EN I I I 2.5 SETB EXO 2 I
DIS TCNT! I I 2.5 CLR ETO 2 I
Table 4.b. Replacing 8048 instruction sequences with single 8x51 Instructions.
8048 8051
Instructions Bytes Cycles uSec Instructions Bytes Cycles & uSec
Flag Control
Set carry:
CLR C
SETB C I I
CPL C = 2 2 5.0
Set Software Flag:

CLR FO
SETB FO 2 I
CPL FO = 2 2 5.0
instructions into a few general operations has been used to

opcodes in the 8048. In every case the MCS-5I'M solution add new functionality to the M CS-51 architecture - both
requires the same number of machine cycles, and executes for byte and bit operations. 144 software flags replace the
2.5 times faster. 8048's two. These flags (and the carry) may be directly set,
not just cleared and complemented, and all can be tested.
for either state, not just one. Operating mode bits pre-
3. BOOLEAN PROCESSOR APPLICATIONS viously inaccessible may be read, tested, or saved. Situa-
So what? Then what does all this buy you? tions where the 8051 instruction set provides new capabili-
ties are contrasted with 8048 instruction sequences
Qualitatively, nothing. All the same capabilities could be in Table 4.b. Here the 8051 speed advantage ranges from
(and often have been) implemented on other machines 5x to 15x!
01489A
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APPLICATIONS
Table 4b (Continued)
8048 8x51
Instructions Bytes Cycles uSec Instructions Bytes Cycles & uS~c
Turn Off Output Pin:
ANL PI,#OFBH = 2 2 5.0 CLR PI.2 2 I
Complement Output Pin:

IN A,PI
XRL A,#04H
aUTL PI,A = 4 6 15.0 CPL PI.2 2 I
Clear Flag in RAM:

May RO,#FLGADR
May A,@RO
ANL A,#FLGMASK
May @RO,A = 6 6 15.0 CLR USER_FLG 2 I
Flag Testing
Jump if Software Flag is 0:
JFO $+4
JMP offset = 4 4 10.0 JNB FO,rel 3 2
Jump if Accumulator bit is 0:

CPL A
JB7 offset
CPL A = 4 4 10.0 JNB ACC.7,rel 3 2
Peripheral Polling
Test if Input Pin is Grounded:
IN A,PI
CPL A
JB3 offset = 4 5 12.5 JNB PI.3,rel 3 2
Test if Interrupt Pin is High:

JNI $+4
JMP offset = 4 4 10.0 JB INTO,rel 3 2
three compare the 8051 with other microprocessors; the last

Combining Boolean and byte-wide instructions can pro- two go into 805I-based system designs in much greater
duce great synergy. An MCS-5 I'M based application will depth.
prove to be:
simpler to write since the architecture correlates more Design Example #1 - Bit Permutation
closely with the problems being solved; First off, we'll use the bit-transfer instructions to permute
a lengthy pattern of bits.
easier to debug because more individual instructions
have no unexpected or undesirable side-effects; A steadily increasing number of data communication
products use encoding methods to protect the security of
more byte efficient due to direct bit addressing and sensitive information. By law, interstate financial transac-
program counter relative branching; tions involving the Federal banking system must be
transmitted using the Federal Information Processing
faster running because fewer bytes of instruction need Data Encryption Standard (DES).
to be fetched and fewer conditional jumps are
processed; Basically, the DES combines eight bytes of "plaintext"
data (in binary, ASCII, or any other format) with a 56-bit
lower cost because of the high level of system- "key", producing a 64-bit encrypted value for transmis-
intergration within one component. sion. At the receiving end the same algorithm is applied to
the incoming data using the same key, reproducing the
These rather unabashed claims of excellence shall not go original eight byte message. The algorithm used for these
unsubstantiated. The rest of this chapter examines less permutations is fixed; different user-defined keys ensure
trivial tasks simplified by the Boolean processor. The first data privacy.
01489A
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At't'LI\iA IIUN~
It is not the purpose of this note to describe the DES in any The bit manipulation performed is typified by the Key
detail. Suffice it to say that encryption/ decryption is a Schedule Calculation represented in Figure 9. This step is
long, iterative piOCCSS consisting of rotations, exciusivt: repeated i6 tiIm:s fur t::a<.:h kt::y ust::d in ihe course of a
-OR operations, function table look-ups, and an extensive transmission. In essence, a seven-byte, 56-bit "Shifted Key
(and quite bizarre) sequence of bit permutation, packing, Buffer" is transformed into an eight-byte, "Permutation
and unpacking steps. (For further details refer to the June Buffer" without altering the shifted Key. The arrows in
21,1979 issue of Electronics magazine.) The bit manipula- Figure 9 indicate a few of the translation steps. Only six
tion steps are included, it is rumored, to impede a general bits of each byte of the Permutation Buffer are used; the
purpose digital supercomputer trying to "break" the code. two high-order bits of each byte are cleared. This means
Any algorithm implementing the DES with previous gen- only 48 of the 56 Shifted Key Buffer bits are used in anyone
eration microprocessors would spend virtually all of its iteration.
time diddling bits.
PERMUTED AND SHIFTED 56-BIT KEY BUFFER
~ ~
-------------------~-------------------- --------------------~-------------------
PERMUTATION BYTE 1 PERM BYTE 2 PERM BYTE 3 PERM BYTE 4 BYTE 5 BYTE 6 PERM BYTE 7 PERM BYTE 8
48-BIT KEY KI
Figure 9. DES Key Schedule Transformation.
Different microprocessor architectures would best imple-

ment this type of permutation in different ways. Most
approaches would share the steps of Figure lO.a:
Initialize the Permutation Buffer to default state

(ones or zeroes);
Isolate the state of a bit of a byte from the Key Buffer.

Depending on the CPU, this might be accomplished
by rotating a word of the Key Buffer through a carry
flag or testing a bit in memory or an accumulator
against a mask byte;
REPEAT
FOR EACH Perform a conditional jump based on the carry or
BIT OF
SHIFTED zero flag if the Permutation Buffer default state is
KEY
BUFFER correct;
(43 TIMES)
SET PERMUTATION (LEAVE PERMUTATION
BUFFER BIT BUFFER BIT
PC2(I) CLEARED) Otherwise reverse the corresponding bit in the permu-
tation buffer with logical operations and mask bytes.
Each step above may require several instructions. The last

three steps must be repeated for all 48 bits. Most micropro-
cessors would spend 300 to 3,000 microseconds on each of
the 16 iterations.
Figure 10.a. Flowchart for Key permutation attemp- Notice, though, that this flow chart looks a lot like Figure 8.
ted with a byte processor. The Boolean Processor can permute bits by simply moving
01489A
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APPLICATIONS
them from the source to the carry to the destination-a Worst-case execution time would be 112 microseconds,
total of two instructions taking four bytes and three since each instruction takes a single cycle. Routine length
microseconds per bit. Assume the Shifted Key Buffer and would also decrease, to 168 bytes. (Actually, in the context
Permutation Buffer both reside in bit-addressable RAM, of the complete encryption algorithm, each permuted byte
with the bits of the former assigned symbolic names S KB_1, would be processed as soon as it is assimilated-saving
SKB~, ... SKB-S6, and that the bytes of the latter are memory and cutting execution time by another 8 usec.)
named PB_I, ... PB_8. Then working from Figure 9, the
software for the permutation algorithm would be that of
Example I.a. The total routine length would be 192 bytes, Example I. DES Key Permutation Software.
requiring 144 microseconds. a.) "Brute Force" technique.
MOY C,SKB_I
The algorithm of Figure 10. b is just slightly more efficient MOY PB_l.1,C
in this time-critical application and illustrates the synergy MOY C,SKB~
of an integrated byte and bit processor. The bits needed for MOY PB_4.O,C
each byte of the Permutation Buffer are assimilated by MOY C,SKB.3
loading each bit into the carry (I usec.) and shifting it into MOY PB~.5,C
the accumulator (I usec.). Each byte is stored in RAM MOY C,SKB_4
when completed. Forty-eight bits thus need a total of 112 MOY PB_1.0,C
instructions, some of which are listed in Example 1.b.
MOY C,SKB-S5
MOY PB-S.O,C
MOY C,SKB-S6
MOY PB_7.2,C
b.) Using Accumulator to Collect Bits.

CLR A
MOY C,SKB_14
RLC A
MOY C,SKB_17
RLC A
MOY C,SKB_II
RLC A
MOY C,SKB~4
REPEAT
FOR EACH RLC A
BYTE OF
PERMUTATION MOY C,sKB_I
BUFFER
(STIMES) RLC A
MOY C,SKB-S
RLC A
MOY PB_I,A
MOY C,SKB-29
RLC A
MOY C,SKB_32
RLC A
MOY PB_8,A
To date, most banking terminals and other systems using

the DES have needed special boards or peripheral con-
troller chips just for the encryption/ decryption process,
and still more hardware to form a serial bit stream for
transmission (Figure II.a). An 8051 solution could pack
Figure 10.b. DES Key Permutation most of the entire system onto the one chip (Figure Il.b).
with Boolean Processor. The whole DES algorithm would require less than one-
01489A
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At't'LIGAIIUNS
fourth of the on-chip program memory, with the remaining interrupt.) Data is received by testing an input pin, setting
bytes free for operating the banking terminal (or whatever) the carry to the same state, shifting the carry into a data buffer,
itself. and saving the partiai frame in internal RAM. Data is
transmitted by shifting an output buffer through the carry,
Moreover, since transmission and reception of data is and generating each bit on an output pin.
performed through the on-board UART, the unencrypted
data (plaintext) never even exists outside the micro-
computer! Naturally, this would afford a high degree of
security from data interception.
r- - -l
----~~~~--- I
I
I~~DEM
a.) Using Multi-chip processor technology.
a.) Reception.
TO
8051
IMODEM
b.) Using one Single-chip Microcomputer.
Figure 11. Secure Banking Terminal Block Diagram.
Design Example #2 - Software Serial 1/0

An exercise often imposed on beginning microcomputer
students is to write a program simulating a UART. (See,
for example, Application Notes AP24, AP29, and AP49.)
Though doing this with the 8051 Family may appear to be
a moot point (given that the hardware for a full UART is b.) Transmission.
on-chip), it is still instructive to see how it would be done,
and maintains a product line tradition.
As it turns out, the 8051 microcomputers can receive or

transmit serial data via software very efficiently using the Figure 12. Serial liD Algorithms.
Boolean instruction set. Since any, I /0 pin may be a serial
input or output, several serial links could be maintained at
once.
A side-by-side comparison of the software for this common
Figures 12.a and 12.b show algorithms for receiving or "bit-banging" application with three different micro-
transmitting a byte of data. (Another section of program processor architectures is shown in Table 5.a and 5.b. The
would invoke this algorithm eight times, synchronizing it 8051 solution is more efficient than the others on every
with a start bit, clock signal, software delay, or timer count!
01489A
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APPLICATIONS
Table 5. Serial I/O Programs

for Various Microprocessors.
a.) Input Routine.

8085 8048 8051
IN SERPORT MOV C,SERPIN
ANI MASK CLR C
JZ LO JNTO LO
CMC CPL C
LO: LXI HL,SERBUF MOV RO,#SERBUF
MOV A,M MOV A,@RO MOV A,SERBUF
RR RRC A RRC A
MOV M,A MOV @RO,A MOV SERBUF,A
RESULTS:
8 INSTRUCTIONS 7 INSTRUCTIONS 4 INSTRUCTIONS
14 BYTES 9 BYTES 7 BYTES
56 STATES 9 CYCLES 4 CYCLES
19 uSEe. 22.5 uSEe. 4 uSEe.
b.) Output Routine.

8085 8048 8051
LXI HL,SERBUF MOV RO,#SERBUF
MOV A,M MOV A,@RO MOV A,SERBUF
RR RRC A RRC A
MOV M,A MOV @RO,A MOV SERBUF,A
IN SERPORT
JC HI JC HI
LO: ANI NOT MASK ANL SERPRT,#NOT MASK MOV SERPIN,C
JMP CNT JMP CNT
HI: ORI MASK HI: ORL SERPRT,#MASK
CNT:OUT SERPORT CNT:
RESULTS:
10 INSTRUCTIONS 8 INSTRUCTIONS 4 INSTRUCTIONS
20 BYTES 13 BYTES 7 BYTES
72 STATES II CYCLES 5 CYCLES
24 uSEe. 27.5 uSEe. 5 uSEe.
Design Example #3 - Combinatorial Logic

Equations Figure 13 shows TTL and relay logic diagrams for a
Next we 'II look at some simple uses for bit-test instructions function of the six variables U through Z. Each is a
and logical operations. (This example is also presented in solution of the equation,
Application Note AP-69.) Q = (U . (V + W + (X . Y) + Z .
Virtually all hardware designers have solved complex Equations of this sort might be reduced using Karnaugh
functions using combinatorial logic. While the hardware Maps or algebraic techniques, but that is not the purpose
involved may vary from relay logic, vacuum tubes, or TTL of this example. As the logic complexity increases, so does
or to more esoteric technologies like fluidics, in each case the difficulty of the reduction process. Even a minor
the goal is the same: to solve a problem represented by a change to the function equations as the design evolves
logical function of several Boolean variables. would require tedious re-reduction from scratch.
014S9A
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AI-'I-'LIGA IIUNS
Figure 13. Hardware Implementations of Boolean functions.
a.) Using TTL: CRl
For the sake of comparison we will implement this function

three ways, restricting the software to three proper subsets
CR2
of the MCS-51'" instruction set. We will also assume that
U and V are input pins from different input ports, Wand X
are status bits for two peripheral controllers, and Y and Z
are software flags set up earlier in the program. The end
result must be written to an output pin on some third port.
The first two implementations follow the flow-chart shown
in Figure 14. Program flow would embark on a route down
a test-and-branch tree and leaves either the "True" or "Not b.) USing Relay Logic:
True" exit ASAP - as soon as the proper result has been
determined. These exits then rewrite the output port with
the result bit respectively one or zero.
Other digital computers must solve equations of this type

with standard word-wide logical instructions and condi-
tionaljumps. So for the first implementation, we won't use
any generalized bit-addressing instructions. As we shall
soon see, being constrained to such an instruction subset
produces somewhat sloppy software solutions. MCS_5ITM
mnemonics are used in Example 2.a; other machines might
further cloud the situation by requiring operation-specific
mnemonics like INPUT, OUTPUT, LOAD, STORE, etc.,
instead of the MOV mnemonic used for all variable trans-
fers in the 8051 instruction set.
The code which results is cumbersome and error prone. It

would be difficult to prove whether the software worked for
all input combinations in programs of this sort. Further-
more, execution time will vary widely with input data.
Thanks to the direct bit-test operations, a single instruc- FUNCTION FUNCTION

IS FALSE IS TRUE
tion can replace each move/ mask/ conditional jump
sequence in Example 2.a, but the algorithm would be
equally convoluted (see Example 2.B). To lessen the con-
fusion "a bit" each input variable is assigned a symbolic
name.
A more elegant and efficient implementation (Example 2.c)

strings together the Boolean ANL and ORL functions to
generate the output function with straight-line code. Figure 14. Flow chart for tree-branching algorithm.
01489A
C-16
APPLICATIONS
When finished, the carry flag contains the result, which is CLRQ: MOV A,OUTBUF
simply copied out to the destination pin. No flow chart is ANL A,#IIIIOIII B
needed-code can be written directly from the logic dia- JMP OUTQ
grams in Figure 14. The result is simplicity itself: fast, SETQ: MOV A,OUTBUF
flexible, reliable, easy to design, and easy to debug. ORL A ,#0000 I000 B
OUTQ: MOV OUTBUF,A
An 8051 program can simulate an N-input AND or OR MOV P3,A
gate with at most N+ I lines of source program-one for
each input and one line to store the results. To simulate b.) Using only bit-test instructions.
N AND and NOR gates, complement the carry after com-
;BFUNC2 SOLVE A RANDOM LOGIC FUNCTION
puting the function. When some inputs to the gate have
OF 6 VARIABLES BY DIRECTLY
"inversion bubbles," perform the ANL or OR L operation
POLLING EACH BIT.
on inverted operands. When the first input is inverted,
(APPROACH USING MCS-51 UNIQUE
either load the operand into the carry and then complement
BIT-TEST INSTRUCTION CAPABILITY.)
it, or use DeMorgan's Theorem to convert the gate to a
SYMBOLS USED IN LOGIC DIAGRAM
different form.
ASSIGNED TO CORRESPONDING 8x51
BIT ADDRESSES.
Example 2. Software Solutions to Logic Function of Fig- U BIT PI. I

ure 13. V BIT P2.2
W BIT TFO
X BIT lEI
a.) Using only byte-wide logical instructions.
Y BIT 20H.0
Z BIT 21H.1
;BFUNCI SOLVE RANDOM LOGIC FUNCTION
Q BIT P3.3
OF 6 VARIABLES BY LOADING AND
MASKING THE APPROPRIATE BITS
TEST_V: JB V,TEST_U
IN THE ACCUMULATOR, THEN
JNB W,TEST_X
EXECUTING CONDITIONAL JUMPS
TEST_U: JB U,SET_Q
BASED ON ZERO CONDITION.
TEST_X: JNB X,TEST--'Z
(APPROACH USED BY BYTE-
JNB Y'sET_Q
ORIENTED ARCHITECTURES.)
TEST--'Z: JNB Z,SET_Q
BYTE AND MASK VALUES
CLR_Q: CLR Q
CORRESPOND TO RESPECTIVE BYTE
JMP NXTTST
ADDRESS AND BIT POSITIONS.
SET_Q: SETB Q
NXTTST: ;(CONTINUATION OF
OUTBUF DATA 22H ;OUTPUT PIN STATE MAP
;PROGRAM)
TESTV; MOV A,P2

ANL A,#OOOOO 100B c.) Using logical operations on Boolean variables.
JNZ TESTU
;FUNC3 SOLVE A RANDOM LOGIC FUNCTION
MOV A,TCON
OF 6 VARIABLES USING
ANL A,#OOIOOOOOB
STRAIGHT_LINE LOGICAL
JZ TESTX
INSTRUCTIONS ON MCS-51 BOOLEAN
TESTU: MOV A,PI
VARIABLES.
ANL A ,#000000 lOB
JNZ SETQ
TESTX: MOV A,TCON MOV C,V
ANL A,#OOOOIOOOB ORL C,W ;OUTPUT OF OR GATE
JZ TESTZ ANL C,U ;OUPUT OF TOP AND GATE
MOV A,20B MOV FO,C ;SAVE INTERMEDIATE STATE
ANL A,#OOOOOOO I B MOV C,X
JZ SETQ ANL C,/Y ;OUTPUT OF BOTTOM AND GATE
TESTZ: MOV A,2IH ORL C,FO ;INCLUDE VALUE SAVED ABOVE
ANL A,#OOOOOO lOB ORL C,/Z ;INCLUDE LAST INPUT VARIABLE
JZ SETQ MOV Q,C ;OUTPUT COMPUTED RESULT
01489A
C-17
AI'II'ILI\,;A IIUN~
An upper-limit can be placed on the complexity of software But we're not done yet. Each of the exterior turn signal
to simulate a large number of gates by summing the total (but not the dashboard) bulbs has a second, somewhat
number of inputs and outputs. The actual total should be dimmci filament fOi the parking lights. J7igure 15 shows
somewhat shorter, since calculations can be "chained," as TTL circuitry which could control all six bulbs. The
shown above. The output of one gate is often the first signals labeled "High Freq." and "Low Freq." represent
input to another, bypassing the intermediate variable to two square-wave inputs. Basically, when one of the turn
eliminate two lines of source. switches is closed or the emergency switch is activated the
low frequency signal (about I Hz) is gated through to the
appropriate dashboard indicator(s) and turn signal(s).
Design Example #4 - Automotive Dash- The rear signals are also activated when the brake pedal is
board Functions depressed provided a turn is not being made in the same
direction. When the parking light switch is closed the
N ow let's apply these techniques to designing the software higher frequency oscillator is gated to each front and rear
for a complete controller system. This application is turn signal, sustaining a low-intensity background level.
patterned after a familiar real-world application which (This is to eliminate the need for additional parking light
isn't nearly as trivial as it might first appear: automobile filaments.)
turn signals.
L. TURN ---p-----I-...,'-_~-...,.
Imagine the three positIOn turn lever on the steering EMERO --+--_---l~ }-.......- - - - L. DASH
column as a single-pole, triple-throw toggle switch. In its
central position all contacts are open. In the up or down L. FRNT
positions contacts close causing corresponding lights in

the rear of the car to blink. So far very simple. BRAKE --+-1>-1---r--....}--t-_ _ _---t-i L. REAR
Two more turn signals blink in the front of the car, and R. TURN --~-+----r-""
1--__+ - - - - R. DASH
two others in the dashboard. All six bulbs flash when an
emergency switch is closed. A thermo-mechanical relay
R. FRNT
(accessible under the dashboard in case it wears out)
causes the blinking.
R. REAR
PARK ---------t---f---..,
Applying the brake pedal turns the taillight filaments on
constantly ... unless a turn is in progress, in which case the LO. HI.
FREQ. FREQ.
blinking taillight is not affected. (Of course, the front turn OSCILLATOR OSCILLATOR
signals and dashboard indicators are not affected by the

brake pedal.) Table 6 summarizes these operating modes.
Figure 15. TTL logic implementation of
automotive turn signals.
Table 6. Truth table for turn-signal operation.
INPUT SIGNALS OUTPUT SIGNALS

BRAKE EMERG. LEFT RIGHT LEFT RIGHT LEFT RIGHT
SWITCH SWITCH TURN TURN FRONT FRONT REAR REAR
SWITCH SWITCH & DASH & DASH
0 0 0 0 OFF OFF OFF OFF
0 0 0 I OFF BLINK OFF BLINK
0 0 I 0 BLINK OFF BLINK OFF
0 I 0 0 BLINK BLINK BLINK BLINK
0 I 0 I BLINK BLINK BLINK BLINK
0 I I 0 BLINK BLINK BLINK BLINK
I 0 0 0 OFF OFF ON ON
I 0 0 I OFF BLINK ON BLINK
I 0 I 0 BLINK OFF BLINK ON
I I 0 0 BLINK BLINK ON ON
I I 0 I BLINK BLINK ON BLINK
I I I 0 BLINK BLINK BLINK ON
01489A
C18
APPLICATIONS
In most cars, the switching logic to generate these func- Design Example #3 demonstrated that symbolic address-
tions requires a number of multiple-throw contacts. As ing with user-defined bit names makes code and documen-
many as 18 conductors thread the steering column of some tation easier to write and maintain. Accordingly, we'll
automobiles solely for turn-signal and emergency blinker assign these 110 pins names for use throughout the pro-
functions. (The author discovered this recently to his gram. (The format of this example will differ somewhat
astonishment and dismay when replacing the whole from the others. Segments of the overall program will be
assembly because of one burned contact.) presented in sequence as each is described.)
A multiple-conductor wiring harness runs to each corner

of the car, behind the dash, up the steering column, and INPUT PIN DECLARATIONS:
down to the blinker relay below. Connectors at each ter- (ALL INPUTS ARE POSITIVE-TRUE LOGIC)
mination for each filament lead to extra cost and labor
during construction, lower reliability and safety, and more BRAKE BIT PI.D ~ BRAKE PEDAL DEPRESSED
costly repairs. And considering the system's present com- EMERG BIT PI. I ~ EMERGENCY BLINKER
plexity, increasing its reliability or detecting failures ACTIVATED
would be quite difficult. PARK BIT PI.2 ~ PARKING LIGHTS ON
L_TURN BIT PI.3 ~ TURN LEVER DOWN
There are two reasons for going into such painful detail R_TURN BIT PI.4 ~ TURN LEVER UP
describing this example. First, to show that the messiest
part of many system designs is determining what the OUTPUT PIN DECLARATIONS:
controller should do. Writing the software to solve these
functions will be comparatively easy. Secondly, to show L_FRNT BIT PI.5 ~ FRONT LEFT-TURN
the many potential failure points in the system. Later we'll INDICATOR
see how the peripheral functions and intelligence built into R_FRNT BIT PI.6 ~ FRONT RIGHT-TURN
a microcomputer (with a little creativity) can greatly INDICATOR
reduce external interconnections and mechanical part L_DASH BIT PI.7 ~ DASHBOARD LEFT-TURN
count. INDICATOR
R_DASH BIT P2.D ~ DASHBOARD RIGHT-TURN
INDICATOR
LREAR BIT P2.1 ~ REAR LEFT-TURN
The Single-chip Solution
INDICATOR
The circuit shown in Figure 16 indicates five input pins to R_REAR BIT P2.2 ~ REAR RIGHT-TURN
the five input variables-left-turn select, right-turn select, INDICATOR
brake pedal down, emergency switch on, and parking
lights on. Six output pins turn on the front, rear, and
dashboard indicators for each side. The microcomputer
implements all logical functions through software, which Another key advantage of symbolic addressing will
periodically updates the output signals as time elapses and appear further on in the design cycle. The locations of
input conditions change. cable connectors, signal conditioning circuitry, voltage
regulators, heat sinks, and the like all affect P.c. board
layout. It's quite likely that the somewhat arbitrary pin
Figure 16. Microcomputer Turn-signal Connections. assignment defined early in the software design cycle will
prove to be less than optimum; rearranging the I 10 pin
assignment could well allow a more compact module, or
eliminate costly jumpers on a single-sided board. (These
8051 considerations apply especially to automotive and other
cost-sensitive applications needing single-chip con-
trollers.) Since other architectures mask bytes or use
"clever" algorithms to isolate bits by rotating them into
LEFT
.----.::,.......... DASHBOARD the carry, re-routing an input signal (from bit I of port I,
for example, to bit 4 of port 3) could require extensive
modifications throughout the software.
LEFT
REAR
RIGHT The Boolean Processor's direct bit addressing makes such

REAR
changes absolutely trivial. The number of the port contain-
MODE SIGNAL OUTPUT SIGNAL
ing the pin is irrelevent, and masks and complex program
SENSORS CONDmoNINQ BUFFERS BULBS
structures are not needed. Only the initial Boolean varia-
01489A 1
C-19
APPLICATIONS
fast to modulate the parking lights; bit 7 will be "tuned" to

; INTERRUPT RATE SUBDIVIDER approximately I Hz for the turn- and emergency-
SUB_DIY D.A.TA 20H indicator blinking rate.
; HIGH-FREQUENCY OSCILLATOR BIT
HLFREQ BIT SUB_DIV.O Loading THO with -16 will cause an interruptafter 4.096
; LOW-FREQUENCY OSCILLATOR BIT msec. The interrupt service routine reloads the high-order
LOJ'REQ BIT SUB_DIV.7 byte of timer 0 for the next interval, saves the CPU regis-
ters likely to be affected on the stack, and then decrements
ORG OOOOH SUB_DIV. Loading SUB_DIV. with 244 initially and
JMP INIT each time it decrements to zero will produce a 0.999
second period for the highest-order bit.
ORG 100H
; PUT TIMER 0 IN MODE 1
INIT: MOV TMOD,#OOOOOOOI B ORG OOOBH ; TIMER 0 SERVICE VECTOR
; INITIALIZE TIMER REGISTERS MOV THO.#-16
MOV TLO.#O PUSH PSW
MOV THO,#-16 PUSH ACC
; SUBDIVIDE INTERRUPT RATE BY 244 PUSH B
MOV SUB_DIV,#244 DJNZ SUB_DIV.TOSERV
; ENABLE TIMER INTERRUPTS MOV SUB_DIV.#244
SETB ETO
; GLOBALLY ENABLE ALL INTERRUPTS The code to sample inputs, perform calculations, and
SETB EA update outputs-the real "meat" of the signal controller
; START TIMER algorithm-may be performed either as part of the inter-
SETB TRO rupt service routine or as part of a background program
loop. The only concern is that it must be executed at least
; (CONTINUE WITH BACKGROUND PROGRAM) several dozen times per second to prevent parking light
flickering. We wiIJ assume the former case, and insert the
; PUT TIMER 0 IN MODE 1 code into the timer 0 service routine.
; INITIALIZE TIMER REGISTERS
First. notice from the logic diagram (Figure IS) that the
; SUBDIVIDE INTERRUPT RATE BY 244 subterm (PARK, H_FREQ), asserted when the parking
; ENABLE TIMER INTERRUPTS lights areto be on dimly, figures into four of the six output
; GLOBALLY ENABLE ALL INTERRUPTS functions. Accordingly, we will first compute that term
; START TIMER and save it in a temporary location named "DIM". The
PSWcontains two general purpose flags: FO, which cor-
ble declarations need to be changed; ASMSI automati- responds to the 8048 flag of the same name. and PSW.I.
cally adjusts all addresses and symbolic references to the Since The PSW has been saved and will be restored to its
reassigned variables. The user is assured that no addi- previous state after servicing the interrupt, we can use
tional debugging or software verification will be required. either bit for temporary storage.
Timer 0 (one of the two on-chip timer/counters) replaces DIM BIT PSW.I ; DECLARE TEMP.
the thermo-mechanical blinker relay in the dashboard STORAGE FLAG
controller. During system initialization it is configured as
a timer in mode 1 by setting the least significant bit of the MOV CPARK ; GATE PARKING
timer mode register (TMOD). In this configuration the LIGHT SWITCH
low-order byte (TLO) is incremented every machine cycle, ANL HLFREQ ; WITH HIGH
overflowing and incrementing the high-order byte (THO) FREQUENCY
every 2S6 J.lSec. Timer interrupt 0 is enabled so that a SIGNAL
hardware interrupt will occur each time THO overflows. MOV DIM.C ; AND SAVE IN
(For details of the numerous timer operating modes see TEMP. VARIABLE.
the MCS-SITM User's Manual.)
An eight-bit variable in the bit-addressable RAM array This simple three-line section of code illustrates a remark-
will be needed to further subdivide the interrupts via able point. The software indicates in very abstract terms
software. The lowest-order bit of this counter toggles very exactly what function is being performed, independent of
01489A-22
C-20
APPLICATIONS
the hardware configuration. The fact that these three bits MOV R_DASH,C ; AND OUTPUT TO
include an input pin, a bit within a program variable, and DASHBOARD.
a software flag in the PSW is totally invisible to the MOV FO,C ; SAVE FUNCTION
programmer. SO FAR.
ORL C,DIM ; ADD IN PARKING
Now generate and output the dashboard left turn signal. LIG HT FUNCTION
MOV R_FRNT,C ; AND OUTPUT TO
TURN SIGNAL.
; SET CARRY IF MOV C,BRAKE ; GATE BRAKE
TURN PEDAL SWITCH
ORL C,EMERG ; OR EMERGENCY ANL C,jR_TURN ; WITH TURN
SELECTED. LEVER.
; GATE IN I HZ ORL C,FO ; INCLUDE TEMP.
SIGNAL V ARIABLE FROM
; AND OUTPUT TO DASH
DASHBOARD. ORL C,DIM ; AND PARKING
To generate the left front turn signal we only need to add LIGHT FUNCTION
the parking light function in FO. But notice that the func- MOV R_REAR,C ; AND OUTPUT TO
tion in the carry will also be needed for the rear signal. We TURN SIGNAL.
can save effort later by saving its current state in FO.
(The perceptive reader may notice that simply rearranging
the steps could eliminate one instruction from each
MOV FO,C ; SAVE FUNCTION sequence.)
SO FAR.
ORL C,DIM ; ADD IN PARKING Now that all six bulbs are in the proper states, we can
LIGHT FUNCTION return from the interrupt routine, and the program is
; AND OUTPUT TO finished. This code essentially needs to reverse the status
TURN SIGNAL. saving steps at the beginning of the interrupt.
Finally, the rear left turn signal should also be on when the
brake pedal is depressed, provided a left turn is not in
progress. POP B ; RESTORE CPU
REGISTERS.
POP ACC
MOV C,BRAKE ; GATE BRAKE
POP PSW
PEDAL SWITCH
RET!
; WITH TURN
LEVER.
ORL C,FO ; INCLUDE TEMP. Program Refinements. The luminescence of an incan-
VARIABLE FROM descent light bulb filament is generally non-linear; the 50%
DASH duty cycle of HLFREQ may not produce the desired
ORL C,DIM ; AND PARKING intensity. If the application requires, duty cycles of 25%,
LIGHT FUNCTION 75%, etc. are easily achieved by ANDing and ORing in
; AND OUTPUT TO additional low-order bits ofSUB_DIV. For example, 30
TURN SIGNAL. Hz signals of seven different duty cycles could be pro-
duced by considering bits 2~0 as shown in Table 7. The
Now we have to go through a similar sequence for the only software change required would be to the code which
right-hand equivalents to all the left-turn lights. This also sets-up variable DIM:
gives us a chance to see how the code segments above look
when combined.
MOV C,SUB_DIV.I ; START WITH 50
PERCENT
; SET CARRY IF ANL C,SUB_DIV.O ; MASK DOWN TO 25
TURN PERCENT
ORL C,EMERG ; OR EMERGENCY ORL C,SUB_DIV.2 ; AND BUILD BACK TO
SELECTED. 62 PERCENT
; IF SO, GATE IN I MOV DIM,C ; DUTY CYCLE FOR
HZ SIGNAL PARKING LIGHTS.
01489A
C-21
r,,- r ... 1"1"'\ 1 IVI"~
Table 7. Non-trivial Duty Cycles.
C!IID nnl . . . . . . . . . . . _ i:C!

..,,,, ... _"'1 DITC!
.., .., nllTV
.... . . . , . I f"'Vf"'1 _ .....
7 6 5 4 3 2 1 0 12.5% 25.0% 37.5% 50.0% 62.5% 75.0% 87.5%

X X X X X 0 0 0 OFF OFF OFF OFF OFF OFF OFF
X X X X X 0 0 I OFF OFF OFF OFF OFF OFF ON
X X X X X 0 I 0 OFF OFF OFF OFF OFF ON ON
X X X X X 0 I I OFF OFF OFF OFF ON ON ON
X X X X X I 0 0 OFF OFF OFF ON ON ON ON
X X X X X I 0 I OFF OFF ON ON ON ON ON
X X X X X I I 0 OFF ON ON ON ON ON ON
X X X X X I I I ON ON ON ON ON ON ON
Interconnections increase cost and decrease reliability.

+12V
The simple buffered pin-per-function circuit in Figure 16
is insufficient when many outputs require higher-than-
TTL drive levels. A lower-cost solution uses the 8051
serial port in the shift-register mode to augment I/O. In 8051
mode O. writing a byte to the serial port data buffer

(SBUF) causes the data to be output sequentially through
the "RXD" pin while a burst of eight clock pulses is
generated on the "TXD" pin. A shift register connected to
these pins (Figure 17) will load the data byte as it is shifted
out. A number of special peripheral driver circuits com-
bining shift-register inputs with high drive level outputs
have been introduced recently. Figure 17. Output expansion using serial port.
Cascading multiple shift registers end-to-end will expand

L_REAR BIT 8.4 : REAR LEFT-TURN
the number of outputs even further. The data rate in the
: INDICATOR
I/O expansion mode is one megabaud, or 8 usec. per byte.
R_REAR BIT B.5 : REAR RIGHT-TURN
This is the mode which the serial port defaults to following
: INDICATOR
a reset. so no initializatiQn is required.
The original program to compute the functions need not
The software for this technique uses the B register as a
change. After computing the output variables, the control
"map" corresponding to the different output functions.
map is transmitted to the buffered shift register through
The program manipulates these bits instead of the output
the serial port:
pins. After all functions have been calculated the B register
is shifted by the serial port to the shift-register/ driver. MOY SBUF.B : LOAD BUFFER ANDTRANSMIT
(While some outputs may glitch as data is shifted through
them, at I Megabaud most people wouldn't notice. Some The Boolean Processor solution holds a number of advan-
shift registers provide an "enable" bit to hold the output tages over older methods. Fewer switches are required.
states while new data is being shifted in.) Each is simpler, requiring fewer poles and lower current
contacts. The flasher relay is eliminated entirely. Only six
This is where the earlier decision to address bits symbol- filaments are driven, rather than 10. The wiring harness is
ically throughout the program is going to payoff. This therefore simpler and less expensive-one conductor for
major I/O restructuring is nearly as simple to implement each of the six lamps and each of the five sensor switches.
as rearranging the input pins. Again, only the bit declara- The fewer cond uctors use far fewer connectors. The whole
tions need to be changed. system is more reliable.
L_FRNT BIT B.O : FRONT LEFT-TURN And since the system is much simpler it would be feasible
INDICATOR to implement redundancy and/ or fault detection on the
R_FRNT BIT B.I : FRONT RIGHT-TURN four main turn indicators. Each could still be a standard
INDICATOR double filament bulb, but with the filaments driven in
L_DASH BIT 8.2 : DASHBOARD LEFT-TURN parallel to tolerate single-element failures.
INDICATOR
R_DASH BIT 8.3 : DASHBOARD RIGHT-TURN Even with redundancy, the lights will eventually fail. To
INDICATOR handle this inescapable fact current or voltage sensing
01489A
C-22
At't'LI\.;A I IUN:::
circuits on each main drive wire can verify that each bulb CLR L_DASH
and its high-current driver is functioning properly. Figure JB TO,FAULT
18 shows one such circuit. SETB L_DASH
CLR L_REAR
WIRING +12V
HARNESS JB TO.FAULT
I
SETB L_REAR
CLR R_FRNT
JB TO.FAULT
SETB R_FRNT
CLR R_DASH
P1.7
JB TO.FAULT
SETB R_DASH
CLR R_REAR
P2.0
JB TO.FAULT
SETB R.~REAR
P2.1
: WITH ALL COLLECTORS GROUNDED. TO

P2.2 SHOULD BE HIGH
: IF SO. CONTINUE WITH INTERRUPT ROUTINE.
JB TO.TOSERV
FAUL T: : ELECTRICAL FAILURE
:PROCESSING ROUTINE
: (LEFT TO READER'S
: IMAGINATION)
TOSERV: : CONTINUE WITH
Figure 18.
:INTERRUPT PROCESSING
Assume all of the lights are turned on except one; i.e., all
but one of the collectors are grounded. For the bulb which
is turned off. if there is continuity from + 12 V through the
bulb base and filament, the control wire, all connectors, The complete assembled program listing is printed in
and the P.e. board traces, and if the transistor is indeed Appendix A. The resulting code consists of 67 program
not shorted to ground, then the collector will be pulled to statements, not counting declarations and comments,
+ 12 V. This turns on the base of Q8 through the corres- which assemble into 150 bytes of object code. Each pass
ponding resistor, and grounds the input pin, verifying that through the service routine requires (coincidently) 67 usec,
the bulb circuit is operational. The continuity of each plus 32 usec once per second for the electrical test. If
circuit can be checked by software in this way. executed every 4 msec as suggested this software would
typically reduce the throughput of the background pro-
N ow turn all the bulbs on, grounding all the collectors. Q7 gram by less than 2%.
should be turned off. and the Test pin should be high.
However, a control wire shorted to + 12 V or an open- Once a microcomputer has been designed into a system,
circuited drive transistor would leave one ofthe collectors new features suddenly become virtually free. Software
at the higher voltage even now. This too would turn on Q7, could make the emergency blinkers flash alternately or at
indicating a different type of failure. Software could per- a rate faster than the turn signals. Turn signals could
form these checks once per second by executing the rou- override the emergency blinkers. Adding more bulbs
tine every time the software counter SUB_DIVis reloaded would allow mUltiple taillight sequencing and
by the interrupt routine. syncopation - true flash factor. so to speak.
DJNZ SUB_DIV.TOSERV Design Example #5 - Complex Control

MOV SUB_DIV.#244 : RELOAD COUNTER Functions
ORL PI.#IIIOOOOOB : SET CONTROL
Finally, we'll mix byte and bit operations to extend the use
OUTPUTS HIGH
of 8051 into extremely complex applications.
ORL P2.#00000111 B
CLR L_FRNT : FLOAT DRIVE Programmers can arbitrarily assign 110 pins to input and
COLLECTOR output functions only if the total does not exceed 32,
JB TO.FAULT : TO SHOULD BE which is insufficient for applications with a very large
PULLED LOW number of input variables. One way to expand the number
SETB L_FRNT : PULL COLLECTOR of inputs is with a technique similar to multiplexed-
BACK DOWN keyboard scanning.
01489A
C-23
Figure 19 shows a block diagram for a moderately com- The 8051 serial port can be configured to detect bytes with
plex programmable industrial controller with the follow- the address bit set, automatically ignoring all others. Pins
ing characteristics: INTO and INT! are interrupts configured respectively as
64 input variable sensors; high-priority, falling-edge triggered and low-priority, low-
level triggered. The remaining 12 I/O pins output TTL-
12 output signals;
Combinational and sequential logic computations; level control signals to 12 actuators.
Remote operation with communications to a host
processor via a high-speed full-duplex serial link; There are several ways to implement the sensor matrix
Two prioritized external interrupts; circuitry, all logically similar. Figure 20.a shows one possi-
Internal real-time and time-of-day clocks. bility. Each of the 64 sensors consists of a pair of simple
switch contacts in series with a diode to permit multiple
While many microprocessors could be programmed to contact closures throughout the matrix.
provide these capabilities with assorted peripheral sup-
port chips, an 8051 microcomputer needs no other inte-
grated circuits! The scan lines from Port I provide eight un-encoded
active-high scan signals for enabling columns of the
The 64 input sensors are logically arranged as an 8x8 matrix. The return lines on rows where a contact is closed
matrix. The pins of Port 1 sequentially enable each are pulled high and read as logic ones. Open return lines
column of the sensor matrix; as each is enabled Port 0 are pulled to ground by one of the 40 kohm resistors and
reads in the state of each sensor in that column. An are read as zeroes. (The resistor values must be chosen to
eight-byte block in bit-addressable RAM remembers the ensure all return lines are pulled above the 2.0 V logic
data as it is read in so that after each complete scan cycle threshold, even in the worst-case, where all contacts in an
there is an internal map of the current state of all sensors. enabled column are closed.) Since PO is provided open-
Logic functions can then directly address the elements of collector outputs and high-impedance MOS inputs its
the bit map. input loading may be considered negligible.
The computer's serial port is configured as a nine-bit

The circuits in Figures 20.b-20.d are variations on this
U ART, transferring data at 17,000 bytes-per-second. The
theme. When input signals must be electrically isolated
ninth bit may distinguish between address and data bytes.
from the computer circuitry as in noisy industrial environ-
ments, phototransistors can replace the switch/ diode
pairs and provide optical isolation as in Figure 20.b. Addi-
tional opto-isolators could also be used on the control
output and special signal lines.
12MHZ =
XTAL2
SERIAL
LINK
1 RXO iNTo 1 - - - - - I.
iNT1 1--_ _ _ j
ASYNCHRONANS
INTERRUPTS
The other circuits assume that input signals are already at
TTL levels. Figure 20.c uses octal three-state buffers
8051
enabled by active-low scan signals to gate eight signals
onto Port O. Port 0 is available for memory expansion or
PO.l peripheral chip interfacing between sensor matrix scans.
PO.2
Eight-to-one multiplexers in Figure 20.d select one of
eight inputs for each return line as determined by encoded
PO.5
PO.S
MACHINE address bits output on three pins of Port I. (Five more
P2.2 ACTUATORS
output pins are thus freed for more control functions.)
Each output can drive at least one standard TTL or up to
P2.6
10 low-power TTL loads without additional buffering.
P2.7
N.C.
Going back to the original matrix circuit, Figure 21 shows
ALE
PSEN N.C. the method used to scan the sensor matrix. Two complete
/
VSS EA bit maps are maintained in the bit-addressable region of
SCAN
LINES the RAM: one for the current state and one for the pre-
vious state read for each sensor. If the need arises, the
program could then sense input transitions and/ or
Figure 19. Block diagram of 64-input machine debounce contact closures by comparing each bit with its
controller. earlier value.
01489A
C-24
APPLIGA IIUN~
+8x4K +8x4K
r- r---
8051
~."56"
~O" ~"
"56"
~.I..*
RETURN
r
f-e---L-~ ,LINES RETURN
. "LlNES
pO.a pO.a
r9!'" ~t ~7"
"1" "9" "57"
~--'--
~ ~~
PO.l
r- PO.l
i 1--1
1 PO.2
1I - I PO.2
1 PO.3
1 PO.3
I I +-'-1- PO.4
PO.S 1 I Hi I PO.4
PO.S
1-1-1-+ I PO.S I+I-=+T PO.6
"15" "63"
I I
~3"
~~ f-e--l-~
PO.7 ~'M15"
i t
PO.7
8x40K 8x40K
= =
'------++------1 P1.0 L------++-------"1P1.0
'------++---....., P1.1 '----_ _ _-1-1---_ _--1 P1.1
'----_ _ _--1+-_ _-----, P1.2 L--_ _ _ _ ++-._ _ _- j Pl.2
'----------++--------1 P1.3 L-_ _ _ _-++--_ _--jP1.3
'----------++------"1 P1.' L - - - - - - - - H - - - - - i P 1 .
' - - - - - - - - - - - 1 1 + - - - - - - 1 P1.5 L - - - - - - - t t - - - - - 1 P1 .5
L - - - - - - - - - - + + - - - - - - " 1 P1 . L - - - - - - - - - - - t - 1 f - - - - - - - I P1 .
L - - - - - - - - - - - - - - H - - - - - 1 P1.7 L-------------+t-------jP1.7
SCAN' SCAN
LINES LINES
a.) Using switch contact/diode matrix. b.) Using optically-coupled isolators.
'8ii5,
rrrrlrrl rr!!!!!l rrrJjjjl 111111J1 rrrr!rrr

lfr7~lSt;
rl~ ~ ~ ~ ~ ~ ~1 ~ ~ ~
E~
; ~ ~ ~ ~l
t tE 7~S~44 E ~
4+-+-+--++-+--1-......+-t-+--t-+-H--+-4--t-+-H-t-++- PO.O
j II
00 D1 2
1 CBA
D:41:~ 05 Os
V$
I~
071 100 01 02 07:1:~
II CBA
05 06 0 7 1
Ys
'------+-++--+-----H-+--+---- po.o
~
I
00 01 02 03 0 4 05 06
1' C
74151
BAY S
1-;1:
071
IL++
1-+-+-++-+_...1+-1
1-+-+-+-+---+_--<l>-+-+I-+--1-t-+-_ PO.1 l'---------+-+-+---4--_ PO.1
1'-+-+++-H---<10--++-t-+---t---I-----41-+--t-+-H,---.., PO.2
"--+-++-+-I---~+-+-+-I---+----+-f_t_+-+--! PO.3 l~I~II~==1j:t=.t=====-=: ::::
L.t
~+-+-+---_......+-+-+---I----+-I_+_+-----! po., 1L.1-::f-----+-Hf--+----l po.,
L+-+-+-----+-+-+-+-----+-f_t_--l PO.5
L+-I--------+--I---+------<>-+----I po. L.1~==1~=':==_:=====:; :~:
4------......-+-----4----i PO.7 '-------J PO.7
I I I I I
lllUllJ III III
~ ~
Pl.0 Pl.D
P1.1 llll 1111 11 Pl.1
\11 Pl.2
Pl.3
~ 1 1
G= Pl.2
I P1.4
Pl.S
Pl.7
'---- L--
C.) Using TTL three-state buffers. d.) Using TTL data selectors.
Figure 20. Sensor Matrix Implementation Methods.
Example 3.
INPUT_SCAN: : SUBROUTINE TO READ
CURRENT STATE
; OF 64 SENSORS AND
The code in Example 3 implements the scanning algo- SAVE IN RAM 20H-27H.
rithm for the circuits in Figure 20.a. Each column is MOY RO,#20H : INITIALIZE
enabled by setting a single bit in a field of zeroes. The bit ; POINTERS
maps are positive logic; ones represent contacts that are MOY R L#28H : FOR BIT MAP
closed or isolators turned on. ; BASES.
01489A
C-25
MOV A,#80H ; SET FIRST BIT IN What happens after the sensors have been scanned
ACe. depends on the individual application. Rather than
SCAN: MOV PI.A . OUTPUT TO SCAN inventing some artificial design problem, softVv'are corres-
LINES. ponding to commonplace logic elements will be discussed.
RR A ; SHIFT TO ENABLE
NEXT COLUMN Combinatorial Output Variables. An output variable
NEXT. which is a simple (or not so simple) combinational func-
MOV R2,A ; REMEMBER CUR- tion of several input variables is computed in the spirit of
RENT SCAN Design Example 3. All 64 inputs are represented in the bit
POSITION. maps; in fact, the sensor numbers in Figure 20 correspond
MOV A,PO ; READ RETURN to the absolute bit addresses in RA M! The code in Exam-
LINES. ple 4 activates an actuator connected to P2.2 when sensors
XCH A,@RO ; SWITCH WITH 12, 23, and 34 are closed and sensors 45 and 56 are open.
PREVIOUS MAP Example 4.
BITS.
MOV @RI,A ; SAVE PREVIOUS Simple Combinatorial Output Variables.
STATE AS WELL.
INC RO ; BUMP POINTERS. ; SET P2.2 = (12) (23) (34) (j 45) (j 56)
INC RI MOV C,12
MOV A,R2 ; RELOAD SCAN LINE ANL C,23
MASK ANL C,34
JNB ACe.7,SCAN; LOOP UNTIL ALL ANL C,/45
EIGHT COLUMNS ANL C,/56
READ. MOV P2.2,C
RET Intermediate Variables. The examination of a typical
relay-logic ladder diagram will show that many of the
rungs control not outputs but rather relays whose con-
tacts figure into the computation of other functions. In
effect, these relays indicate the state of intermediate varia-
bles of a computation.
The M CS-5 I'M solution can use any directly addressable

bit for the storage of such intermediate variables. Even
when all 128 bits of the RAM array are dedicated (to input
bit maps in this example), the accumulator, PSW, and B
register provide 18 additional flags for intermediate
variables.
For example, suppose switches 0 through 3 control a

safety interlock system. Closing any of them should deac-
tivate certain outputs. Figure 22 is a ladder diagram for
this situation. The interlock function could be recomputed
for every output affected, or it may be computed once and
saved (as implied by the diagram). As the program pro-
ceeds this bit can qualify each output.
Example 5. Incorporating Override signal into actuator

outputs.
CALL INPUT-SCAN
MOV C,O
ORL C,I
ORL C,2
ORL C,3
MOV FO,C
Figure 21. Flowchart for reading in sensor matrix.
01489A-28
C-26
At't'LI\"A IIUI~i)
COMPUTE FUNCTION 0 Example 6. Simulating a latching relay.
ANL C,/FO ;L.-SET SET FLAG 0 IF C=I

MOY PI.O,C L.-SET: ORL C,FO
MOY FO,C
COMPUTE FUNCTION I
ANL C,/FO ;L_RSET RESET FLAG 0 IF C=I

MOY PI.I,C L_RSET: CPS C
ANL C,FO
COMPUTE FUNCTION 2 MOY FO,C
ANL C,/FO
MOY PI.2,C
Time Delay Relays. A time delay relay does not respond
to an input signal until it has been present (or absent) for
some predefined time. For example, a ballast or load
resistor may be switched in series with a D.C. motor when
it is first turned on, and shunted from the circuit after one
second. This sort of time delay may be simulated by an
interrupt routine driven by one of the two 8051 timer I
"2" counters. The procedure followed by the routine depends
heavily on the details of the exact function needed; time-
"3"
outs or time delays with resettable or non-resettable inputs
are possible. If the interrupt routine is executed every IO
milliseconds the code in Example 7 will clear an inter-
mediate variable set by the background program after it
has been active for two seconds.
Example 7. Code to clear USRFLG after a fixed time delay.
JNB USR_FLG,NXTTST
DJNZ DLA Y_COUNT,NXTTST
CLR USR_FLG
MOY DLA Y_COUNT,#200
NXTTST:
Serial Interface to Remote Processor. When it detects

emergency conditions represented by certain input com-
Figure 22. Ladder diagram for output override binations (such as the earlier Emergency Override), the
circuitry. controller could shut down the machine immediately
andl or alert the host processor via the serial port. Code
bytes indicating the nature of the problem could be trans-
mitted to a central computer. In fact, at 17,000 bytes-per-
Latching Relays. A latching relay can be forced into either second, the entire contents of both bit maps could be sent
the ON or OFF state by two corresponding input signals, to the host processor for further analysis in less than a
where it will remain until forced onto the opposite state- millisecond! If the host decides that conditions warrant, it
analogous to a TTL Setl Reset flip-flop. The relay is used could alert other remote processors in the system that a
as an intermediate variable for other calculations. In the problem exists and specify which shut-down sequence
previous example, the emergency condition could be each should initiate. For more information on using the
remembered and remain active until an "emergency serial port, consult the MCS-5ITM User's Manual.
cleared" button is pressed. Response Timing.
One difference between relay and programmed industrial
controllers (when each is considered as a "black box") is
Any flag or addressable bit may represent a latching relay their respective reaction times to input changes. As
with a few lines of code (see Example 6). reflected by a ladder diagram, relay systems contain a
01489A
C-2?
At"t"LI~A HUN:>
large number of "rungs" operating in parallel. A change in ~EXCLUSIVE-OR FUNCTION IMPOSEDON CARRY
input conditions will begin propagating through the sys- ~USING FO IS INPUT VARIABLE.
tem immediately, possibly affecting the output state XO!LFO: JNB FO.XORCNT ; ("J8" FOR X-NOR)
within milliseconds. CPL C
XORCNT: ...
Software, on the other hand, operates sequentially. A
change in input states will not be detected until the next XCH. The contents of the carry and some other bit may be
time an input scan is performed, and will not affect the exchanged (switched) by using the accumulator as tempo-
outputs until that section of the program is reached. For rary storage. Bits can be moved into and out of the accu-
that reason the raw speed of computing the logical func- mulator simultaneously using the Rotate-through-carry
tions is of extreme importance. instructions. though this would alter the accumulator
data.
Here the Boolean processor pays off. Every instruction
mentioned in this Note completes in one or two micro-
; EXCHANGE CARRY WITH USRFLG
seconds-the minimum instruction execution time for
XCHBIT: RLC A
many other microcontrollers! A ladder diagram contain-
MOV c'USR_FLG
ing a hundred rungs, with an average of four contacts per
RRC A
rung can be replaced by approximately five hundred lines
MOV USR_FLG.C
of software. A complete pass through the entire matrix
RLC A
scanning routine and all computations would require
about a millisecond~ less than the time it takes for most
relays to change state. Extended Bit Addressing. The 8051 can directly address
144 general-purpose bits for all instructions in Figure 3.b.
A programmed controller which simulates each Boolean Similar operations may be extended to any bit anywhere
function with a subroutine would be less efficient by at on the chip with some loss of efficiency.
least an order of magnitude. Extra software is needed for
the simulation routines, and each step takes longer to The logical operations AND, OR. and Exclusive-OR are
execute for three reasons: several byte-wide logical performed on byte variables using six different addressing
instructions are executed per user program step (rather modes. one of which lets the source be an immediate
than one Boolean operation)~ most of those instructions mask. and the destination any directly addressable byte.
take longer to execute with microprocessors performing Any bit may thus be set, cleared, or complemented with a
multiple off-chip accesses~ and calling and returning from three-byte. two-cycle instruction if the mask has all bits
the various subroutines requires overhead for stack but one set or cleared.
operations.
Byte variables, registers. and indirectly addressed RAM
In fact. the speed of the Boolean Processor solution is may be moved to a bit addressable register (usually the
likely to be much faster than the system requires. The accumulator) in one instruction. Once transferred, the bits
CPU might use the time left over to compute feedback may be tested with a conditional jump, allowing any bit to
parameters, collect and analyze execution statistics, per- be polled in 3 microseconds-still much faster than most
form system diagnostics, and so forth. architectures,-or used for logical calculations. (This
technique can also simulate additional bit addressing
modes with byte operations.)
Additional functions and uses.
Parity of bytes or bits. The parity of the current accumu-
lator contents is always available in the PSW, from
With the building-block basics mentioned above many whence it may be moved to the carry and further pro-
more operations may be synthesized by short instruction cessed. Error-correcting Hamming codes and similar
sequences. applications require computing parity on groups of iso-
lated bits. This can be dO,ne by conditionally complement-
ing the carry flag based on those bits or by gathering the
Exclusive-OR. There are no common mechanical devices
bits into the accumulator (as shown in the DES example)
or relays analogous to the Exclusive-OR operation, so this
and then testing the parallel parity flag.
instruction was omitted from the Boolean Processor.
However. the Exclusive-OR or Exclusive-NOR operation
Multiple byte sh((t and C RC codes.
may be performed in two instructions by conditionally
complementing the carry or a Boolean variable based on Though the 8051 serial port can accommodate eight- or
the state of any other testable bit. nine-bit data transmissions, some protocols involve much
01489A-30
C-28
APPLICATIONS
longer bit streams. The algorithms presented in Design This Application Note has detailed the information
Example 2 can be extended quite readily to 16 or more bits needed by a microcomputer system designer to make full
by using multi-byte input and output buffers. use of these capabilities. Five design examples were used
Many mass data storage peripherals and serial communi- to contrast the solutions allowed by the 8051 and those
cations protocols include Cyclic Redundancy (CRC) required by previous architectures. Depending on the
codes to verify data integrity. The function is generally individual application, the 8051 solution will be easier to
computed serially by hardware using shift registers and design, more reliable to implement, debug, and verify, use
Exclusive-OR gates, but it can be done with software. As less program memory, and run up to an order of magni-
each bit is received into the carry, appropriate bits in the tude faster than the same function implemented on pre-
multi-byte data buffer are conditionally complemented vious digital computer architectures.
based on the incoming data bit. When finished, the CRC
register contents may be checked for zero by ORing the Combining byte- and bit-handling capabilities in a single
two bytes in the accumulator. microcomputer has a strong synergistic effect: the power
of the result exceeds the power of byte- and bit-processors
4. SUMMARY laboring individually. Virtually all user applications will
A truly unique facet of the Intel MCS-5 I'M microcomputer benefit in some ways from this duality. Data intensive
family design is the collection of features optimized for the applications will use bit addressing for test pin monitoring
one-bit operations so often desired in real-world, real-time or program control flags; control applications will use
control applications. Included are 17 special instructions, byte manipulation for parallel I I 0 expansion or arith-
a Boolean accumulator, implicit and direct addressing metic calculations.
modes, program and mass data storage, and many 1/0
options. These are the world's first single-chip micro- It is hoped that these design examples give the reader an
computers able to efficiently manipulate, operate on, and appreciation of these unique features and suggest ways to
transfer either bytes or individual bits as data. exploit them in his or her own application.
01489A
r..?Q
ISIS-II MCS-51 MACRO ASSEMBLER Vl.O
l'~
0"
fOeD
OB~ECT MODULE PLACED IN :FO:AP70.HEX ill ;:,
ASSEMBLER INVOKED BY: : fl:asm51 ap70. src date(328) 39:
LOC OB~ LINE SOURCE r->C
~;t>
$XREF TITLE(AP-70 APPENDIX)
~J>
. c
2 i***************************************************** ***
3 o3
4 THE FOLLOWING PROGRAM USES THE BOOLEAN INSTRUCTION SET
5 OF THE INTEL 8051 MICROCOMPUTER TO PERFORM A NUMBER OF o
CT
6
7
AUTOMOTIVE DASHBOARD CONTROL FUNCTIONS RELATING TO
TURN SIGNAL CONTROL, EMERGENCY BLINKERS, BRAKE LIGHT
f
8 CONTROL, AND PARKING LIGHT OPERATION. '2
9
10
THE ALGORITHMS AND HARDWARE ARE DESCRIBED IN DESJGN
EXAMPLE #4 OF INTEL APPLICATION NOTE AP-70, ~
"USING THE INTEL MCS-51<TM) S-
11 o.
12 BOOLEAN PROCESSING CAPABILITIES" n
I
13
14 i***************************************************** **** ~
15
16 INPUT PIN DECLARATIONS: f}
17 (ALL INPUTS ARE POSITIVE-TRUE LOGIC. a. ))
18 INPUTS ARE HIGH WHEN RESPECTIVE SWITCH CONTACT IS CLOSED. ) 2- "tl
0090
19
20 BRAKE BIT PI.O BRAKE PEDAL DEPRESSED ..
CD "tl
r-
n
o 0091 21 EMERG BIT PI. 1 EMERGENCY BLINKER ACTIVATED
W
o
0092 22 PARK BIT PI. 2 PARKING LIGHTS ON
~
0093
0094
23
24
25
L_TURN
R_TURN
BIT
BIT
PI.
PI.
3
4
i TURN LEVER DOWN
TURN LEVER UP a2
26 OUTPUT PIN DECLARATIONS: CIl
27 (ALL OUTPUTS ARE POSITIVE TRUE LOGIC.
28 BULB IS TURNED ON WHEN OUTPUT PIN IS HIGH. )
29
0095 30 L_FRNT BIT Pl. 5 FRONT LEFT-TURN INDICATOR
0096 31 R_FRNT BIT PI. 6 i FRONT RIGHT-TURN INDICATOR
0097 32 L_DASH BIT PI. 7 DASHBOARD LEFT-TURN INDICATOR
OOAO 33 R_DASH BIT P2. 0 DASHBOARD RIGHT-TURN INDICATOR
OOAI 34 L_REAR BIT P2. 1 REAR LEFT-TURN INDICATOR
00A2 35 R_REAR BIT P2.2 REAR RIGHT-TURN INDICATOR
36
00A3 37 S_FAIL BIT P2. 3 ELECTRICAL SYSTEM FAULT INDICATOR
38
39 INTERNAL VARIABLE DEFINITIONS:
40
0020 41 SUB_DIV DATA 20H INTERRUPT RATE SUBDIVIDER
0000 42 HIJ'REG BIT SUB_DIV.O HIGH-FREGUENCY OSCILLATOR BIT
0007 43 LO_FREG BIT SUB_DIV. 7 LOW-FREGUENCY OSCILLATOR BIT
44
OODI 45 DIM BIT PSW.l PARKING LIGHTS ON FLAG
0 46
co 47 ;=======================================================
'" 48 +1 $E~ECT
LOC OBJ LINE SOURCE
49 ORG OOOOH RESET VECTOR

0000 020040 50 LJMP INIT
51
OOOB 52 ORG OOOBH TIMER 0 SERVICE VECTOR
OOOB 758CFO 53 MOV THO. #-16 HIGH TIMER BYTE ADJUSTED TO CONTROL INT. RATE
OOOE CODO 54 PUSH PSW EXECUTE CODE TO SAVE ANY REGISTERS USED BELOW
0010 0154 55 AJMP UPDATE (CONTINUE WITH REST OF ROUTINE)
56
0040 57 ORG 0040H
0040 758AOO 58 INIT: MOV TLO.#O ; ZERO LOADED INTO LOW-ORDER BYTE AND
0043 758CFO 59 MOV THO. #-16 -16 IN HIGH-ORDER BYTE GIVES 4 MSEC PERIOD
0046 758961 60 MOV TMOD.#OllOOOOlB 8-BIT AUTO RELOAD COUNTER MODE FOR TIMER 1.
61 16-BIT TIMER MODE FOR TIMER 0 SELECTED
0049 7520F4 62 MOV SUB_DIV.#244 SUBDIVIDE INTERRUPT RATE BY 244 FOR 1 HZ
004C D2A9 63 SETB ETO USE TIMER 0 OVERFLOWS TO INTERRUPT PROGRAM
004E D2AF 64 SETB EA CONFIGURE IE TO GLOBALLY ENABLE INTERRUPTS
0050 D28C 65 SETB TRO KEEP INSTRUCTION CYCLE COUNT UNTIL OVERFLOW
0052 80FE 66 SJMP $ START BACKGROUND PROGRAM EXECUTION
67
68
0054 D52038 69 UPDATE: DJNZ SUB_DIV.TOSERV EXECUTE SYSTEM TEST ONLY ONCE PER SECOND
"0
0057 7520F4 70 MOV SUB_DIV, #244 GET VALUE FOR NEXT ONE SECOND DELAY AND
71 GO THROUGH ELECTRICAL SYSTEM TEST CODE: "0
005A 4390EO 72 ORL Pi. #111000008 SET CONTROL OUTPUTS HIGH
r-
0
P2,#000001118 0
~ 005D
0060
43A007
C295
73
74
ORL
CLR L_FRNT FLOAT DRIVE COLLECTOR
0062 20B428 75 JB TO. FAULT TO SHOULD BE PULLED LOW -I
0065 D295 76 SETB L_FRNT PULL COLLECTOR BACK DOWN 0
0067 C297 77 CLR L DASH ; REPEAT SEQUENCE FOR L_DASH. Z
0069 20B421 78 JB TO, FAULT (Jl
006C D297 79 SETB L_DASH
006E C2Al 80 CLR L_REAR L REAR.
0070 20B41A 81 JB TO. FAULT
0073 D2Al 82 SETB L_REAR
0075 C296 83 CLR R_FRNT R_FRNT.
0077 20B413 84 JB TO,FAULT
007A D296 85 SETB R_FRNT
007C C2AO 86 CLR R_DASH R_DASH,
007E 20B40C 87 JB TO. FAULT
0081 D2AO 88 SETB R DASH
0083 C2A2 89 CLR R:=REAR AND R__REAR.
0085 20B405 90 JB TO, FAULT
0088 D2A2 91 SETB R_REAR
92
93 WITH ALL COLLECTORS GROUNDED, TO SHOULD BE HIGH
94 IF SO, CONTINUE WITH INTERRUPT ROUTINE.
95
008A 20B402 96 JB TO. TOSERV
0 008D B2A3 97 FAULT: CPL S_FAIL ELECTRICAL FAILURE PROCESSING ROUTINE
98 ; (TOGGLE INDICATOR ONCE PER SECOND)
'"'":.- 99 +1 $EJECT
LoC oBJ LINE SOURCE
100 CONTINUE WITH INTERRUPT PROCESSING:

101
102 1) COMPUTE LOW BULB INTENSITY WHEN PARKING LIGHTS ARE ON.
103
008F A201 104 TOSERV: MOV C, SUB_DIV. 1 START WITH 50 PERCENT,
0091 8200 105 ANL C,SUB_DIV.O ; MASK DOWN TO 25 PERCENT,
0093 7202 106 ORL C,SUB_DIV.2 ; BUILD BACK TO 62. 5 PERCENT,
0095 8292 107 ANL C,PARK ; GATE WITH PARKING LIGHT SWITCH,
0097 9201 108 MOV DIM,C ; AND SAVE IN TEMP. VARIABLE.
109
110 2) COMPUTE AND OUTPUT LEFT-HAND DASHBOARD INDICATOR.
111
0099 A293 112 MOV C,L_TURN ; SET CARRY IF TURN
009B 7291 113 ORL C,EMERG OR EMERGENCY SELECTED.
0090 8207 114 ANL C,LO_FREG ; IF SO, GATE IN 1 HZ SIGNAL
009F 9297 115 MOV L_DASH,C AND OUTPUT TO DASHBOARD.
116
117 3) COMPUTE AND OUTPUT LEFT-HAND FRONT TURN SIGNAL.
118
OOAI 92D5 119 MoV FO,C ; SAVE FUNCTION SO FAR.
00A3 7201
00A5 9295
120
121
oRL
MoV
C,DIM
L_FRNT, C
; ADD IN PARKING LIGHT FUNCTION
AND OUTPUT TO TURN SIGNAL.
."
122 ."
123 4) COMPUTE AND OUTPUT LEFT-HAND REAR TURN SIGNAL. !:
o
W
124 o
I\.) 00A7 A290 125 MoV
ANL
C,BRAKE
C, IL_TURN
GATE BRAKE PEDAL SWITCH
WITH TURN LEVER.

00A9 B093 126 :::!
OOAB 7205 127 oRL C,FO ; INCLUDE TEMP. VARIABLE FROM DASH
o
OOAD 7201
92Al
128 oRL
MOV
C. DIM
L_REAR, C
; AND PARKING LIGHT FUNCTION
AND OUTPUT TO TURN SIGNAL.
z
OO.~F 129
130
en
131 5) REPEAT ALL OF ABOVE FOR RIGHT-HAND COUNTERPARTS.
132
OOBI A294 133 MoV C,R_TURN SET CARRY IF TURN
00B3 7291 134 oRL C,EMERG ; OR EMERGENCY SELECTED.
00B5 8207 135 ANL C. LO_FREG IF SO, GATE IN 1 HZ SIGNAL
00B7 92AO 136 MoV R_DASH,C ; AND OUTPUT TO DASHBOARD.
00B9 9205 137 MoV FO,C i SAVE FUNCTION SO FAR.
OOBB 7201 138 oRL C,DIM ; ADD IN PARKING LIGHT FUNCTION
OOBD 9296 139 MoV R_FRNT, C AND OUTPUT TO TURN SIGNAL.
OOBF A290 140 MoV C,BRAKE GATE BRAKE PEDAL SWITCH
OOCI B094 141 ANL C,/R_TURN WITH TURN LEVER.
00C3 7205 142 oRL C,FO ; INCLUDE TEMP. VARIABLE FROM DASH
00C5 7201 143 oRL C. DIM ; AND PARKING LIGHT FUNCTION
00C7 92A2 144 MoV R_REAR, C AND OUTPUT TO TURN SIGNAL.
145
146 RESTORE STATUS REGISTER AND RETURN.
147
00C9 DODO 148 POP PSW RESTORE PSW
o OOCB 32 149 RETI AND RETURN FROM INTERRUPT ROUTINE
150
'" ! 51 END
XREF SYMBOL TABLE LISTING
-------
NAME TYPE VALUE AND REFERENCES
BRAKE N BSEG 0090H 20# 125 140

DIM N BSEG OODIH 45# 108 120 128 138 143
EA. N BSEG OOAFH 64
EMERG N BSEG 0091H 21# 113 134
ETa N BSEG 00A9H 63
FO. N BSEG 00D5H 119 127 137 142
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u.s. AND CANADIAN SALES OFFICES
3065 Bowers Avenue
Santa Clara, California 95051
Tel: (408) 987-8080
TWX: 9103380026
TELEX: 34-6372
ALABAMA CONNECTICUT MICHIGAN OHIO

Intel Corp. Intel Corp. Intel Corp.' Intel Corp."
303 Williams Avenue. S.W. Peacock Alley 26500 Northwestern Hwy. 6500 Poe Avenue
Suite 1422 1 Padanaram Road, Suite 146 Suite 401 Dayton 45415
Huntsville 35801 Danbury 06610 Southfield 48075 Tel: (513) 890-5350
Tel: (205) 5339353 Tel: (203) 792-l1366 Tel: (313) 353'()920 TWX: 8104502528
TWX: 710-4561199 TWX: 810-2444915
Pen-Tech Associates, Inc. Intel Corp."
Holiday Office Center Lowry & Associates, Inc. ChagrinBrainard Bldg., No. 210
3322 Memorial Pkwy., S.w. FLORIDA 135 W. North Street 28001 Chagrin Blvd
Huntsville 35801 Intel Corp. Suite 4 Cleveland 44122
Tel: (205) 8819298 1001 N.w. 62nd Street, Suite 406 Brighton 48116 Tel: (216) 4642736
Ft. Lauderdale 33309 Tel: (313) 2277067 TWX: 810-4279298
ARIZONA Tel: (305) 7710600 Lowry & Associates, Inc.
Intel Corp. TWX: 510-9569407 3902 Costa NE OREGON
10210 N. 25th Avenue, Suite 11 Intel Corp. Grand Rapids 49505 Intel Corp.
Phoenix 85021 5151 Adanson Street, Suite 203 Tel: (616) 363-9839 t0700 S.w. Beaverton
Tel: (602) 9979695 Orlando 32804 Hiltsdale Highway
Tel: (305) 628-2393 MINNESOTA Suite 324
BFA
TWX: 810-8539219 Beaverton 97005
4426 North Saddle Bag Trail Intel Corp.
Scottsdale 85251 PenTech ASSOciates, Inc. 7401 Metro Blvd. Tel: (503) 641-8086
Tel: (602) 9945400 201 S.E. 15th Terrace, Suite K Suite 355 TWX: 910-467-8741
Deerfield Beach 33441 Edina 55435
CALIFORNIA Tel: (305) 4214989 Tel: (612) 835-6722 PENNSYLVANIA
Intel Corp. PenTech ASSOciates, Inc. TWX: 910-576-2887 Intel Corp."

7670 Opportunity Rd 111 So. Maitland Ave., Suite 202 275 Commerce Dr.
Suite 135 P.O. Box 1475 MISSOURI 200 Office Center
San Diego 92111 Maitland 32751 Intel Corp. Suite 300
Tel: (714) 2663563 Tel: (305) 6453444 502 Earth City Plaza Fort Washington 19Q3.4
Suite 121 Tel: (215) 5429444
Intel Corp.' TWX: 510-6612077
GEORGIA Earth City 63045
2000 East 4th Street
Pen Tech Associates, Inc Tel: (314) 2911990 Q.E.D. Electronics
Suite 100
Santa Ana 92705 Cherokee Center, Suite 21 Technical Representatives, Inc. 300 N. York Road
Tel: (714) 8359642 627 Cherokee Street 320 Brookes Drive, Suite 104 Hatboro 19040
TWX: 910-5951114 Marietta 30060 Hazelwood 63042 Tel: (215) 6749600
Tel: (404) 4241931 Tel: (314) 7315200
Intel Corp.' TEXAS
15335 Morrison TWX: 910762'()618
ILLINOtS Intel Corp."
Suite 345
Sherman Oaks 91403 Intel Corp.' NEW JERSEY 2925 L. B.J. Freeway
Tel: (213) 9669510 2550 Golf Road, Suite 815 Intel Corp. Suite 175
TWX: 910-4952045 Rolling Meadows 60008 Raritan Plaza Daltas 75234
Tel: (312) 9817200 2nd Floor Tel: (214) 2419521
Intel Corp.' TWX: 910-8605617
TWX: 910-6515661 Raritan Center
3375 Scott Illvd.
Technical Representatlv'.'2 Edison 06617 Intel Corp."
Santa Clara 95051
1502 North Lee Street Tel: (201) 2253000 6420 Richmond Ave.
Tel: (408) 9876086
Bloomington 61701 TWX: 710480-6238 Suite 280
TWX: 9103399279
9103380255 Tel: (309) 8298080 Houston 77057
NEW MEXICO Tel: (713) 7843400
Earle Associates, Inc. TWX: 910-8812490
INDIANA BFA Corporation
4617 Ruffner Street
Intel Corp. P.O. Box 1237 Industrial Digital Systems Corp.
Suite 202
9101 Wesleyan Road Las Cruces 88001 5925 Sovereign
San Diego 92111
Suite 204 Tel: (505) 523-0601 Suite 101
Tel: (714) 2785441
Indianapolis 46268 TWX: 910983'()543 Houston 77036
Mac1 Tel: (713) 9669421
Tel: (317) 2990623 BFA Corporation
2576 Shattuck Ave.
3705 Westerfield, N.E. Intel Corp.
Suite 4B
IOWA Albuquerque 87111 313 E. Anderson Lane
Berkeley 94704
Technical Representatives, Inc. Tel: (505) 2921212 Suite 314
Tel: (415) 8437625
St. Andrews Building TWX: 9109891157 Austin 78752
Mac1 Tel: (512) 4543628
1930 St. Andrews Drive N.E.
P.O. Box 1420 NEW YORK
Cedar Rapids 52405
Cupertino 95014 WASHINGTON
Tel: (319) 3935510 Intel Corp.'
Tel: (408) 2579660
350 Vanderbilt Motor Pkwy. Intel Corp.
Mac' KANSAS Suite 402 Suite 114, Bldg. 3
558 Valley Way Hauppauge 11787 1803 116th Ave. N.e.
Intel Corp.
Calaveras Business Park Tel: (516) 231-3300 Bellevue 98005
9393 W. 110th St., Ste. 265
Milpitas 95035 TWX: 5102276236 Tel: (206) 453-8066
Overland Park 66210
Tel: (408) 9468665 TWX: 9104433002
Tel: (913) 6428080 Intel Corp.
Mac1 80 WaShington 51.
Technical Representatives, Inc. WISCONSIN
P.O. Box 8763 Poughkeepsie 12601
8245 Nieman Road, Suite 100
Fountain Valley 92708 Tel: (914) 473-2303 Intel Corp.
Lenexa 66214
Tel: (714) 8393341 TWX: 510248'()060 150 S. Sunny slope Rd.
Tel: (913) 8880212, 3, & 4
Mac' TWX: 9107496412 Intel Corp.' Brookfield 53005
1321 Centinela Avenue 2255 Lyell Avenue Tel: 1414) 7849080
Technical Representatives, Inc.
Suite 1 Lower Floor East Suite
360 N. Rock Road CANADA
Santa Monica 90404 Rochester 14606
Suite 4
Tel: (213) 8294797 Tel: (716) 254-6120 Intel Semiconductor Corp.
Wichita 67206
Mac1 Tel: (316) 68Hl242 TWX: 5102537391 Suite 233, Bell Mews
20121 Ventura Blvd., Suite 240E Measurement Technology, Inc. 39 Highway 7, 8ells Corners
Woodland HillS 91364 MARYLAND 159 Northern Boulevard Ottawa, OntariO K2H 8R2
Tel: (213) 3475900 Great Neck 11021 Tel: (613) 8299714
Intel Corp.' TELEX: 0534115
7257 Parkway Drive Tel: (516) 4823500
COLORADO Intel Semiconductor Corp.
Hanover 21076 TSquared
Intel Corp.' Tel: (301) 7967500 4054 Newcourt Avenue 50 Galaxy Blvd.
650 S. Cherry Street TWX: 7108621944 Syracuse 13206 Unit 12
Suite 720 Tel: (315) 463-8592 Rexdale, Ontario
Mesa Inc. M9W4Y5
Denver 80222 TWX: 710541'()554
11900 Park lawn Drive Tel: (416) 6752105
Tel: (303) 3218066
Rockville 20852 TSquared TELEX: 06983574
TWX: 9109312289
Tel: Washington (301) 6618430 2 E. Main
Westek Data Products. Inc. Baltimore (301) 792'()021 Victor 14564 Multilek, Inc."
25921 Fern Gulch Tel: (716) 9249101 15 Grenfell Crescent
P.O. Box 1355 MASSACHUSETIS TWX: 5102548542 Ottawa, Ontario K2G OG3
Evergreen 80439 Tel: (613) 2262365
Intel Corp.' TELEX: 0534585
Tel: (303) 6745255 NORTH CAROLINA
27 Industrial Ave.
Westek Data Products, Inc Chelmsford 01824 Intel Corp. Multilek, Inc
1322 Arapahoe Tel: (617) 6678126 154 Huffman Mill Rd. Toronto
Boulder 80302 TWX: 710343-6333 Burlington 27215 Tel: (416) 2454622
Tel: (303) 4492620 Tel: (919) 5643631 Multilek, Inc.
EMC Corp.
Westek Data Products, Inc. 381 Elliot Street PenTech ASSOCiates, Inc. Montreal
1228 W. Hinsdale Dr. Newton 02164 1202 Eastchester Dr. Tel: (514) 481-1350
Littleton 80120 Tel: (617) 2444740 Highpoint 27280
Tel: (303) 7970482 TWX: 922531 Tel: (919) 8839125
Field Application Location

u.s. AND CANADIAN DISTRIBUTORS
ALABAMA COLORADO ILLINOIS MINNESOTA

tHamilton/Avnet Electronics Arrow Electronics, Inc. Arrow Electronics tlndustrial Components
4812 Commercial Drive N.w. Electronics Distribution Division 492 Lunt Avenue 5229 Edina Industrial Blvd.
Huntsville 35805 2121 South Hudson Street P.O. Box 94248 Minneapolis 55435
Tel: (205) 8377210 Denver 80222 Schaumburg 60193 Tel: (612) 8312666
Tel: (303) 7582100 Tel: (312) 8939420 TWX: 9105763153
tPloneer/Huntsvilie
TWX: 9102221807
1207 Putman Drive NW tWyle Distribution Group tArrow Electronics
Huntsville 35805 6777 E. 50th Avenue tHamilton/Avnet Electronics 5230 W. 73rd Street
Tel: (205) 8379033 Commerce City 80022 3901 No. 25th Avenue Edina 55435
TWX: 8107262197 Tel: (303) 2879611 Schiller Park 60176 Tel: (612) 8301800
TWX: 910931'()510 Tel: (312) 6786310 TWX: 9105762726
ARIZONA TWX: 910227'()060
t Hamilton/Avnet Electronics tHamilton/Avnet Electronics
tHamliton/Avnet Electronics 8765 E. Orchard Road Pioneer/Chicago 7449 Cahill Road
505 S. Madison Drive Suite 708 1551 Carmen Drive Edina 55435
Tempe 85281 Englewood 80111 Elk Grove 60007 Tel: (612) 9413801
Tel: (602) 2757851 Tel: (303) 7401000 Tel: (312) 4379680 TWX: 9105762720
TWX: 9109310510 TWX: 9102221834
tWyle Distribution Group
8155 N. 24th Avenue MISSOURI
CONNECTICUT INDIANA
Phoenix 85021 tHamillon/Avnet Electronics
Tel: (602) 2492232 tArrow Electronics tPioneerlindiana 396 Brookes Lane
TWX: 910951-4282 12 Beaumont Road 6408 Castleplace Drive Hazelwood 63042
Wallingford 06492 Indianapolis 46250 Tel: (314) 7311144
CALIFORNIA Tel: (203) 2657741 Tel: (317) 8497300 TWX: 910762'()606
Arrow Electronics, Inc. TWX: 710476'()162 TWX: 8102601794
Electronics Distribution Division NEW HAMPSHIRE
tHamiiton/Avnet Electronics
9511 Ridge Haven Court 643 Danbury Road KANSAS tArrow Electronics
San Diego 92123 Georgetown 06829 tHamiitonlAvnet Electronics 1 Perimeter Road
Tel: (714) 5654800 Tel: (203) 7620361 9219 Quivira Road Manchester 03103
Arrow Electronics, Inc. Overland Park 66215 Tel: (603) 6686968
tHarvey Electronics
Electronics Distribution Division 112 Main Street Tel: (913) 8888900
720 Palomar Avenue NEW JERSEY
Norwalk 06851 tComponent Specialties, Inc.
Sunnyvale, California 94086 Tel: (203) 8531515 8369 Nieman Road tArrow Electronics
Tel: (408) 7393011 TWX: 7104683373 Lenexa 66214 Pleasant Valley Avenue
t Avnet Electronics Tel: (913) 4923555 Moorestowll 08057
350 McCormick Avenue FLORIDA Tel: (609) 2351900
Costa Mesa 92626 MARYLAND TWX: 710897'()829
tArrow Electronics
Tel: (714) 7546111 1001 N.w. 62nd Street Arrow Electronics, Inc. tArrow Electronics
TWX: 9105951928 Suite 108 Electronics Distribution Division 285 Midland Avenue
Hamilton/Avnet Electronics Flo Lauderdale 33309 4801 Benson Avenue Saddle Brook 07662
1175 Bordeaux' Dr. Tel: (305) 7767790 Baltimore 21227 Tel: (201) 7975800
Sunnyvale 94086 Tel: (301) 2475200 TWX: 7109882206
tArrow Electronics
(202) 7371700
Tel: (408) 7433355 115 Palm Bay Road, NW Hamilton/Avnet Electronics
TWX: 9103399332 Suite 10, Bldg. 200 tHamiltonlAvnet Electronics 10 Industrial Road
tHamiiton/Avnet Electronics Palm Bay 32905 7235 Standard Drive Fairfield 07006
Tel: (305) 7251480 Hanover 21076 Tel: (201) 5753390
4545 Viewridge Ave.
TWX: 5109596337 Tel: (301) 7965684 TWX: 7107344338
San Diego 92123
TWX: 7108621861
Tel: (714) 5717510 tHamilton/Avnet Electronics t Harvey Electronics
TWX: 9103351216 6800 Northwest 20th Ave. tPioneer/Washington 45 Route 46
Flo Lauderdale 33309 9100 Gaither Road Pinebrook 07058
tHamilton/Avnet Electronics
10950 W. Washington Blvd. Tel: (305) 9712900 Gaithersburg 20760 Tel: (201) 5753510
TWX: 5109553097 Tel: (301) 9480710 TWX: 7107344382
Culver City 90230
Tel: (213) 5582609 TWX: 7108280545 tHamilton/Avnet Electronics
tPioneer/Orlando
TWX: 910340-6364 or 7073 6220 S. Orange Blossom Trail 1 Keystone Ave.
MASSACHUSETTS Bldg. 36
tHamilton Electro Sales Suite 412
Orlando 32609 tHamiltonlAvnet Electronics Cherry Hill 08034
3170 Pullman Street
Costa Mesa 92626 Tel: (305) 8593600 50 Tower Office Park Tel: (609) 424'()100
Tel: (714) 6414100 TWX: 8108500177 Woburn 01801 TWX: 7108971405
Tel: (617) 2737500
t Avnet Electronics Hamilton/Avnet Electronics
NEW MEXICO
4942 Rosecrans Ave. 3197 Tech. Drive North tArrow Electronics
Hawthorne 90250 SI. Petersburg 33702 960 Commerce Way tAliiance Electronics Inc.
Tel: (213) 9700956 Tel: (813) 5763930 Woburn 01801 11721 Central Ave. N.E.
TWX: 810-863'()374 Tel: (617) 9338130 Albuquerque 87123
tWyle Distribution Group Tel: (505) 2923360
124 Maryland Street Harvey/Boston
GEORGIA TWX: 9109891151
EI Segundo 90245 44 Hartwell Ave.
Tel: (213) 3223826 Arrow Electronics Lexington 02173 Arrow Electronics, Inc.
TWX: 9103487140 or 7111 2979 Pacific Drive Tel: (617) 8619200 Electronics Distribution Division
Norcross 30071 2460 Alamo Avenue, Southeast
tWyle Distribution Group Tel: (404) 4498252 MICHIGAN Albuquerque 87106
9525 Chesapeake Dr. TWX: 8107574213 . Tel: (505) 2434566
San Diego 92123 tArrow Electronics
Tel: (714) 5659171 tHamiltonlAvnet Electronics 3810 Varsity Drive tHamiiton/Avnet Electronics
TWX: 9103351590 6700 185 Access Road, No. 11 Ann Arbor 48104 2524 Baylor Drive, S.E.
Suite IE Tel: (313) 9718220 Albuquerque 87106
tWyle Distribution Group Norcross 30071 TWX: 810223-6020 Tel: (505) 7651500
3000 Bowers Avenue Tel: (404) 448'()800
Santa Clara 95052 tPioneer/Michigan
Tel: (408) 7272500 13485 Stamford
TWX: 910338'()451 or 0296 Livonia 48150
Tel: (313) 5251800
Hamilton/Avnet Electronics TWX: 8102423271
3170 Pullman
Costa Mesa 92626 tHamiitonlAvnet Electronics
Tel: (714) 6411850 32487 Schoolcraft Road
Livonia 48150
Tel: (313) 5224700
TWX: 8102428775
tMicrocomputer System Technical Demonstrator Centers

u.s. AND CANADIAN DISTRIBUTORS
NEW YORK OHIO TEXAS CANADA

Harvey Electronics Arrow Electronics Arrow Electronics
P.O. Box 1208 7620 McEwen Road 13715 Gamma Road ALBERTA
Blnghampton 13902 Centerville 45459 Dallas 75234 Zentronics
Tel: (607) 7488211 Tel: (513) 4355563 Tel: (214) 3867500 9224 27th Avenue
TWX: 510252'()893 TWX: 8104591611 TWX: 910-8615495 Edmonton T6N 1 B2
Arrow Electronics Arrow Electronics Arrow Electronics, Inc. tL.A. Varah Ltd.
900 Broad Hollow Road 6238 Cochran Rd. Electronics Distribution Division 4742 14th Street N.E.
Farmingdale 11735 Solon 44139 10700 Corporate Drive, Suite 100 Calgary T2E 6L7
Tel: (516) 694-6800 Tel: (216) 2483990 Stafford 77477 Tel: (403) 2301235
TWX: 510224-6494 Tel: (713) 491-4100 TWX: 01825897
tHamilton/Avnet Electronics
tArrow Electronics 954 Senate Drive Component Specialties Inc. Zentronics
3000 South Winton Road Dayton 45459 8222 Jamestown Drive 3651 21st N.E.
Rochester 14623 Tel: (513) 4330610 Suite 115 Calgary T2E 6T5
Tel: (716) 2750300 TWX: 9103402531 Austin 78757 Tel: (403) 2301422
TWX: 910338'()026 Tel: (512) 837-8922
tPioneerlDayton
1900 Troy Street TWX: 9108741320 BRITISH COLUMBIA
t Hamllton/Avnet Electronics
167 Clay Road Dayton 45404 Hamilton/Avnet Electronics tL.A. Varah Ltd.
Rochester 14623 Tel: (513) 2369900 10508A Boyer Blvd. 2077 Alberta Street
Tel: (716) 4759130 TWX: 81()"4591622 Austin 78757 Vancouver V5Y lC4
TWX: 910340-6364 Tel: (512) 8378911 Tel: (604) 8733211
Arrow Electronics
tArrow ElectroniCS 10 Knollcrest Dr. tHamiiton/Avnet ElectroniCS TWX: 6109291068
7705 Maltlage Drive Cincinnati 45237 4445 Sigma Road Zentronlcs
Liverpool 13088 Tel: (513) 7615432 Dallas 75240 550 Cambie SI.
Tel: (315) 6521000 TWX: 8104612670 Tel: (214) 6618661 Vancouver V6B 2N7
TWX: 710545'()230 TWX: 910-8605371 Tel: (604) 6882533
t Pioneer/Cleveland
Arrow ElectroniCS 4800 E. 131st Street tHamilton/Avnet Electronics TWX: 045077-89
20 Oser Avenue Cleveland 44105 3939 Ann Arbor Drive
Hauppauge 11787 Tel: (216) 5873600 Houston 77063 MANITOBA
Tel: (516) 231-1000 TWX: 810-4222210 Tel: (713) 7801771 L.A. Varah
TWX: 510224-6494 11832 King Edward Street
t Hamllton/Avnet Electronics tComponent Specialties, Inc.
t Hamilton/Avnet Electronics 4588 Emery Industrial Parkway 10907 Shady Trail, Suite 101 Winnipeg R2R ONl
16 Corporate Circle Warrensville Heights 44128 Dallas 75220 Tel: (204) 633-6190
E. Syracuse 13057 Tel: (216) 8313500 Tel: (214) 3576511 TWX: 0755365
Tel: (315) 4372641 TWX: 910-8614999 Zentronics
tHamiiton/Avnet Electronics OKLAHOMA tComponent Specialties, Inc. 590 Berry SI.
5 Hub Drive tComponents Specialties, Inc. 8585 Commerce Park Drive, Suite 590 Winnipeg R3H OSl
Melville, Long Island 11746 7920 E. 40th Street Houston 77036 Tel: (204) 7758661
Tel: (516) 4546000 Tulsa 74145 Tel: (713) 7717237
TWX: 510252'()893 Tel: (918) 6642820 TWX: 910-8812422 ONTARIO
t Harvey ElectroniCS TWX: 910-8452215 tL.A. Varah, Ltd.
UTAH 505 Kenora Avenue
60 Crossways Park West
Woodbury 11797 OREGON tHamilton/Avnet Electronics Hamilton L8E 3P2
Tel: (516) 9218700 t Hamilton/Avnet Electronics 1585 West 2110 South Tel: (416) 5619311
TWX: 5102212184 6024 SW Jean Rd. Salt Lake City 84119 TWX: 061-8349
Bldg. C, Suite 10 Tel: (801) 9722800 tHamiiton/Avnet ElectroniCS
Harvey/Rochester
840 Airport Park Lake Oswego 97034 3688 Nashua Drive, Units G & H
Fairport 14450 Tel: (503) 635-8157 WASHINGTON M isslssauga L4V 1 M5
Tel: (716) 3817070 tAlmac/Stroum Electronics Arrow Electronics, Inc. Tel: (416) 6777432
8022 S.W. Nimbus, Bldg. 7 Electronics Distribution Division TWX: 6104928660
NORTH CAROLINA Beaverton 97005 1059 Andover Park East tHamliton/Avnet Electronics
Tel: (503) 6419070 Tukwila 98188 1735 Courtwood Crescent
Pioneer/Carolina
Tel: (206) 575'()907 Ottawa K2C 3J2
106 Industrial Ave.
PENNSYLVANIA Tel: (613) 2261700
Greensboro 27406 tHamilton/Avnet Electronics
Tel: (919) 2734441 Pioneer/Pittsburgh 14212 N.E. 21st Street tZentronics
TWX: 510925111:4 560 Alpha Drive Bellevue 98005 141 Catherine Street
Pittsburgh 15238 Tel: (206) 7468750 Ottawa K2P 1C3
t Hamilton/Avnet Electronics
Tel: (412) 7822300 Tel: (613) 238-6411
2803 Industrial Drive tAlmac/Stroum Electronics
TWX: 7107953122 TWX: 0533636
Raleigh 27609 5811 Sixth Ave. South
Tel: (919) 8298030 Pioneer/Delaware Valley Seattle 98108 tZentronics
141 Gibraltar Road Tel: (206) 7632300 1355 Meyerside Drive
Arrow Electronics
Horsham 19044 TWX: 9104442067 Mississauga, Ontario L5T lC9
938 Burke Street
Tel: (215) 6744000 Tel: (416) 6769000
WinstonSalem 27102 tWyle Distribution Group
TWX: 510-665-6778 Telex: 06983-657
Tel: (919) 7258711 1750 132nd Avenue NE
TWX: 5109224765 tArrow/ ElectroniCS Bellevue 98005
4297 Greensburg Pike Tel: (206) 4538300 QUEBEC
Suite 3114 TWX: 9104432526 tHamilton/Avnet Electronics
Pittsburgh 15221 2670 Sabourin Street
Tel: (412) 3514000 WISCONSIN SI. Laurent H4S 1M2
tArrow ElectroniCS Tel: (514) 3316443
TENNESSEE TWX: 6104213731
430 W. Rawson Avenue
tArrow Electronics Oak Creek 53154 Zentronics
P.O. Box 129 Tel: (414) 764-6600 5010 Pare Street
W. Andrew Johnson Hwy. TWX: 910338'()026 Montreal H4P 1 P3
Talbott 37677 Tel: (514) 7355361
t Hamilton/Avnet Electronics
Tel: (615) 5872137 TWX: 05827535
2975 Moorland Road
New Berlin 53151
Tel: (414) 7844510
TWX: 9102621182
tMicrocomputer System Technical Demonstrator Centers

INTERNATIONAL SALES AND MARKETING OFFICES
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ARGENTINA FINLAND ITALY SOUTH AFRICA

Micro Sistemas S.A. Oy Fintronic AB Eledra 3S S.P.A. Electronic Building Elements
9 De Julio 561 Melkonkatu 24 A Viale Elvezia, 18 Pine Square
Cordoba SF-00210 I 20154 Milan 18th Street
Tel: 54-51-32-880 Helsinki 21 Tel: (02) 34.93.041-31.85.441 Hazelwood, Pretoria 0001
TELEX: 51837 BICCO Tel: 0-6926022 TELEX: 332332 Tel: 789221
TELEX: 124224 Ftron SF TELEX: 30181SA
AUSTRALIA JAPAN
A_J_F. Systems & Components Pty. Ltd. FRANCE Asahi Electronics Co. Ltd. SPAIN
310 Queen Street Celdis S.A.' KMM Bldg. Room 407 Interface
Melbourne 53, Rue Charles Frerot 2-14-1 Asano, Kokura Av. Generalisimo 51 9'
Victoria 3000 F-94250 Genti IIy Kita-Ku, Kitokyushu City 802 E-Madrid 16
Tel: Tel: (1) 581 00 20 Tel: (093) 511-6471 Tel: 4563151
TELEX: TELEX: 200 485 TELEX: AECKY 7126-16
ITT SESA
Warburton Franki Feutrier Hamilton-Avnet Electronics Japan Ltd. Miguel Angel 16
Corporate Headquarters Rue des Trois Glorieuses YU and YOU Bldg. 1-4 Horidome-Cho Madrid 10
372 Eastern Valley Way F-42270 SI. Priest-en-Jarez Nihonbashi Tel: (1) 4190957
Chats wood, New South Wales 2067 Tel: (77) 74 67 33 Tel: (03) 662-9911 TELEX: 27707/27461
Tel: 407-3261 TELEX: 300 0 21 TELEX: 2523774
TELEX: AA 21299 SWEDEN
Metrologie' Nippon Micro Computer Co. Ltd.
AUSTRIA La Tour d' Asnieres Mutsumi Bldg. 4-5-21 Kojimachi AB Gosta Backstrom
4, Avenue Laurent Cely Chlyoda-ku, Tokyo 102 Box 12009
Bacher Elektronische Geraete GmbH 92606-Asnieres Tel: (03) 230-0041 10221 Stockholm
Rotenmulgasse 26 Tel: 791 44 44 Tel: (08) 541 080
A 1120 Vienna Ryoyo Electric Corp.
TELEX: 611 448 Konwa Bldg. TELEX: 10135
Tel: (0222) 83 63 96
Tekelec Airtronic' 1-12-22, Tsukiji, l-Chome Nordisk Electronik AB
TELEX: (01) 1532
Cite des Bruyeres Chuo-Ku, Tokyo 104 Box 27301
Rekirsch Elektronik Geraete GmbH Rue Carle Vernet Tel: (03) 543-7711 S-10254 Stockholm
Lichtensteinstrasse 97 F-92310 Sevres Tel: (08) 635040
Tokyo Electron Ltd.
A 1000 Vienna Tel: (1) 534 7535 TELEX: 10547
No.1 Higashikata-Machi
Tel: (222) 347646 TELEX: 204552 Midori-Ku, Yokohama 226
TELEX: 74759 SWITZERLAND
Tel: (045) 471-8811
GERMANY TELEX: 781-4473
BELGIUM Industrade AG
Electronic 2000 Vertriebs GmbH Gemsenstrasse 2
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TWX: 910-467-8741 K2H 8R2
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INTEL CORPORATION, 1981 AFN01300A1

Memory Organization, Addressing Modes and Instruction Set

Expanded 8051 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-1

8051 Software Routines

Device Specifications ................................... 6-1

Component Data Sheets

Development Support Tools

MANUAL ORGANIZATION 8051 Family

0) An 8-bit timer/counter with a divide-by-32 Development Support Tools

symbolic debugging support for the 8051 microcom-

All references to program variables and labels are sym-

The first three methods can be used for addressing

INTERNAL DATA MEMORY

Figure 21. 8051 Family Memory Organization

Instruction Decoder B Register

The Internal Data RAM provides a convenient 128-byte Stack Pointer

REGISTER BANK 1 CONTROL

Figure 22. 8051 Family Functional Block Diagram

21H OF OE 00 OC OB OA 09 08 OOOH 07 I 06 I D5 I 04 I 03 I 02 I 01 I DO PSW

Figure 23. Data RAM Bit Address Space

On any addressable bit, the Boolean processor can per-

if-set, jump-if-not-set, jump-if-set-then-clear and move

Figure 24. Special Function Register Bit

The processor records the active priority level(s) by set-

Interrupt Source Starting Address

stead of the logic level at the pin/pins. Pins comprising

and write to a port's bit/byte are INC, DEC, CPL, JBC,

WRITE PULSE Accessing External Memory

ing pins of Port 3 may be individually programmed as ACCESSING EXTERNAL MEMORY-OPERATION

Figure 27. Program Memory Read Cycle Timing

Figure 28. Data Memory Read Cycle Timing

Figure 29. Data Memory Write Cycle Timing

Figure 210. Timer/Event Counter 0 Control and Status Flag Circuitry

Figure 211. Timer/Event Counter 1 Control and Status Flag Circuitry

OPERATION the time when a toggled input (transition from high to

8051 8051 8051 8051 8051 8051 8051 8251

Figure 212. UART Interface Technique

Operating Modes 1 through 3

First, the 8051 's serial channel provides no indication

Figure 218. Power Down Sequence

A verify may be performed on the programmed bits to

Table 2-11 describes the levels needed on the pins to pro-

Table 211. Voltage Inputs for EPROM ProgrammingNerifying

PROGRAM VIHI VIL VIH Vpp VIL VIL

EXTE1RNAL OVERLAPPED SPACE

INTERNAL DATA MEMORY

Figure 3-1. 8051 Family Memory Organization

128 ...127....:::.- 23H 1F 1E 10 1C 1B 1A 19 18 35

ADORE SS- 48 21H OF DE 00 DC DB OA 09 08 33

Registers Program Status PSW 208(DOH)

Stack Pointer SP 129(8IH)

Ports Port 0* PO 128(80H)

Interrupt Priority IPC 184(B8H)

Timer Mode TMOD 137(89H)

Timer Control* TCON 136(88H)

Serial I/O Serial Control* SCON 152(98H)

contents of RO or Rl, according to bit 0 of the instruc-

'BU' !'" '" II'"

REGTER 1..........-"--"'1/<-16----;1 REGIST':~DIRECT 1

Encoding: 1-10_01....1____1 _.....J I immediate data "