International Journal on Recent and Innovation Trends in Computing and Communication ISSN: 2321-8169

Volume: 4 Issue: 5 66 - 71
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Baseband Data Handling System Using LEON3FT Processor
Arun. N Dr. S Revathi
School of Electronics Engineering (SENSE) School of Electronics Engineering (SENSE)
VIT UNIVERSITY VIT UNIVERSITY
Tamil Nadu, INDIA Tamil Nadu, INDIA
arun.n@outlook.com srevathi@vit.ac.in

Abstract The data handling system is used to receive the data from the payloads of the satellite and format the data into suitable form so that it
can be successfully received at the ground station. Data handling system consists of payload interface unit, preprocessor unit, data compression
unit, data encryption unit, and channel coding and frame formatter. Till now, data handling systems were developed with the help of FPGAs.
The current project involves the development of on board data handling system based on LEON3FT processor. Processor provides the
advantages of reduced hardware complexity, programmability and computational performance.

Keywords- leon3,data handling system, satellite, leon3 IP core, formatter

__________________________________________________*****_________________________________________________

I. INTRODUCTION II. DATA HANDLING SYSTEM : A SURVEY

Data Handling Systems are required to perform the capacity The payload data from the different payload will enter into
of preparing the Digital Video/Science information got from the data handling system through different payload interfaces
the optical/microwave/science payloads of IRS/SS satellites, such as low LVDS, ECL, TTL, LSTTL etc. Payload interface
utilizing a few uncommon strategies and advancements and logic provides obligatory control signals to payloads, if
configuration into the Digital Data Stream(s) suitable for required, and receives payload data. Data is transferred to BDH
transmission of the information from the satellite to ground at system with deference to the control signals or predefined
information rates going from many Kbps to several Gigabits protocols. Commonly used logic families for interfacing are
for every second contingent on the payload and mission. TTL, LSTTL, LVDS, and ECL etc. Standard buses like 1553B,
Depending on the type of payload data types and requirement CAN, Space wire etc. are additionally utilized in categorical
of the mission, a typical data handling system shall implement cases. Payloads have different interfaces and data rates.
functions like data compression, Data Formatting, Data
encryption and channel coding techniques.
Spacecraft-generated application data are formatted into PAYLOAD 1
end-to-end transportable data units and a transfer Frame is
generated to reliably transport the data through the RF channel
to the receiving ground station network. Transfer Frame begins RF
PAYLOAD 2 SYS
with an attached frame synchronization marker followed by BDH SYSTEM
header information and payload data units. Formatted data is TEM
usually randomized except for the frame sync marker to ensure PAYLOAD N
proper receiver operation and to maintain bit (or symbol)
synchronization. On the receiving end, a frame synchronizer is
used to detect beginning and end of the frame. Once the frame
is identified based on the frame synchronization marker, header DATA FROM
and payload data units are separated for further data processing. OTHER SSR
At the ground formatted data is stored in the onboard in SUBSYSTEM
solid state recorders (SSR) for later playback. SSR plays a key S
role in remote sensing mission for the worldwide scope and is Figure 1. Block Diagram of typical data handling system
utilized for putting away the information as well as for
executing rate supports when arranged information rate is Pre-handling is done on the payload information to make
higher/lower than the download transmission rate. BDH system the resulting processing (compression) more effective, and is
receives data from payloads as well as from other subsystems extremely applicable on account of imaging payloads.
on board spacecraft. Formatted/encrypted/compressed data is Radiometric correction is carried out on the raw image data
routed either to RF system for transmission to ground or to received from the electro-optical instrument to remove photo
SSR for recording. Recorded data will be played back later response non-uniformities in sensor output levels. There are
during ground station visibility. many other types of onboard processing that could be applied
Major imaging payloads include PAN & multispectral in remote sensing to amend overall system efficiency. For
Charge Coupled Device (CCD) cameras payloads which are example, it might be benign to analyze the images in order to
usually used in different satellite missions. Normally the data detect the presence of clouds or other undesirable features.
rates of typical payloads are very high and are variable from Information arrangement is consummated to make a physical
few hundreds of megabits per second to Gigabits per second picture as required by information compression calculation. In
particular, cases preprocessing and arrangement may not be
pertinent as on account of exploratory missions.
The main purport of compressing the data is to store as well
as represent the data in fewer bits so that we can eschew the
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International Journal on Recent and Innovation Trends in Computing and Communication ISSN: 2321-8169
Volume: 4 Issue: 5 66 - 71
_______________________________________________________________________________________________
redundancy of the data and make the system overall efficient. LEON3 processor will accept the payload data from the
The compression is more germane when the abundance of data different interfaces such as CAN, SpaceWire and this data can
is to process and to be stored. The compression techniques can be processed inside the processor or it can pass the data into
be mainly classified into two types, Lossy, and Lossless the FPGA so that it can handle the data through some
compression technique. In the lossless compression technique, dedicated modules inside the FPGA which includes
information content is not lost but the compression ratio will be formatting, compression, channel coding or preprocessing
much lesser when compared to the Lossy compression such as Non Uniformity correction (NUC).
technique. The FPGA also have its own interfaces such as Serializer and
One of the Encryption scheme utilized in the satellite is
Deserializer, Transceiver 1553, LVDS which will also able to
stream ciphering. A stream cipher engenders a sequence of bits
accept the payload data directly through the FPGA and will be
called key stream. An LFSR (Linear Feedback Shift Register)
can engender such stream. Encryption is accomplished by able to process those data with the help of the LEON3
coalescing the key stream with payload data bit sagacious XOR processor. The memory units connected to the FPGA are
operation. Now AES (Advanced Encryption Standards) is SRAM, SDRAM and programmable ROM.
becoming more popular and is recommended by CCSDS. A. SCHEMATIC DESIGN
Multiple individual payloads in the satellite system will be
having different data rates and the packet length will be also The main interfaces provided for the LEON3 are Debug
different. So the necessity of making this asynchronous payload Support Unit (DSU), JTAG, CAN, and SpaceWire. The storage
data into a synchronous data is by converting it into the connected to the LEON3 are 2 Gb SDRAM. An LVTH is also
standardized format. The asynchronous payload data is connected to the processor so that to interface with the 5v
multiplexed together into a single synchronous data stream of devices.
fixed length coded frames for the reliable data reception by the Interface connected to the FPGA Prosaic3 are LVDS,
ground base station. LVTH and memory is connected as SRAM and NOR flash
Channel coding is a strategy by which information can memory. EEPROM is connected to PROASIC3 and is accessed
be sent from a source to a destination by preparing information by the LEON3. SpaceWire control is also connected to the
so that distinct messages are effortlessly recognizable from PROASIC. The FPGA will acts as a memory mapping devices
each other. This permits recreation of the information with low for the LEON3.
error probability The FPGA and Processor is connected through the general
purpose input output device (GPIO). It will also act as a
III. SYSTEM DESIGN programmable interrupt. The signals shared between the two
devices are Chip select signals, SRAM control signals, PROM
In the design diagram, FPGA provides the interface and read write signals
for various payloads, stores the data into memory
whenever necessary.
FPGA interacts with LEON3 processor to receive the
data from payloads that are interfaced with processor
(CAN, SpaceWire).
FPGA also interacts with processor during
mathematical calculations, reception of commands,
transmission of telemetry parameters etc.
FPGA further processes all the payload data into
desirable format and transmits it to the further
subsystems

Transcei PROM SRAM/ PROM/ ME

ver chip SDRA MO
M NOR RY
1553

Interfa Figure 3 Schematic Design

PROASIC LEON3 SRAM/
ce 3 FPGA FT SDRAM B. COMPONENTS
devices
SER/D 1) Power, Reset & Clock
ESER, Clock signal is of 40 Mhz for the other interfacing
LVDS, devices the voltage generated by the system are 3.3v, 5v, 2.5v
CMOS and 1.5v. 3v is also generated for the RESET purpose for the
Power/auxiliar
etc.,
y circuits LEON3. However the input signal voltage given to the system
is of ONLY 5v.
Figure 2. Block Diagram of Schematic

The heart of the system is the LEON3 processor which will 2) LEON3FT
be able to do more complex mathematical calculations so that The LEON3FT is fault-tolerant SPARC V8 32 bit 66 MHz
overall hardware complexity of the system can be reduced. processor. It is fabricated in monolithic technology. The
processor is having pipelined design and hold the ability to
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International Journal on Recent and Innovation Trends in Computing and Communication ISSN: 2321-8169
Volume: 4 Issue: 5 66 - 71
_______________________________________________________________________________________________
execute various high performance tasks.LEON3FT is mainly SpaceWire, UART or through JTAG. DSU unit will access all
settled for space backgrounds. It is having the ability to correct the registers of the processor and cache memory.
the errors present in the on-chip RAM. The interface present in 4) ProASIC3E
the LEON3FT includes SpaceWire, PCI, CAN bus, Ethernet, ProASIC3E is the third-generation flash FPGA family from
memory controller, programmable interrupt and contain an the Actel which deals performance, density, and features
AMBA interface which is integrated to the core of LEON3FT further than the ProASICPLUS family. The main advantage of
LEON3FT was fundamentally intended for the space this FPGA is it provide high security, low power and is Live at
exploration application and is funded by the European Space power-up (LPA). This also provides a 1 Kbit of on-chip, non-
Agency (ESA). It is designed to have high performance with volatile, programmable Flash ROM memory.
low complexity and with low power consumption.
The important features of LEON3FT are it is IEEE-1754 IV. IP CORE INSTANTIATION
SPARC V8 compliant, 32-bit processor. It comes with a 5 The GIRLAB IP core is a reusable set of integrated core.
stages pipeline. The processor also support the This is developed mainly for system on chip development. This
multiprocessing ability in which multiple core can used for core is dependent on vendor and will support multiple CAD
processing. On-chip debugging ability with trace buffer tools and different mark technologies. The configuration will
support is also available for this processor. be using the paly and play method which result in unaltered
global resources. The LEON3 processor is also a synthesizable
3) LEON3 Core VHDL models with the architecture of SPARC V8 32 bit.
A. Minimal System Requirement
IP cores required for the minimal LEON3 is
CLKGEN: Clock Generator
MEMCNTRL: Controller to access ROM and RAM
RSTGEN: Reset Generator
GPTIMER: General purpose Timer
AHBCNTRL: Controller for AHB bus
APBCNTRL: Controller for APB bus
B. Typical Memory Map
The most important memory map area are RAM and
PROM area, the RAM area will starts from 0x40000000 and
PROM area is from 0x00000000. The location of APB/AHB is
little bit less important and the location is from 0x80000000
C. Installation
GRLIB is available as a zip file and can be installed in any
location on the system.
gunzip the tar file using the gunzip command in bash shell
The distribution includes the following files in the
hierarchy:
Figure 4. LEON 3FT Core Doc: will contain the documentation about the process
lib: various VHDL libraries which is useful
The main features of LEON3FT is the 7 stage pipelining with software: various software utilities available
Harvard Architecture, which is having a distinct instruction verification: contain the test benches
and data cache, hardware divider and multiplier, floating point board: files for different FPGA prototyping design boards
unit, hardware debug support. designs: template designs for various board
bin: contain different scripts and tool support files
The main features of the SPARC architecture is it will achieve
a 60MIPS throughput when a clock frequency of 75 MHz is D. Implementation
used. The size of the cache parity is about 4bit and the size of Implementation is typically done in three steps
instruction cache memory and data cache is 32 byte and 16 1. CONFIGURATION USING XCONFIG
byte respectively. The pipeline available is seven stage which 2. SIMULATION OF DESIGN
will help in handling the multiple tasks simultaneously. The 3. SYNTHESIS, PLACE&ROUTE
floating point unit will work as parallel operation.
The number of interrupts available are 15 hardware interrupts The template design is based on three VHDL files
which has been generated by the general purpose input output
(GPIO). This processor also support the SPARC trap models. 1) config.vhd: This package contain design configuration
The sensitivity of interrupt can be either level sensitive or edge parameters. This is automatically generated by using the
sensitive. The interrupts are also programmable. xconfig GUI tools
Debug Support Unit (DSU) will provide an platform for 2) leon3mp.vhd: Top level entities of the on chip IP-cores,
debugging without the disturbing the whole system. Debug It will also use the config.vhd files to instantiate the cores
unit can be connected with the interfaces such as PCI, 3) testbench.vhd: test bench

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International Journal on Recent and Innovation Trends in Computing and Communication ISSN: 2321-8169
Volume: 4 Issue: 5 66 - 71
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E. Configuration Consultative Committee for Space Data Systems (CCSDS).
Using the command make xconfig in bash shell (Unix This protocol is designed to meet the requirement of space
machine) or Cygwin (windows machine). It will start the GUI mission to efficiently transfer the data of various length, type
for configuration, from that window the LEON3 is modified and characteristics over the network that involves a ground-to-
according to the design space or space-to-space link of communication.
The formatter provides a unidirectional transfer of data
F. Design flow from a single or multiple source user application to one or more
Download LEON3FT source code from the web destination user application through one or more subnetworks.
Modifying the design of the IP core and making it to The definition of Logical Data Path (LDP) is the path from the
compactable in the ACTEL ProAsic3 FPGA and also source user application to the destination.
by adding design blocks for the target FPGA A. Block Diagram
Simulate using a ModelSim simulator
The only interface with the FPGA is the interface with the
Synthesize using Synplify
LEON3FT. The data from the LEON3FT through its
Place and route FPGA using vendor specific tools
CAN/SPACEWIRE/UART interface is collected from the
Actel Libero Designer
LEON3FT by the formatter FPGA.
Target design to one of many development boards
The data will be either in the form of serial data or in parallel
G. Instantiation Result form, the proposed formatter design is flexible for both the
Result section will show the transcript window of the data through separate enable signal to switch between the two
Instantiated LEON3 IP core using the Libero IDE 10.2. The options. The data are typical payload data which are the
Instantiated number of master and slaves can be seen in the output of the Charge Coupled Device (CCD) or PAN
output of the transcript. This IP care can be directly fused into multispectral imaging devices.
the FPGA to make the Processor into an FPGA. From the The compressed data is converted into packet in this
output it is obvious that the Design contain 3 masters and 8 module. The packet is generated by adding the packet header
slaves. The masters are Leon3 SPARC v8 processor AHB into the payload data. The packet header contains the
UART debug UART and JTAG Debug link. Application process ID (APID), Packet count, number of
bytes in the packet.

PACKETIZATION FRAME
FORMATION

COMPRESSION RANDOMIZATI
ON

PREPROCESSING FRAME SYNC

MARKER

LEON3FT

FRAME

Data from payload through

CAN/SPACEWIRE/UART interface

Figure 6. Block Diagram of formatter

PACKET HEADER PRE-PROCESSED DATA

APID PACKET COUNT NUMBER OF BYTES

Figure 7. Packet Format

Here FRAME is formed by taking multiple packets and

adding the frame header into the constant or fixed length.
Figure 5. Transcript of the Instantiation.

V. DATA HANDLING CHAIN FORMATTER

The purpose of the formatting is to specify a standard
protocol. This formatter design is inspired from the
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International Journal on Recent and Innovation Trends in Computing and Communication ISSN: 2321-8169
Volume: 4 Issue: 5 66 - 71
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C. Output of the Formatter
FRAME HEADER PACKET_1
PACKET_2 . PACKET_N

SATELLITE ID FRAME COUNT NUMBER OF BYTES

Figure 8. Frame Format

PACKET HEADER

Pseudo-randomizer is used to improve symbol transition

density as an aid to bit synchronization at the receiving end. Figure 11. Packet with Packet header
The method for ensuring sufficient transitions is to exclusive-
OR each bit of the Transfer Frame with a standard pseudo-
random sequence.
Frame synchronization marker is used to identify the
Frame from the ground station. The frame synchronization
marker include the code as 1A CF FC 1D.
Frame sync
Marker
FRAME SYNC M FRAME

Figure 12. Frame with sync marker

1A CF FC 1D VI. SOFTWARE FOR READ AND WRITE OPERATION

FOR LEON3FT
Figure 9. Frame Synchronization marking
A. Flow Chart For The Application
B. Flow Chart
START
DATA FROM
LEON3FT
Declaration of the pointer
PACKET
HEADER
PARALLEL DATA Allocation of memory
Define number of data is to be
written

PACKET DATA If the

HEADER numbe
r >0

Writing the memory with

FRAME the random hexadecimal
HEADER data

FRAME PACKET1
HEADER PACKET2 Printing the progress of
the write operation

SYNC
MARKER

N Y Reading the Random data,

Random?
stored in the memory

RANDOMIZATION
BLOCK
Printing the data written
data from the memory
SYNC MARKER FRAME

Stop
SYNC MARKER RANDOM DATA

Figure 13. Flow chart of the program

Figure 10. Flowchart of Formatter
LEON3FT Aeroflex Gaisler development tools are
installed. With the help of Eclipse environment an application
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International Journal on Recent and Innovation Trends in Computing and Communication ISSN: 2321-8169
Volume: 4 Issue: 5 66 - 71
_______________________________________________________________________________________________
is coded which will write some random data directly into the convert the payload data which has been acquired with the
internal registers of LEO3FT and reading the data from the help of LEON3 processor interface into the frame format.
LEON3FT processor. In the last module a software has been designed which will
B. Execution Result link the module three and module four in such a way that the
data from the payload will be acquired through LEON3 is
written into the LEON3 and it read the written data back from
the LEON3 so that it will be available to the formatter
VIII. FUTURE SCOPE
Channel coding, compression, Encryption module can also
be incorporated into the system to make the design robust.
The IP Core can be further modified to make the processor
more dedicated for handling the data
More applications can be developed to utilize the
programming capability of the LEON3.
IX. APPLICATION
Since the schematic is flexible, this can be used for any on
board processing mission such as Space exploration satellites,
Imaging satellites, Reconnaissance or spy satellites,
Astronomy satellite.
REFERENCES
[1] Aeroflex Colorado Springs Inc., UT699 LEON
3FT/SPARC V8 MicroProcessor Advanced User Manual,
Aug. 2010
Figure 14. Output: Memory writing [2] Aeroflex Colorado Springs Inc., UT699 32-bit Fault-
Tolerant SPARC V8/LEON 3FT Processor Data Sheet,
Feb.2011
[3] AMBA Specification (Rev. 2.0), http://www.arm.com/.
[4] SPARC assembly language reference manual,
http://docs.sun.com/
[5] Cadence Design System, http://www.cadence.com/.
[6] Microsemi Axcelerator Family FPGAs ProASIC3
Revision-18 March 2012
[7] GRLIB IP Library Users Manual (V1.1.0),
http://gaisler.com/products/grlib/grlib.pdf

Figure 15. Output: Memory reading

VII. CONCLUSION
Data handling system using the LEON3FT processor is
designed successfully, the outcome of this project is based on
the result obtained from the four design modules.
In the first module schematic for the PCB fabrication for the
proposed system is designed.
The second module IP core of the LEON3FT has been
instantiated successfully which allows the flexibility for the
future design simulation for the modified LEON3FT core.
In third module the formatter chain for a typical data handling
system is designed inside a FPGA, which will successfully
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