0

R XC9536XL High Performance

CPLD
DS058 (v1.9) April 3, 2007 0 0 Product Specification

Features 54V18 Function Blocks, providing 800 usable gates with

5 ns pin-to-pin logic delays propagation delays of 5 ns. See Figure 2 for architecture
System frequency up to 178 MHz overview.
36 macrocells with 800 usable gates Power Estimation
Available in small footprint packages Power dissipation in CPLDs can vary substantially depend-
- 44-pin PLCC (34 user I/O pins) ing on the system frequency, design application and output
- 44-pin VQFP (34 user I/O pins) loading. To help reduce power dissipation, each macrocell
- 48-pin CSP (36 user I/O pins) in a XC9500XL device may be configured for low-power
- 64-pin VQFP (36 user I/O pins) mode (from the default high-performance mode). In addi-
- Pb-free available for all packages tion, unused product-terms and macrocells are automati-
Optimized for high-performance 3.3V systems cally deactivated by the software to further conserve power.
- Low power operation For a general estimate of ICC, the following equation may be
- 5V tolerant I/O pins accept 5 V, 3.3V, and 2.5V used:
signals ICC(mA) = MCHS(0.175*PTHS + 0.345) + MCLP(0.052*PTLP
- 3.3V or 2.5V output capability + 0.272) + 0.04 * MCTOG(MCHS +MCLP)* f
- Advanced 0.35 micron feature size CMOS where:
Fast FLASH technology
MCHS = # macrocells in high-speed configuration
Advanced system features
PTHS = average number of high-speed product terms
- In-system programmable
per macrocell
- Superior pin-locking and routability with
Fast CONNECT II switch matrix MCLP = # macrocells in low power configuration
- Extra wide 54-input Function Blocks PTLP = average number of low power product terms per
- Up to 90 product-terms per macrocell with macrocell
individual product-term allocation f = maximum clock frequency
- Local clock inversion with three global and one MCTOG = average % of flip-flops toggling per clock
product-term clocks (~12%)
- Individual output enable per output pin This calculation was derived from laboratory measurements
- Input hysteresis on all user and boundary-scan pin of an XC9500XL part filled with 16-bit counters and allowing
inputs a single output (the LSB) to be enabled. The actual ICC
- Bus-hold circuitry on all user pin inputs value varies with the design application and should be veri-
- Full IEEE Standard 1149.1 boundary-scan (JTAG) fied during normal system operation. Figure 1 shows the
Fast concurrent programming above estimation in a graphical form. For a more detailed
Slew rate control on individual outputs discussion of power consumption in this device, see Xilinx
Enhanced data security features
Excellent quality and reliability
- Endurance exceeding 10,000 program/erase
cycles
- 20 year data retention
- ESD protection exceeding 2,000V
Pin-compatible with 5V-core XC9536 device in the
44-pin PLCC package and the 48-pin CSP package
WARNING: Programming temperature range of
TA = 0 C to +70 C
Description
The XC9536XL is a 3.3V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of two

2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

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Product Specification
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application note XAPP114, Understanding XC9500XL

CPLD Power.
70

60
178 MHz
nce
or ma
Typical ICC (mA)

50
P e rf
h
Hig
40
er
30 P ow
L ow 125 MHz
20

10

0 50 100 150 200 250

Clock Frequency (MHz)
DS058_01_121501

Figure 1: Typical ICC vs. Frequency for XC9536XL

3
JTAG
JTAG Port 1 In-System Programming Controller
Controller

54
Function
I/O 18 Block 1
Macrocells
I/O 1 to 18
I/O
Fast CONNECT II Switch Matrix

I/O 54
Function
18 Block 2
Macrocells
I/O 1 to 18
Blocks
I/O

I/O

I/O

I/O
3
I/O/GCK
1
I/O/GSR
2
I/O/GTS

DS058_02_081500

Figure 2: XC9536XL Architecture

Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.

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Product Specification
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Absolute Maximum Ratings(2)

Symbol Description Value Units
VCC Supply voltage relative to GND 0.5 to 4.0 V
VIN Input voltage relative to GND(1) 0.5 to 5.5 V
VTS Voltage applied to 3-state output(1) 0.5 to 5.5 V
TSTG Storage temperature (ambient)(3) 65 to +150 oC

TJ Junction temperature +150 oC

Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the
device pins may undershoot to 2.0 V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA. External I/O voltage may not exceed VCCINT by 4.0V.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
3. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb-free
packages, see XAPP427.

Recommended Operation Conditions

Symbol Parameter Min Max Units
VCCINT Supply voltage for internal logic Commercial TA = 0 oC to 70oC 3.0 3.6 V
and input buffers Industrial TA = 40oC to +85oC 3.0 3.6 V
VCCIO Supply voltage for output drivers for 3.3V operation 3.0 3.6 V
Supply voltage for output drivers for 2.5V operation 2.3 2.7 V
VIL Low-level input voltage 0 0.80 V
VIH High-level input voltage 2.0 5.5 V
VO Output voltage 0 VCCIO V

Quality and Reliability Characteristics

Symbol Parameter Min Max Units
TDR Data Retention 20 - Years
NPE Program/Erase Cycles (Endurance) 10,000 - Cycles
VESD Electrostatic Discharge (ESD) 2,000 - Volts

DC Characteristic Over Recommended Operating Conditions

Symbol Parameter Test Conditions Min Max Units
VOH Output high voltage for 3.3V outputs IOH = 4.0 mA 2.4 - V
Output high voltage for 2.5V outputs IOH = 500 A 90% VCCIO - V
VOL Output low voltage for 3.3V outputs IOL = 8.0 mA - 0.4 V
Output low voltage for 2.5V outputs IOL = 500 A - 0.4 V
IIL Input leakage current VCC = Max; VIN = GND or VCC - 10 A
IIH I/O high-Z leakage current VCC = Max; VIN = GND or VCC - 10 A
IIH I/O high-Z leakage current VCC = Max; VCCIO = Max; - 10 A
VIN = GND or 3.6V
VCC Min < VIN < 5.5V - 50 A
CIN I/O capacitance VIN = GND; f = 1.0 MHz - 10 pF
ICC Operating supply current VIN = GND, No load; f = 1.0 MHz 10 (Typical) mA
(low power mode, active)

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AC Characteristics
XC9536XL-5 XC9536XL-7 XC9536XL-10
Symbol Parameter Min Max Min Max Min Max Units
TPD I/O to output valid - 5.0 - 7.5 - 10.0 ns
TSU I/O setup time before GCK 3.7 - 4.8 - 6.5 - ns
TH I/O hold time after GCK 0 - 0 - 0 - ns
TCO GCK to output valid - 3.5 - 4.5 - 5.8 ns
fSYSTEM Multiple FB internal operating frequency - 178.6 - 125 - 100 MHz
TPSU I/O setup time before p-term clock input 1.7 - 1.6 - 2.1 - ns
TPH I/O hold time after p-term clock input 2.0 - 3.2 - 4.4 - ns
TPCO P-term clock output valid - 5.5 - 7.7 - 10.2 ns
TOE GTS to output valid - 4.0 - 5.0 - 7.0 ns
TOD GTS to output disable - 4.0 - 5.0 - 7.0 ns
TPOE Product term OE to output enabled - 7.0 - 9.5 - 11.0 ns
TPOD Product term OE to output disabled - 7.0 - 9.5 - 11.0 ns
TAO GSR to output valid - 10.0 - 12.0 - 14.5 ns
TPAO P-term S/R to output valid - 10.5 - 12.6 - 15.3 ns
TWLH GCK pulse width (High or Low) 2.8 - 4.0 - 4.5 - ns
TAPRPW Asynchronous preset/reset pulse width (High or Low) 5.0 - 6.5 - 7.0 - ns
TPLH P-term clock pulse width (High or Low) 5.0 - 6.5 - 7.0 - ns

VTEST

R1
Output Type VCCIO VTEST R1 R2 CL
Device Output 3.3V 3.3V 320 360 35 pF
2.5V 2.5V 250 660 35 pF
R2 CL

DS058_03_081500

Figure 3: AC Load Circuit

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Internal Timing Parameters

XC9536XL-5 XC9536XL-7 XC9536XL-10
Symbol Parameter Min Max Min Max Min Max Units
Buffer Delays
TIN Input buffer delay - 1.5 - 2.3 - 3.5 ns
TGCK GCK buffer delay - 1.1 - 1.5 - 1.8 ns
TGSR GSR buffer delay - 2.0 - 3.1 - 4.5 ns
TGTS GTS buffer delay - 4.0 - 5.0 - 7.0 ns
TOUT Output buffer delay - 2.0 - 2.5 - 3.0 ns
TEN Output buffer enable/disable delay - 0 - 0 - 0 ns
Product Term Control Delays
TPTCK Product term clock delay - 1.6 - 2.4 - 2.7 ns
TPTSR Product term set/reset delay - 1.0 - 1.4 - 1.8 ns
TPTTS Product term 3-state delay - 5.5 - 7.2 - 7.5 ns
Internal Register and Combinatorial Delays
TPDI Combinatorial logic propagation delay - 0.5 - 1.3 - 1.7 ns
TSUI Register setup time 2.3 - 2.6 - 3.0 - ns
THI Register hold time 1.4 - 2.2 - 3.5 - ns
TECSU Register clock enable setup time 2.3 - 2.6 - 3.0 - ns
TECHO Register clock enable hold time 1.4 - 2.2 - 3.5 - ns
TCOI Register clock to output valid time - 0.4 - 0.5 - 1.0 ns
TAOI Register async. S/R to output delay - 6.0 - 6.4 - 7.0 ns
TRAI Register async. S/R recover before clock 5.0 7.5 10.0 ns
TLOGI Internal logic delay - 1.0 - 1.4 - 1.8 ns
TLOGILP Internal low power logic delay - 5.0 - 6.4 - 7.3 ns
Feedback Delays
TF Fast CONNECT II feedback delay - 1.9 - 3.5 - 4.2 ns
Time Adders
TPTA Incremental product term allocator delay - 0.7 - 0.8 - 1.0 ns
TSLEW Slew-rate limited delay - 3.0 - 4.0 - 4.5 ns

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Product Specification
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XC9536XL I/O Pins(2)

Function Macro- BScan Function Macro- BScan
Block cell PC44 VQ44 CS48 VQ64 Order Block cell PC44 VQ44 CS48 VQ64 Order
1 1 2 40 D6 9 105 2 1 1 39 D7 8 51
1 2 3 41 C7 10 102 2 2 44 38 E5 7 48
1 3 5(1) 43(1) B7(1) 15(1) 99 2 3 42(1) 36(1) E6(1) 5(1) 45
1 4 4 42 C6 11 96 2 4 43 37 E7 6 42
1 5 6(1) 44(1) B6(1) 16(1) 93 2 5 40(1) 34(1) F6(1) 2(1) 39
1 6 8 2 A6 19 90 2 6 39(1) 33(1) G7(1) 64(1) 36
1 7 7(1) 1(1) A7(1) 17(1) 87 2 7 38 32 G6 63 33
1 8 9 3 C5 20 84 2 8 37 31 F5 62 30
1 9 11 5 B5 22 81 2 9 36 30 G5 61 27
1 10 12 6 A4 24 78 2 10 35 29 F4 60 24
1 11 13 7 B4 25 75 2 11 34 28 G4 57 21
1 12 14 8 A3 27 72 2 12 33 27 E3 56 18
1 13 18 12 B2 33 69 2 13 29 23 F2 50 15
1 14 19 13 B1 35 66 2 14 28 22 G1 48 12
1 15 20 14 C2 36 63 2 15 27 21 F1 45 9
1 16 22 16 C3 38 60 2 16 26 20 E2 44 6
1 17 24 18 D2 42 57 2 17 25 19 E1 43 3
1 18 - - D3 39 54 2 18 - - E4 49 0
Notes:
1. Global control pin.
2. The pin-outs are the same for Pb-free versions of packages.

XC9536XL Global, JTAG and Power Pins(1)

Pin Type PC44 VQ44 CS48 VQ64
I/O/GCK1 5 43 B7 15
I/O/GCK2 6 44 B6 16
I/O/GCK3 7 1 A7 17
I/O/GTS1 42 36 E6 5
I/O/GTS2 40 34 F6 2
I/O/GSR 39 33 G7 64
TCK 17 11 A1 30
TDI 15 9 B3 28
TDO 30 24 G2 53
TMS 16 10 A2 29
VCCINT 3.3V 21, 41 15, 35 C1, F7 3, 37
VCCIO 2.5V/3.3V 32 26 G3 55
GND 10, 23, 31 4, 17, 25 A5, D1, F3 21, 41, 54
No Connects - - C4, D4 1, 4, 12, 13, 14, 18,
23, 26, 31, 32, 34, 40,
46, 47, 51, 52, 58, 59
Notes:
1. The pin-outs are the same for Pb-free versions of packages.

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Device Part Marking and Ordering Combination Information

Device Type XC95xxxXL

Package TQ144
This line not
Speed 7C related to device
part number
Operating Range

Sample package with part marking.

Notes:
1. Due to the small size of chip scale packages, part marking on these packages does not follow the above
sample and the complete part number cannot be included in the marking. Part marking on chip scale
packages by line:
Line 1 = X (Xilinx logo), then truncated part number (no XC), i.e., 95xxxXL.
Line 2 = Not related to device part number.
Line 3 = Not related to device part number.
Line 4 = Package code, speed, operating temperature, three digits not related to part
number. Package codes: C1 = CS48, C2 = CSG48.

Speed
Device Ordering and (pin-to-pin Pkg. No. of Operating
Part Marking Number delay) Symbol Pins Package Type Range(1)
XC9536XL-5PC44C 5 ns PC44 44-pin Plastic Lead Chip Carrier (PLCC) C
XC9536XL-5VQ44C 5 ns VQ44 44-pin Quad Flat Pack (VQFP) C
XC9536XL-5CS48C 5 ns CS48 48-ball Chip Scale Package (CSP) C
XC9536XL-5VQ64C 5 ns VQ64 64-pin Quad Flat Pack (VQFP) C
XC9536XL-7PC44C 7.5 ns PC44 44-pin Plastic Lead Chip Carrier (PLCC) C
XC9536XL-7VQ44C 7.5 ns VQ44 44-pin Quad Flat Pack (VQFP) C
XC9536XL-7CS48C 7.5 ns CS48 48-ball Chip Scale Package (CSP) C
XC9536XL-7VQ64C 7.5 ns VQ64 64-pin Quad Flat Pack (VQFP) C
XC9536XL-7PC44I 7.5 ns PC44 44-pin Plastic Lead Chip Carrier (PLCC) I
XC9536XL-7VQ44I 7.5 ns VQ44 44-pin Quad Flat Pack (VQFP) I
XC9536XL-7CS48I 7.5 ns CS48 48-ball Chip Scale Package (CSP) I
XC9536XL-7VQ64I 7.5 ns VQ64 64-pin Quad Flat Pack (VQFP) I
XC9536XL-10PC44C 10 ns PC44 44-pin Plastic Lead Chip Carrier (PLCC) C
XC9536XL-10VQ44C 10 ns VQ44 44-pin Quad Flat Pack (VQFP) C
XC9536XL-10CS48C 10 ns CS48 48-ball Chip Scale Package (CSP) C
XC9536XL-10VQ64C 10 ns VQ64 64-pin Quad Flat Pack (VQFP) C
XC9536XL-10PC44I 10 ns PC44 44-pin Plastic Lead Chip Carrier (PLCC) I
XC9536XL-10VQ44I 10 ns VQ44 44-pin Quad Flat Pack (VQFP) I
XC9536XL-10CS48I 10 ns CS48 48-ball Chip Scale Package (CSP) I
XC9536XL-10VQ64I 10 ns VQ64 64-pin Quad Flat Pack (VQFP) I
XC9536XL-5PCG44C 5 ns PCG44 44-pin Plastic Lead Chip Carrier (PLCC); Pb-free C
XC9536XL-5VQG44C 5 ns VQG44 44-pin Quad Flat Pack (VQFP); Pb-free C

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Speed
Device Ordering and (pin-to-pin Pkg. No. of Operating
Part Marking Number delay) Symbol Pins Package Type Range(1)
XC9536XL-5CSG48C 5 ns CSG48 48-ball Chip Scale Package (CSP); Pb-free C
XC9536XL-5VQG64C 5 ns VQG64 64-pin Quad Flat Pack (VQFP); Pb-free C
XC9536XL-7PCG44C 7.5 ns PCG44 44-pin Plastic Lead Chip Carrier (PLCC); Pb-free C
XC9536XL-7VQG44C 7.5 ns VQG44 44-pin Quad Flat Pack (VQFP); Pb-free C
XC9536XL-7CSG48C 7.5 ns CSG48 48-ball Chip Scale Package (CSP); Pb-free C
XC9536XL-7VQG64C 7.5 ns VQG64 64-pin Quad Flat Pack (VQFP); Pb-free C
XC9536XL-7PCG44I 7.5 ns PCG44 44-pin Plastic Lead Chip Carrier (PLCC); Pb-free I
XC9536XL-7VQG44I 7.5 ns VQG44 44-pin Quad Flat Pack (VQFP); Pb-free I
XC9536XL-7CSG48I 7.5 ns CSG48 48-ball Chip Scale Package (CSP); Pb-free I
XC9536XL-7VQG64I 7.5 ns VQG64 64-pin Quad Flat Pack (VQFP); Pb-free I
XC9536XL-10PCG44C 10 ns PCG44 44-pin Plastic Lead Chip Carrier (PLCC); Pb-free C
XC9536XL-10VQG44C 10 ns VQG44 44-pin Quad Flat Pack (VQFP); Pb-free C
XC9536XL-10CSG48C 10 ns CSG48 48-ball Chip Scale Package (CSP); Pb-free C
XC9536XL-10VQG64C 10 ns VQG64 64-pin Quad Flat Pack (VQFP); Pb-free C
XC9536XL-10PCG44I 10 ns PCG44 44-pin Plastic Lead Chip Carrier (PLCC); Pb-free I
XC9536XL-10VQG44I 10 ns VQG44 44-pin Quad Flat Pack (VQFP); Pb-free I
XC9536XL-10CSG48I 10 ns CSG48 48-ball Chip Scale Package (CSP); Pb-free I
XC9536XL-10VQG64I 10 ns VQG64 64-pin Quad Flat Pack (VQFP); Pb-free I
Notes:
1. C = Commercial: TA = 0 to +70C; I = Industrial: TA = 40 to +85C.

Standard Example: XC9536XL -4 TQ 144 C Pb-Free Example: XC9536XL -4 TQ G 144 C

Device Device
Speed Grade Speed Grade
Package Type Package Type
Number of Pins Pb-Free
Temperature Range Number of Pins
Temperature Range

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Warranty Disclaimer
THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED
AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE
PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE
THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE
AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF
LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.

Further Reading
The following Xilinx links go to relevant XC9500XL CPLD documentation, including XAPP111, Using the XC9500XL Timing
Model, and XAPP784, Bulletproof CPLD Design Practices. Simply click on the link and scroll down.
Data Sheets, Application Notes, and White Papers.
Packaging

Revision History
The following table shows the revision history for this document.

Date Version Revision

09/28/98 1.0 Initial Xilinx release.
08/28/00 1.1 Added VQ44 package.
06/20/02 1.2 Updated ICC equation, page 1. Removed -4 device. Added industrial availability to -7
device. Added additional IIH test conditions and measurements to DC Characteristics table.
06/18/03 1.3 Updated TSOL from 260 to 220oC. Added Device Part Marking and updated Ordering
Information.
08/21/03 1.4 Updated Package Device Marking Pin 1 orientation.
07/15/04 1.5 Added Pb-free documentation
09/15/04 1.6 Added TAPRPW specification to AC Characteristics.
07/15/05 1.7 Move to Product Specification
03/22/06 1.8 Add Warranty Disclaimer.
04/03/07 1.9 Add programming temperature range warning on page 1.

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