Industry's Highest Performance Simulation Solution: Key Benefits
Industry's Highest Performance Simulation Solution: Key Benefits
Industry's Highest Performance Simulation Solution: Key Benefits
VCS
Industrys Highest Performance Simulation Solution
Language compliance
VCS supports all popular design and verification languages, including SystemVerilog, Verilog, VHDL,
OpenVera, SystemC, and the Accellera UVM, VMM, and OVM methodologies (Figure 2). VCS support
for Accellera UVM also includes access to the VMM/UVM interoperability kit, which enables the use of VMM
with UVM and vice versa. Besides supporting digital circuit design, VCS also supports analog and mixed-
analog designs through Verilog-AMS, SPICE and SPF. This comprehensive support for advanced flows and
methodologies enables VCS to help users develop the highest-quality mixed language functional verification
environments in the shortest amount of time.
Verification Verification
planning management
Coverage Constraint
and analysis solver
Protocol Template
debug generators
Debug
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Performance
VCS is the industrys highest performance simulation solution. VCS offers both industry-leading compile time
and run time performance improvement technologies.
Compile for all blocks Run only with the blocks or versions you need
TOP TOP
Partition compile
VCS Partition Compile technology allow users to achieve up to 10x faster compile time by only recompiling
code that has changed, and reusing the libraries for the unchanged modules already compiled earlier.
Precompiled IP
VCS Precompiled IP flows enables up to 2X compile time improvement in IP integration for SoC flows.
Precompiled IP flows reduce scratch compile time for hierarchical designs, enable integration of IPs with
different debug and coverage capabilities, and allows automatic incremental compile of IPs and clusters.
Dynamic Reconfiguration
VCS Dynamic Reconfiguration (Figure 4) feature enables turnaround time reduction over entire regressions by
allowing users to compile once, and run different configurations/testbenches without need for recompiles. All
debug and coverage features work seamlessly regardless of configuration.
Save/Restore
Save/Restore feature (Figure 5) lets the user save the state of simulation in a file for it to be restored at another
time or on a different machine. Designs that have a long design initialization simulation can benefit from this
feature by saving the initial state and restoring the simulation to after initialization in subsequent runs thereby
reducing simulation time.
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reset test1
reset test2
reset test3
t
Long design initialization simulation repeated by each test case
SimState
Productivity gain
Save Restore/ Restore/
reseed reseed
reset test1 test2 test3
t
Constraint Solver
VCS industry-leading, high-performance constraint solver technology is powered by multiple solver engines
that simultaneously analyze all user specified constraints to rapidly generate high-quality random stimulus that
verifies corner case behavior. The constraint solver engines will find a solution to user constraints if one exists,
minimizing constraint conflicts and maximizing verification productivity. This feature is essential for directing
the randomized testing strategy towards a meaningful space and speeds up bug finding.
Multicore Support
VCS multicore technology offers two robust use models: design-level parallelism (DLP) and application-level
parallelism (ALP) (Figure 6). DLP enables users to concurrently simulate multiple instances of a core, several
partitions of a large design, or a combination of the two. ALP allows users to run testbench, assertions,
coverage, and debugging concurrently on multiple cores. Multicore technology has shown up to 2x runtime
speed ups on GLS designs.
Multicore Multicore
Assertion
compiler
Debug
compiler
Design Design
Coverage Coverage
4
X-Propagation
Certain RTL semantics, such as using x-value to denote indeterminate state, may not model actual hardware
behavior accurately. Instead of having to rely on increasingly costly gate level simulation, VCS provides a
way to simulate x-propagation in multiple modes to model x-value in either more, less or equally optimistic
modelling as compared to the regular gate-level simulation
Conventional RTL simulation masks power-on reset bug RTL simulation with X-Propagation uncovers bug
RST
if ( a ) if ( a ) b
a b a
b = 0; b = 0;
else X else X
X b = 1; 1 b = 1;
Component Percentage
HSIM 0.00%
SystemC
SystemC 10.07% profile data
KERNEL 0.5%
Module 89.88%
VERILOG
Total 89.88%
TOTAL 100.00%
Table 1. VCS
AMS Cosimulation
VCS provides many benefits for AMS designers namely real number modeling, native low power and
advanced methodology with AMS testbench. In addition, all analog and mixed signal data can be viewed in
Verdis advanced AMS debug environment, which is natively integrated with VCS to enable fastest analysis
and finding root cause.
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Plan
Coverage
entry
summary
Attributes
Metrics
Source
code
Native Integrations
Native integrations between the high performance VCS simulation engine and the other advanced engines
in the Synopsys Verification Continuum Platform (Figure 3) enables improvements in time-to-market by up
to months.
The Verification Continuum Platforms unified verification architecture eliminates these discontinuities with
VCS Unified Compile, Verdi Unified Debug, and key native integrations such as the following:
VerdiVerdi Reverse Interactive Debug exemplifies the power of VCS engines and technologies natively
``
integrated in the Verdi debug environment, and vice versa (Figure 9).
Reverse debug
control
Full interactive
control
Figure 9. Verdi/VCS Reverse Interactive Debuggo back in time without setting checkpoints
Static and FormalVC LP and VC Formal both fully support Unified Compile with VCS and Unified Debug
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with Verdi
Emulation VCS congruent mode enables simulation to match actual hardware and facilitates emulation-
``
simulation interoperability
VIPSynopsys VC Verification IP solution offers native integration with VCS planning, coverage and
``
constraint solver technologies, and provides native Verdi-based debug and Protocol Analyzer capabilities
Conclusion
With VCS, not only does one get the industry leading performance and capacity in simulation, but also the
fully integrated suite of technologies and tools built around the simulator to drive any verification strategy a
designer wants to execute. The product roadmap for VCS technologies and verification flow in general follows
the path treaded by the design leaders in the industry. In addition, VCS comes with the top-notch support so
that verification schedules stay on track.
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For more information about Synopsys products, support services or training, visit us on the web at:
www.synopsys.com, contact your local sales representative or call 650.584.5000.
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05/17/16.AL_CS7167_VCS_DS.