Industry's Highest Performance Simulation Solution: Key Benefits
Industry's Highest Performance Simulation Solution: Key Benefits
VCS
Industry’s Highest Performance Simulation Solution
Language compliance
VCS supports all popular design and verification languages, including SystemVerilog, Verilog, VHDL,
OpenVera™, SystemC™, and the Accellera® UVM™, VMM, and OVM methodologies (Figure 2). VCS’ support
for Accellera UVM also includes access to the VMM/UVM interoperability kit, which enables the use of VMM
with UVM and vice versa. Besides supporting digital circuit design, VCS also supports analog and mixed-
analog designs through Verilog-AMS, SPICE and SPF. This comprehensive support for advanced flows and
methodologies enables VCS to help users develop the highest-quality mixed language functional verification
environments in the shortest amount of time.
Verification Verification
planning management
Coverage Constraint
and analysis solver
Protocol Template
debug generators
Debug
Virtual Static
Simulation Emulation Prototyping
prototyping and formal
2
Performance
VCS is the industry’s highest performance simulation solution. VCS offers industry-leading compile time
and run time performance improvement technologies, and advanced fine-grained parallelism for simulation
runtime reduction.
Compile for all blocks Run only with the blocks or versions you need
TOP TOP
Partition compile
VCS’ Partition Compile technology allow users to achieve up to 10x faster compile time by only recompiling
code that has changed, and reusing the libraries for the unchanged modules already compiled earlier.
Precompiled IP
VCS’ Precompiled IP flows enables up to 2X compile time improvement in IP integration for SoC flows.
Precompiled IP flows reduce scratch compile time for hierarchical designs, enable integration of IPs with
different debug and coverage capabilities, and allows automatic incremental compile of IPs and clusters.
Dynamic Reconfiguration
VCS’ Dynamic Reconfiguration (Figure 4) feature enables turnaround time reduction over entire regressions by
allowing users to compile once, and run different configurations/testbenches without need for recompiles. All
debug and coverage features work seamlessly regardless of configuration.
3
VCS FGP
4 cores
16 cores
Many-cores
Because VCS FGP is a native feature, serial performance gains and parallel performance gains multiply, and
all simulation technologies are supported, including X-Prop, Native Low Power, SDF support, and parallelized
FSDB dumping.
Save/Restore
Save/Restore feature (Figure 5) lets the user save the state of simulation in a file for it to be restored at another
time or on a different machine. Designs that have a long design initialization simulation can benefit from this
feature by saving the initial state and restoring the simulation to after initialization in subsequent runs thereby
reducing simulation time.
reset test1
reset test2
reset test3
t
Long design initialization simulation repeated by each test case
SimState
Productivity gain
Save Restore/ Restore/
reseed reseed
reset test1 test2 test3
t
4
Constraint Solver
VCS’ industry-leading, high-performance constraint solver technology is powered by multiple solver engines
that simultaneously analyze all user specified constraints to rapidly generate high-quality random stimulus that
verifies corner case behavior. The constraint solver engines will find a solution to user constraints if one exists,
minimizing constraint conflicts and maximizing verification productivity. This feature is essential for directing
the randomized testing strategy towards a meaningful space and speeds up bug finding.
Multicore Multicore
Assertion
compiler
Debug
compiler
Design Design
Coverage Coverage
X-Propagation
Certain RTL semantics, such as using x-value to denote indeterminate state, may not model actual hardware
behavior accurately. Instead of having to rely on increasingly costly gate level simulation, VCS provides a
way to simulate x-propagation in multiple modes to model x-value in either more, less or equally optimistic
modelling as compared to the regular gate-level simulation
Conventional RTL simulation masks power-on reset bug RTL simulation with X-Propagation uncovers bug
RST
if ( a ) if ( a ) b
a b a
b = 0; b = 0;
else X else X
X b = 1; 1 b = 1;
5
SystemC simulation and Cosimulation support
VCS SystemC support is fully compliant with IEEE 1666 SystemC versions, and provides both direct
simulation and cosimulation support. Direct variable access from/to SystemVerilog is supported, as are
function calls across languages. VCS Profiler supports native SystemC profiling, and advanced debug is
supported in Verdi CBug feature.
Component Percentage
HSIM 0.00%
SystemC
SystemC 10.07% profile data
KERNEL 0.5%
Module 89.88%
VERILOG
Total 89.88%
TOTAL 100.00%
Table 1. VCS
AMS Cosimulation
VCS provides many benefits for AMS designers namely – real number modeling, native low power and
advanced methodology with AMS testbench. In addition, all analog and mixed signal data can be viewed in
Verdi’s advanced AMS debug environment, which is natively integrated with VCS to enable fastest analysis
and finding root cause.
Plan
Coverage
entry
summary
Attributes
Metrics
Source
code
6
Native Integrations
Native integrations between the high performance VCS simulation engine and the other advanced engines
in the Synopsys Verification Continuum Platform (Figure 3) enables improvements in time-to-market by up
to months.
The Verification Continuum Platform’s unified verification architecture eliminates these discontinuities with
VCS Unified Compile, Verdi Unified Debug, and key native integrations such as the following:
Verdi — Verdi Reverse Interactive Debug exemplifies the power of VCS engines and technologies natively
``
integrated in the Verdi debug environment, and vice versa (Figure 10).
Reverse debug
control
Full interactive
control
Figure 10. Verdi/VCS Reverse Interactive Debug—go back in time without setting checkpoints
Static and Formal – VC LP and VC Formal both fully support Unified Compile with VCS and Unified Debug
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with Verdi
Emulation – VCS congruent mode enables simulation to match actual hardware and facilitates emulation-
``
simulation interoperability
VIP – Synopsys’ VC Verification IP solution offers native integration with VCS’ planning, coverage and
``
constraint solver technologies, and provides native Verdi-based debug and Protocol Analyzer capabilities
Conclusion
VCS leads the industry in simulation performance and capacity, and provides the most comprehensive fully
integrated suite of technologies and tools to support the broadest range of verification strategies. VCS’
technology roadmap is driven by continuous collaboration with industry leaders, and is targeted at verification
for today’s and tomorrow’s largest and most complex designs. In addition VCS is complemented by the best
support in the industry, all targeted at keeping verification schedules on track.
For more information about Synopsys products, support services or training, visit us on the web at:
www.synopsys.com, contact your local sales representative or call 650.584.5000.
Synopsys, Inc. • 690 East Middlefield Road • Mountain View, CA 94043 • www.synopsys.com
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