Reprinted from W I R E L E S S SYSTE M S D E S I G N November/December 2003 issue.

TOOLKIT
DESIGNERS TOOLKIT

Slice And Dice Chunks

Of Radio Spectrum BY JOHN LILLINGTON

radios (SDRs), and satellite communica-

Various Methods Exist For Filtering And tions. Additional demands are spawned
by monitoring, instrumentation, and
Channelizing Wideband Signals In Real Time, surveillance activities. Often, such activi-
But Each One Comes With Its Own Tradeoffs. ties create a need to observe signals in dif-
ferent resolution bandwidthssome-
times simultaneously.
path to real-time wideband verter technologies do exist for the selec- This article compares the main com-
THE channelization is camouflaged by
different techniques. Among the compet-
tion of narrowband channels from a
medium-bandwidth spectrum (e.g.,
peting techniques for real-time, wide-
band channelization. It focuses on the
ing approaches are Pipelined FFT, Conexant, which was formerly basic techniques that provide multiple
polyphase DFTs, multiple digital down- Globespan Virata; TI-Graychip; and channels from a broad band for further
converters (DDCs), and both the Analog Devices). But theyre limited to processing, such as demodulation or sig-
Pipelined Frequency Transform (PFT) only a few simultaneous channels for an nal detection. The architectures discussed
and its derivativethe tunable PFT economical amount of silicon. here are generally biased toward being
(TPFT). When selecting a technique, Alternative technologies do exist that implemented in hardware, such as field-
remember that the main objective is to require the spectrum to be channelized programmable gate arrays (FPGAs) or
establish the optimum solution for dif- into equally spaced, equal-bandwidth application-specific integrated circuits
ferent application types. Currently, high- channels. Among them is the FFT, where (ASICs). In terms of multiply/accumu-
speed analog-to-digital converters channel filter performance isnt too criti- late operations (MACs), the required
(ADCs) are available off-the-shelf with cal. Another example, polyphase DFT, processing power is very high. In most
conversion rates of up to 1.5 GSamples/s provides higher-performance filters. cases, its very much in excess of the peak
(e.g., the Maxim MAX108). Their By using pipelining architectures, real- MAC performance of todays program-
dynamic range is constantly improving as time multichannel performance can be mable DSPs. The most difficult aspect to
well. However, the problems really start achieved in a practical amount of silicon. overcome is the memory bandwidth
with the area of signal processing that Yet real-world situations often require requirements of a wideband, real-time
resides immediately after the ADC. channels of non-equal width and spacing system. For high-end specifications, its
Typically, processing at this stage along with time-varying channel plans. not clear how this bandwidth could be
involves frequency conversion and chan- This statement applies to multistandard achieved without using a totally imprac-
nelization. Standard digital-downcon- mobile base stations, software-defined tical number of DSPs.
Digital downconverters (DDCs)
Low-pass Digital downconverters are well estab-
A filters
(CIC/FIR)
lished as a technique. Using custom or
B+C Decimators standard cores, this approach is relatively
I
B
N I straightforward to implement in FPGAs.
Input sample rate = Fs In cases that require only a few channels
(complex) Output sample rate = Fs/N (typically 4 to 8) to be selected from the
Input bandwidth
FS/2 C (complex) broad band, such a solution is quite effi-
Output bandwidth =
FS/2N cient. It also proves to be very flexible.
Q
D Each channel can be independently con-
N Q figured for center frequency, bandwidth,
DA and filter response. For larger numbers of
Cosine Sine channels, however, the logic and more
Local oscillator particularly the memory requirements
frequency = FLO become excessive.
Fast Fourier Transform (FFT)
1. Here is a simplified representation of a typical single-channel The Fast Fourier Transform and its real-
digital downconverter using complex-downconverter (CDC) and time pipelined implementation also are
decimating-filter techniques. well-known techniques. The FFT pro-

W I R E L E S S SYSTE M S D E S I G N N O V E M B E R/ D E C E M B E R 2003 1
DESIGNERS TOOLKIT
[ WIDEBAND CHANNELIZATION ]

vides a very economical solu- Next, low-pass filtering

tion to the channelization extracts the required channel.
0 dB ,<FS/2
Input bandwidth ,< FSS/2
F /2
problem. Its especially well That channel may consist of
Input sample rate
suited to scenarios in which a 20 dB (S/R) = Fs (complex)
any combination of Finite
large number of channels are Impulse Response (FIR) or
required, but the channel fil- 40 dB Infinite Impulse Response
ter performance isnt too crit- Output bandwidth < FS/2N (IIR) filters. Typical examples
ical. Generally, the FFT is 60 dB Output S/R = Fs/N (complex) of these filters include the cas-
restricted to cases that require 80 dB caded integrator comb (CIC),
channels with even frequency half-band, and decimating
spacing and equal filtering. 100 dB FIR. For the simple analysis
Fs/2 0 +Fs/2
WOLA and polyphase-DFT Frequency presented here, assume a
filter banks multi-stage CIC followed by a
To achieve an improvement in 2. This frequency performance is typical for a single- decimating FIR.
filtering performance, dont channel digital downconverter (DDC). Its normal to perform some
just use the windowing of of the decimation in the FIR
time data. Utilize polyphase filter banks of choosing between these approaches, filters. This is partly because very high
ahead of the FFT. This technique, which its necessary to examine each technique decimation factors in the CIC require sig-
is generally called Weight Overlap and in more detail. For example, look at the nificant bit growth in the CIC compo-
Add (WOLA), has a subset: the polyphase general architecture of a typical DDC nents. Its also partially done to avoid hav-
DFT. This approach is gaining recogni- (FIG. 1). Although there are many vari- ing alias sidelobes spoil the stop-band
tion. Its very efficient when large, high- ants of this design, the principle is broad- response. To achieve adequate passband
quality filter banks are required. Like the ly the same in each case. The input can be flatness in the DDC, the FIR filter also
FFT, however, its generally restricted to complex or real. For this discussion, may need to compensate for rolloff in the
cases that require evenly spaced channels assume a complex input. The broad- CIC passband. The typical performance
with equal filtering. band input signal is frequency shifted up of a single DDC is shown in FIGURE 2.
Pipelined Frequency Transform (PFT) or down to center the required narrow- CIC filters permit high-rate signal
The PFT processing form takes a differ- band channel on zero frequency. This decimation or interpolation. And by
ent approach. Based on a tree struc- step is achieved using a complex local eliminating the need for multipliers,
ture, it successively splits and filters the oscillator. That oscillator is some form of they use a very compact architecture.1
frequency band to achieve a finer and numerically controlled oscillator (NCO). The two basic building blocks of a CIC
finer resolution of the broad band. The It also is a complex mixer which, in its filter are an integrator and a comb. The
time interleaving of common processes basic form, comprises four complex mul- integrator or accumulator is simply a
can lead to a very efficient structure. One tipliers and two adders. The complexity single-pole IIR filter with unity feedback
of its advantages is that it makes simul- of the NCO will depend on the final fre- coefficient. A typical comb filter behaves
taneous outputs available from succes- quency-setting accuracy thats required as a high-pass filter with a 20-dB-per-
sive stages. These stages are at different as well as the systems spurious-free decade gain (FIG. 3).
frequency resolutions. PFT also offers dynamic range (SFDR). Building a CIC filter involves cascading
the ability to independently tailor the fil-
ters for different frequency bins. If cer- Input sample rate = Output sample rate =
Fs (complex) Decimator Fs/N (complex)
tain frequency bins or blocks of spec-
trum arent required, its easy to exclude G=1/RN Integ. Integ. Integ. R Comb. Comb. Comb.
them from the processing. The result is
greater efficiency.
Tunable PFT (TPFT) z M
In its simplest form, the PFT mentioned z 1
1
above still produces equally spaced fre-
quency bins. To overcome this limita-

tion, a derived form may be used. 
Known as the TPFT, it allows the inde-
pendent tuning of the center frequency 3. This schematic illustrates a three-stage CIC filter.
of all bins. It also permits independent
filters for each bin. Because of the avail-
ability of different stage outputs with DIF Crossover switch
butterfly I
varied frequency resolutions, the end FIFO z 2 z 1 Bit
result is like having the flexibility of the reverser Q
DDC approach. At the same time, the FIFO z 2 z 1
designer gains the efficiency of the PFT. Fs Fs/2
This efficiency is vital for a larger num-
ber of channels. 4. This illustration of a Radix-2 Pipelined FFT Core is based on succes-
To really understand the implications sive n-stages, where 2n is the size of the FFT.

2 N O V E M B E R/ D E C E M B E R 2003 W I R E L E S S SYSTE M S D E S I G N
DESIGNERS TOOLKIT
[ WIDEBAND CHANNELIZATION ]

There are n butterflies that implement

20 the complex arithmetic. Each one per-
Unweighted FFT filter response forms a two-point DFT and complex
0 phase rotations (twiddles). The input to
20 the first butterfly has a FIFO n/2 buffer
stage, which ensures efficient utilization
40 of the butterfly arithmetic. The normal
output of the final stage is bit-reversed
dBc

60
complex (I/Q) data. To achieve normal-
80 ly ordered frequency data, it requires a
DDC filter bit reverser.
100 response
The filter banks performance also
120 Kaiser weighted FFT must be considered when weighing the
filter response benefits of the FFT. In FIGURE 5, the
140 effective frequency response is shown for
0.00E+00 5.00E+06 1.00E+07 1.50E+07 2.00E+07 2.50E+07 3.00E+07
the unweighted FFT. The figure displays
Offset (Hz)
the Sinx/x nature of the sidelobe struc-
ture. Compare it to the filter response of
5. The frequency response of a single FFT bin is compared to an a typical DDC filter (85 dBc stop-band
unweighted FFT, Kaiser weighted FFT, and a digital-downconverter filter. and low-passband ripple). A clear advan-
tage exists in the filter frequency response
N integrators with N combs. They are fol- into a pipelined version of each.2 when using the DDC.
lowed by a decimate-by-R block. The next focus is the vast area of FFT The standard approach to improving
Although such a scheme works, it can be techniques. These methods boast a mul- stop-band performance is to weight or
greatly simplified by placing the comb titude of algorithms for programmable window the time-domain data. For
after the decimator. In general, a CIC fil- DSP implementations and a number of example, Figure 5 also shows the effect
ter would have N integrator/comb pairs COTS ASIC implementations that are of Kaiser weighting. Here, the stop-band
with N typically ranging from 3 to 6. A readily available. Here, coverage is level is improved. Yet a significant price
three-stage CIC is schematically illustrat- restricted to wideband, pipelined hard- is paid: a significant widening of the
ed in Figure 3. ware solutionsparticularly those that passband. FIGURE 6 demonstrates this
The magnitude response of a CIC filter are suitable for FPGA realization.3 tradeoff a little more clearly. It shows the
can be shown, for large R, to approximate FIGURE 4 shows an implementation equivalent set of overlapping filters for a
to a (Sinc)N function. Spectral nulls will of the Pipelined FFT (PFFT).4 This 32-point complex FFT with a Kaiser
appear as multiples of 1Fs/MR Hz, where implementation is based on successive n window. Obviously, a signal thats occu-
Fs is the input sample rate and M is the stages, where 2n is the size of the FFT. pying a narrow frequency band (e.g.,
integer number of delays in the comb sec- Each stage has switched delay elements CW) will actually appear in a number of
tion (typically 1). The stopband relative and butterflies. The switches and delays adjacent bins in decreasingbut still
attenuation is a function of the number re-order the data for processing at the significantlevels.
of stages that are used and equals approx- next butterfly. To achieve performance approaching
imately N  13 dB at the first sidelobe. In
contrast, the DC gain is a function of the
decimation rate R and equals (RM)N.
When designing a CIC filter, its critical to
account for bit growth. Insufficient bit
width would lead to an unstable filter.
To provide multiple channels, its pos-
sible to have a number of DDCs in a par-
allel stack. The number of output chan-
nels is equal to the number of DDCs that
are employed in such an architecture.
Clearly, a linear relationship exists
between the amount of silicon and the
number of channels required.
Its possible, however, to optimize the
DDC stack architecture by taking advan-
tage of the changes in sample rate across
the system. From each CIC decimator
onward, the comb half of the CICs and
the FIRs are clocked at a fraction of the 6. Shown here is an equivalent set of overlapping filters for a 32-point
input rate. As a result, theres potential complex FFT with a Kaiser window. A narrow frequency-band signal
for recycling all of the combs and FIRs (i.e., CW) appears in a number of adjacent bins.

3 N O V E M B E R/ D E C E M B E R 2003 W I R E L E S S SYSTE M S D E S I G N
DESIGNERS TOOLKIT Weighting function
h[n]
[ WIDEBAND CHANNELIZATION ]
L 0 Sample
that of a typical DDC, a window is PFT increases the num- number (n)
needed in the time domain that match- ber of bands by a factor x[n] Weight data by weighting function
es the overall DDC filter impulse of two (FIG. 10). This input data
response. For instance, a 1024-bin filter increase could be MSamples Divide into blocks of KSamples
at a time
bank might require a window some achieved, for example,
4000 to 5000 samples long. Such a win- by a simple tree struc-
dow could be achieved by using an FFT ture (FIG. 11). The Time-
of this length and decimating the out- input is complex to pre- aliasing
Overlap process
put by 4 or 5. But it would be very inef- serve positive and nega- and
ficient. It would particularly impact real tive frequencies. First, it add
time, which needs the parallel process- is split into two equal +++++++
ing of several large FFTs. bands using a complex
Fortunately, a much more elegant and downconverter (CDC) K-point DFT
efficient solution exists.5 In its most gen- and a complex upcon- Adjust kmM Short-time FT
W x Sliding-time reference
eral form, the Weight Overlap and Add verter (CUC). Because time K
reference
(WOLA) method is shown in FIGURE 7. the bandwidth of each Short-time FT
The required filter shape is determined one has been halved, its Fixed-time reference
by the weighting function, which is L possible to halve the
samples long. To match the DFT length, sample rate for each of 7. This image is a depiction of a typical Weighted
the weighted data is divided into blocks the sub-bands. Overlap and Add DFT filter-bank implementation.
of KSamples. The blocks are then added In practice, a degree
together before processing by the DFT. of oversampling is
Next, the input data is shifted along by required to avoid the K I h0[m] x0[m]
MSamples and the process is repeated. In image response prob- z 1
the simple case where M = K, a fresh lems caused by finite fil-
result is attained every KSample. The sys- ter cutoff rates. At the K I h1[m] x1[m]



tem is then known as critically sampled output of the first stage,


(i.e., the sample rate just satisfies the 2X oversampling is xk[m] yk[m] K-point
z 1 DFT
Nyquist criterion). This method may be used. For all successive K I hk[m] xk[m]

adequate for some processes, such as stages, the output is


spectral analysis or analysis/synthesis fil- decimated by two. The

ter-bank pairs. But the alias problems, overall 2X oversam- z 1

which are caused by the critical sampling pling is thus preserved x[n] K I hK1[m] xK1[m]
of a filter bank with finite cutoff rates, throughout the system.
often require some degree of oversam- Yet this approach also 8. This schematic represents a polyphase-DFT
pling. This oversampling is achieved by has at least one obvious filter-bank implementation.
making M < K so that the oversampling disadvantage. For large
factor, I = K/M, is greater than unity. An numbers of channels, the tree gets impos- shows the conventional form of the
advantage of the WOLA is that I need not sibly large. For instance, 1024 channels CDC(A) module. It consists of four mul-
be an integer. For those cases in which it would require 2046 complex CDC or tiplies, two adds/subtracts, a sine/cosine
can be an integer, a different structure CUC modules. Each of these modules lookup table, and a pair of low-pass fil-
usually known as the polyphase DFT would take the form of Figure 1, which ters. The CUC(A) module would be very
may be used (FIG. 8).
The PDFT may sometimes be a more Channel spacing = FS/N
efficient structure, provided that the lim- 0 dB Per-channel output S/R = FS/N
itation of integer oversampling is accept- (complex)
ed.6 It may be shown that the stacked 20 dB
DDC, WOLA, and PDFT give identical
results for a given filter response and inte-
40 dB
ger oversampling. The choice between Superior cutoff and
them is mainly based on silicon efficien- stop-band performance
cy. The performance of a PDFT filter 60 dB
bank is illustrated in FIGURE 9. When
compared with the standard weighted 80 dB
FFT response in Figure 6, its easy to see
the improvement that it offers. 100 dB
Unlike the previously mentioned tech- Fs/2 0 +Fs/2
Frequency
niques, the Pipelined Frequency
Transforms underlying concept is one of
frequency-band splitting. In the simplest 9. By looking at the typical performance of a 32-bin polyphase-DFT filter
radix 2 form, each successive stage of the bank, one can see its superiority over the standard weighted FFT response.

4 N O V E M B E R/ D E C E M B E R 2003 W I R E L E S S SYSTE M S D E S I G N
DESIGNERS TOOLKIT
[ WIDEBAND CHANNELIZATION ]
similar. It would differ tuning over the whole input bandwidth.
Fs/2 +Fs/2
only in the signs of the Overall, this structure is an ideal replace-
adder/subtracter ele- Input ment for multiple DDCs in applications
ments. Successive stages 0 +Fs/4 Fs/4 0 like multi-standard base stations, satel-
Fs/4 +Fs/4
also would be quite sim- Filter bank lite communications, and intelligent
ilar except that the local A output antenna systems (FIG. 14).
oscillators would then Fs/8 +Fs/8 A brief comparison of silicon usage for
0 0 0 0
be at Fx/8 (where Fx is Filter bank the different filter banks also must be
the input sampling rate B output made. Within the limited scope of this
for the stage). In addi- article, only a few examples can be con-
Fs/16 +Fs/16
tion, the output would sidered. They are based on designs that
0 0 0 0 0 0 0 0
be decimated by two. Filter bank have been placed and routed in Xilinx
Fortunately, this C output FPGAs. A comparison is done for filter
architecture can be banks with the following parameters
greatly simplified in 10. Here is a representation of the PFT principle of (SEE TABLE):
several ways. With the frequency-band splitting in its most fundamental form. Number of bins = 256, 512, or 1024
tree system, the sam- Filter stop band = 100 dB
pling rate drops by a factor of two at er. That converters local oscillator is a Passband ripple = 0.1 dB
each stage. The result is inefficient use of numerically controlled oscillator driven Filter overlap = 75%
the hardware, which is capable of run- by the routing engine (FIG. 13). Input bit width = 14
ning at the full rate, Fs. The most pro- By performing the tuning operation Sample rate = 102.4e6 complex, 2x
cessing-intensive part of each stage lies in two steps, the designer gains a reduc- oversampled
in the low-pass filters. Because those fil- tion of sizefor a given frequency reso- Device: Virtex 2-6000
ters take an identical form within any lutionof the LUT used for fine tuning. LUTs = 67584
given stage, interleaving techniques may The tuning range thats required at each RAM = 18432 bits
be used to regain full efficiency. This step successive stage is reduced by a factor of 18-b multipliers = 144
involves interleaving the samples for two. In contrast, a DDC would need fine Compared to the other two techniques,
each of the branches within a given
stage. It also means modifying the filters Input sample Sample rate = Fs Sample rate = Fs/2 Sample
(which are normally FIR filters) by rate = Fs rate = Fs/4
adding extra delays between the coeffi- I CDC(C)
cient multipliers (FIG. 12). Several other CDC(B)
Q CUC(C)
simplifications save silicon, including
the avoidance of lookup tables and mul- I I I CDC(C)
tipliers.2 CDC(A) CDC(B)
Q Q Q CUC(C)
The PFT passband performance is very
similar to that of the polyphase DFT that I I CDC(C)
was illustrated in Figure 9. But differences CUC(B) CDC(B)
Q Q CUC(C)
exist in the stop band, because the PFT is
a cascade of filters. Its form potentially CDC = complex I CDC(C)
allows higher stop-band attenuation over downconverter CDC(B)
CUC = complex upconverter Q CUC(C)
a large percentage of the broad bandan
effect that increases with the number of
stages. Simultaneous outputs also are 11. This simple PFT tree structure, which uses complex up- and down-
available at each stage of the PFT. Each converters, would be impractical for a large number of channels.
one gives a different resolution. Finally,
IIR filters can be used at any stage of the
PFT. Silicon may therefore be saved for 2:4 sample 4:8 sample
applications in which linear phase isnt 1:2 sample interleavers/ interleavers/
critical and/or low latency is required. interleavers decimators decimators
Input sample Output sample Output sample Output sample
The tunable PFT actually makes use of rate = Fs rate = 2Fs rate = 2Fs rate = 2Fs
the PFT cascaded structure where inter-
7 I
mediate outputs are readily available. By
CDC I ICDC I ICDC I
modifying the PFT architecture, its pos- Q (A) (B) (C)
sible to extract frequency bands of the
desired size while ensuring that those
bands are centered at any given frequen- CUC Q ICUC Q ICUC Q
(B) (B) (C)
cy. This level of tunability is achieved in
two stages. First, the signals are coarsely
tuned within the PFT stages. Then, 12. This diagram of a simplified PFT depicts the use of interleaving tech-
theyre fine tuned by a complex convert- niques, which allow the FPGA to be run at maximum efficiency.

W I R E L E S S SYSTE M S D E S I G N N O V E M B E R/ D E C E M B E R 2003 5
DESIGNERS TOOLKIT
[ WIDEBAND CHANNELIZATION ]

PFT stage 1 PFT stage 2 PFT stage 3 PFT stage N

Interleaver

To
CDC/CUC
multi-rate
Coarse tuning fine tuning
section
by PFT stages
Final
shaping filter to
match bandwidth
and shape

13. In this schematic of the tunable PFT architecture, 14. Using the tunable PFT, this screen shot shows
the extraction of channels at intermediate outputs is the extraction of the required channel frequency
followed by coarse tuning at the PFT stage. The plan from the wideband. The channel plan can be
channels are then fine-tuned by a complex converter. reconfigured on demand.

the most obvious conclusion is that the choice for single, fixed filter banks. downconverters. Then, the crossover
stacked DDC approach is very ineffi- For tunable filter banks, the best com- point for tunable filter banks (channels)
cient. To be fair, however, the particular parison is between stacked DDCs and the is at around the 16 channel point.
design that was utilized didnt make use tunable PFT. FIGURE 15 compares the REFERENCES:
of the dedicated multipliers that are logic requirements of the two approach- [1] Hogenauer, E.B., An economical class of digital
available in Xilinxs Virtex 2 devices. es for up to 256 bins.Above about 16 bins, filters for decimation and interpolation, IEEE
Transactions on Acoustic, Speech and Signal
Even so, the use of stacked DDCs for the TPFT wins rapidly. A similar compar- Processing, ASSP-29(2):155-162, 1981.
more than about eight bins just isnt ison exists for the memory requirements. [2] PFT Architecture and Comparisons with FFT/Digital
economical. Obviously, the most suitable design Down-Converter Techniques, www.rfel.com/download/
W02001-PFT White Paper.pdf.
Its not easy to directly compare the technique for any given application can-
[3] Rabiner, L.R., and Gold, B., Theory and Application
polyphase DFT and PFT approaches. The not be covered within a short paper. At of Digital Signal Processing, Prentice-Hall, 1975.
PFT has been configured as a multiplier- the higher subsystem level, too many fac- [4] Pipelined FFT, www.rfel.com/download/W02004-
less design. It doesnt make use of the tors need to be considered: form factor, Pipelined FFT White Paper.pdf.
dedicated multipliers even though it power consumption, weight, legacy sys- [5] Crochiere, R.E., and Rabiner, L.R., Multirate Digital
Signal Processing, Prentice-Hall, 1983.
could. Plus, the PFT has outputs available tems, etc. At the board and chip level, one [6] Gumas, C.C., Window-presum FFT achieves high
at each stage. Those outputs make it very must factor in the major considerations dynamic range, resolution, Personal Engineering &
useful in certain applications. of speed/sample rate, number of chan- Instrumentation News, July 1997, pg. 58-64,
www.chipcenter.com/dsp/DSP000315F1.html.
Furthermore, silicon efficiency is much nels, dynamic range/filter performance,
[7] TPFT-Tuneable Pipelined Frequency Transform,
improved if its only necessary to output target device, etc. Only then can the engi- www.rfel.com/download/W02003-Tuneable PFT White
bins over selected portions of the broad neer decide which architecture is the most Paper.pdf.
band. The general conclusion is that for appropriate to adopt.
smaller numbers of bins (up to around At the device level, however, the situa- John Lillington, CTO, RF Engines Ltd.,
256), the silicon requirements are similar. tion is a bit clearer. If more than approxi- Innovation Centre, St. Cross Business Park,
For larger numbers of bins, the polyphase mately eight fixed channels are required, Newport, Isle of Wight, PO30 5WB, UK; +44
DFT gains rapidlyparticularly in terms the polyphase DFT approach provides a (0)1983 550330, e-mail: john.lillington@
of memory. It becomes the preferred more efficient solution than digital rfel.com, www.rfel.com.

Silicon Comparisons for Various Filter Banks

350,000
Logic resources (LUTs)

Filter- No. of Bin Logic RAM 18-b 300,000 Stacked DDCs

bank type bins spacing (LUTs) (bits) Multipliers
(kHz) 250,000
Stacked 256 400 317,498 436,224 N/A 200,000
Logic limit for
DDC 512 200 650,114 876,544 N/A 150,000 Virtex 2-6000 FPGA
1024 100 1,336,754 1,761,280 N/A 100,000

Polyphase 256 400 8070 4608 30 50,000

TPFT
DFT 512 200 9169 4793 34 0
1 10 100 1000
(Radix 2) 1024 100 10,341 5345 42
Number of bins
PFT 256 400 27,930 3840 N/A
15. This chart compares the logic requirements between
(Radix2) 512 200 32,270 6529 N/A
DDCs and the TPFT. The TPFT is significantly more efficient
1024 100 36,610 10,625 N/A
above 16 channels for both logic and memory.

6 N O V E M B E R/ D E C E M B E R 2003 W I R E L E S S SYSTE M S D E S I G N
Copyright 2003 by Penton Media, Inc.