Pic16f8x PDF

PIC16F8X
18-pin Flash/EEPROM 8-Bit Microcontrollers

Devices Included in this Data Sheet: Pin Diagrams
PIC16F83 PDIP, SOIC
PIC16F84
PIC16CR83 RA2 1 18 RA1
PIC16CR84 RA3 2 17 RA0
Extended voltage range devices available RA4/T0CKI 3 16 OSC1/CLKIN
PIC16CR8X
PIC16F8X
(PIC16LF8X, PIC16LCR8X) MCLR 4 15 OSC2/CLKOUT
VSS 5 14 VDD
High Performance RISC CPU Features: RB0/INT 6 13 RB7
Only 35 single word instructions to learn RB1 7 12 RB6
All instructions single cycle except for program RB2 8 11 RB5
branches which are two-cycle RB3 9 10 RB4
Operating speed: DC - 10 MHz clock input

DC - 400 ns instruction cycle
Program Data Data Max.
Special Microcontroller Features:
Device Memory RAM EEPROM Freq In-Circuit Serial Programming (ICSP) - via two
(words) (bytes) (bytes) (MHz) pins (ROM devices support only Data EEPROM
PIC16F83 512 Flash 36 64 10 programming)
PIC16F84 1 K Flash 68 64 10 Power-on Reset (POR)
PIC16CR83 512 ROM 36 64 10 Power-up Timer (PWRT)
PIC16CR84 1 K ROM 68 64 10 Oscillator Start-up Timer (OST)
14-bit wide instructions Watchdog Timer (WDT) with its own on-chip RC
8-bit wide data path oscillator for reliable operation
15 special function hardware registers Code-protection
Eight-level deep hardware stack Power saving SLEEP mode
Direct, indirect and relative addressing modes Selectable oscillator options
Four interrupt sources: CMOS Flash/EEPROM Technology:
- External RB0/INT pin Low-power, high-speed technology
- TMR0 timer overflow
Fully static design
- PORTB<7:4> interrupt on change
- Data EEPROM write complete Wide operating voltage range:
1000 erase/write cycles Flash program memory - Commercial: 2.0V to 6.0V
- Industrial: 2.0V to 6.0V
10,000,000 erase/write cycles EEPROM data mem-
ory Low power consumption:
EEPROM Data Retention > 40 years - < 2 mA typical @ 5V, 4 MHz
- 15 A typical @ 2V, 32 kHz
Peripheral Features: - < 1 A typical standby current @ 2V
13 I/O pins with individual direction control
High current sink/source for direct LED drive
- 25 mA sink max. per pin
- 20 mA source max. per pin
TMR0: 8-bit timer/counter with 8-bit
programmable prescaler
1998 Microchip Technology Inc. DS30430C-page 1

PIC16F8X
Table of Contents
1.0 General Description ...................................................................................................................................................................... 3
2.0 PIC16F8X Device Varieties .......................................................................................................................................................... 5
3.0 Architectural Overview.................................................................................................................................................................. 7
4.0 Memory Organization ................................................................................................................................................................. 11
5.0 I/O Ports...................................................................................................................................................................................... 21
6.0 Timer0 Module and TMR0 Register............................................................................................................................................ 27
7.0 Data EEPROM Memory.............................................................................................................................................................. 33
8.0 Special Features of the CPU ...................................................................................................................................................... 37
9.0 Instruction Set Summary ............................................................................................................................................................ 53
10.0 Development Support ................................................................................................................................................................. 69
11.0 Electrical Characteristics for PIC16F83 and PIC16F84.............................................................................................................. 73
12.0 Electrical Characteristics for PIC16CR83 and PIC16CR84........................................................................................................ 85
13.0 DC & AC Characteristics Graphs/Tables.................................................................................................................................... 97
14.0 Packaging Information .............................................................................................................................................................. 109
Appendix A: Feature Improvements - From PIC16C5X To PIC16F8X .......................................................................................... 113
Appendix B: Code Compatibility - from PIC16C5X to PIC16F8X.................................................................................................. 113
Appendix C: Whats New In This Data Sheet ................................................................................................................................. 114
Appendix D: Whats Changed In This Data Sheet ......................................................................................................................... 114
Appendix E: Conversion Considerations - PIC16C84 to PIC16F83/F84 And PIC16CR83/CR84.................................................. 115
Index ................................................................................................................................................................................................. 117
On-Line Support................................................................................................................................................................................. 119
Reader Response .............................................................................................................................................................................. 120
PIC16F8X Product Identification System ........................................................................................................................................... 121
Sales and Support.............................................................................................................................................................................. 121
To Our Valued Customers

We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of
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DS30430C-page 2 1998 Microchip Technology Inc.

PIC16F8X
1.0 GENERAL DESCRIPTION Table 1-1 lists the features of the PIC16F8X. A simpli-
fied block diagram of the PIC16F8X is shown in
The PIC16F8X is a group in the PIC16CXX family of Figure 3-1.
low-cost, high-performance, CMOS, fully-static, 8-bit
microcontrollers. This group contains the following The PIC16F8X fits perfectly in applications ranging
devices: from high speed automotive and appliance motor
control to low-power remote sensors, electronic locks,
PIC16F83 security devices and smart cards. The Flash/EEPROM
PIC16F84 technology makes customization of application
PIC16CR83 programs (transmitter codes, motor speeds, receiver
PIC16CR84 frequencies, security codes, etc.) extremely fast and
All PICmicro microcontrollers employ an advanced convenient. The small footprint packages make this
RISC architecture. PIC16F8X devices have enhanced microcontroller series perfect for all applications with
core features, eight-level deep stack, and multiple space limitations. Low-cost, low-power, high
internal and external interrupt sources. The separate performance, ease-of-use and I/O flexibility make the
instruction and data buses of the Harvard architecture PIC16F8X very versatile even in areas where no
allow a 14-bit wide instruction word with a separate microcontroller use has been considered before
8-bit wide data bus. The two stage instruction pipeline (e.g., timer functions; serial communication; capture,
allows all instructions to execute in a single cycle, compare and PWM functions; and co-processor
except for program branches (which require two applications).
cycles). A total of 35 instructions (reduced instruction The serial in-system programming feature (via two
set) are available. Additionally, a large register set is pins) offers flexibility of customizing the product after
used to achieve a very high performance level. complete assembly and testing. This feature can be
PIC16F8X microcontrollers typically achieve a 2:1 code used to serialize a product, store calibration data, or
compression and up to a 4:1 speed improvement (at 20 program the device with the current firmware before
MHz) over other 8-bit microcontrollers in their class. shipping.
The PIC16F8X has up to 68 bytes of RAM, 64 bytes of 1.1 Family and Upward Compatibility
Data EEPROM memory, and 13 I/O pins. A timer/
counter is also available. Those users familiar with the PIC16C5X family of
microcontrollers will realize that this is an enhanced
The PIC16CXX family has special features to reduce
version of the PIC16C5X architecture. Please refer to
external components, thus reducing cost, enhancing
Appendix A for a detailed list of enhancements. Code
system reliability and reducing power consumption.
written for PIC16C5X devices can be easily ported to
There are four oscillator options, of which the single pin
PIC16F8X devices (Appendix B).
RC oscillator provides a low-cost solution, the LP
oscillator minimizes power consumption, XT is a 1.2 Development Support
standard crystal, and the HS is for High Speed crystals.
The SLEEP (power-down) mode offers power saving. The PIC16CXX family is supported by a full-featured
The user can wake the chip from sleep through several macro assembler, a software simulator, an in-circuit
external and internal interrupts and resets. emulator, a low-cost development programmer and a
A highly reliable Watchdog Timer with its own on-chip full-featured programmer. A C compiler and fuzzy
RC oscillator provides protection against software lock- logic support tools are also available.
up.
The devices with Flash program memory allow the
same device package to be used for prototyping and
production. In-circuit reprogrammability allows the
code to be updated without the device being removed
from the end application. This is useful in the
development of many applications where the device
may not be easily accessible, but the prototypes may
require code updates. This is also useful for remote
applications where the code may need to be updated
(such as rate information).

PIC16F8X
TABLE 1-1 PIC16F8X FAMILY OF DEVICES
PIC16F83 PIC16CR83 PIC16F84 PIC16CR84
Maximum Frequency 10 10 10 10
Clock
of Operation (MHz)
Flash Program Memory 512 1K
EEPROM Program Memory
Memory ROM Program Memory 512 1K
Data Memory (bytes) 36 36 68 68
Data EEPROM (bytes) 64 64 64 64
Peripherals Timer Module(s) TMR0 TMR0 TMR0 TMR0
Interrupt Sources 4 4 4 4
I/O Pins 13 13 13 13
Features Voltage Range (Volts) 2.0-6.0 2.0-6.0 2.0-6.0 2.0-6.0
Packages 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP,
SOIC SOIC SOIC SOIC
All PICmicro Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capa-
bility. All PIC16F8X Family devices use serial programming with clock pin RB6 and data pin RB7.

PIC16F8X
2.0 PIC16F8X DEVICE VARIETIES 2.3 Serialized Quick-Turnaround-
Production (SQTP SM ) Devices
A variety of frequency ranges and packaging options
are available. Depending on application and production Microchip offers the unique programming service
requirements the proper device option can be selected where a few user-defined locations in each device are
using the information in this section. When placing programmed with different serial numbers. The serial
orders, please use the PIC16F8X Product numbers may be random, pseudo-random
Identification System at the back of this data sheet to or sequential.
specify the correct part number.
Serial programming allows each device to have a
There are four device types as indicated in the device unique number which can serve as an entry-code,
number. password or ID number.
1. F, as in PIC16F84. These devices have Flash For information on submitting a SQTP code, please
program memory and operate over the standard contact your Microchip Regional Sales Office.
voltage range.
2. LF, as in PIC16LF84. These devices have Flash 2.4 ROM Devices
program memory and operate over an extended
voltage range. Some of Microchips devices have a corresponding
device where the program memory is a ROM. These
3. CR, as in PIC16CR83. These devices have
devices give a cost savings over Microchips traditional
ROM program memory and operate over the
user programmed devices (EPROM, EEPROM).
standard voltage range.
4. LCR, as in PIC16LCR84. These devices have ROM devices (PIC16CR8X) do not allow serialization
ROM program memory and operate over an information in the program memory space. The user
extended voltage range. may program this information into the Data EEPROM.
When discussing memory maps and other architectural For information on submitting a ROM code, please
features, the use of F and CR also implies the LF and contact your Microchip Regional Sales Office.
LCR versions.
2.1 Flash Devices

These devices are offered in the lower cost plastic
package, even though the device can be erased and
reprogrammed. This allows the same device to be used
for prototype development and pilot programs as well
as production.
A further advantage of the electrically-erasable Flash
version is that it can be erased and reprogrammed in-
circuit, or by device programmers, such as Microchip's
PICSTART Plus or PRO MATE II programmers.
2.2 Quick-Turnaround-Production (QTP)

Devices
Microchip offers a QTP Programming Service for
factory production orders. This service is made
available for users who choose not to program a
medium to high quantity of units and whose code
patterns have stabilized. The devices have all Flash
locations and configuration options already pro-
grammed by the factory. Certain code and prototype
verification procedures do apply before production
shipments are available.
For information on submitting a QTP code, please
contact your Microchip Regional Sales Office.

PIC16F8X
NOTES:

PIC16F8X
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC16CXX family can be
attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC16CXX uses a Harvard architecture. This
architecture has the program and data accessed from
separate memories. So the device has a program
memory bus and a data memory bus. This improves
bandwidth over traditional von Neumann architecture
where program and data are fetched from the same
memory (accesses over the same bus). Separating
program and data memory further allows instructions to
be sized differently than the 8-bit wide data word.
PIC16CXX opcodes are 14-bits wide, enabling single
word instructions. The full 14-bit wide program memory
bus fetches a 14-bit instruction in a single cycle. A two-
stage pipeline overlaps fetch and execution of instruc-
tions (Example 3-1). Consequently, all instructions exe-
cute in a single cycle except for program branches.
The PIC16F83 and PIC16CR83 address 512 x 14 of
program memory, and the PIC16F84 and PIC16CR84
address 1K x 14 program memory. All program mem-
ory is internal.
The PIC16CXX can directly or indirectly address its
register files or data memory. All special function
registers including the program counter are mapped in
the data memory. An orthogonal (symmetrical)
instruction set makes it possible to carry out any oper-
ation on any register using any addressing mode. This
symmetrical nature and lack of special optimal
situations make programming with the PIC16CXX
simple yet efficient. In addition, the learning curve is
reduced significantly.

PIC16F8X
PIC16CXX devices contain an 8-bit ALU and working The W register is an 8-bit working register used for ALU
register. The ALU is a general purpose arithmetic unit. operations. It is not an addressable register.
It performs arithmetic and Boolean functions between Depending on the instruction executed, the ALU may
data in the working register and any register file. affect the values of the Carry (C), Digit Carry (DC), and
The ALU is 8-bits wide and capable of addition, Zero (Z) bits in the STATUS register. The C and DC bits
subtraction, shift and logical operations. Unless operate as a borrow and digit borrow out bit,
otherwise mentioned, arithmetic operations are twos respectively, in subtraction. See the SUBLW and SUBWF
complement in nature. In two-operand instructions, instructions for examples.
typically one operand is the working register A simplified block diagram for the PIC16F8X is shown
(W register), and the other operand is a file register or in Figure 3-1, its corresponding pin description is
an immediate constant. In single operand instructions, shown in Table 3-1.
the operand is either the W register or a file register.
FIGURE 3-1: PIC16F8X BLOCK DIAGRAM
13 Data Bus 8
Flash/ROM Program Counter EEPROM Data Memory
Program
Memory
PIC16F83/CR83 RAM
512 x 14 File Registers EEPROM
8 Level Stack EEDATA Data Memory
PIC16F84/CR84 PIC16F83/CR83
(13-bit) 36 x 8 64 x 8
1K x 14
PIC16F84/CR84
68 x 8
Program
Bus 14
7 RAM Addr EEADR
Addr Mux
Instruction reg
5 Direct Addr 7 Indirect TMR0

Addr
FSR reg
RA4/T0CKI
STATUS reg
8
MUX
Power-up
Timer I/O Ports
8
Instruction Oscillator
Decode & Start-up Timer
Control ALU
Power-on RA3:RA0
Reset
Timing Watchdog RB7:RB1
Timer W reg
Generation
RB0/INT
OSC2/CLKOUT MCLR VDD, VSS

OSC1/CLKIN

PIC16F8X
TABLE 3-1 PIC16F8X PINOUT DESCRIPTION
DIP SOIC I/O/P Buffer
Pin Name Description
No. No. Type Type
OSC1/CLKIN 16 16 I ST/CMOS (3) Oscillator crystal input/external clock source input.

OSC2/CLKOUT 15 15 O Oscillator crystal output. Connects to crystal or resonator in crystal
oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has
1/4 the frequency of OSC1, and denotes the instruction cycle rate.
MCLR 4 4 I/P ST Master clear (reset) input/programming voltage input. This pin is an
active low reset to the device.
PORTA is a bi-directional I/O port.
RA0 17 17 I/O TTL
RA1 18 18 I/O TTL
RA2 1 1 I/O TTL
RA3 2 2 I/O TTL
RA4/T0CKI 3 3 I/O ST Can also be selected to be the clock input to the TMR0 timer/
counter. Output is open drain type.
PORTB is a bi-directional I/O port. PORTB can be software pro-
grammed for internal weak pull-up on all inputs.
RB0/INT 6 6 I/O TTL/ST (1) RB0/INT can also be selected as an external interrupt pin.
RB1 7 7 I/O TTL
RB2 8 8 I/O TTL
RB3 9 9 I/O TTL
RB4 10 10 I/O TTL Interrupt on change pin.
RB5 11 11 I/O TTL Interrupt on change pin.
RB6 12 12 I/O TTL/ST (2) Interrupt on change pin. Serial programming clock.
RB7 13 13 I/O TTL/ST (2) Interrupt on change pin. Serial programming data.
VSS 5 5 P Ground reference for logic and I/O pins.
VDD 14 14 P Positive supply for logic and I/O pins.
Legend: I= input O = output I/O = Input/Output P = power
= Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.

PIC16F8X
3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining
The clock input (from OSC1) is internally divided by An Instruction Cycle consists of four Q cycles (Q1,
four to generate four non-overlapping quadrature Q2, Q3 and Q4). The instruction fetch and execute are
clocks namely Q1, Q2, Q3 and Q4. Internally, the pipelined such that fetch takes one instruction cycle
program counter (PC) is incremented every Q1, the while decode and execute takes another instruction
instruction is fetched from the program memory and cycle. However, due to the pipelining, each instruction
latched into the instruction register in Q4. The effectively executes in one cycle. If an instruction
instruction is decoded and executed during the causes the program counter to change (e.g., GOTO)
following Q1 through Q4. The clocks and instruction then two cycles are required to complete the instruction
execution flow is shown in Figure 3-2. (Example 3-1).
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-2: CLOCK/INSTRUCTION CYCLE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2 Internal
phase
Q3 clock
Q4
PC PC PC+1 PC+2
OSC2/CLKOUT
(RC mode)
Fetch INST (PC)
Execute INST (PC-1) Fetch INST (PC+1)
Execute INST (PC) Fetch INST (PC+2)
Execute INST (PC+1)
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
1. MOVLW 55h Fetch 1 Execute 1

2. MOVWF PORTB Fetch 2 Execute 2
3. CALL SUB_1 Fetch 3 Execute 3
4. BSF PORTA, BIT3 Fetch 4 Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is flushed from the pipeline while the new instruction is being fetched and then executed.

PIC16F8X
4.0 MEMORY ORGANIZATION FIGURE 4-1: PROGRAM MEMORY MAP
AND STACK - PIC16F83/CR83
There are two memory blocks in the PIC16F8X. These
are the program memory and the data memory. Each PC<12:0>
block has its own bus, so that access to each block can CALL, RETURN 13
occur during the same oscillator cycle. RETFIE, RETLW
The data memory can further be broken down into the Stack Level 1

general purpose RAM and the Special Function
Registers (SFRs). The operation of the SFRs that Stack Level 8

control the core are described here. The SFRs used
to control the peripheral modules are described in the Reset Vector 0000h
section discussing each individual peripheral module. Peripheral Interrupt Vector 0004h
User Memory
The data memory area also contains the data
Space
EEPROM memory. This memory is not directly mapped
into the data memory, but is indirectly mapped. That is,
an indirect address pointer specifies the address of the
data EEPROM memory to read/write. The 64 bytes of
data EEPROM memory have the address range
1FFh
0h-3Fh. More details on the EEPROM memory can be
found in Section 7.0.
4.1 Program Memory Organization

The PIC16FXX has a 13-bit program counter capable 1FFFh
of addressing an 8K x 14 program memory space. For
the PIC16F83 and PIC16CR83, the first 512 x 14
(0000h-01FFh) are physically implemented FIGURE 4-2: PROGRAM MEMORY MAP
(Figure 4-1). For the PIC16F84 and PIC16CR84, the AND STACK - PIC16F84/CR84
first 1K x 14 (0000h-03FFh) are physically imple-
mented (Figure 4-2). Accessing a location above the PC<12:0>
physically implemented address will cause a wrap- CALL, RETURN 13
around. For example, for the PIC16F84 locations 20h, RETFIE, RETLW
420h, 820h, C20h, 1020h, 1420h, 1820h, and 1C20h Stack Level 1

will be the same instruction.

The reset vector is at 0000h and the interrupt vector is Stack Level 8
at 0004h. Reset Vector 0000h
Peripheral Interrupt Vector 0004h

User Memory
Space
3FFh
1FFFh

PIC16F8X
4.2 Data Memory Organization 4.2.1 GENERAL PURPOSE REGISTER FILE
The data memory is partitioned into two areas. The first All devices have some amount of General Purpose
is the Special Function Registers (SFR) area, while the Register (GPR) area. Each GPR is 8 bits wide and is
second is the General Purpose Registers (GPR) area. accessed either directly or indirectly through the FSR
The SFRs control the operation of the device. (Section 4.5).
Portions of data memory are banked. This is for both The GPR addresses in bank 1 are mapped to
the SFR area and the GPR area. The GPR area is addresses in bank 0. As an example, addressing loca-
banked to allow greater than 116 bytes of general tion 0Ch or 8Ch will access the same GPR.
purpose RAM. The banked areas of the SFR are for the
registers that control the peripheral functions. Banking 4.2.2 SPECIAL FUNCTION REGISTERS
requires the use of control bits for bank selection. The Special Function Registers (Figure 4-1, Figure 4-2
These control bits are located in the STATUS Register. and Table 4-1) are used by the CPU and Peripheral
Figure 4-1 and Figure 4-2 show the data memory map functions to control the device operation. These
organization. registers are static RAM.
Instructions MOVWF and MOVF can move values from The special function registers can be classified into two
the W register to any location in the register file (F), sets, core and peripheral. Those associated with the
and vice-versa. core functions are described in this section. Those
The entire data memory can be accessed either related to the operation of the peripheral features are
directly using the absolute address of each register file described in the section for that specific feature.
or indirectly through the File Select Register (FSR)
(Section 4.5). Indirect addressing uses the present
value of the RP1:RP0 bits for access into the banked
areas of data memory.
Data memory is partitioned into two banks which
contain the general purpose registers and the special
function registers. Bank 0 is selected by clearing the
RP0 bit (STATUS<5>). Setting the RP0 bit selects Bank
1. Each Bank extends up to 7Fh (128 bytes). The first
twelve locations of each Bank are reserved for the
Special Function Registers. The remainder are Gen-
eral Purpose Registers implemented as static RAM.

PIC16F8X
FIGURE 4-1: REGISTER FILE MAP - FIGURE 4-2: REGISTER FILE MAP -
PIC16F83/CR83 PIC16F84/CR84
File Address File Address File Address File Address
00h Indirect addr.(1) Indirect addr.(1) 80h 00h Indirect addr.(1) Indirect addr.(1) 80h
01h TMR0 OPTION 81h 01h TMR0 OPTION 81h
02h PCL PCL 82h 02h PCL PCL 82h
03h STATUS STATUS 83h 03h STATUS STATUS 83h
04h FSR FSR 84h 04h FSR FSR 84h
05h PORTA TRISA 85h 05h PORTA TRISA 85h
06h PORTB TRISB 86h 06h PORTB TRISB 86h
07h 87h 07h 87h
08h EEDATA EECON1 88h 08h EEDATA EECON1 88h
09h EEADR EECON2(1) 89h 09h EEADR EECON2(1) 89h
0Ah PCLATH PCLATH 8Ah 0Ah PCLATH PCLATH 8Ah
0Bh INTCON INTCON 8Bh 0Bh INTCON INTCON 8Bh
0Ch 8Ch 0Ch 8Ch
36
General Mapped
Purpose (accesses)
registers in Bank 0 68
(SRAM) General Mapped
Purpose (accesses)
2Fh AFh registers in Bank 0
(SRAM)
30h B0h
4Fh CFh
50h D0h
7Fh FFh 7Fh FFh

Bank 0 Bank 1 Bank 0 Bank 1
Unimplemented data memory location; read as 0. Unimplemented data memory location; read as 0.
Note 1: Not a physical register. Note 1: Not a physical register.

PIC16F8X
TABLE 4-1 REGISTER FILE SUMMARY
Value on Value on all

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-on other resets
Reset (Note3)
Bank 0
00h INDF Uses contents of FSR to address data memory (not a physical register) ---- ---- ---- ----
01h TMR0 8-bit real-time clock/counter xxxx xxxx uuuu uuuu
02h PCL Low order 8 bits of the Program Counter (PC) 0000 0000 0000 0000
(2) TO
03h STATUS IRP RP1 RP0 PD Z DC C 0001 1xxx 000q quuu
04h FSR Indirect data memory address pointer 0 xxxx xxxx uuuu uuuu
05h PORTA RA4/T0CKI RA3 RA2 RA1 RA0 ---x xxxx ---u uuuu
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT xxxx xxxx uuuu uuuu
07h Unimplemented location, read as '0' ---- ---- ---- ----
08h EEDATA EEPROM data register xxxx xxxx uuuu uuuu
09h EEADR EEPROM address register xxxx xxxx uuuu uuuu
0Ah PCLATH Write buffer for upper 5 bits of the PC (1) ---0 0000 ---0 0000
0Bh INTCON GIE EEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
Bank 1
80h INDF Uses contents of FSR to address data memory (not a physical register) ---- ---- ---- ----
OPTION_ 1111 1111 1111 1111

81h RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
REG
82h PCL Low order 8 bits of Program Counter (PC) 0000 0000 0000 0000
83h STATUS (2) IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu
84h FSR Indirect data memory address pointer 0 xxxx xxxx uuuu uuuu
85h TRISA PORTA data direction register ---1 1111 ---1 1111
86h TRISB PORTB data direction register 1111 1111 1111 1111
87h Unimplemented location, read as '0' ---- ---- ---- ----
88h EECON1 EEIF WRERR WREN WR RD ---0 x000 ---0 q000
89h EECON2 EEPROM control register 2 (not a physical register) ---- ---- ---- ----
0Ah PCLATH Write buffer for upper 5 bits of the PC (1) ---0 0000 ---0 0000
0Bh INTCON GIE EEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
Legend: x = unknown, u = unchanged. - = unimplemented read as 0, q = value depends on condition.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a slave register for PC<12:8>. The contents
of PCLATH can be transferred to the upper byte of the program counter, but the contents of PC<12:8> is never transferred
to PCLATH.
2: The TO and PD status bits in the STATUS register are not affected by a MCLR reset.
3: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.

PIC16F8X
4.2.2.1 STATUS REGISTER Only the BCF, BSF, SWAPF and MOVWF instructions
should be used to alter the STATUS register (Table 9-2)
The STATUS register contains the arithmetic status of because these instructions do not affect any status bit.
the ALU, the RESET status and the bank select bit for
data memory. Note 1: The IRP and RP1 bits (STATUS<7:6>) are
not used by the PIC16F8X and should be
As with any register, the STATUS register can be the
programmed as cleared. Use of these bits
destination for any instruction. If the STATUS register is
as general purpose R/W bits is NOT
the destination for an instruction that affects the Z, DC
recommended, since this may affect
or C bits, then the write to these three bits is disabled.
upward compatibility with future products.
These bits are set or cleared according to device logic.
Furthermore, the TO and PD bits are not writable. Note 2: The C and DC bits operate as a borrow
Therefore, the result of an instruction with the STATUS and digit borrow out bit, respectively, in
register as destination may be different than intended. subtraction. See the SUBLW and SUBWF
instructions for examples.
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register Note 3: When the STATUS register is the
as 000u u1uu (where u = unchanged). destination for an instruction that affects
the Z, DC or C bits, then the write to these
three bits is disabled. The specified bit(s)
will be updated according to device logic
FIGURE 4-1: STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD Z DC C R = Readable bit
bit7 bit0 W = Writable bit
U = Unimplemented bit,
read as 0
- n = Value at POR reset
bit 7: IRP: Register Bank Select bit (used for indirect addressing)
0 = Bank 0, 1 (00h - FFh)
1 = Bank 2, 3 (100h - 1FFh)
The IRP bit is not used by the PIC16F8X. IRP should be maintained clear.
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h - 7Fh)
01 = Bank 1 (80h - FFh)
10 = Bank 2 (100h - 17Fh)
11 = Bank 3 (180h - 1FFh)
Each bank is 128 bytes. Only bit RP0 is used by the PIC16F8X. RP1 should be maintained clear.
bit 4: TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3: PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2: Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1: DC: Digit carry/borrow bit (for ADDWF and ADDLW instructions) (For borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0: C: Carry/borrow bit (for ADDWF and ADDLW instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note:For borrow the polarity is reversed. A subtraction is executed by adding the twos complement of
the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low
order bit of the source register.

PIC16F8X
4.2.2.2 OPTION_REG REGISTER
Note: When the prescaler is assigned to
The OPTION_REG register is a readable and writable the WDT (PSA = 1), TMR0 has a 1:1
register which contains various control bits to configure prescaler assignment.
the TMR0/WDT prescaler, the external INT interrupt,
TMR0, and the weak pull-ups on PORTB.
FIGURE 4-1: OPTION_REG REGISTER (ADDRESS 81h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit
read as 0
bit 7: RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled (by individual port latch values)
bit 6: INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5: T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4: T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3: PSA: Prescaler Assignment bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to TMR0
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
000 1:2 1:1

001 1:4 1:2
010 1:8 1:4
011 1 : 16 1:8
100 1 : 32 1 : 16
101 1 : 64 1 : 32
110 1 : 128 1 : 64
111 1 : 256 1 : 128

PIC16F8X
4.2.2.3 INTCON REGISTER
Note: Interrupt flag bits get set when an interrupt
The INTCON register is a readable and writable condition occurs regardless of the state of
register which contains the various enable bits for all its corresponding enable bit or the global
interrupt sources. enable bit, GIE (INTCON<7>).
FIGURE 4-1: INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE EEIE T0IE INTE RBIE T0IF INTF RBIF R = Readable bit
read as 0
bit 7: GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
Note: For the operation of the interrupt structure, please refer to Section 8.5.
bit 6: EEIE: EE Write Complete Interrupt Enable bit
1 = Enables the EE write complete interrupt
0 = Disables the EE write complete interrupt
bit 5: T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4: INTE: RB0/INT Interrupt Enable bit
1 = Enables the RB0/INT interrupt
0 = Disables the RB0/INT interrupt
bit 3: RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2: T0IF: TMR0 overflow interrupt flag bit
1 = TMR0 has overflowed (must be cleared in software)
0 = TMR0 did not overflow
bit 1: INTF: RB0/INT Interrupt Flag bit
1 = The RB0/INT interrupt occurred
0 = The RB0/INT interrupt did not occur
bit 0: RBIF: RB Port Change Interrupt Flag bit
1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state

PIC16F8X
4.3 Program Counter: PCL and PCLATH manipulation of the PCLATH<4:3> is not required for
the return instructions (which pops the PC from the
The Program Counter (PC) is 13-bits wide. The low stack).
byte is the PCL register, which is a readable and
writable register. The high byte of the PC (PC<12:8>) is Note: The PIC16F8X ignores the PCLATH<4:3>
not directly readable nor writable and comes from the bits, which are used for program memory
PCLATH register. The PCLATH (PC latch high) register pages 1, 2 and 3 (0800h - 1FFFh). The
is a holding register for PC<12:8>. The contents of use of PCLATH<4:3> as general purpose
PCLATH are transferred to the upper byte of the R/W bits is not recommended since this
program counter when the PC is loaded with a new may affect upward compatibility with
value. This occurs during a CALL, GOTO or a write to future products.
PCL. The high bits of PC are loaded from PCLATH as
4.4 Stack
shown in Figure 4-1.
The PIC16FXX has an 8 deep x 13-bit wide hardware
FIGURE 4-1: LOADING OF PC IN stack (Figure 4-1). The stack space is not part of either
DIFFERENT SITUATIONS program or data space and the stack pointer is not
PCH PCL readable or writable.
12 8 7 0 The entire 13-bit PC is pushed onto the stack when a
PC INST with PCL
as dest CALL instruction is executed or an interrupt is acknowl-
PCLATH<4:0> 8 edged. The stack is popped in the event of a
5 ALU result RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not affected by a push or a pop operation.
PCLATH
Note: There are no instruction mnemonics
PCH PCL called push or pop. These are actions that
12 11 10 8 7 0 occur from the execution of the CALL,
PC GOTO, CALL RETURN, RETLW, and RETFIE instruc-
11 tions, or the vectoring to an interrupt
PCLATH<4:3>
2 Opcode <10:0> address.
The stack operates as a circular buffer. That is, after the
PCLATH
stack has been pushed eight times, the ninth push over-
writes the value that was stored from the first push. The
4.3.1 COMPUTED GOTO tenth push overwrites the second push (and so on).
If the stack is effectively popped nine times, the PC
A computed GOTO is accomplished by adding an offset value is the same as the value from the first pop.
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care should Note: There are no status bits to indicate stack
be exercised if the table location crosses a PCL memory overflow or stack underflow conditions.
boundary (each 256 word block). Refer to the application
note Implementing a Table Read (AN556).
4.3.2 PROGRAM MEMORY PAGING
The PIC16F83 and PIC16CR83 have 512 words of pro-

gram memory. The PIC16F84 and PIC16CR84 have
1K of program memory. The CALL and GOTO instruc-
tions have an 11-bit address range. This 11-bit address
range allows a branch within a 2K program memory
page size. For future PIC16F8X program memory
expansion, there must be another two bits to specify
the program memory page. These paging bits come
from the PCLATH<4:3> bits (Figure 4-1). When doing a
CALL or a GOTO instruction, the user must ensure that
these page bits (PCLATH<4:3>) are programmed to
the desired program memory page. If a CALL instruc-
tion (or interrupt) is executed, the entire 13-bit PC is
pushed onto the stack (see next section). Therefore,

PIC16F8X
4.5 Indirect Addressing; INDF and FSR A simple program to clear RAM locations 20h-2Fh
Registers using indirect addressing is shown in Example 4-2.
The INDF register is not a physical register. Address- EXAMPLE 4-2: HOW TO CLEAR RAM
ing INDF actually addresses the register whose USING INDIRECT
address is contained in the FSR register (FSR is a
ADDRESSING
pointer). This is indirect addressing. movlw 0x20 ;initialize pointer
movwf FSR ; to RAM
EXAMPLE 4-1: INDIRECT ADDRESSING NEXT clrf INDF ;clear INDF register
Register file 05 contains the value 10h incf FSR ;inc pointer
Register file 06 contains the value 0Ah btfss FSR,4 ;all done?
Load the value 05 into the FSR register goto NEXT ;NO, clear next
A read of the INDF register will return the value of CONTINUE
: ;YES, continue
10h
Increment the value of the FSR register by one An effective 9-bit address is obtained by concatenating
(FSR = 06) the 8-bit FSR register and the IRP bit (STATUS<7>), as
A read of the INDF register now will return the shown in Figure 4-1. However, IRP is not used in the
value of 0Ah. PIC16F8X.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).
FIGURE 4-1: DIRECT/INDIRECT ADDRESSING

Direct Addressing Indirect Addressing
RP1 RP0 6 from opcode 0 IRP 7 (FSR) 0
bank select location select bank select location select
00 01 10 11
00h 00h
not used not used
0Bh
0Ch
Addresses
Data 2Fh (1) map back
Memory (3) 30h (1) to Bank 0
4Fh (2)
50h (2)
7Fh 7Fh
Bank 0 Bank 1 Bank 2 Bank 3
Note 1: PIC16F83 and PIC16CR83 devices.

2: PIC16F84 and PIC16CR84 devices
3: For memory map detail see Figure 4-1.

PIC16F8X
NOTES:

PIC16F8X
5.0 I/O PORTS EXAMPLE 5-1: INITIALIZING PORTA
CLRF PORTA ; Initialize PORTA by
The PIC16F8X has two ports, PORTA and PORTB. ; setting output
Some port pins are multiplexed with an alternate func- ; data latches
tion for other features on the device. BSF STATUS, RP0 ; Select Bank 1
MOVLW 0x0F ; Value used to
5.1 PORTA and TRISA Registers ; initialize data
; direction
PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger MOVWF TRISA ; Set RA<3:0> as inputs
input and an open drain output. All other RA port pins ; RA4 as outputs
have TTL input levels and full CMOS output drivers. All ; TRISA<7:5> are always
pins have data direction bits (TRIS registers) which can ; read as 0.
configure these pins as output or input.
Setting a TRISA bit (=1) will make the corresponding FIGURE 5-2: BLOCK DIAGRAM OF PIN RA4
PORTA pin an input, i.e., put the corresponding output
driver in a hi-impedance mode. Clearing a TRISA bit Data
(=0) will make the corresponding PORTA pin an output, bus D Q
i.e., put the contents of the output latch on the selected WR
pin. PORT
CK Q
RA4 pin
N
Reading the PORTA register reads the status of the pins
Data Latch
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write VSS
D Q
to a port implies that the port pins are first read, then this
value is modified and written to the port data latch. WR
TRIS CK Q
The RA4 pin is multiplexed with the TMR0 clock input. Schmitt
TRIS Latch Trigger
input
FIGURE 5-1: BLOCK DIAGRAM OF PINS buffer
RA3:RA0
Data
bus RD TRIS
D Q
Q D
VDD
WR
Port
CK Q EN
EN
P
RD PORT
Data Latch
N I/O pin
TMR0 clock input
D Q
WR Note: I/O pin has protection diodes to VSS only.

VSS
TRIS
CK Q
TRIS Latch TTL

input
buffer
RD TRIS
Q D
EN
RD PORT
Note: I/O pins have protection diodes to VDD and VSS.

PIC16F8X
TABLE 5-1 PORTA FUNCTIONS
Name Bit0 Buffer Type Function

RA0 bit0 TTL Input/output
RA4/T0CKI bit4 ST Input/output or external clock input for TMR0.
Output is open drain type.
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 5-2 SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on
Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-on
other resets
Reset
05h PORTA RA4/T0CKI RA3 RA2 RA1 RA0 ---x xxxx ---u uuuu
85h TRISA TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as 0. Shaded cells are unimplemented, read as 0

PIC16F8X
5.2 PORTB and TRISB Registers This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the
PORTB is an 8-bit wide bi-directional port. The interrupt in the following manner:
corresponding data direction register is TRISB. A 1 on
a) Read (or write) PORTB. This will end the mis-
any bit in the TRISB register puts the corresponding
match condition.
output driver in a hi-impedance mode. A 0 on any bit
in the TRISB register puts the contents of the output b) Clear flag bit RBIF.
latch on the selected pin(s). A mismatch condition will continue to set the RBIF bit.
Each of the PORTB pins have a weak internal pull-up. Reading PORTB will end the mismatch condition, and
A single control bit can turn on all the pull-ups. This is allow the RBIF bit to be cleared.
done by clearing the RBPU (OPTION_REG<7>) bit. This interrupt on mismatch feature, together with
The weak pull-up is automatically turned off when the software configurable pull-ups on these four pins allow
port pin is configured as an output. The pull-ups are easy interface to a key pad and make it possible for
disabled on a Power-on Reset. wake-up on key-depression (see AN552 in the
Four of PORTBs pins, RB7:RB4, have an interrupt on Embedded Control Handbook).
change feature. Only pins configured as inputs can Note 1: For a change on the I/O pin to be
cause this interrupt to occur (i.e., any RB7:RB4 pin recognized, the pulse width must be at
configured as an output is excluded from the interrupt least TCY (4/fOSC) wide.
on change comparison). The pins value in input mode
are compared with the old value latched on the last The interrupt on change feature is recommended for
read of PORTB. The mismatch outputs of the pins are wake-up on key depression operation and operations
ORed together to generate the RB port where PORTB is only used for the interrupt on change
change interrupt. feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
FIGURE 5-3: BLOCK DIAGRAM OF PINS
RB7:RB4 FIGURE 5-4: BLOCK DIAGRAM OF PINS
RB3:RB0
VDD
VDD RBPU(1) weak
P pull-up
RBPU(1) weak
P pull-up Data Latch
Data bus
Data Latch D Q
Data bus
D Q I/O
WR Port
CK pin(2)
I/O
WR Port
CK pin(2)
TRIS Latch
D Q
TRIS Latch TTL
WR TRIS Input
D Q
CK Buffer
WR TRIS TTL
CK
Input
Buffer
RD TRIS
Latch Q D
RD TRIS
Q D RD Port EN
RD Port
EN
Set RBIF RB0/INT
Schmitt Trigger
Buffer RD Port
From other Q D
RB7:RB4 pins
Note 1: TRISB = 1 enables weak pull-up
EN (if RBPU = 0 in the OPTION_REG register).
2: I/O pins have diode protection to VDD and VSS.
RD Port
Note 1: TRISB = 1 enables weak pull-up
(if RBPU = 0 in the OPTION_REG register).
2: I/O pins have diode protection to VDD and VSS.

PIC16F8X
EXAMPLE 5-1: INITIALIZING PORTB
CLRF PORTB ; Initialize PORTB by
; setting output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISB ; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
TABLE 5-3 PORTB FUNCTIONS
Name Bit Buffer Type I/O Consistency Function

(1)
RB0/INT bit0 TTL/STInput/output pin or external interrupt input. Internal software
programmable weak pull-up.
RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up.
RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
RB6 bit6 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable
weak pull-up. Serial programming clock.
RB7 bit7 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable
weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger.
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
TABLE 5-4 SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Value on
Value on all
other resets
Reset
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT xxxx xxxx uuuu uuuu
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
OPTION_ 1111 1111 1111 1111
REG
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.

PIC16F8X
5.3 I/O Programming Considerations 5.3.2 SUCCESSIVE OPERATIONS ON I/O
PORTS
5.3.1 BI-DIRECTIONAL I/O PORTS
The actual write to an I/O port happens at the end of an
Any instruction which writes, operates internally as a instruction cycle, whereas for reading, the data must be
read followed by a write operation. The BCF and BSF valid at the beginning of the instruction cycle
instructions, for example, read the register into the (Figure 5-5). Therefore, care must be exercised if a
CPU, execute the bit operation and write the result back write followed by a read operation is carried out on the
to the register. Caution must be used when these same I/O port. The sequence of instructions should be
instructions are applied to a port with both inputs and such that the pin voltage stabilizes (load dependent)
outputs defined. For example, a BSF operation on bit5 before the next instruction which causes that file to be
of PORTB will cause all eight bits of PORTB to be read read into the CPU is executed. Otherwise, the previous
into the CPU. Then the BSF operation takes place on state of that pin may be read into the CPU rather than
bit5 and PORTB is written to the output latches. If the new state. When in doubt, it is better to separate
another bit of PORTB is used as a bi-directional I/O pin these instructions with a NOP or another instruction not
(i.e., bit0) and it is defined as an input at this time, the accessing this I/O port.
input signal present on the pin itself would be read into
Example 5-1 shows the effect of two sequential
the CPU and rewritten to the data latch of this particular
read-modify-write instructions (e.g., BCF, BSF, etc.) on
pin, overwriting the previous content. As long as the pin
an I/O port.
stays in the input mode, no problem occurs. However, if
bit0 is switched into output mode later on, the content
of the data latch is unknown. EXAMPLE 5-1: READ-MODIFY-WRITE
INSTRUCTIONS ON AN
Reading the port register, reads the values of the port
I/O PORT
pins. Writing to the port register writes the value to the
;Initial PORT settings: PORTB<7:4> Inputs
port latch. When using read-modify-write instructions ; PORTB<3:0> Outputs
(i.e., BCF, BSF, etc.) on a port, the value of the port ;PORTB<7:6> have external pull-ups and are
pins is read, the desired operation is done to this value, ;not connected to other circuitry
and this value is then written to the port latch. ;
A pin actively outputting a Low or High should not be ; PORT latch PORT pins
; ---------- ---------
driven from external devices at the same time in order
BCF PORTB, 7 ; 01pp ppp 11pp ppp
to change the level on this pin (wired-or, wired-and). BCF PORTB, 6 ; 10pp ppp 11pp ppp
The resulting high output current may damage the chip. BSF STATUS, RP0 ;
BCF TRISB, 7 ; 10pp ppp 11pp ppp
BCF TRISB, 6 ; 10pp ppp 10pp ppp
;
;Note that the user may have expected the
;pin values to be 00pp ppp. The 2nd BCF
;caused RB7 to be latched as the pin value
;(high).
FIGURE 5-5: SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Note:
PC PC PC + 1 PC + 2 PC + 3 This example shows a write to PORTB
Instruction followed by a read from PORTB.
fetched MOVWF PORTB MOVF PORTB,W
write to NOP NOP
PORTB Note that:
RB7:RB0 data setup time = (0.25TCY - TPD)
where TCY = instruction cycle
Port pin
sampled here TPD = propagation delay
TPD Therefore, at higher clock frequencies,
Instruction
executed NOP
a write followed by a read may be prob-
MOVWF PORTB MOVF PORTB,W
write to lematic.
PORTB

PIC16F8X
NOTES:

PIC16F8X
6.0 TIMER0 MODULE AND TMR0 edge select bit, T0SE (OPTION_REG<4>). Clearing bit
T0SE selects the rising edge. Restrictions on the exter-
REGISTER
nal clock input are discussed in detail in Section 6.2.
The Timer0 module timer/counter has the following
The prescaler is shared between the Timer0 Module
features:
and the Watchdog Timer. The prescaler assignment is
8-bit timer/counter controlled, in software, by control bit PSA
Readable and writable (OPTION_REG<3>). Clearing bit PSA will assign the
8-bit software programmable prescaler prescaler to the Timer0 Module. The prescaler is not
readable or writable. When the prescaler (Section 6.3)
Internal or external clock select
is assigned to the Timer0 Module, the prescale value
Interrupt on overflow from FFh to 00h (1:2, 1:4, ..., 1:256) is software selectable.
Edge select for external clock
Timer mode is selected by clearing the T0CS bit 6.1 TMR0 Interrupt
(OPTION_REG<5>). In timer mode, the Timer0 mod- The TMR0 interrupt is generated when the TMR0
ule (Figure 6-1) will increment every instruction cycle register overflows from FFh to 00h. This overflow sets
(without prescaler). If the TMR0 register is written, the the T0IF bit (INTCON<2>). The interrupt can be
increment is inhibited for the following two cycles masked by clearing enable bit T0IE (INTCON<5>). The
(Figure 6-2 and Figure 6-3). The user can work around T0IF bit must be cleared in software by the Timer0
this by writing an adjusted value to the TMR0 register. Module interrupt service routine before re-enabling this
Counter mode is selected by setting the T0CS bit interrupt. The TMR0 interrupt (Figure 6-4) cannot wake
(OPTION_REG<5>). In this mode TMR0 will increment the processor from SLEEP since the timer is shut off
either on every rising or falling edge of pin RA4/T0CKI. during SLEEP.
The incrementing edge is determined by the T0 source
FIGURE 6-1: TMR0 BLOCK DIAGRAM
Data bus
FOSC/4 0
PSout 8
1
Sync with
1 Internal TMR0 register
RA4/T0CKI clocks
Programmable 0 PSout
pin Prescaler
T0SE (2 cycle delay)
3
Set bit T0IF
PS2, PS1, PS0 PSA on Overflow
T0CS
Note 1: Bits T0CS, T0SE, PS2, PS1, PS0 and PSA are located in the OPTION_REG register.
2: The prescaler is shared with the Watchdog Timer (Figure 6-6)
FIGURE 6-2: TMR0 TIMING: INTERNAL CLOCK/NO PRESCALER
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6
Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Fetch
TMR0 T0 T0+1 T0+2 NT0 NT0 NT0 NT0+1 NT0+2 T0
Instruction
Executed Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0
executed reads NT0 reads NT0 reads NT0 reads NT0 + 1 reads NT0 + 2

PIC16F8X
FIGURE 6-3: TMR0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6
Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Fetch
TMR0 T0 T0+1 NT0 NT0+1
Instruction
Execute Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0
executed reads NT0 reads NT0 reads NT0 reads NT0 reads NT0 + 1
FIGURE 6-4: TMR0 INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(3)
TMR0 timer FEh FFh 00h 01h 02h

1 1
T0IF bit 4
(INTCON<2>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW Interrupt Latency(2)
PC PC PC +1 PC +1 0004h 0005h
Instruction
fetched Inst (PC) Inst (PC+1) Inst (0004h) Inst (0005h)
Instruction
Inst (PC-1) Inst (PC) Dummy cycle Dummy cycle Inst (0004h)
executed
Note 1: T0IF interrupt flag is sampled here (every Q1).

2: Interrupt latency = 3.25Tcy, where Tcy = instruction cycle time.
3: CLKOUT is available only in RC oscillator mode.
4: The timer clock (after the synchronizer circuit) which increments the timer from FFh to 00h immediately sets the T0IF bit.
The TMR0 register will roll over 3 Tosc cycles later.

PIC16F8X
6.2 Using TMR0 with External Clock 6.2.2 TMR0 INCREMENT DELAY
When an external clock input is used for TMR0, it must Since the prescaler output is synchronized with the
meet certain requirements. The external clock internal clocks, there is a small delay from the time the
requirement is due to internal phase clock (TOSC) external clock edge occurs to the time the Timer0
synchronization. Also, there is a delay in the actual Module is actually incremented. Figure 6-5 shows the
incrementing of the TMR0 register after delay from the external clock edge to the timer
synchronization. incrementing.
6.2.1 EXTERNAL CLOCK SYNCHRONIZATION 6.3 Prescaler

When no prescaler is used, the external clock input is An 8-bit counter is available as a prescaler for the
the same as the prescaler output. The synchronization Timer0 Module, or as a postscaler for the Watchdog
of pin RA4/T0CKI with the internal phase clocks is Timer (Figure 6-6). For simplicity, this counter is being
accomplished by sampling the prescaler output on the referred to as prescaler throughout this data sheet.
Q2 and Q4 cycles of the internal phase clocks Note that there is only one prescaler available which is
(Figure 6-5). Therefore, it is necessary for T0CKI to be mutually exclusive between the Timer0 Module and the
high for at least 2Tosc (plus a small RC delay) and low Watchdog Timer. Thus, a prescaler assignment for the
for at least 2Tosc (plus a small RC delay). Refer to the Timer0 Module means that there is no prescaler for the
electrical specification of the desired device. Watchdog Timer, and vice-versa.
When a prescaler is used, the external clock input is The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
divided by an asynchronous ripple counter type determine the prescaler assignment and prescale ratio.
prescaler so that the prescaler output is symmetrical. When assigned to the Timer0 Module, all instructions
For the external clock to meet the sampling writing to the Timer0 Module (e.g., CLRF 1, MOVWF
requirement, the ripple counter must be taken into 1, BSF 1,x ....etc.) will clear the prescaler. When
account. Therefore, it is necessary for T0CKI to have a assigned to WDT, a CLRWDT instruction will clear the
period of at least 4Tosc (plus a small RC delay) divided prescaler along with the Watchdog Timer. The
by the prescaler value. The only requirement on T0CKI prescaler is not readable or writable.
high and low time is that they do not violate the
minimum pulse width requirement of 10 ns. Refer to
parameters 40, 41 and 42 in the AC Electrical
Specifications of the desired device.

PIC16F8X
FIGURE 6-5: TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Ext. Clock Input or
Prescaler Out (Note 2)
(Note 3)
Ext. Clock/Prescaler
Output After Sampling
Increment TMR0 (Q4)
TMR0 T0 T0 + 1 T0 + 2
Note 1: Delay from clock input change to TMR0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on TMR0 input = 4Tosc max.
2: External clock if no prescaler selected, Prescaler output otherwise.
3: The arrows indicate where sampling occurs. A small clock pulse may be missed by sampling.
FIGURE 6-6: BLOCK DIAGRAM OF THE TMR0/WDT PRESCALER
CLKOUT (= Fosc/4) Data Bus
M 8
0 1
RA4/T0CKI U M
X SYNC
pin U 2 TMR0 register
1 0
X Cycles
T0SE
T0CS
PSA Set bit T0IF
on overflow
0
M 8-bit Prescaler
U
Watchdog 1 X 8
Timer
8 - to - 1MUX PS2:PS0
PSA
0 1
WDT Enable bit
MUX PSA
WDT
time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION_REG register.

PIC16F8X
6.3.1 SWITCHING PRESCALER ASSIGNMENT EXAMPLE 6-1: CHANGING PRESCALER
(TIMER0WDT)
The prescaler assignment is fully under software BCF STATUS, RP0 ;Bank 0
control (i.e., it can be changed on the fly during CLRF TMR0 ;Clear TMR0
program execution). ; and Prescaler
BSF STATUS, RP0 ;Bank 1
Note: To avoid an unintended device RESET, the
CLRWDT ;Clears WDT
following instruction sequence MOVLW bxxxx1xxx ;Select new
(Example 6-1) must be executed when MOVWF OPTION_REG ; prescale value
changing the prescaler assignment from BCF STATUS, RP0 ;Bank 0
Timer0 to the WDT. This sequence must
be taken even if the WDT is disabled. To EXAMPLE 6-2: CHANGING PRESCALER
change prescaler from the WDT to the
(WDTTIMER0)
Timer0 module use the sequence shown in CLRWDT ;Clear WDT and
Example 6-2. ; prescaler
BSF STATUS, RP0 ;Bank 1
MOVLW bxxxx0xxx ;Select TMR0, new
; prescale value
and clock source
MOVWF OPTION_REG ;
BCF STATUS, RP0 ;Bank 0
TABLE 6-1 REGISTERS ASSOCIATED WITH TIMER0
Value on
Value on all
other resets
Reset
01h TMR0 Timer0 modules register xxxx xxxx uuuu uuuu
0Bh INTCON GIE EEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 0000
OPTION_ 1111 1111 1111 1111

REG
85h TRISA TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111
Legend: x = unknown, u = unchanged. - = unimplemented read as 0. Shaded cells are not associated with Timer0.

PIC16F8X
NOTES:

PIC16F8X
7.0 DATA EEPROM MEMORY data memory is rated for high erase/write cycles. The
write time is controlled by an on-chip timer. The write-
The EEPROM data memory is readable and writable time will vary with voltage and temperature as well as
during normal operation (full VDD range). This memory from chip to chip. Please refer to AC specifications for
is not directly mapped in the register file space. Instead exact limits.
it is indirectly addressed through the Special Function
Registers. There are four SFRs used to read and write When the device is code protected, the CPU may
this memory. These registers are: continue to read and write the data EEPROM memory.
The device programmer can no longer access
EECON1 this memory.
EECON2
EEDATA 7.1 EEADR
EEADR
The EEADR register can address up to a maximum of
EEDATA holds the 8-bit data for read/write, and EEADR
256 bytes of data EEPROM. Only the first 64 bytes of
holds the address of the EEPROM location being
data EEPROM are implemented.
accessed. PIC16F8X devices have 64 bytes of data
EEPROM with an address range from 0h to 3Fh. The upper two bits are address decoded. This means
that these two bits must always be '0' to ensure that the
The EEPROM data memory allows byte read and write.
address is in the 64 byte memory space.
A byte write automatically erases the location and
writes the new data (erase before write). The EEPROM
FIGURE 7-1: EECON1 REGISTER (ADDRESS 88h)
U U U R/W-0 R/W-x R/W-0 R/S-0 R/S-x

EEIF WRERR WREN WR RD R = Readable bit
S = Settable bit
read as 0
bit 7:5 Unimplemented: Read as 0
bit 4 EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation is not complete or has not been started
bit 3 WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated
(any MCLR reset or any WDT reset during normal operation)
0 = The write operation completed
bit 2 WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the data EEPROM
bit 1 WR: Write Control bit
1 = initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit can only
be set (not cleared) in software.
0 = Write cycle to the data EEPROM is complete
bit 0 RD: Read Control bit
1 = Initiates an EEPROM read (read takes one cycle. RD is cleared in hardware. The RD bit can only
be set (not cleared) in software).
0 = Does not initiate an EEPROM read

PIC16F8X
7.2 EECON1 and EECON2 Registers 7.4 Writing to the EEPROM Data Memory
EECON1 is the control register with five low order bits To write an EEPROM data location, the user must first
physically implemented. The upper-three bits are non- write the address to the EEADR register and the data
existent and read as 0s. to the EEDATA register. Then the user must follow a
Control bits RD and WR initiate read and write, specific sequence to initiate the write for each byte.
respectively. These bits cannot be cleared, only set, in
software. They are cleared in hardware at completion EXAMPLE 7-1: DATA EEPROM WRITE
of the read or write operation. The inability to clear the BSF STATUS, RP0 ; Bank 1
WR bit in software prevents the accidental, premature BCF INTCON, GIE ; Disable INTs.
termination of a write operation. BSF EECON1, WREN ; Enable Write
The WREN bit, when set, will allow a write operation. MOVLW 55h ;
MOVWF EECON2 ; Write 55h
On power-up, the WREN bit is clear. The WRERR bit is
Sequence
MOVLW AAh ;
Required
set when a write operation is interrupted by a MCLR MOVWF EECON2 ; Write AAh
reset or a WDT time-out reset during normal operation. BSF EECON1,WR ; Set WR bit
In these situations, following reset, the user can check ; begin write
the WRERR bit and rewrite the location. The data and BSF INTCON, GIE ; Enable INTs.
address will be unchanged in the EEDATA and
The write will not initiate if the above sequence is not
EEADR registers.
exactly followed (write 55h to EECON2, write AAh to
Interrupt flag bit EEIF is set when write is complete. It EECON2, then set WR bit) for each byte. We strongly
must be cleared in software. recommend that interrupts be disabled during this
EECON2 is not a physical register. Reading EECON2 code segment.
will read all 0s. The EECON2 register is used Additionally, the WREN bit in EECON1 must be set to
exclusively in the Data EEPROM write sequence. enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
7.3 Reading the EEPROM Data Memory code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
To read a data memory location, the user must write the
updating EEPROM. The WREN bit is not cleared
address to the EEADR register and then set control bit
by hardware
RD (EECON1<0>). The data is available, in the very
next cycle, in the EEDATA register; therefore it can be After a write sequence has been initiated, clearing the
read in the next instruction. EEDATA will hold this value WREN bit will not affect this write cycle. The WR bit will
until another read or until it is written to by the user be inhibited from being set unless the WREN bit is set.
(during a write operation). At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
EXAMPLE 7-1: DATA EEPROM READ Interrupt Flag bit (EEIF) is set. The user can either
BCF STATUS, RP0 ; Bank 0
enable this interrupt or poll this bit. EEIF must be
MOVLW CONFIG_ADDR ; cleared by software.
MOVWF EEADR ; Address to read
BSF STATUS, RP0 ; Bank 1
BSF EECON1, RD ; EE Read
MOVF EEDATA, W ; W = EEDATA

PIC16F8X
7.5 Write Verify SUBWF EEDATA, W ;
BTFSS STATUS, Z ; Is difference 0?
Depending on the application, good programming prac- GOTO WRITE_ERR ; NO, Write error
tice may dictate that the value written to the Data : ; YES, Good write
EEPROM should be verified (Example 7-1) to the : ; Continue program
desired value to be written. This should be used in
7.6 Protection Against Spurious Writes
applications where an EEPROM bit will be stressed
near the specification limit. The Total Endurance disk There are conditions when the device may not want to
will help determine your comfort level. write to the data EEPROM memory. To protect against
Generally the EEPROM write failure will be a bit which spurious EEPROM writes, various mechanisms have
was written as a 1, but reads back as a 0 (due to been built in. On power-up, WREN is cleared. Also, the
leakage off the bit). Power-up Timer (72 ms duration) prevents
EEPROM write.
EXAMPLE 7-1: WRITE VERIFY The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
: ; Any code can go here power glitch, or software malfunction.
: ;
MOVF EEDATA, W ; Must be in Bank 0 7.7 Data EEPROM Operation during Code
BSF STATUS, RP0 ; Bank 1 Protect
READ
BSF EECON1, RD ; YES, Read the When the device is code protected, the CPU is able to
; value written read and write unscrambled data to the Data EEPROM.
BCF STATUS, RP0 ; Bank 0 For ROM devices, there are two code protection bits
;
(Section 8.1). One for the ROM program memory and
; Is the value written (in W reg) and
; read (in EEDATA) the same?
one for the Data EEPROM memory.
;
TABLE 7-1 REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
Value on
Value on all
other resets
Reset
08h EEDATA EEPROM data register xxxx xxxx uuuu uuuu
09h EEADR EEPROM address register xxxx xxxx uuuu uuuu
88h EECON1 EEIF WRERR WREN WR RD ---0 x000 ---0 q000
89h EECON2 EEPROM control register 2 ---- ---- ---- ----
Legend: x = unknown, u = unchanged, - = unimplemented read as 0, q = value depends upon condition. Shaded cells are not
used by Data EEPROM.

PIC16F8X
NOTES:

PIC16F8X
8.0 SPECIAL FEATURES OF THE
CPU
What sets a microcontroller apart from other
processors are special circuits to deal with the needs of
real time applications. The PIC16F8X has a host of
such features intended to maximize system reliability,
minimize cost through elimination of external
components, provide power saving operating modes
and offer code protection. These features are:
OSC Selection
Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
Interrupts
Watchdog Timer (WDT)
SLEEP
Code protection
ID locations
In-circuit serial programming
The PIC16F8X has a Watchdog Timer which can be
shut off only through configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep
the chip in reset until the crystal oscillator is stable. The
other is the Power-up Timer (PWRT), which provides a
fixed delay of 72 ms (nominal) on power-up only. This
design keeps the device in reset while the power supply
stabilizes. With these two timers on-chip, most
applications need no external reset circuitry.
SLEEP mode offers a very low current power-down
mode. The user can wake-up from SLEEP through
external reset, Watchdog Timer time-out or through an
interrupt. Several oscillator options are provided to
allow the part to fit the application. The RC oscillator
option saves system cost while the LP crystal option
saves power. A set of configuration bits are used to
select the various options.

PIC16F8X
8.1 Configuration Bits Address 2007h is beyond the user program memory
space and it belongs to the special test/configuration
The configuration bits can be programmed (read as 0) memory space (2000h - 3FFFh). This space can only
or left unprogrammed (read as 1) to select various be accessed during programming.
device configurations. These bits are mapped in
To find out how to program the PIC16C84, refer to
program memory location 2007h.
PIC16C84 EEPROM Memory Programming Specifica-
tion (DS30189).
FIGURE 8-1: CONFIGURATION WORD - PIC16CR83 AND PIC16CR84
R-u R-u R-u R-u R-u R-u R/P-u R-u R-u R-u R-u R-u R-u R-u
CP CP CP CP CP CP DP CP CP CP PWRTE WDTE FOSC1 FOSC0
bit13 bit0
R = Readable bit
P = Programmable bit
u = unchanged
bit 13:8 CP: Program Memory Code Protection bit
1 = Code protection off
0 = Program memory is code protected
bit 7 DP: Data Memory Code Protection bit
0 = Data memory is code protected
bit 6:4 CP: Program Memory Code Protection bit
0 = Program memory is code protected
bit 3 PWRTE: Power-up Timer Enable bit
1 = Power-up timer is disabled
0 = Power-up timer is enabled
bit 2 WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1:0 FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator

PIC16F8X
FIGURE 8-2: CONFIGURATION WORD - PIC16F83 AND PIC16F84
R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u
CP CP CP CP CP CP CP CP CP CP PWRTE WDTE FOSC1 FOSC0
bit13 bit0
R = Readable bit
P = Programmable bit
u = unchanged
bit 13:4 CP: Code Protection bit
0 = All memory is code protected
bit 3 PWRTE: Power-up Timer Enable bit
1 = Power-up timer is disabled
0 = Power-up timer is enabled
bit 2 WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1:0 FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
8.2 Oscillator Configurations FIGURE 8-3: CRYSTAL/CERAMIC

RESONATOR OPERATION
8.2.1 OSCILLATOR TYPES
(HS, XT OR LP OSC
The PIC16F8X can be operated in four different CONFIGURATION)
oscillator modes. The user can program two C1(1) OSC1
configuration bits (FOSC1 and FOSC0) to select one of
these four modes: To
internal
LP Low Power Crystal XTAL logic
RF(3)
XT Crystal/Resonator OSC2
SLEEP
HS High Speed Crystal/Resonator RS(2)
RC Resistor/Capacitor C2(1) PIC16FXX
8.2.2 CRYSTAL OSCILLATOR / CERAMIC Note1: See Table 8-1 for recommended values of
RESONATORS C1 and C2.
2: A series resistor (RS) may be required for
In XT, LP or HS modes a crystal or ceramic resonator
AT strip cut crystals.
is connected to the OSC1/CLKIN and OSC2/CLKOUT
3: RF varies with the crystal chosen.
pins to establish oscillation (Figure 8-3).
The PIC16F8X oscillator design requires the use of a

parallel cut crystal. Use of a series cut crystal may give
a frequency out of the crystal manufacturers
specifications. When in XT, LP or HS modes, the device
can have an external clock source to drive the
OSC1/CLKIN pin (Figure 8-4).

PIC16F8X
FIGURE 8-4: EXTERNAL CLOCK INPUT
Crystals Tested:
OPERATION (HS, XT OR LP
OSC CONFIGURATION) 32.768 kHz Epson C-001R32.768K-A 20 PPM
100 kHz Epson C-2 100.00 KC-P 20 PPM
200 kHz STD XTL 200.000 KHz 20 PPM
Clock from OSC1
1.0 MHz ECS ECS-10-13-2 50 PPM
ext. system PIC16FXX
2.0 MHz ECS ECS-20-S-2 50 PPM
Open OSC2 4.0 MHz ECS ECS-40-S-4 50 PPM
10.0 MHz ECS ECS-100-S-4 50 PPM
TABLE 8-1 CAPACITOR SELECTION FOR 8.2.3 EXTERNAL CRYSTAL OSCILLATOR

CERAMIC RESONATORS CIRCUIT
Either a prepackaged oscillator can be used or a simple

Ranges Tested:
oscillator circuit with TTL gates can be built.
Mode Freq OSC1/C1 OSC2/C2 Prepackaged oscillators provide a wide operating
XT 455 kHz 47 - 100 pF 47 - 100 pF range and better stability. A well-designed crystal
2.0 MHz 15 - 33 pF 15 - 33 pF oscillator will provide good performance with TTL
4.0 MHz 15 - 33 pF 15 - 33 pF gates. Two types of crystal oscillator circuits are
available; one with series resonance, and one with
HS 8.0 MHz 15 - 33 pF 15 - 33 pF
parallel resonance.
10.0 MHz 15 - 33 pF 15 - 33 pF
Note : Recommended values of C1 and C2 are identical to Figure 8-5 shows a parallel resonant oscillator circuit.
the ranges tested table. The circuit is designed to use the fundamental
Higher capacitance increases the stability of the frequency of the crystal. The 74AS04 inverter performs
oscillator but also increases the start-up time. the 180-degree phase shift that a parallel oscillator
These values are for design guidance only. Since requires. The 4.7 k resistor provides negative
each resonator has its own characteristics, the user feedback for stability. The 10 k potentiometer biases
should consult the resonator manufacturer for the the 74AS04 in the linear region. This could be used for
appropriate values of external components. external oscillator designs.
Resonators Tested:
455 kHz Panasonic EFO-A455K04B 0.3%
FIGURE 8-5: EXTERNAL PARALLEL
RESONANT CRYSTAL
2.0 MHz Murata Erie CSA2.00MG 0.5%
OSCILLATOR CIRCUIT
4.0 MHz Murata Erie CSA4.00MG 0.5%
8.0 MHz Murata Erie CSA8.00MT 0.5% +5V
To Other
10.0 MHz Murata Erie CSA10.00MTZ 0.5% Devices
10k PIC16FXX
None of the resonators had built-in capacitors.
4.7k 74AS04
TABLE 8-2 CAPACITOR SELECTION FOR 74AS04 CLKIN
CRYSTAL OSCILLATOR
Mode Freq OSC1/C1 OSC2/C2 10k

LP 32 kHz 68 - 100 pF 68 - 100 pF XTAL
200 kHz 15 - 33 pF 15 - 33 pF
10k
XT 100 kHz 100 - 150 pF 100 - 150 pF
2 MHz 15 - 33 pF 15 - 33 pF
20 pF 20 pF
4 MHz 15 - 33 pF 15 - 33 pF
HS 4 MHz 15 - 33 pF 15 - 33 pF
10 MHz 15 - 33 pF 15 - 33 pF Figure 8-6 shows a series resonant oscillator circuit.
Note : Higher capacitance increases the stability of This circuit is also designed to use the fundamental
oscillator but also increases the start-up time. frequency of the crystal. The inverter performs a
These values are for design guidance only. Rs may 180-degree phase shift. The 330 k resistors provide
be required in HS mode as well as XT mode to the negative feedback to bias the inverters in their
avoid overdriving crystals with low drive level speci- linear region.
fication. Since each crystal has its own characteris-
tics, the user should consult the crystal
manufacturer for appropriate values of external
components.
For VDD > 4.5V, C1 = C2 30 pF is recommended.

PIC16F8X
FIGURE 8-6: EXTERNAL SERIES FIGURE 8-7: RC OSCILLATOR MODE
RESONANT CRYSTAL VDD
OSCILLATOR CIRCUIT
Rext
Internal
OSC1
To Other clock
330 k 330 k Devices
PIC16FXX
Cext PIC16FXX
74AS04 74AS04 74AS04
VSS
CLKIN
OSC2/CLKOUT
0.1 F Fosc/4
XTAL Recommended values: 5 k Rext 100 k
Cext > 20pF
Note: When the device oscillator is in RC mode,

8.2.4 RC OSCILLATOR do not drive the OSC1 pin with an external
clock or you may damage the device.
For timing insensitive applications the RC device option
offers additional cost savings. The RC oscillator 8.3 Reset
frequency is a function of the supply voltage, the
The PIC16F8X differentiates between various kinds
resistor (Rext) values, capacitor (Cext) values, and the
of reset:
operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal Power-on Reset (POR)
process parameter variation. Furthermore, the MCLR reset during normal operation
difference in lead frame capacitance between package MCLR reset during SLEEP
types also affects the oscillation frequency, especially WDT Reset (during normal operation)
for low Cext values. The user needs to take into
WDT Wake-up (during SLEEP)
account variation due to tolerance of the external
R and C components. Figure 8-7 shows how an R/C Figure 8-8 shows a simplified block diagram of the
combination is connected to the PIC16F8X. For Rext on-chip reset circuit. The MCLR reset path has a noise
values below 4 k, the oscillator operation may filter to ignore small pulses. The electrical specifica-
become unstable, or stop completely. For very high tions state the pulse width requirements for the MCLR
Rext values (e.g., 1 M), the oscillator becomes pin.
sensitive to noise, humidity and leakage. Thus, we Some registers are not affected in any reset condition;
recommend keeping Rext between 5 k and 100 k. their status is unknown on a POR reset and unchanged
Although the oscillator will operate with no external in any other reset. Most other registers are reset to a
capacitor (Cext = 0 pF), we recommend using values reset state on POR, MCLR or WDT reset during
above 20 pF for noise and stability reasons. With little normal operation and on MCLR reset during SLEEP.
or no external capacitance, the oscillation frequency They are not affected by a WDT reset during SLEEP,
can vary dramatically due to changes in external since this reset is viewed as the resumption of normal
capacitances, such as PCB trace capacitance or operation.
package lead frame capacitance. Table 8-3 gives a description of reset conditions for the
See the electrical specification section for RC program counter (PC) and the STATUS register.
frequency variation from part to part due to normal Table 8-4 gives a full description of reset states for all
process variation. The variation is larger for larger R registers.
(since leakage current variation will affect RC The TO and PD bits are set or cleared differently in dif-
frequency more for large R) and for smaller C (since ferent reset situations (Section 8.7). These bits are
variation of input capacitance has a greater affect on used in software to determine the nature of the reset.
RC frequency).
See the electrical specification section for variation of
oscillator frequency due to VDD for given Rext/Cext
values as well as frequency variation due to
operating temperature.
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin, and can be used for test
purposes or to synchronize other logic (see Figure 3-2
for waveform).

PIC16F8X
FIGURE 8-8: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
SLEEP
WDT WDT
Module Time_Out
Reset
VDD rise
detect S
Power_on_Reset
VDD
OST/PWRT
OST
Chip_Reset
10-bit Ripple counter R Q
OSC1/
CLKIN
PWRT
On-chip
RC OSC(1) 10-bit Ripple counter
Enable PWRT
See Table 8-5

Note 1: This is a separate oscillator from the
RC oscillator of the CLKIN pin. Enable OST

PIC16F8X
TABLE 8-3 RESET CONDITION FOR PROGRAM COUNTER AND THE STATUS REGISTER
Condition Program Counter STATUS Register
Power-on Reset 000h 0001 1xxx

MCLR Reset during normal operation 000h 000u uuuu
MCLR Reset during SLEEP 000h 0001 0uuu
WDT Reset (during normal operation) 000h 0000 1uuu
WDT Wake-up PC + 1 uuu0 0uuu
(1)
Interrupt wake-up from SLEEP PC + 1 uuu1 0uuu
Legend: u = unchanged, x = unknown.
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
TABLE 8-4 RESET CONDITIONS FOR ALL REGISTERS

MCLR Reset during: Wake-up from SLEEP:
normal operation through interrupt
Register Address Power-on Reset SLEEP through WDT Time-out
WDT Reset during nor-
mal operation
W xxxx xxxx uuuu uuuu uuuu uuuu
INDF 00h ---- ---- ---- ---- ---- ----
TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu
PCL 02h 0000h 0000h PC + 1(2)
STATUS 03h 0001 1xxx 000q quuu(3) uuuq quuu(3)
FSR 04h xxxx xxxx uuuu uuuu uuuu uuuu
PORTA 05h ---x xxxx ---u uuuu ---u uuuu
PORTB 06h xxxx xxxx uuuu uuuu uuuu uuuu
EEDATA 08h xxxx xxxx uuuu uuuu uuuu uuuu
EEADR 09h xxxx xxxx uuuu uuuu uuuu uuuu
PCLATH 0Ah ---0 0000 ---0 0000 ---u uuuu
INTCON 0Bh 0000 000x 0000 000u uuuu uuuu(1)
INDF 80h ---- ---- ---- ---- ---- ----
OPTION_REG 81h 1111 1111 1111 1111 uuuu uuuu
PCL 82h 0000h 0000h PC + 1
(3)
STATUS 83h 0001 1xxx 000q quuu uuuq quuu(3)
FSR 84h xxxx xxxx uuuu uuuu uuuu uuuu
TRISA 85h ---1 1111 ---1 1111 ---u uuuu
TRISB 86h 1111 1111 1111 1111 uuuu uuuu
EECON1 88h ---0 x000 ---0 q000 ---0 uuuu
EECON2 89h ---- ---- ---- ---- ---- ----
PCLATH 8Ah ---0 0000 ---0 0000 ---u uuuu
INTCON 8Bh 0000 000x 0000 000u uuuu uuuu(1)
Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0',
q = value depends on condition.
Note 1: One or more bits in INTCON will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: Table 8-3 lists the reset value for each specific condition.

PIC16F8X
8.4 Power-on Reset (POR) FIGURE 8-9: EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
A Power-on Reset pulse is generated on-chip when
VDD POWER-UP)
VDD rise is detected (in the range of 1.2V - 1.7V). To
take advantage of the POR, just tie the MCLR pin
directly (or through a resistor) to VDD. This will VDD VDD
eliminate external RC components usually needed to
create Power-on Reset. A minimum rise time for VDD D R
must be met for this to operate properly. See Electrical R1
Specifications for details. MCLR
When the device starts normal operation (exits the C PIC16FXX

reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be meet to ensure
operation. If these conditions are not met, the device Note 1: External Power-on Reset circuit is required
must be held in reset until the operating conditions only if VDD power-up rate is too slow. The
are met. diode D helps discharge the capacitor
For additional information, refer to Application Note quickly when VDD powers down.
AN607, "Power-up Trouble Shooting." 2: R < 40 k is recommended to make sure
that voltage drop across R does not exceed
The POR circuit does not produce an internal reset 0.2V (max leakage current spec on MCLR
when VDD declines. pin is 5 A). A larger voltage drop will
degrade VIH level on the MCLR pin.
8.5 Power-up Timer (PWRT)
3: R1 = 100 to 1 k will limit any current
The Power-up Timer (PWRT) provides a fixed 72 ms flowing into MCLR from external
nominal time-out (TPWRT) from POR (Figure 8-10, capacitor C in the event of an MCLR pin
Figure 8-11, Figure 8-12 and Figure 8-13). The breakdown due to ESD or EOS.
Power-up Timer operates on an internal RC oscillator.
The chip is kept in reset as long as the PWRT is active.
The PWRT delay allows the VDD to rise to an accept-
able level (Possible exception shown in Figure 8-13).
A configuration bit, PWRTE, can enable/disable the
PWRT. See either Figure 8-1 or Figure 8-2 for the oper-
ation of the PWRTE bit for a particular device.
The power-up time delay TPWRT will vary from chip to
chip due to VDD, temperature, and process variation.
See DC parameters for details.
8.6 Oscillator Start-up Timer (OST)

The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle delay (from OSC1 input) after the
PWRT delay ends (Figure 8-10, Figure 8-11,
Figure 8-12 and Figure 8-13). This ensures the crystal
oscillator or resonator has started and stabilized.
The OST time-out (TOST) is invoked only for XT, LP and
HS modes and only on Power-on Reset or wake-up
from SLEEP.
When VDD rises very slowly, it is possible that the
TPWRT time-out and TOST time-out will expire before
VDD has reached its final value. In this case
(Figure 8-13), an external power-on reset circuit may
be necessary (Figure 8-9).

PIC16F8X
FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 8-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT TOST
OST TIME-OUT
INTERNAL RESET

PIC16F8X
FIGURE 8-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 8-13: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME
V1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT TOST
OST TIME-OUT
INTERNAL RESET
When VDD rises very slowly, it is possible that the TPWRT time-out and TOST time-out will expire before VDD
has reached its final value. In this example, the chip will reset properly if, and only if, V1 VDD min.

PIC16F8X
8.7 Time-out Sequence and Power-down 8.8 Reset on Brown-Out
Status Bits (TO/PD)
A brown-out is a condition where device power (VDD)
On power-up (Figure 8-10, Figure 8-11, Figure 8-12 dips below its minimum value, but not to zero, and then
and Figure 8-13) the time-out sequence is as follows: recovers. The device should be reset in the event of a
First PWRT time-out is invoked after a POR has brown-out.
expired. Then the OST is activated. The total time-out To reset a PIC16F8X device when a brown-out occurs,
will vary based on oscillator configuration and PWRTE external brown-out protection circuits may be built, as
configuration bit status. For example, in RC mode with shown in Figure 8-14 and Figure 8-15.
the PWRT disabled, there will be no time-out at all.
TABLE 8-5 TIME-OUT IN VARIOUS FIGURE 8-14: BROWN-OUT PROTECTION
SITUATIONS CIRCUIT 1
Oscillator Power-up Wake-up VDD

Configuration PWRT PWRT from VDD
Enabled Disabled SLEEP
33k
XT, HS, LP 72 ms + 1024TOSC 1024TOSC
1024TOSC 10k MCLR
RC 72 ms
40k PIC16F8X
Since the time-outs occur from the POR reset pulse, if
MCLR is kept low long enough, the time-outs will
expire. Then bringing MCLR high, execution will begin
immediately (Figure 8-10). This is useful for testing
purposes or to synchronize more than one PIC16F8X
device when operating in parallel. This circuit will activate reset when VDD goes below
(Vz + 0.7V) where Vz = Zener voltage.
Table 8-6 shows the significance of the TO and PD bits.
Table 8-3 lists the reset conditions for some special
registers, while Table 8-4 lists the reset conditions for
all the registers.
FIGURE 8-15: BROWN-OUT PROTECTION
CIRCUIT 2
TABLE 8-6 STATUS BITS AND THEIR VDD
SIGNIFICANCE VDD
R1
TO PD Condition
Q1
1 1 Power-on Reset
MCLR
0 x Illegal, TO is set on POR R2 40k
x 0 Illegal, PD is set on POR PIC16F8X
0 1 WDT Reset (during normal operation)
0 0 WDT Wake-up
1 1 MCLR Reset during normal operation
1 0 MCLR Reset during SLEEP or interrupt
This brown-out circuit is less expensive, although less
wake-up from SLEEP
accurate. Transistor Q1 turns off when VDD is below a
certain level such that:
R1
VDD = 0.7V
R1 + R2

PIC16F8X
8.9 Interrupts The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
The PIC16F8X has 4 sources of interrupt: the INTCON register.
External interrupt RB0/INT pin When an interrupt is responded to; the GIE bit is
TMR0 overflow interrupt cleared to disable any further interrupt, the return
PORTB change interrupts (pins RB7:RB4) address is pushed onto the stack and the PC is loaded
Data EEPROM write complete interrupt with 0004h. For external interrupt events, such as the
RB0/INT pin or PORTB change interrupt, the interrupt
The interrupt control register (INTCON) records latency will be three to four instruction cycles. The
individual interrupt requests in flag bits. It also contains exact latency depends when the interrupt event occurs
the individual and global interrupt enable bits. (Figure 8-17). The latency is the same for both one and
The global interrupt enable bit, GIE (INTCON<7>) two cycle instructions. Once in the interrupt service
enables (if set) all un-masked interrupts or disables (if routine the source(s) of the interrupt can be determined
cleared) all interrupts. Individual interrupts can be by polling the interrupt flag bits. The interrupt flag bit(s)
disabled through their corresponding enable bits in must be cleared in software before re-enabling
INTCON register. Bit GIE is cleared on reset. interrupts to avoid infinite interrupt requests.
The return from interrupt instruction, RETFIE, exits
interrupt routine as well as sets the GIE bit, which
Note 1: Individual interrupt flag bits are set
re-enable interrupts.
regardless of the status of their
corresponding mask bit or the GIE bit.
FIGURE 8-16: INTERRUPT LOGIC
Wake-up
T0IF (If in SLEEP mode)
T0IE
INTF
INTE
Interrupt to CPU
RBIF
RBIE
EEIF
EEIE
GIE

PIC16F8X
FIGURE 8-17: INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT 3
4
INT pin
1
1
INTF flag 5 Interrupt Latency 2
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC PC PC+1 PC+1 0004h 0005h
Instruction
fetched Inst (PC) Inst (PC+1) Inst (0004h) Inst (0005h)
Instruction Dummy Cycle Dummy Cycle Inst (0004h)

executed Inst (PC-1) Inst (PC)
Note 1: INTF flag is sampled here (every Q1).

2: Interrupt latency = 3-4Tcy where Tcy = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in RC oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
8.9.1 INT INTERRUPT 8.9.3 PORT RB INTERRUPT
External interrupt on RB0/INT pin is edge triggered: An input change on PORTB<7:4> sets flag bit RBIF
either rising if INTEDG bit (OPTION_REG<6>) is set, (INTCON<0>). The interrupt can be enabled/disabled
or falling, if INTEDG bit is clear. When a valid edge by setting/clearing enable bit RBIE (INTCON<3>)
appears on the RB0/INT pin, the INTF bit (Section 5.2).
(INTCON<1>) is set. This interrupt can be disabled by
Note 1: For a change on the I/O pin to be
clearing control bit INTE (INTCON<4>). Flag bit INTF
recognized, the pulse width must be at
must be cleared in software via the interrupt service
least TCY wide.
routine before re-enabling this interrupt. The INT
interrupt can wake the processor from SLEEP
(Section 8.12) only if the INTE bit was set prior to going
into SLEEP. The status of the GIE bit decides whether
the processor branches to the interrupt vector
following wake-up.
8.9.2 TMR0 INTERRUPT
An overflow (FFh 00h) in TMR0 will set flag bit T0IF

(INTCON<2>). The interrupt can be enabled/disabled
by setting/clearing enable bit T0IE (INTCON<5>)
(Section 6.0).

PIC16F8X
8.10 Context Saving During Interrupts Example 8-1 does the following:
a) Stores the W register.
During an interrupt, only the return PC value is saved
on the stack. Typically, users wish to save key register b) Stores the STATUS register in STATUS_TEMP.
values during an interrupt (e.g., W register and c) Executes the Interrupt Service Routine code.
STATUS register). This is implemented in software. d) Restores the STATUS (and bank select bit)
Example 8-1 stores and restores the STATUS and W register.
registers values. The User defined registers, W_TEMP e) Restores the W register.
and STATUS_TEMP are the temporary storage
locations for the W and STATUS registers values.
EXAMPLE 8-1: SAVING STATUS AND W REGISTERS IN RAM

PUSH MOVWF W_TEMP ; Copy W to TEMP register,
SWAPF STATUS, W ; Swap status to be saved into W
MOVWF STATUS_TEMP ; Save status to STATUS_TEMP register
ISR : :
: ; Interrupt Service Routine
: ; should configure Bank as required
: ;
POP SWAPF STATUS_TEMP, W ; Swap nibbles in STATUS_TEMP register
; and place result into W
MOVWF STATUS ; Move W into STATUS register
; (sets bank to original state)
SWAPF W_TEMP, F ; Swap nibbles in W_TEMP and place result in W_TEMP
SWAPF W_TEMP, W ; Swap nibbles in W_TEMP and place result into W

PIC16F8X
8.11 Watchdog Timer (WDT) part (see DC specs). If longer time-out periods are
desired, a prescaler with a division ratio of up to 1:128
The Watchdog Timer is a free running on-chip RC can be assigned to the WDT under software control by
oscillator which does not require any external writing to the OPTION_REG register. Thus, time-out
components. This RC oscillator is separate from the periods up to 2.3 seconds can be realized.
RC oscillator of the OSC1/CLKIN pin. That means that
The CLRWDT and SLEEP instructions clear the WDT
the WDT will run even if the clock on the OSC1/CLKIN
and the postscaler (if assigned to the WDT) and pre-
and OSC2/CLKOUT pins of the device has been
vent it from timing out and generating a device
stopped, for example, by execution of a SLEEP
RESET condition.
instruction. During normal operation a WDT time-out
generates a device RESET. If the device is in SLEEP The TO bit in the STATUS register will be cleared upon
mode, a WDT Wake-up causes the device to wake-up a WDT time-out.
and continue with normal operation. The WDT can be
permanently disabled by programming configuration bit 8.11.2 WDT PROGRAMMING CONSIDERATIONS
WDTE as a 0 (Section 8.1). It should also be taken into account that under worst
8.11.1 WDT PERIOD case conditions (VDD = Min., Temperature = Max., max.
WDT prescaler) it may take several seconds before a
The WDT has a nominal time-out period of 18 ms, (with WDT time-out occurs.
no prescaler). The time-out periods vary with
temperature, VDD and process variations from part to
FIGURE 8-18: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source

(Figure 6-6)
0
M Postscaler
WDT Timer 1 U
X 8
8 - to -1 MUX PS2:PS0
PSA
WDT
Enable Bit
To TMR0 (Figure 6-6)
0 1
MUX PSA
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
TABLE 8-7 SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER

Value on
Value on all
other resets
Reset
2007h Config. bits (2) (2) (2) (2) PWRTE(1) WDTE FOSC1 FOSC0 (2)
OPTION_ 1111 1111 1111 1111

REG
Legend: x = unknown. Shaded cells are not used by the WDT.
Note 1: See Figure 8-1 and Figure 8-2 for operation of the PWRTE bit.
2: See Figure 8-1, Figure 8-2 and Section 8.13 for operation of the Code and Data protection bits.

PIC16F8X
8.12 Power-down Mode (SLEEP) 8.12.2 WAKE-UP FROM SLEEP
A device may be powered down (SLEEP) and later The device can wake-up from SLEEP through one of
powered up (Wake-up from SLEEP). the following events:
1. External reset input on MCLR pin.
8.12.1 SLEEP
2. WDT Wake-up (if WDT was enabled).
The Power-down mode is entered by executing the 3. Interrupt from RB0/INT pin, RB port change, or
SLEEP instruction. data EEPROM write complete.
If enabled, the Watchdog Timer is cleared (but keeps Peripherals cannot generate interrupts during SLEEP,
running), the PD bit (STATUS<3>) is cleared, the TO bit since no on-chip Q clocks are present.
(STATUS<4>) is set, and the oscillator driver is turned
The first event (MCLR reset) will cause a device reset.
off. The I/O ports maintain the status they had before
The two latter events are considered a continuation of
the SLEEP instruction was executed (driving high, low,
program execution. The TO and PD bits can be used to
or hi-impedance).
determine the cause of a device reset. The PD bit,
For the lowest current consumption in SLEEP mode, which is set on power-up, is cleared when SLEEP is
place all I/O pins at either at VDD or VSS, with no invoked. The TO bit is cleared if a WDT time-out
external circuitry drawing current from the I/O pins, and occurred (and caused wake-up).
disable external clocks. I/O pins that are hi-impedance
While the SLEEP instruction is being executed, the next
inputs should be pulled high or low externally to avoid
instruction (PC + 1) is pre-fetched. For the device to
switching currents caused by floating inputs. The
wake-up through an interrupt event, the corresponding
T0CKI input should also be at VDD or VSS. The
interrupt enable bit must be set (enabled). Wake-up
contribution from on-chip pull-ups on PORTB should be
occurs regardless of the state of the GIE bit. If the GIE
considered.
bit is clear (disabled), the device continues execution at
The MCLR pin must be at a logic high level (VIHMC). the instruction after the SLEEP instruction. If the GIE bit
It should be noted that a RESET generated by a WDT is set (enabled), the device executes the instruction
time-out does not drive the MCLR pin low. after the SLEEP instruction and then branches to the
interrupt address (0004h). In cases where the
execution of the instruction following SLEEP is not
desirable, the user should have a NOP after the
SLEEP instruction.
FIGURE 8-19: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4) TOST(2)
INT pin
INTF flag
(INTCON<1>) Interrupt Latency
(Note 2)
GIE bit Processor in
(INTCON<7>)
SLEEP
INSTRUCTION FLOW
PC PC PC+1 PC+2 PC+2 PC + 2 0004h 0005h
Instruction
Inst(PC) = SLEEP Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h)
fetched
Instruction Dummy cycle Dummy cycle
Inst(PC - 1) SLEEP Inst(PC + 1) Inst(0004h)
executed
Note 1: XT, HS or LP oscillator mode assumed.

2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.
3: GIE = 1 assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.

PIC16F8X
8.12.3 WAKE-UP USING INTERRUPTS 8.15 In-Circuit Serial Programming
When global interrupts are disabled (GIE cleared) and PIC16F8X microcontrollers can be serially
any interrupt source has both its interrupt enable bit programmed while in the end application circuit. This is
and interrupt flag bit set, one of the following will occur: simply done with two lines for clock and data, and three
If the interrupt occurs before the execution of a other lines for power, ground, and the programming
SLEEP instruction, the SLEEP instruction will com- voltage. Customers can manufacture boards with
plete as a NOP. Therefore, the WDT and WDT unprogrammed devices, and then program the
postscaler will not be cleared, the TO bit will not microcontroller just before shipping the product,
be set and PD bits will not be cleared. allowing the most recent firmware or custom firmware
to be programmed.
If the interrupt occurs during or after the execu-
tion of a SLEEP instruction, the device will imme- The device is placed into a program/verify mode by
diately wake up from sleep. The SLEEP instruction holding the RB6 and RB7 pins low, while raising the
will be completely executed before the wake-up. MCLR pin from VIL to VIHH (see programming
Therefore, the WDT and WDT postscaler will be specification). RB6 becomes the programming clock
cleared, the TO bit will be set and the PD bit will and RB7 becomes the programming data. Both RB6
be cleared. and RB7 are Schmitt Trigger inputs in this mode.
Even if the flag bits were checked before executing a After reset, to place the device into programming/verify
SLEEP instruction, it may be possible for flag bits to mode, the program counter (PC) points to location 00h.
become set before the SLEEP instruction completes. To A 6-bit command is then supplied to the device, 14-bits
determine whether a SLEEP instruction executed, test of program data is then supplied to or from the device,
the PD bit. If the PD bit is set, the SLEEP instruction using load or read-type instructions. For complete
was executed as a NOP. details of serial programming, please refer to the
PIC16CXX Programming Specifications (Literature
To ensure that the WDT is cleared, a CLRWDT instruc-
#DS30189).
tion should be executed before a SLEEP instruction.
8.13 Program Verification/Code Protection FIGURE 8-20: TYPICAL IN-SYSTEM SERIAL

PROGRAMMING
If the code protection bit(s) have not been CONNECTION
programmed, the on-chip program memory can be
read out for verification purposes.
To Normal
Note: Microchip does not recommend code pro- External Connections
tecting widowed devices. Connector PIC16FXX
Signals
8.14 ID Locations
+5V VDD
Four memory locations (2000h - 2003h) are designated 0V VSS
as ID locations to store checksum or other code VPP MCLR/VPP
identification numbers. These locations are not
accessible during normal execution but are readable CLK RB6
and writable only during program/verify. Only the
4 least significant bits of ID location are usable. Data I/O RB7
For ROM devices, these values are submitted along

with the ROM code. VDD
To Normal
Connections
For ROM devices, both the program memory and Data

EEPROM memory may be read, but only the Data
EEPROM memory may be programmed.

PIC16F8X

PIC16F8X
9.0 INSTRUCTION SET SUMMARY The instruction set is highly orthogonal and is grouped
into three basic categories:
Each PIC16CXX instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type Byte-oriented operations
and one or more operands which further specify the Bit-oriented operations
operation of the instruction. The PIC16CXX instruction Literal and control operations
set summary in Table 9-2 lists byte-oriented, bit-ori-
All instructions are executed within one single instruc-
ented, and literal and control operations. Table 9-1
tion cycle, unless a conditional test is true or the pro-
shows the opcode field descriptions.
gram counter is changed as a result of an instruction.
For byte-oriented instructions, f represents a file reg- In this case, the execution takes two instruction cycles
ister designator and d represents a destination desig- with the second cycle executed as a NOP. One instruc-
nator. The file register designator specifies which file tion cycle consists of four oscillator periods. Thus, for
register is to be used by the instruction. an oscillator frequency of 4 MHz, the normal instruction
The destination designator specifies where the result of execution time is 1 s. If a conditional test is true or the
the operation is to be placed. If d is zero, the result is program counter is changed as a result of an instruc-
placed in the W register. If d is one, the result is placed tion, the instruction execution time is 2 s.
in the file register specified in the instruction. Table 9-2 lists the instructions recognized by the
For bit-oriented instructions, b represents a bit field MPASM assembler.
designator which selects the number of the bit affected Figure 9-1 shows the general formats that the instruc-
by the operation, while f represents the number of the tions can have.
file in which the bit is located.
Note: To maintain upward compatibility with
For literal and control operations, k represents an future PIC16CXX products, do not use the
eight or eleven bit constant or literal value. OPTION and TRIS instructions.
TABLE 9-1 OPCODE FIELD All examples use the following format to represent a
DESCRIPTIONS hexadecimal number:
Field Description 0xhh
f Register file address (0x00 to 0x7F) where h signifies a hexadecimal digit.

W Working register (accumulator)
b Bit address within an 8-bit file register FIGURE 9-1: GENERAL FORMAT FOR
k Literal field, constant data or label INSTRUCTIONS
x Dont care location (= 0 or 1) Byte-oriented file register operations
The assembler will generate code with x = 0. It is the 13 8 7 6 0
recommended form of use for compatibility with all OPCODE d f (FILE #)
Microchip software tools.
d = 0 for destination W
d Destination select; d = 0: store result in W,
d = 1 for destination f
d = 1: store result in file register f. f = 7-bit file register address
Default is d = 1
label Label name
Bit-oriented file register operations
TOS Top of Stack 13 10 9 7 6 0
PC Program Counter OPCODE b (BIT #) f (FILE #)
PCLATH Program Counter High Latch
GIE Global Interrupt Enable bit b = 3-bit bit address
f = 7-bit file register address
WDT Watchdog Timer/Counter
TO Time-out bit
Literal and control operations
PD Power-down bit
dest Destination either the W register or the specified General
register file location
13 8 7 0
[ ] Options
OPCODE k (literal)
( ) Contents
Assigned to k = 8-bit immediate value
<> Register bit field

CALL and GOTO instructions only
In the set of
13 11 10 0
italics User defined term (font is courier)
OPCODE k (literal)
k = 11-bit immediate value

PIC16F8X
TABLE 9-2 PIC16FXX INSTRUCTION SET
Mnemonic, Description Cycles 14-Bit Opcode Status Notes
Operands Affected
MSb LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF f, d Add W and f 1 00 0111 dfff ffff C,DC,Z 1,2
ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1,2
CLRF f Clear f 1 00 0001 lfff ffff Z 2
CLRW - Clear W 1 00 0001 0xxx xxxx Z
COMF f, d Complement f 1 00 1001 dfff ffff Z 1,2
DECF f, d Decrement f 1 00 0011 dfff ffff Z 1,2
DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1,2,3
INCF f, d Increment f 1 00 1010 dfff ffff Z 1,2
INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1,2,3
IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 1,2
MOVF f, d Move f 1 00 1000 dfff ffff Z 1,2
MOVWF f Move W to f 1 00 0000 lfff ffff
NOP - No Operation 1 00 0000 0xx0 0000
RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1,2
RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1,2
SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C,DC,Z 1,2
SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 1,2
XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF f, b Bit Clear f 1 01 00bb bfff ffff 1,2
BSF f, b Bit Set f 1 01 01bb bfff ffff 1,2
BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3
BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3
LITERAL AND CONTROL OPERATIONS
ADDLW k Add literal and W 1 11 111x kkkk kkkk C,DC,Z
ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z
CALL k Call subroutine 2 10 0kkk kkkk kkkk
CLRWDT - Clear Watchdog Timer 1 00 0000 0110 0100 TO,PD
GOTO k Go to address 2 10 1kkk kkkk kkkk
IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z
MOVLW k Move literal to W 1 11 00xx kkkk kkkk
RETFIE - Return from interrupt 2 00 0000 0000 1001
RETLW k Return with literal in W 2 11 01xx kkkk kkkk
RETURN - Return from Subroutine 2 00 0000 0000 1000
SLEEP - Go into standby mode 1 00 0000 0110 0011 TO,PD
SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C,DC,Z
XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is 1 for a pin configured as input and is driven low by an external
device, the data will be written back with a 0.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.

PIC16F8X
9.1 Instruction Descriptions
ADDLW Add Literal and W ANDLW AND Literal with W

Syntax: [label] ADDLW k Syntax: [label] ANDLW k
Operands: 0 k 255 Operands: 0 k 255
Operation: (W) + k (W) Operation: (W) .AND. (k) (W)
Status Affected: C, DC, Z Status Affected: Z
Encoding: 11 111x kkkk kkkk Encoding: 11 1001 kkkk kkkk
Description: The contents of the W register are Description: The contents of W register are
added to the eight bit literal k and the ANDed with the eight bit literal 'k'. The
result is placed in the W register. result is placed in the W register.
Words: 1 Words: 1
Cycles: 1 Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Q1 Q2 Q3 Q4
Decode Read Process Write to Decode Read Process Write to
literal k data W literal "k" data W
Example: ADDLW 0x15 Example ANDLW 0x5F
Before Instruction Before Instruction

W = 0x10 W = 0xA3
After Instruction After Instruction
W = 0x25 W = 0x03
ADDWF Add W and f ANDWF AND W with f

Syntax: [label] ADDWF f,d Syntax: [label] ANDWF f,d
Operands: 0 f 127 Operands: 0 f 127
d [0,1] d [0,1]
Operation: (W) + (f) (destination) Operation: (W) .AND. (f) (destination)
Status Affected: C, DC, Z Status Affected: Z
Encoding: 00 0111 dfff ffff Encoding: 00 0101 dfff ffff
Description: Add the contents of the W register with Description: AND the W register with register 'f'. If 'd'
register f. If d is 0 the result is stored is 0 the result is stored in the W regis-
in the W register. If d is 1 the result is ter. If 'd' is 1 the result is stored back in
stored back in register f. register 'f'.
Words: 1 Words: 1
Cycles: 1 Cycles: 1
register data destination register data destination
f f
Example ADDWF FSR, 0 Example ANDWF FSR, 1

W = 0x17 W = 0x17
FSR = 0xC2 FSR = 0xC2
W = 0xD9 W = 0x17
FSR = 0xC2 FSR = 0x02

PIC16F8X
BCF Bit Clear f BTFSC Bit Test, Skip if Clear

Syntax: [label] BCF f,b Syntax: [label] BTFSC f,b
0b7 0b7
Operation: 0 (f<b>) Operation: skip if (f<b>) = 0
Status Affected: None Status Affected: None
Encoding: 01 00bb bfff ffff Encoding: 01 10bb bfff ffff
Description: Bit b in register f is cleared. Description: If bit b in register f is 1 then the next
instruction is executed.
Words: 1 If bit b, in register f, is 0 then the next
Cycles: 1 instruction is discarded, and a NOP is
executed instead, making this a 2TCY
Q Cycle Activity: Q1 Q2 Q3 Q4
instruction.
Decode Read Process Write
register data register f Words: 1
f
Cycles: 1(2)
Example BCF FLAG_REG, 7
Decode Read Process No-Operat
Before Instruction register f data ion
FLAG_REG = 0xC7
After Instruction If Skip: (2nd Cycle)
FLAG_REG = 0x47 Q1 Q2 Q3 Q4
No-Operati No-Opera No-Operat
No-Operat on tion ion
ion
Example HERE BTFSC FLAG,1

FALSE GOTO PROCESS_CODE
TRUE

Before Instruction
PC = address HERE
After Instruction
BSF Bit Set f if FLAG<1> = 0,
PC = address TRUE
Syntax: [label] BSF f,b if FLAG<1>=1,
Operands: 0 f 127 PC = address FALSE
0b7
Operation: 1 (f<b>)
Status Affected: None
Encoding: 01 01bb bfff ffff
Description: Bit b in register f is set.
Words: 1
Cycles: 1
register data register f
f
Example BSF FLAG_REG, 7

Before Instruction
FLAG_REG = 0x0A
After Instruction
FLAG_REG = 0x8A

PIC16F8X
BTFSS Bit Test f, Skip if Set CALL Call Subroutine

Syntax: [label] BTFSS f,b Syntax: [ label ] CALL k
Operands: 0 f 127 Operands: 0 k 2047
0b<7
Operation: (PC)+ 1 TOS,
Operation: skip if (f<b>) = 1 k PC<10:0>,
Status Affected: None (PCLATH<4:3>) PC<12:11>
Encoding: 01 11bb bfff ffff Status Affected: None

Description: If bit b in register f is 0 then the next Encoding: 10 0kkk kkkk kkkk
instruction is executed.
If bit b is 1, then the next instruction is Description: Call Subroutine. First, return address
(PC+1) is pushed onto the stack. The
discarded and a NOP is executed eleven bit immediate address is loaded
instead, making this a 2TCY instruction.
into PC bits <10:0>. The upper bits of
Words: 1 the PC are loaded from PCLATH. CALL
is a two cycle instruction.
Cycles: 1(2)
Words: 1
Cycles: 2
Decode Read Process No-Operat
register f data ion Q Cycle Activity: Q1 Q2 Q3 Q4
1st Cycle Decode Read Process Write to
If Skip: (2nd Cycle) literal k, data PC
Q1 Q2 Q3 Q4 Push PC
to Stack
No-Operati No-Opera No-Operat
No-Operat on tion ion 2nd Cycle No-Opera No-Opera No-Operat
No-Opera tion tion ion
ion
tion
Example HERE BTFSC FLAG,1

Example HERE CALL THERE
FALSE GOTO PROCESS_CODE
TRUE Before Instruction
PC = Address HERE
After Instruction
Before Instruction PC = Address THERE
PC = address HERE TOS = Address HERE+1
After Instruction
if FLAG<1> = 0,
PC = address FALSE
if FLAG<1> = 1,
PC = address TRUE

PIC16F8X
CLRF Clear f CLRW Clear W

Syntax: [label] CLRF f Syntax: [ label ] CLRW
Operands: 0 f 127 Operands: None
Operation: 00h (f) Operation: 00h (W)
1Z 1Z
Status Affected: Z Status Affected: Z
Encoding: 00 0001 1fff ffff
Encoding: 00 0001 0xxx xxxx
Description: The contents of register f are cleared
Description: W register is cleared. Zero bit (Z) is
and the Z bit is set.
set.
Words: 1 Words: 1
Cycles: 1 Cycles: 1
Decode No-Opera Process Write to
register data register f
tion data W
f
Example CLRF FLAG_REG Example CLRW

FLAG_REG = 0x5A W = 0x5A
FLAG_REG = 0x00 W = 0x00
Z = 1
Z = 1
CLRWDT Clear Watchdog Timer

Syntax: [ label ] CLRWDT
Operands: None
Operation: 00h WDT
0 WDT prescaler,
1 TO
1 PD
Status Affected: TO, PD
Encoding: 00 0000 0110 0100
Description: CLRWDT instruction resets the Watch-
dog Timer. It also resets the prescaler
of the WDT. Status bits TO and PD are
set.
Words: 1
Cycles: 1
Decode No-Opera Process Clear
tion data WDT
Counter
Example CLRWDT
Before Instruction
WDT counter = ?
After Instruction
WDT counter = 0x00
WDT prescaler= 0
TO = 1
PD = 1

PIC16F8X
COMF Complement f DECFSZ Decrement f, Skip if 0

Syntax: [ label ] COMF f,d Syntax: [ label ] DECFSZ f,d
d [0,1] d [0,1]
Operation: (f) (destination) Operation: (f) - 1 (destination);
Status Affected: Z skip if result = 0
Encoding: 00 1001 dfff ffff Status Affected: None
Description: The contents of register f are comple- Encoding: 00 1011 dfff ffff
mented. If d is 0 the result is stored in
W. If d is 1 the result is stored back in Description: The contents of register f are decre-
register f. mented. If d is 0 the result is placed in the
W register. If d is 1 the result is placed
Words: 1 back in register f.
If the result is 1, the next instruction, is
Cycles: 1 executed. If the result is 0, then a NOP is
executed instead making it a 2TCY instruc-
Q Cycle Activity: Q1 Q2 Q3 Q4 tion.
Decode Read Process Write to Words: 1
register data destination
f Cycles: 1(2)
Example COMF REG1,0 Decode Read Process Write to
register f data destination
Before Instruction
REG1 = 0x13
If Skip: (2nd Cycle)
After Instruction
REG1 = 0x13 Q1 Q2 Q3 Q4
W = 0xEC No-Opera No-Operat No-Operati
No-Operat tion ion on
ion
DECF Decrement f
Syntax: [label] DECF f,d Example HERE DECFSZ CNT, 1
Operands: 0 f 127 GOTO LOOP
d [0,1] CONTINUE

Operation: (f) - 1 (destination)
Status Affected: Z Before Instruction

PC = address HERE
Encoding: 00 0011 dfff ffff After Instruction
Description: Decrement register f. If d is 0 the CNT = CNT - 1
result is stored in the W register. If d is if CNT = 0,
1 the result is stored back in register f. PC = address CONTINUE
Words: 1 if CNT 0,
PC = address HERE+1
Cycles: 1
Decode Read Process Write to
f
Example DECF CNT, 1

Before Instruction
CNT = 0x01
Z = 0
After Instruction
CNT = 0x00
Z = 1

PIC16F8X
GOTO Unconditional Branch INCF Increment f

Syntax: [ label ] GOTO k Syntax: [ label ] INCF f,d
Operands: 0 k 2047 Operands: 0 f 127
d [0,1]
Operation: k PC<10:0>
PCLATH<4:3> PC<12:11> Operation: (f) + 1 (destination)
Status Affected: None Status Affected: Z
Encoding: 10 1kkk kkkk kkkk Encoding: 00 1010 dfff ffff
Description: GOTO is an unconditional branch. The Description: The contents of register f are incre-
eleven bit immediate value is loaded mented. If d is 0 the result is placed in
into PC bits <10:0>. The upper bits of the W register. If d is 1 the result is
PC are loaded from PCLATH<4:3>.
GOTO is a two cycle instruction. placed back in register f.
Words: 1 Words: 1
Cycles: 2 Cycles: 1

1st Cycle Decode Read Process Write to
literal k data PC
f
2nd Cycle No-Operat No-Opera No-Operat
No-Operat ion tion ion
ion Example INCF CNT, 1
Before Instruction
Example GOTO THERE CNT = 0xFF
Z = 0
After Instruction
PC = Address THERE
After Instruction
CNT = 0x00
Z = 1

PIC16F8X
INCFSZ Increment f, Skip if 0 IORLW Inclusive OR Literal with W

Syntax: [ label ] INCFSZ f,d Syntax: [ label ] IORLW k
d [0,1] Operation: (W) .OR. k (W)
Operation: (f) + 1 (destination), Status Affected: Z
skip if result = 0
Encoding: 11 1000 kkkk kkkk
Description: The contents of the W register is
Encoding: 00 1111 dfff ffff ORed with the eight bit literal 'k'. The
Description: The contents of register f are incre- result is placed in the W register.
mented. If d is 0 the result is placed in
the W register. If d is 1 the result is Words: 1
placed back in register f.
If the result is 1, the next instruction is Cycles: 1
executed. If the result is 0, a NOP is exe-
cuted instead making it a 2TCY instruc- Q Cycle Activity: Q1 Q2 Q3 Q4
tion. Decode Read Process Write to
Words: 1 literal k data W
Cycles: 1(2)
Example IORLW 0x35
Before Instruction
W = 0x9A
After Instruction
If Skip: (2nd Cycle) W = 0xBF
Z = 1
Q1 Q2 Q3 Q4
No-Opera No-Opera No-Operati
No-Operat tion tion on
ion
Example HERE INCFSZ CNT, 1

GOTO LOOP
CONTINUE

Before Instruction
PC = address HERE
After Instruction
CNT = CNT + 1
if CNT= 0,
PC = address CONTINUE
if CNT 0,
PC = address HERE +1

PIC16F8X
IORWF Inclusive OR W with f MOVLW Move Literal to W

Syntax: [ label ] IORWF f,d Syntax: [ label ] MOVLW k
d [0,1]
Operation: k (W)
Operation: (W) .OR. (f) (destination)
Status Affected: Z
Encoding: 11 00xx kkkk kkkk
Encoding: 00 0100 dfff ffff
Description: The eight bit literal k is loaded into W
Description: Inclusive OR the W register with regis- register. The dont cares will assemble
ter f. If d is 0 the result is placed in the
as 0s.
W register. If d is 1 the result is placed
back in register f. Words: 1
Words: 1 Cycles: 1
Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4
Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to
literal k data W
f
Example MOVLW 0x5A
After Instruction
Example IORWF RESULT, 0
W = 0x5A
Before Instruction
RESULT = 0x13
W = 0x91
After Instruction
RESULT = 0x13
W = 0x93
Z = 1
MOVWF Move W to f
MOVF Move f
Syntax: [ label ] MOVWF f
Syntax: [ label ] MOVF f,d
Operands: 0 f 127
Operands: 0 f 127
d [0,1] Operation: (W) (f)
Operation: (f) (destination) Status Affected: None
Status Affected: Z Encoding: 00 0000 1fff ffff
Encoding: 00 1000 dfff ffff Description: Move data from W register to register
'f'.
Description: The contents of register f is moved to a
destination dependant upon the status Words: 1
of d. If d = 0, destination is W register. If
Cycles: 1
d = 1, the destination is file register f
itself. d = 1 is useful to test a file regis- Q Cycle Activity: Q1 Q2 Q3 Q4
ter since status flag Z is affected. Decode Read Process Write
Words: 1 register data register f
f
Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4 Example MOVWF OPTION_REG
Decode Read Process Write to Before Instruction
OPTION = 0xFF
f
W = 0x4F
After Instruction
Example MOVF FSR, 0 OPTION = 0x4F
After Instruction W = 0x4F
W = value in FSR register
Z =1

PIC16F8X
NOP No Operation RETFIE Return from Interrupt

Syntax: [ label ] NOP Syntax: [ label ] RETFIE
Operands: None Operands: None
Operation: No operation Operation: TOS PC,
Status Affected: None 1 GIE
Encoding: 00 0000 0xx0 0000 Status Affected: None
Description: No operation. Encoding: 00 0000 0000 1001
Words: 1 Description: Return from Interrupt. Stack is POPed

and Top of Stack (TOS) is loaded in the
Cycles: 1 PC. Interrupts are enabled by setting
Global Interrupt Enable bit, GIE
(INTCON<7>). This is a two cycle
Decode No-Opera No-Opera No-Operat instruction.
tion tion ion
Words: 1
Example NOP Cycles: 2
1st Cycle Decode No-Opera Set the Pop from
tion GIE bit the Stack
2nd Cycle No-Opera No-Opera No-Operat

No-Operat tion tion ion
ion
Example RETFIE
After Interrupt
PC = TOS
GIE = 1
OPTION Load Option Register
Syntax: [ label ] OPTION
Operands: None
Operation: (W) OPTION
Encoding: 00 0000 0110 0010
Description: The contents of the W register are
loaded in the OPTION register. This
instruction is supported for code com-
patibility with PIC16C5X products.
Since OPTION is a readable/writable
register, the user can directly address
it.
Words: 1
Cycles: 1
Example
To maintain upward compatibility
with future PIC16CXX products,
do not use this instruction.

PIC16F8X
RETLW Return with Literal in W RETURN Return from Subroutine

Syntax: [ label ] RETLW k Syntax: [ label ] RETURN
Operands: 0 k 255 Operands: None
Operation: k (W); Operation: TOS PC
TOS PC Status Affected: None
Status Affected: None Encoding: 00 0000 0000 1000
Encoding: 11 01xx kkkk kkkk
Description: Return from subroutine. The stack is
Description: The W register is loaded with the eight POPed and the top of the stack (TOS)
bit literal k. The program counter is is loaded into the program counter. This
loaded from the top of the stack (the is a two cycle instruction.
return address). This is a two cycle Words: 1
instruction.
Cycles: 2
Words: 1
Cycles: 2
1st Cycle Decode No-Opera No-Opera Pop from
Q Cycle Activity: Q1 Q2 Q3 Q4 tion tion the Stack
1st Cycle Decode Read No-Opera Write to 2nd Cycle No-Opera No-Opera No-Opera
literal k tion W, Pop No-Operat tion tion tion
from the ion
Stack
2nd Cycle No-Opera No-Opera No-Operat

Example RETURN
No-Operat tion tion ion
ion After Interrupt
PC = TOS
Example CALL TABLE ;W contains table
;offset value
;W now has table value

TABLE ADDWF PC ;W = offset
RETLW k1 ;Begin table
RETLW k2 ;

RETLW kn ; End of table
Before Instruction
W = 0x07
After Instruction
W = value of k8

PIC16F8X
RLF Rotate Left f through Carry RRF Rotate Right f through Carry
Syntax: [ label ] RLF f,d Syntax: [ label ] RRF f,d
d [0,1] d [0,1]
Operation: See description below Operation: See description below
Status Affected: C Status Affected: C
Encoding: 00 1101 dfff ffff Encoding: 00 1100 dfff ffff
Description: The contents of register f are rotated Description: The contents of register f are rotated
one bit to the left through the Carry one bit to the right through the Carry
Flag. If d is 0 the result is placed in the Flag. If d is 0 the result is placed in the
W register. If d is 1 the result is stored W register. If d is 1 the result is placed
back in register f. back in register f.
C Register f C Register f
Words: 1 Words: 1
Cycles: 1 Cycles: 1
register data destination register data destination
f f
Example RLF REG1,0 Example RRF REG1,0

REG1 = 1110 0110 REG1 = 1110 0110
C = 0 C = 0
REG1 = 1110 0110 REG1 = 1110 0110
W = 1100 1100 W = 0111 0011
C = 1 C = 0

PIC16F8X
SLEEP SUBLW Subtract W from Literal
Syntax: [ label ] SLEEP Syntax: [ label ] SUBLW k

Operands: None Operands: 0 k 255
Operation: 00h WDT, Operation: k - (W) (W)
0 WDT prescaler, Status Affected: C, DC, Z
1 TO,
Encoding: 11 110x kkkk kkkk
0 PD
Description: The W register is subtracted (2s comple-
Status Affected: TO, PD ment method) from the eight bit literal 'k'.
Encoding: 00 0000 0110 0011 The result is placed in the W register.
Description: The power-down status bit, PD is Words: 1
cleared. Time-out status bit, TO is
Cycles: 1
set. Watchdog Timer and its pres-
caler are cleared. Q Cycle Activity: Q1 Q2 Q3 Q4
The processor is put into SLEEP Decode Read Process Write to W
mode with the oscillator stopped. See literal k data
Section 14.8 for more details.
Words: 1 Example 1: SUBLW 0x02
Cycles: 1 Before Instruction
Q Cycle Activity: Q1 Q2 Q3 Q4 W = 1
Decode No-Opera No-Opera Go to C = ?
tion tion Sleep Z = ?
After Instruction
Example: SLEEP W = 1
C = 1; result is positive
Z = 0
Example 2: Before Instruction
W = 2
C = ?
Z = ?
After Instruction
W = 0
C = 1; result is zero
Z = 1
Example 3: Before Instruction
W = 3
C = ?
Z = ?
After Instruction
W = 0xFF
C = 0; result is negative
Z = 0

PIC16F8X
SUBWF Subtract W from f SWAPF Swap Nibbles in f

Syntax: [ label ] SUBWF f,d Syntax: [ label ] SWAPF f,d
d [0,1] d [0,1]
Operation: (f) - (W) (destination) Operation: (f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
Status Affected: C, DC, Z
Description: Subtract (2s complement method) W reg-
ister from register 'f'. If 'd' is 0 the result is Description: The upper and lower nibbles of register
stored in the W register. If 'd' is 1 the 'f' are exchanged. If 'd' is 0 the result is
result is stored back in register 'f'. placed in W register. If 'd' is 1 the result
is placed in register 'f'.
Words: 1
Words: 1
Cycles: 1
Cycles: 1
register f data destination Decode Read Process Write to
Example 1: SUBWF REG1,1

Example SWAPF REG, 0
Before Instruction
REG1 = 3
Before Instruction
W = 2 REG1 = 0xA5
C = ?
Z = ?
After Instruction
REG1 = 0xA5
After Instruction
W = 0x5A
REG1 = 1
W = 2
C = 1; result is positive
Z = 0
Example 2: Before Instruction TRIS Load TRIS Register
REG1 = 2 Syntax: [label] TRIS f
W = 2
Operands: 5f7
C = ?
Z = ? Operation: (W) TRIS register f;
After Instruction Status Affected: None
REG1 = 0 Encoding: 00 0000 0110 0fff
W = 2 Description: The instruction is supported for code
C = 1; result is zero compatibility with the PIC16C5X prod-
Z = 1 ucts. Since TRIS registers are read-
Example 3: Before Instruction able and writable, the user can directly
address them.
REG1 = 1
W = 2
Words: 1
C = ? Cycles: 1
Z = ? Example
After Instruction To maintain upward compatibility
REG1 = 0xFF with future PIC16CXX products,
W = 2 do not use this instruction.
C = 0; result is negative
Z = 0

PIC16F8X
XORLW Exclusive OR Literal with W XORWF Exclusive OR W with f
Syntax: [label] XORLW k Syntax: [label] XORWF f,d
Operands: 0 k 255 Operands: 0 f 127

d [0,1]
Operation: (W) .XOR. k (W)
Operation: (W) .XOR. (f) (destination)
Status Affected: Z
Status Affected: Z
Encoding: 11 1010 kkkk kkkk
Description: The contents of the W register are
XORed with the eight bit literal 'k'. Description: Exclusive OR the contents of the W
The result is placed in the W regis- register with register 'f'. If 'd' is 0 the
ter. result is stored in the W register. If 'd' is
1 the result is stored back in register 'f'.
Words: 1
Words: 1
Cycles: 1
Cycles: 1
literal k data W Decode Read Process Write to
f
Example: XORLW 0xAF
Before Instruction Example XORWF REG 1
W = 0xB5 Before Instruction
After Instruction REG = 0xAF
W = 0x1A W = 0xB5
After Instruction
REG = 0x1A
W = 0xB5

PIC16F8X
10.0 DEVELOPMENT SUPPORT 10.3 ICEPIC: Low-Cost PICmicro
In-Circuit Emulator
10.1 Development Tools
ICEPIC is a low-cost in-circuit emulator solution for the
The PICmicr microcontrollers are supported with a Microchip PIC12CXXX, PIC16C5X and PIC16CXXX
full range of hardware and software development tools: families of 8-bit OTP microcontrollers.
PICMASTER/PICMASTER CE Real-Time ICEPIC is designed to operate on PC-compatible
In-Circuit Emulator machines ranging from 286-AT through Pentium
ICEPIC Low-Cost PIC16C5X and PIC16CXXX based machines under Windows 3.x environment.
In-Circuit Emulator ICEPIC features real time, non-intrusive emulation.
PRO MATE II Universal Programmer
10.4 PRO MATE II: Universal Programmer
PICSTART Plus Entry-Level Prototype
Programmer The PRO MATE II Universal Programmer is a full-fea-
PICDEM-1 Low-Cost Demonstration Board tured programmer capable of operating in stand-alone
PICDEM-2 Low-Cost Demonstration Board mode as well as PC-hosted mode. PRO MATE II is CE
compliant.
PICDEM-3 Low-Cost Demonstration Board
MPASM Assembler The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
MPLAB SIM Software Simulator
at VDD min and VDD max for maximum reliability. It has
MPLAB-C17 (C Compiler) an LCD display for displaying error messages, keys to
Fuzzy Logic Development System enter commands and a modular detachable socket
(fuzzyTECHMP) assembly to support various package types. In stand-
alone mode the PRO MATE II can read, verify or pro-
10.2 PICMASTER: High Performance gram PIC12CXXX, PIC14C000, PIC16C5X,
Universal In-Circuit Emulator with PIC16CXXX and PIC17CXX devices. It can also set
MPLAB IDE configuration and code-protect bits in this mode.
The PICMASTER Universal In-Circuit Emulator is 10.5 PICSTART Plus Entry Level
intended to provide the product development engineer Development System
with a complete microcontroller design tool set for all
microcontrollers in the PIC14C000, PIC12CXXX, The PICSTART programmer is an easy-to-use,
PIC16C5X, PIC16CXXX and PIC17CXX families. low-cost prototype programmer. It connects to the PC
PICMASTER is supplied with the MPLAB Integrated via one of the COM (RS-232) ports. MPLAB Integrated
Development Environment (IDE), which allows editing, Development Environment software makes using the
make and download, and source debugging from a programmer simple and efficient. PICSTART Plus is not
single environment. recommended for production programming.
Interchangeable target probes allow the system to be PICSTART Plus supports all PIC12CXXX, PIC14C000,
easily reconfigured for emulation of different proces- PIC16C5X, PIC16CXXX and PIC17CXX devices with
sors. The universal architecture of the PICMASTER up to 40 pins. Larger pin count devices such as the
allows expansion to support all new Microchip micro- PIC16C923, PIC16C924 and PIC17C756 may be sup-
controllers. ported with an adapter socket. PICSTART Plus is CE
The PICMASTER Emulator System has been designed compliant.
as a real-time emulation system with advanced fea-
tures that are generally found on more expensive devel-
opment tools. The PC compatible 386 (and higher)
machine platform and Microsoft Windows 3.x environ-
ment were chosen to best make these features avail-
able to you, the end user.
A CE compliant version of PICMASTER is available for
European Union (EU) countries.

PIC16F8X
10.6 PICDEM-1 Low-Cost PICmicro an RS-232 interface, push-button switches, a potenti-
Demonstration Board ometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
The PICDEM-1 is a simple board which demonstrates module and a keypad. Also provided on the PICDEM-3
the capabilities of several of Microchips microcontrol- board is an LCD panel, with 4 commons and 12 seg-
lers. The microcontrollers supported are: PIC16C5X ments, that is capable of displaying time, temperature
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, and day of the week. The PICDEM-3 provides an addi-
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and tional RS-232 interface and Windows 3.1 software for
PIC17C44. All necessary hardware and software is showing the demultiplexed LCD signals on a PC. A sim-
included to run basic demo programs. The users can ple serial interface allows the user to construct a hard-
program the sample microcontrollers provided with ware demultiplexer for the LCD signals.
the PICDEM-1 board, on a PRO MATE II or
PICSTART-Plus programmer, and easily test firm- 10.9 MPLAB Integrated Development
ware. The user can also connect the PICDEM-1 Environment Software
board to the PICMASTER emulator and download
the firmware to the emulator for testing. Additional pro- The MPLAB IDE Software brings an ease of software
totype area is available for the user to build some addi- development previously unseen in the 8-bit microcon-
tional hardware and connect it to the microcontroller troller market. MPLAB is a windows based application
socket(s). Some of the features include an RS-232 which contains:
interface, a potentiometer for simulated analog input, A full featured editor
push-button switches and eight LEDs connected to Three operating modes
PORTB. - editor
- emulator
10.7 PICDEM-2 Low-Cost PIC16CXX - simulator
Demonstration Board A project manager
Customizable tool bar and key mapping
The PICDEM-2 is a simple demonstration board that
A status bar with project information
supports the PIC16C62, PIC16C64, PIC16C65,
Extensive on-line help
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to MPLAB allows you to:
run the basic demonstration programs. The user Edit your source files (either assembly or C)
can program the sample microcontrollers provided One touch assemble (or compile) and download
with the PICDEM-2 board, on a PRO MATE II pro- to PICmicro tools (automatically updates all
grammer or PICSTART-Plus, and easily test firmware. project information)
The PICMASTER emulator may also be used with the Debug using:
PICDEM-2 board to test firmware. Additional prototype - source files
area has been provided to the user for adding addi- - absolute listing file
tional hardware and connecting it to the microcontroller Transfer data dynamically via DDE (soon to be
socket(s). Some of the features include a RS-232 inter- replaced by OLE)
face, push-button switches, a potentiometer for simu- Run up to four emulators on the same PC
lated analog input, a Serial EEPROM to demonstrate
The ability to use MPLAB with Microchips simulator
usage of the I2C bus and separate headers for connec-
allows a consistent platform and the ability to easily
tion to an LCD module and a keypad.
switch from the low cost simulator to the full featured
10.8 PICDEM-3 Low-Cost PIC16CXXX emulator with minimal retraining due to development
Demonstration Board tools.
The PICDEM-3 is a simple demonstration board that 10.10 Assembler (MPASM)

supports the PIC16C923 and PIC16C924 in the PLCC
The MPASM Universal Macro Assembler is a
package. It will also support future 44-pin PLCC
PC-hosted symbolic assembler. It supports all micro-
microcontrollers with a LCD Module. All the neces-
controller series including the PIC12C5XX, PIC14000,
sary hardware and software is included to run the
PIC16C5X, PIC16CXXX, and PIC17CXX families.
basic demonstration programs. The user can pro-
gram the sample microcontrollers provided with MPASM offers full featured Macro capabilities, condi-
the PICDEM-3 board, on a PRO MATE II program- tional assembly, and several source and listing formats.
mer or PICSTART Plus with an adapter socket, and It generates various object code formats to support
easily test firmware. The PICMASTER emulator may Microchip's development tools as well as third party
also be used with the PICDEM-3 board to test firm- programmers.
ware. Additional prototype area has been provided to MPASM allows full symbolic debugging from
the user for adding hardware and connecting it to the PICMASTER, Microchips Universal Emulator System.
microcontroller socket(s). Some of the features include

PIC16F8X
MPASM has the following features to assist in develop- 10.14 MP-DriveWay Application Code
ing software for specific use applications. Generator
Provides translation of Assembler source code to
MP-DriveWay is an easy-to-use Windows-based Appli-
object code for all Microchip microcontrollers.
cation Code Generator. With MP-DriveWay you can
Macro assembly capability. visually configure all the peripherals in a PICmicro
Produces all the files (Object, Listing, Symbol, device and, with a click of the mouse, generate all the
and special) required for symbolic debug with initialization and many functional code modules in C
Microchips emulator systems. language. The output is fully compatible with Micro-
Supports Hex (default), Decimal and Octal source chips MPLAB-C C compiler. The code produced is
and listing formats. highly modular and allows easy integration of your own
MPASM provides a rich directive language to support code. MP-DriveWay is intelligent enough to maintain
programming of the PICmicro. Directives are helpful in your code through subsequent code generation.
making the development of your assemble source code
10.15 SEEVAL Evaluation and
shorter and more maintainable.
Programming System
10.11 Software Simulator (MPLAB-SIM)
The SEEVAL SEEPROM Designers Kit supports all
The MPLAB-SIM Software Simulator allows code Microchip 2-wire and 3-wire Serial EEPROMs. The kit
development in a PC host environment. It allows the includes everything necessary to read, write, erase or
user to simulate the PICmicro series microcontrollers program special features of any Microchip SEEPROM
on an instruction level. On any given instruction, the product including Smart Serials and secure serials.
user may examine or modify any of the data areas or The Total Endurance Disk is included to aid in
provide external stimulus to any of the pins. The trade-off analysis and reliability calculations. The total
input/output radix can be set by the user and the exe- kit can significantly reduce time-to-market and result in
cution can be performed in; single step, execute until an optimized system.
break, or in a trace mode.
10.16 KEELOQ Evaluation and
MPLAB-SIM fully supports symbolic debugging using Programming Tools
MPLAB-C and MPASM. The Software Simulator offers
the low cost flexibility to develop and debug code out- KEELOQ evaluation and programming tools support
side of the laboratory environment making it an excel- Microchips HCS Secure Data Products. The HCS eval-
lent multi-project software development tool. uation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a pro-
10.12 C Compiler (MPLAB-C17) gramming interface to program test transmitters.
The MPLAB-C Code Development System is a
complete C compiler and integrated development
environment for Microchips PIC17CXXX family of
microcontrollers. The compiler provides powerful inte-
gration capabilities and ease of use not found with
other compilers.
For easier source level debugging, the compiler pro-
vides symbol information that is compatible with the
MPLAB IDE memory display.
10.13 Fuzzy Logic Development System

(fuzzyTECH-MP)
fuzzyTECH-MP fuzzy logic development tool is avail-
able in two versions - a low cost introductory version,
MP Explorer, for designers to gain a comprehensive
working knowledge of fuzzy logic system design; and a
full-featured version, fuzzyTECH-MP, Edition for imple-
menting more complex systems.
Both versions include Microchips fuzzyLAB demon-
stration board for hands-on experience with fuzzy logic
systems implementation.

DS30430C-page 74
TABLE 10-1:
PIC16F8X
24CXX HCS200
PIC12C5XX PIC14000 PIC16C5X PIC16CXXX PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X PIC17C75X 25CXX HCS300
93CXX HCS301
PICMASTER/
Emulator Products
PICMASTER-CE
In-Circuit Emulator
DEVELOPMENT TOOLS FROM MICROCHIP

ICEPIC Low-Cost
In-Circuit Emulator

MPLAB
Integrated
Development
Environment
MPLAB C17

Software Tools
Compiler
fuzzyTECH-MP
Explorer/Edition
Fuzzy Logic
Dev. Tool
MP-DriveWay
Applications
Code Generator
Total Endurance
Software Model
PICSTARTPlus
Low-Cost

Programmers
Universal Dev. Kit

PRO MATE II
Universal
Programmer
KEELOQ
Programmer
SEEVAL
1998 Microchip Technology Inc.
Designers Kit
Demo Boards
PICDEM-1
PICDEM-2
PICDEM-3
KEELOQ
Evaluation Kit
PIC16F83/84 PIC16F8X
11.0 ELECTRICAL CHARACTERISTICS FOR PIC16F83 AND PIC16F84
Absolute Maximum Ratings
Ambient temperature under bias.............................................................................................................-55C to +125C
Storage temperature .............................................................................................................................. -65C to +150C
Voltage on VDD with respect to VSS ........................................................................................................... -0.3 to +7.5V
Voltage on MCLR with respect to VSS(2) .......................................................................................................-0.3 to +14V
Voltage on any pin with respect to VSS (except VDD and MCLR).................................................... -0.6V to (VDD + 0.6V)
Total power dissipation(1) .....................................................................................................................................800 mW
Maximum current out of VSS pin ...........................................................................................................................150 mA
Maximum current into VDD pin ..............................................................................................................................100 mA
Input clamp current, IIK (VI < 0 or VI > VDD)..................................................................................................................... 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ............................................................................................................. 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................20 mA
Maximum current sunk by PORTA ..........................................................................................................................80 mA
Maximum current sourced by PORTA .....................................................................................................................50 mA
Maximum current sunk by PORTB........................................................................................................................150 mA
Maximum current sourced by PORTB...................................................................................................................100 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL)
Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus,
a series resistor of 50-100 should be used when applying a low level to the MCLR pin rather than pulling
this pin directly to VSS.
NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

PIC16F8X PIC16F83/84
TABLE 11-1 CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS

AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
PIC16F84-04 PIC16F84-10 PIC16LF84-04

OSC
PIC16F83-04 PIC16F83-10 PIC16LF83-04
RC VDD: 4.0V to 6.0V VDD: 4.5V to 5.5V VDD: 2.0V to 6.0V
IDD: 4.5 mA max. at 5.5V IDD: 1.8 mA typ. at 5.5V IDD: 4.5 mA max. at 5.5V
IPD: 14 A max. at 4V WDT dis IPD: 1.0 A typ. at 5.5V WDT dis IPD: 7.0 A max. at 2V WDT dis
Freq: 4.0 MHz max. Freq: 4..0 MHz max. Freq: 2.0 MHz max.
XT VDD: 4.0V to 6.0V VDD: 4.5V to 5.5V VDD: 2.0V to 6.0V
IPD: 14 A max. at 4V WDT dis IPD: 1.0 A typ. at 5.5V WDT dis IPD: 7.0 A max. at 2V WDT dis
Freq: 4.0 MHz max. Freq: 4.0 MHz max. Freq: 2.0 MHz max.
HS VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V
IDD: 4.5 mA typ. at 5.5V IDD: 10 mA max. at 5.5V typ.
Do not use in HS mode
IPD: 1.0 A typ. at 4.5V WDT dis IPD: 1.0 A typ. at 4.5V WDT dis
Freq: 4.0 MHz max. Freq: 10 MHz max.
LP VDD: 4.0V to 6.0V VDD: 2.0V to 6.0V
IDD: 48 A typ. at 32 kHz, 2.0V IDD: 45 A max. at 32 kHz, 2.0V
Do not use in LP mode
IPD: 0.6 A typ. at 3.0V WDT dis IPD: 7 A max. at 2.0V WDT dis
Freq: 200 kHz max. Freq: 200 kHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifica-
tions. It is recommended that the user select the device type that ensures the specifications required.

11.1 DC CHARACTERISTICS: PIC16F84, PIC16F83 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)

DC Characteristics
Operating temperature 0C TA +70C (commercial)
Power Supply Pins
-40C TA +85C (industrial)
Parameter Sym Characteristic Min Typ Max Units Conditions
No.
D001 VDD Supply Voltage 4.0 6.0 V XT, RC and LP osc configuration
D001A 4.5 5.5 V HS osc configuration
D002 VDR RAM Data Retention 1.5* V Device in SLEEP mode
Voltage(1)
D003 VPOR VDD start voltage to VSS V See section on Power-on Reset for details
ensure internal
Power-on Reset signal
D004 SVDD VDD rise rate to ensure 0.05* V/ms See section on Power-on Reset for details
internal Power-on
Reset signal
IDD Supply Current(2) RC and XT osc configuration(4)
D010 1.8 4.5 mA FOSC = 4.0 MHz, VDD = 5.5V
D010A 7.3 10 mA FOSC = 4.0 MHz, VDD = 5.5V
(During Flash programming)
HS osc configuration (PIC16F84-10)
D013 5 10 mA FOSC = 10 MHz, VDD = 5.5V
D020 IPD Power-down Current(3) 7.0 28 A VDD = 4.0V, WDT enabled, industrial
D021 1.0 14 A VDD = 4.0V, WDT disabled, commercial
D021A 1.0 16 A VDD = 4.0V, WDT disabled, industrial
* These parameters are characterized but not tested.
Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1=external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, T0CKI = VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.

11.2 DC CHARACTERISTICS: PIC16LF84, PIC16LF83 (Commercial, Industrial)

DC Characteristics
Power Supply Pins
No.
D001 VDD Supply Voltage 2.0 6.0 V XT, RC, and LP osc configuration
Voltage(1)
ensure internal
internal Power-on
Reset signal
D010 1 4 mA FOSC = 2.0 MHz, VDD = 5.5V
(During Flash programming)
LP osc configuration
D014 15 45 A FOSC = 32 kHz, VDD = 2.0V,
WDT disabled
D021 0.4 7.0 A VDD = 2.0V, WDT disabled, commercial
D021A 0.4 9.0 A VDD = 2.0V, WDT disabled, industrial
and are not tested.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be
estimated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.

PIC16LF84, PIC16LF83 (Commercial, Industrial)
DC Characteristics Operating temperature 0C TA +70C (commercial)
All Pins Except -40C TA +85C (industrial)
Power Supply Pins Operating voltage VDD range as described in DC spec
Section 11.1 and Section 11.2.
Parame-
ter
No. Sym Characteristic Min Typ Max Units Conditions
Input Low Voltage
VIL I/O ports
D030 with TTL buffer VSS 0.8 V 4.5 V VDD 5.5 V(4)
D030A VSS 0.16VDD V entire range(4)
D031 with Schmitt Trigger buffer VSS 0.2VDD V entire range
D032 MCLR, RA4/T0CKI Vss 0.2VDD V
D033 OSC1 (XT, HS and LP modes)(1) Vss 0.3VDD V
D034 OSC1 (RC mode) Vss 0.1VDD V
Input High Voltage
VIH I/O ports
D040 with TTL buffer 2.4 VDD V 4.5 V VDD 5.5V(4)
D040A 0.48VDD VDD V entire range(4)
D041 with Schmitt Trigger buffer 0.45VDD VDD entire range
D042 MCLR, RA4/T0CKI, OSC1 0.85 VDD V
(RC mode) VDD
D043 OSC1 (XT, HS and LP modes)(1) 0.7 VDD VDD V
D050 VHYS Hysteresis of TBD V
Schmitt Trigger inputs
D070 IPURB PORTB weak pull-up current 50* 250* 400* A VDD = 5.0V, VPIN = VSS
Input Leakage Current(2,3)
D060 IIL I/O ports 1 A Vss VPIN VDD,
Pin at hi-impedance
D061 MCLR, RA4/T0CKI 5 A Vss VPIN VDD
D063 OSC1 5 A Vss VPIN VDD, XT, HS
and LP osc configuration
Output Low Voltage
D080 VOL I/O ports 0.6 V IOL = 8.5 mA, VDD = 4.5V
D083 OSC2/CLKOUT 0.6 V IOL = 1.6 mA, VDD = 4.5V
Output High Voltage
D090 VOH I/O ports(3) VDD-0.7 V IOH = -3.0 mA, VDD = 4.5V
D092 OSC2/CLKOUT VDD-0.7 V IOH = -1.3 mA, VDD = 4.5V
Data in Typ column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. Do not drive the PIC16F8X with an
external clock while the device is in RC mode, or chip damage may result.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified lev-
els represent normal operating conditions. Higher leakage current may be measured at different input volt-
ages.
3: Negative current is defined as coming out of the pin.
4: The user may choose the better of the two specs.


PIC16LF84, PIC16F83 (Commercial, Industrial)

No.
Capacitive Loading Specs
on Output Pins
D100 COSC2 OSC2 pin 15 pF In XT, HS and LP modes
when external clock is used to
drive OSC1.
D101 CIO All I/O pins and OSC2 50 pF
(RC mode)
Data EEPROM Memory
D120 ED Endurance 1M 10M E/W 25C at 5V
D121 VDRW VDD for read/write VMIN 6.0 V VMIN = Minimum operating
voltage
D122 TDEW Erase/Write cycle time 10 20* ms
Program Flash Memory
D130 EP Endurance 100 1000 E/W
D131 VPR VDD for read VMIN 6.0 V VMIN = Minimum operating
voltage
D132 VPEW VDD for erase/write 4.5 5.5 V
D133 TPEW Erase/Write cycle time 10 ms
and are not tested.

TABLE 11-2 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created fol-
lowing one of the following formats:
1. TppS2ppS
2. TppS
T
F Frequency T Time
Lowercase symbols (pp) and their meanings:
pp
2 to os,osc OSC1
ck CLKOUT ost oscillator start-up timer
cy cycle time pwrt power-up timer
io I/O port rbt RBx pins
inp INT pin t0 T0CKI
mc MCLR wdt watchdog timer
Uppercase symbols and their meanings:
S
F Fall P Period
H High R Rise
I Invalid (Hi-impedance) V Valid
L Low Z High Impedance
FIGURE 11-1: PARAMETER MEASUREMENT INFORMATION

All timings are measure between high and low mea-
surement points as indicated in the figures below.
0.7 VDD XTAL

0.8 VDD RC (High) 0.9 VDD (High)
0.3 VDD XTAL 0.1 VDD (Low)
0.15 VDD RC (Low)
OSC1 Measurement Points I/O Port Measurement Points
FIGURE 11-2: LOAD CONDITIONS
Load Condition 1 Load Condition 2
VDD/2
RL Pin CL
CL VSS
Pin
VSS
RL = 464
CL = 50 pF for all pins except OSC2.
15 pF for OSC2 output.

11.5 Timing Diagrams and Specifications
FIGURE 11-3: EXTERNAL CLOCK TIMING

Q4 Q1 Q2 Q3 Q4 Q1
OSC1
1 3 3 4 4
2
CLKOUT
TABLE 11-3 EXTERNAL CLOCK TIMING REQUIREMENTS

Parameter
FOSC External CLKIN Frequency(1) DC 2 MHz XT, RC osc PIC16LF8X-04

DC 4 MHz XT, RC osc PIC16F8X-04
DC 10 MHz HS osc PIC16F8X-10
DC 200 kHz LP osc PIC16LF8X-04
Oscillator Frequency(1) DC 2 MHz RC osc PIC16LF8X-04
DC 4 MHz RC osc PIC16F8X-04
0.1 2 MHz XT osc PIC16LF8X-04
0.1 4 MHz XT osc PIC16F8X-04
1.0 10 MHz HS osc PIC16F8X-10
DC 200 kHz LP osc PIC16LF8X-04
1 Tosc External CLKIN Period(1) 500 ns XT, RC osc PIC16LF8X-04
250 ns XT, RC osc PIC16F8X-04
100 ns HS osc PIC16F8X-10
5.0 s LP osc PIC16LF8X-04
Oscillator Period(1) 500 ns RC osc PIC16LF8X-04
250 ns RC osc PIC16F8X-04
500 10,000 ns XT osc PIC16LF8X-04
250 10,000 ns XT osc PIC16F8X-04
100 1,000 ns HS osc PIC16F8X-10
5.0 s LP osc PIC16LF8X-04
2 TCY Instruction Cycle Time(1) 0.4 4/Fosc DC s
3 TosL, Clock in (OSC1) High or Low 60 * ns XT osc PIC16LF8X-04
TosH Time 50 * ns XT osc PIC16F8X-04
2.0 * s LP osc PIC16LF8X-04
35 * ns HS osc PIC16F8X-10
4 TosR, Clock in (OSC1) Rise or Fall Time 25 * ns XT osc PIC16F8X-04
TosF 50 * ns LP osc PIC16LF8X-04
15 * ns HS osc PIC16F8X-10
* These parameters are characterized but no tested.
and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at "min." values with an external
clock applied to the OSC1 pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.

FIGURE 11-4: CLKOUT AND I/O TIMING
Q4 Q1 Q2 Q3
OSC1
11
10
22
CLKOUT 23
13 12
19 18
14 16
I/O Pin
(input)
17 15
I/O Pin old value new value

(output)
20, 21
Note: All tests must be done with specified capacitive loads (Figure 11-2) 50 pF on I/O pins and CLKOUT.
TABLE 11-4 CLKOUT AND I/O TIMING REQUIREMENTS

Parameter
10 TosH2ckL OSC1 to CLKOUT PIC16F8X 15 30 * ns Note 1
10A PIC16LF8X 15 120 * ns Note 1
11 TosH2ckH OSC1 to CLKOUT PIC16F8X 15 30 * ns Note 1
12 TckR CLKOUT rise time PIC16F8X 15 30 * ns Note 1
13 TckF CLKOUT fall time PIC16F8X 15 30 * ns Note 1
14 TckL2ioV CLKOUT to Port out valid 0.5TCY +20 * ns Note 1
15 TioV2ckH Port in valid before PIC16F8X 0.30TCY + 30 * ns Note 1
CLKOUT PIC16LF8X 0.30TCY + 80 * ns Note 1
16 TckH2ioI Port in hold after CLKOUT 0* ns Note 1
17 TosH2ioV OSC1 (Q1 cycle) to PIC16F8X 125 * ns
Port out valid PIC16LF8X 250 * ns
18 TosH2ioI OSC1 (Q2 cycle) to PIC16F8X 10 * ns
Port input invalid PIC16LF8X 10 * ns
(I/O in hold time)
19 TioV2osH Port input valid to PIC16F8X -75 * ns
OSC1 PIC16LF8X -175 * ns
(I/O in setup time)
20 TioR Port output rise time PIC16F8X 10 35 * ns
20A PIC16LF8X 10 70 * ns
21 TioF Port output fall time PIC16F8X 10 35 * ns
21A PIC16LF8X 10 70 * ns
22 Tinp INT pin high PIC16F8X 20 * ns
22A or low time PIC16LF8X 55 * ns
23 Trbp RB7:RB4 change INT PIC16F8X TOSC ns
23A high or low time PIC16LF8X TOSC ns
and are not tested.
By design
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.

FIGURE 11-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34 34
I/O Pins
TABLE 11-5 RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter
30 TmcL MCLR Pulse Width (low) 1000 * ns 2.0V VDD 6.0V
31 Twdt Watchdog Timer Time-out Period 7* 18 33 * ms VDD = 5.0V
(No Prescaler)
32 Tost Oscillation Start-up Timer Period 1024TOSC ms TOSC = OSC1 period
33 Tpwrt Power-up Timer Period 28 * 72 132 * ms VDD = 5.0V
34 TIOZ I/O Hi-impedance from MCLR Low 100 * ns
or reset
Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.

FIGURE 11-6: TIMER0 CLOCK TIMINGS
RA4/T0CKI
40 41
42
TABLE 11-6 TIMER0 CLOCK REQUIREMENTS

No.
40 Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 * ns
With Prescaler 50 * ns 2.0V VDD 3.0V
30 * ns 3.0V VDD 6.0V
41 Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 * ns
20 * ns 3.0V VDD 6.0V
42 Tt0P T0CKI Period TCY + 40 * ns N = prescale value
N (2, 4, ..., 256)
Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.

NOTES:

PIC16CR83/84 PIC16F8X
12.0 ELECTRICAL CHARACTERISTICS FOR PIC16CR83 AND PIC16CR84
Absolute Maximum Ratings
Ambient temperature under bias.............................................................................................................-55C to +125C
Storage temperature .............................................................................................................................. -65C to +150C
Voltage on VDD with respect to VSS ........................................................................................................... -0.3 to +7.5V
Voltage on MCLR with respect to VSS(2) .......................................................................................................-0.3 to +14V
Voltage on any pin with respect to VSS (except VDD and MCLR).................................................... -0.6V to (VDD + 0.6V)
Total power dissipation(1) .....................................................................................................................................800 mW
Maximum current out of VSS pin ...........................................................................................................................150 mA
Maximum current into VDD pin ..............................................................................................................................100 mA
Input clamp current, IIK (VI < 0 or VI > VDD)..................................................................................................................... 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ............................................................................................................. 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................20 mA
Maximum current sunk by PORTA ..........................................................................................................................80 mA
Maximum current sourced by PORTA .....................................................................................................................50 mA
Maximum current sunk by PORTB........................................................................................................................150 mA
Maximum current sourced by PORTB...................................................................................................................100 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL)
Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus,
a series resistor of 50-100 should be used when applying a low level to the MCLR pin rather than pulling
this pin directly to VSS.
NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

PIC16F8X PIC16CR83/84
TABLE 12-1 CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS

AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
PIC16CR84-04 PIC16CR84-10 PIC16LCR84-04

OSC
PIC16CR83-04 PIC16CR83-10 PIC16LCR83-04
RC VDD: 4.0V to 6.0V VDD: 4.5V to 5.5V VDD: 2.0V to 6.0V
IPD: 14 A max. at 4V WDT dis IPD: 1.0 A typ. at 5.5V WDT dis IPD: 5 A max. at 2V WDT dis
Freq: 4.0 MHz max. Freq: 4..0 MHz max. Freq: 2.0 MHz max.
XT VDD: 4.0V to 6.0V VDD: 4.5V to 5.5V VDD: 2.0V to 6.0V
IPD: 14 A max. at 4V WDT dis IPD: 1.0 A typ. at 5.5V WDT dis IPD: 5 A max. at 2V WDT dis
Freq: 4.0 MHz max. Freq: 4.0 MHz max. Freq: 2.0 MHz max.
HS VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V
IDD: 4.5 mA typ. at 5.5V IDD: 10 mA max. at 5.5V typ.
Do not use in HS mode
IPD: 1.0 A typ. at 4.5V WDT dis IPD: 1.0 A typ. at 4.5V WDT dis
Freq: 4.0 MHz max. Freq: 10 MHz max.
LP VDD: 4.0V to 6.0V VDD: 2.0V to 6.0V
IDD: 48 A typ. at 32 kHz, 2.0V IDD: 45 A max. at 32 kHz, 2.0V
Do not use in LP mode
IPD: 0.6 A typ. at 3.0V WDT dis IPD: 5 A max. at 2V WDT dis
Freq: 200 kHz max. Freq: 200 kHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifica-
tions. It is recommended that the user select the device type that ensures the specifications required.

12.1 DC CHARACTERISTICS: PIC16CR84, PIC16CR83 (Commercial, Industrial)

DC Characteristics
Power Supply Pins
No.
D001 VDD Supply Voltage 4.0 6.0 V XT, RC and LP osc configuration
D001A 4.5 5.5 V HS osc configuration
Voltage(1)
ensure internal
internal Power-on
Reset signal
D010 1.8 4.5 mA FOSC = 4.0 MHz, VDD = 5.5V
(During EEPROM programming)
HS OSC CONFIGURATION (PIC16CR84-10)
D013 5 10 mA FOSC = 10 MHz, VDD = 5.5V
D020 IPD Power-down Current (3) 7.0 28 A VDD = 4.0V, WDT enabled, industrial
D021 1.0 14 A VDD = 4.0V, WDT disabled, commercial
D021A 1.0 16 A VDD = 4.0V, WDT disabled, industrial
and are not tested.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.

12.2 DC CHARACTERISTICS: PIC16LCR84, PIC16LCR83 (Commercial, Industrial)

DC Characteristics
Power Supply Pins
No.
D001 VDD Supply Voltage 2.0 6.0 V XT, RC, and LP osc configuration
Voltage(1)
ensure internal
internal Power-on
Reset signal
D010 1 4 mA FOSC = 2.0 MHz, VDD = 5.5V
(During EEPROM programming)
LP osc configuration
D014 15 45 A FOSC = 32 kHz, VDD = 2.0V,
WDT disabled
D021 0.4 5.0 A VDD = 2.0V, WDT disabled, commercial
D021A 0.4 6.0 A VDD = 2.0V, WDT disabled, industrial
and are not tested.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be
estimated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.

PIC16LCR84, PIC16LCR83 (Commercial, Industrial)
Parame-
ter
Input Low Voltage
VIL I/O ports
D030 with TTL buffer VSS 0.8 V 4.5 V Vdd 5.5 V(4)
D030A VSS 0.16VDD V entire range(4)
D031 with Schmitt Trigger buffer VSS 0.2VDD V entire range
D032 MCLR, RA4/T0CKI Vss 0.2VDD V
D033 OSC1 (XT, HS and LP modes)(1) Vss 0.3VDD V
D034 OSC1 (RC mode) Vss 0.1VDD V
Input High Voltage
VIH I/O ports
D040 with TTL buffer 2.4 VDD V 4.5 V VDD 5.5V(4)
D040A 0.48VDD VDD V entire range(4)
D041 with Schmitt Trigger buffer 0.45VDD VDD entire range
D042 MCLR, RA4/T0CKI, OSC1 0.85 VDD V
(RC mode) VDD
D043 OSC1 (XT, HS and LP modes)(1) 0.7 VDD VDD V
D050 VHYS Hysteresis of TBD V
Schmitt Trigger inputs
D070 IPURB PORTB weak pull-up current 50* 250* 400* A VDD = 5.0V, VPIN = VSS
Input Leakage Current(2,3)

D060 IIL I/O ports 1 A Vss VPIN VDD,
Pin at hi-impedance
D061 MCLR, RA4/T0CKI 5 A Vss VPIN VDD
D063 OSC1 5 A Vss VPIN VDD, XT, HS
and LP osc configuration
Output Low Voltage
D080 VOL I/O ports 0.6 V IOL = 8.5 mA, VDD = 4.5V
D083 OSC2/CLKOUT 0.6 V IOL = 1.6 mA, VDD = 4.5V
Output High Voltage
D090 VOH I/O ports(3) VDD-0.7 V IOH = -3.0 mA, VDD = 4.5V
D092 OSC2/CLKOUT VDD-0.7 V IOH = -1.3 mA, VDD = 4.5V
and are not tested.
Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. Do not drive the PIC16CR8X with an
external clock while the device is in RC mode, or chip damage may result.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified lev-
els represent normal operating conditions. Higher leakage current may be measured at different input volt-
ages.
3: Negative current is defined as coming out of the pin.
4: The user may choose the better of the two specs.


PIC16LCR84, PIC16LCR83 (Commercial, Industrial)

No.
Capacitive Loading Specs
on Output Pins
D100 COSC2 OSC2 pin 15 pF In XT, HS and LP modes
when external clock is used to
drive OSC1.
D101 CIO All I/O pins and OSC2 50 pF
(RC mode)
Data EEPROM Memory
D120 ED Endurance 1M 10M E/W 25C at 5V
D121 VDRW VDD for read/write VMIN 6.0 V VMIN = Minimum operating
voltage
D122 TDEW Erase/Write cycle time 10 20* ms
and are not tested.

TABLE 12-2 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created fol-
lowing one of the following formats:
1. TppS2ppS
2. TppS
T
F Frequency T Time
Lowercase symbols (pp) and their meanings:
pp
2 to os,osc OSC1
ck CLKOUT ost oscillator start-up timer
cy cycle time pwrt power-up timer
io I/O port rbt RBx pins
inp INT pin t0 T0CKI
mc MCLR wdt watchdog timer
Uppercase symbols and their meanings:
S
F Fall P Period
H High R Rise
I Invalid (Hi-impedance) V Valid
L Low Z High Impedance
FIGURE 12-1: PARAMETER MEASUREMENT INFORMATION

All timings are measure between high and low mea-
surement points as indicated in the figures below.
0.7 VDD XTAL

0.8 VDD RC (High) 0.9 VDD (High)
0.3 VDD XTAL 0.1 VDD (Low)
0.15 VDD RC (Low)
OSC1 Measurement Points I/O Port Measurement Points
FIGURE 12-2: LOAD CONDITIONS
Load Condition 1 Load Condition 2
VDD/2
RL Pin CL
CL VSS
Pin
VSS
RL = 464
CL = 50 pF for all pins except OSC2.
15 pF for OSC2 output.

12.5 Timing Diagrams and Specifications
FIGURE 12-3: EXTERNAL CLOCK TIMING

Q4 Q1 Q2 Q3 Q4 Q1
OSC1
1 3 3 4 4
2
CLKOUT
TABLE 12-3 EXTERNAL CLOCK TIMING REQUIREMENTS

Parameter
FOSC External CLKIN Frequency(1) DC 2 MHz XT, RC osc PIC16LCR8X-04

DC 4 MHz XT, RC osc PIC16CR8X-04
DC 10 MHz HS osc PIC16CR8X-10
DC 200 kHz LP osc PIC16LCR8X-04
(1)
Oscillator Frequency DC 2 MHz RC osc PIC16LCR8X-04
DC 4 MHz RC osc PIC16CR8X-04
0.1 2 MHz XT osc PIC16LCR8X-04
0.1 4 MHz XT osc PIC16CR8X-04
1.0 10 MHz HS osc PIC16CR8X-10
DC 200 kHz LP osc PIC16LCR8X-04
1 Tosc External CLKIN Period(1) 500 ns XT, RC osc PIC16LCR8X-04

250 ns XT, RC osc PIC16CR8X-04
100 ns HS osc PIC16CR8X-10
5.0 s LP osc PIC16LCR8X-04
(1)
Oscillator Period 500 ns RC osc PIC16LCR8X-04
250 ns RC osc PIC16CR8X-04
500 10,000 ns XT osc PIC16LCR8X-04
250 10,000 ns XT osc PIC16CR8X-04
100 1,000 ns HS osc PIC16CR8X-10
5.0 s LP osc PIC16LCR8X-04
2 TCY Instruction Cycle Time(1) 0.4 4/Fosc DC s

3 TosL, Clock in (OSC1) High or Low 60 * ns XT osc PIC16LCR8X-04
TosH Time 50 * ns XT osc PIC16CR8X-04
2.0 * s LP osc PIC16LCR8X-04
35 * ns HS osc PIC16CR8X-10
4 TosR, Clock in (OSC1) Rise or Fall Time 25 * ns XT osc PIC16CR8X-04
TosF 50 * ns LP osc PIC16LCR8X-04
15 * ns HS osc PIC16CR8X-10
and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at "min." values with an external
clock applied to the OSC1 pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.

FIGURE 12-4: CLKOUT AND I/O TIMING
Q4 Q1 Q2 Q3
OSC1
11
10
22
CLKOUT 23
13 12
19 18
14 16
I/O Pin
(input)
17 15
I/O Pin old value new value

(output)
20, 21
Note: All tests must be done with specified capacitive loads (Figure 12-2) 50 pF on I/O pins and CLKOUT.
TABLE 12-4 CLKOUT AND I/O TIMING REQUIREMENTS

Parameter
10 TosH2ckL OSC1 to CLKOUT PIC16CR8X 15 30 * ns Note 1
10A PIC16LCR8X 15 120 * ns Note 1
11 TosH2ckH OSC1 to CLKOUT PIC16CR8X 15 30 * ns Note 1
12 TckR CLKOUT rise time PIC16CR8X 15 30 * ns Note 1
13 TckF CLKOUT fall time PIC16CR8X 15 30 * ns Note 1
14 TckL2ioV CLKOUT to Port out valid 0.5TCY +20 * ns Note 1
15 TioV2ckH Port in valid before PIC16CR8X 0.30TCY + 30 * ns Note 1
CLKOUT PIC16LCR8X 0.30TCY + 80 * ns Note 1
16 TckH2ioI Port in hold after CLKOUT 0* ns Note 1
17 TosH2ioV OSC1 (Q1 cycle) to PIC16CR8X 125 * ns
Port out valid PIC16LCR8X 250 * ns
18 TosH2ioI OSC1 (Q2 cycle) to PIC16CR8X 10 * ns
Port input invalid (I/O PIC16LCR8X 10 * ns
in hold time)
19 TioV2osH Port input valid to PIC16CR8X -75 * ns
OSC1 (I/O in setup PIC16LCR8X -175 * ns
time)
20 TioR Port output rise time PIC16CR8X 10 35 * ns
20A PIC16LCR8X 10 70 * ns
21 TioF Port output fall time PIC16CR8X 10 35 * ns
21A PIC16LCR8X 10 70 * ns
22 Tinp INT pin high PIC16CR8X 20 * ns
22A or low time PIC16LCR8X 55 * ns
23 Trbp RB7:RB4 change INT PIC16CR8X TOSC ns
23A high or low time PIC16LCR8X TOSC ns
and are not tested.
By design
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.

FIGURE 12-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34 34
I/O Pins
TABLE 12-5 RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter
30 TmcL MCLR Pulse Width (low) 1000 * ns 2.0V VDD 6.0V
31 Twdt Watchdog Timer Time-out Period 7* 18 33 * ms VDD = 5.0V
(No Prescaler)
32 Tost Oscillation Start-up Timer Period 1024TOSC ms TOSC = OSC1 period
33 Tpwrt Power-up Timer Period 28 * 72 132 * ms VDD = 5.0V
34 TIOZ I/O Hi-impedance from MCLR Low 100 * ns
or reset
Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.

FIGURE 12-6: TIMER0 CLOCK TIMINGS
RA4/T0CKI
40 41
42
TABLE 12-6 TIMER0 CLOCK REQUIREMENTS

No.
40 Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 * ns
30 * ns 3.0V VDD 6.0V
41 Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 * ns
20 * ns 3.0V VDD 6.0V
42 Tt0P T0CKI Period TCY + 40 * ns N = prescale value
N (2, 4, ..., 256)
Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.

NOTES:

PIC16F8X
13.0 DC & AC CHARACTERISTICS GRAPHS/TABLES
The graphs and tables provided in this section are for design guidance and are not tested or guaranteed.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are guaranteed to operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period
of time and matrix samples. Typical represents the mean of the distribution at 25C, while max or min represents
(mean + 3) and (mean - 3) respectively, where is standard deviation.
FIGURE 13-1: TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE

FOSC Frequency normalized to +25C
FOSC (25C)
1.20
Rext = 10 k
1.16
Cext = 100 pF
1.12
1.08
1.04
1.00
0.96 VDD = 5.5 V
0.92 VDD = 3.5 V

0.88
0.84
-40 -20 0 20 25 40 60 70 80 85 100
T(C)
TABLE 13-1 RC OSCILLATOR FREQUENCIES*
Average
Cext Rext Fosc @ 5V, 25C
Part to Part Variation
20 pF 5k 4.61 MHz 25%
10 k 2.66 MHz 24%
100 k 311 kHz 39%
100 pF 5k 1.34 MHz 21%
10 k 756 kHz 18%
100 k 82.8 kHz 28%
300 pF 5k 428 kHz 13%
10 k 243 kHz 13%
100 k 26.2 kHz 23%
* Measured on DIP packages. The percentage variation indicated here is part-to-part variation due to normal process
distribution. The variation indicated is 3 standard deviation from average value for full VDD range.

PIC16F8X
FIGURE 13-2: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 20 PF
Measured on DIP Packages, T = 25C
5.5
5.0
R = 5k
4.5
4.0
3.5
Fosc (MHz)
R = 10k
3.0
2.5
2.0
1.5
1.0
0.5 R = 100k
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)

PIC16F8X
1.8
R = 5k
1.6
1.4
1.2
Fosc (MHz)
1.0
R = 10k
0.8
0.6
0.4
0.2
R = 100k
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)

0.6
R = 5k
0.5
FOSC (MHz)
0.4
R = 10k
0.3
0.2
0.1
R = 100k
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)

PIC16F8X
FIGURE 13-5: TYPICAL IPD vs. VDD, FIGURE 13-6: TYPICAL IPD vs. VDD,
WATCHDOG DISABLED WATCHDOG ENABLED
6.0 10
5.0 8
T = 25C T = 25C
7
4.0 6
IPD (A)
5
IPD (A)
3.0 4
2.0 2
1.0 0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
FIGURE 13-7: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS vs. VDD
1.40
1.30
1.20
VTH (Volts)
C )
( +25
1.10 Typ
1.00
0.90
0.80
0.70
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
Note: These input pins have TTL input buffers.

PIC16F8X
FIGURE 13-8: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT
(IN XT, HS, AND LP MODES) vs. VDD
3.0
2.8
2.6
2.4
2.2
VTH (Volts)
2.0 C)
( +25
1.8 Typ
1.6
1.4
1.2
1.0
0.8
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
Note: This input pin is CMOS input.
FIGURE 13-9: VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) vs. VDD
5.0
4.5
4.0
3.5
3.0 25C
VIH, VIL (Volts)
ty p +
V IH
2.5
2.0
1.5
VIL typ +25C
1.0
0.5
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
Note: These input pins have Schmitt Trigger input buffers.

PIC16F8X
FIGURE 13-10: TYPICAL IDD vs. FREQUENCY (RC MODE @20PF, 25C)
TYPICAL IDD vs FREQ (RC MODE @20pF)
10000
1000
6.0V
5.5V
5.0V
4.5V
4.0V
3.5V
100 3.0V
2.5V
2.0V
10
100000 1000000 10000000
FREQ (Hz)

PIC16F8X
TYPICAL IDD vs FREQ (RC MODE @100 pF)
10000
1000
6.0V
5.5V
100 5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
10
10000 100000 1000000 10000000
FREQ (Hz)

PIC16F8X
TYPICAL IDD vs FREQ (RC MODE @300pF)
1000
6.0V
5.5V
100 5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
10
10000 100000 1000000
FREQ (Hz)

PIC16F8X
FIGURE 13-13: WDT TIMER TIME-OUT FIGURE 13-14: TRANSCONDUCTANCE (gm)
PERIOD vs. VDD OF HS OSCILLATOR vs. VDD
50 9000
45 8000
40 7000
35 6000
WDT period (ms)
30 5000
gm (A/V)
Typ +25C
25 Typ +25C 4000
20 3000
15 2000
10 100
5 0
2.0 3.0 4.0 5.0 6.0 2.0 3.0 4.0 5.0 6.0
VDD (Volts) VDD (Volts)

PIC16F8X
FIGURE 13-15: TRANSCONDUCTANCE (gm) FIGURE 13-16: TRANSCONDUCTANCE (gm)
OF LP OSCILLATOR vs. VDD OF XT OSCILLATOR vs. VDD
45 2500
40
2000
35
30
1500
25 Typ +25C
gm (A/V)
gm (A/V)
20 1000
Typ +25C
15
500
10
5
0
2.0 3.0 4.0 5.0 6.0
0 VDD (Volts)
2.0 3.0 4.0 5.0 6.0
VDD (Volts)

PIC16F8X
FIGURE 13-17: IOH vs. VOH, VDD = 3 V FIGURE 13-19: IOL vs. VOL, VDD = 3 V
45
0
40
5 35
30
10
Typ +25C
IOH (mA)
25 Typ +25C
IOL (mA)
20
15
15
20 10
5
25
0.0 0.5 1.0 1.5 2.0 2.5 3.0
0
VOH (Volts) 0.0 0.5 1.0 1.5 2.0 2.5 3.0
VOL (Volts)
FIGURE 13-18: IOH vs. VOH, VDD = 5 V FIGURE 13-20: IOL vs. VOL, VDD = 5 V
90
0
80
5
70
10
60
15
Typ +25C
IOH (mA)
50
IOL (mA)
20
Typ +25C
40
25
30
30
20
35
10
40
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0
VOH (Volts) 0.0 0.5 1.0 1.5 2.0 2.5 3.0
VOL (Volts)

PIC16F8X
FIGURE 13-21: TYPICAL DATA MEMORY ERASE/WRITE CYCLE TIME VS. VDD
10
7
DMEM Typ. E/W Cycle Time (ms)
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
VDD (Volts)
Shaded area is beyond recommended range.
TABLE 13-2 INPUT CAPACITANCE*
Typical Capacitance (pF)

Pin Name
18L PDIP 18L SOIC
PORTA 5.0 4.3

PORTB 5.0 4.3
MCLR 17.0 17.0
OSC1/CLKIN 4.0 3.5
OSC2/CLKOUT 4.3 3.5
T0CKI 3.2 2.8
* All capacitance values are typical at 25C. A part to part variation of 25% (three standard deviations) should
be taken into account.

PIC16F8X
14.0 PACKAGING INFORMATION
14.1 Package Marking Information
18L PDIP Example

XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX PIC16F84-04I/P
AABBCDE 9632SAW
18L SOIC Example

XXXXXXXXXXXX
XXXXXXXXXXXX PIC16F84-04
XXXXXXXXXXXX /SO
AABBCDE 9648SAN
Legend: XX...X Microchip part number & customer specific information*

AA Year code (last two digits of calendar year)
BB Week code (week of January 1 is week 01)
C Facility code of the plant at which wafer is manufactured
C = Chandler, Arizona, U.S.A.,
S = Tempe, Arizona, U.S.A.
D Mask revision number
E Assembly code of the plant or country of origin in which
part was assembled
Note: In the event the full Microchip part number cannot be marked on one line,
it will be carried over to the next line, thus limiting the number of available
characters for customer specific information.
* Standard OTP marking consists of Microchip part number, year code, week
code, facility code, mask rev# and assembly code. For OTP marking beyond
this, certain price adders apply. Please check with your Microchip Sales Office.
For QTP devices, any special marking adders are included in QTP price.

PIC16F8X
Package Type: K04-007 18-Lead Plastic Dual In-line (P) 300 mil
n 1
E1
A1
R
c L
A2
B1

B p
eB
Units INCHES* MILLIMETERS

Dimension Limits MIN NOM MAX MIN NOM MAX
PCB Row Spacing 0.300 7.62
Number of Pins n 18 18
Pitch p 0.100 2.54
Lower Lead Width B 0.013 0.018 0.023 0.33 0.46 0.58
Upper Lead Width B1 0.055 0.060 0.065 1.40 1.52 1.65
Shoulder Radius R 0.000 0.005 0.010 0.00 0.13 0.25
Lead Thickness c 0.005 0.010 0.015 0.13 0.25 0.38
Top to Seating Plane A 0.110 0.155 0.155 2.79 3.94 3.94
Top of Lead to Seating Plane A1 0.075 0.095 0.115 1.91 2.41 2.92
Base to Seating Plane A2 0.000 0.020 0.020 0.00 0.51 0.51
Tip to Seating Plane L 0.125 0.130 0.135 3.18 3.30 3.43
Package Length D 0.890 0.895 0.900 22.61 22.73 22.86
Molded Package Width E 0.245 0.255 0.265 6.22 6.48 6.73
Radius to Radius Width E1 0.230 0.250 0.270 5.84 6.35 6.86
Overall Row Spacing eB 0.310 0.349 0.387 7.87 8.85 9.83
Mold Draft Angle Top 5 10 15 5 10 15
Mold Draft Angle Bottom 5 10 15 5 10 15
* Controlling Parameter.

Dimension B1 does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003
(0.076 mm) per side or 0.006 (0.152 mm) more than dimension B1.

Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions D or E.

PIC16F8X
Package Type: K04-051 18-Lead Plastic Small Outline (SO) Wide, 300 mil
E1
p
E
2
B n 1
45
L
R2
c
A
A1
R1

L1 A2
Units INCHES* MILLIMETERS

Dimension Limits MIN NOM MAX MIN NOM MAX
Pitch p 0.050 1.27
Number of Pins n 18 18
Overall Pack. Height A 0.093 0.099 0.104 2.36 2.50 2.64
Shoulder Height A1 0.048 0.058 0.068 1.22 1.47 1.73
Standoff A2 0.004 0.008 0.011 0.10 0.19 0.28
Molded Package Length D 0.450 0.456 0.462 11.43 11.58 11.73
Molded Package Width E 0.292 0.296 0.299 7.42 7.51 7.59
Outside Dimension E1 0.394 0.407 0.419 10.01 10.33 10.64
Chamfer Distance X 0.010 0.020 0.029 0.25 0.50 0.74
Shoulder Radius R1 0.005 0.005 0.010 0.13 0.13 0.25
Gull Wing Radius R2 0.005 0.005 0.010 0.13 0.13 0.25
Foot Length L 0.011 0.016 0.021 0.28 0.41 0.53
Foot Angle 0 4 8 0 4 8
Radius Centerline L1 0.010 0.015 0.020 0.25 0.38 0.51
Lead Thickness c 0.009 0.011 0.012 0.23 0.27 0.30
Lower Lead Width B 0.014 0.017 0.019 0.36 0.42 0.48
Mold Draft Angle Top 0 12 15 0 12 15
Mold Draft Angle Bottom 0 12 15 0 12 15
* Controlling Parameter.
Dimension B does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003
(0.076 mm) per side or 0.006 (0.152 mm) more than dimension B.

Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions D or E.

PIC16F8X
NOTES:

PIC16F8X
APPENDIX A: FEATURE APPENDIX B: CODE COMPATIBILITY
IMPROVEMENTS - - FROM PIC16C5X TO
FROM PIC16C5X TO PIC16F8X
PIC16F8X To convert code written for PIC16C5X to PIC16F8X,
The following is the list of feature improvements over the user should take the following steps:
the PIC16C5X microcontroller family: 1. Remove any program memory page select
1. Instruction word length is increased to 14 bits. operations (PA2, PA1, PA0 bits) for CALL, GOTO.
This allows larger page sizes both in program 2. Revisit any computed jump operations (write to
memory (2K now as opposed to 512 before) and PC or add to PC, etc.) to make sure page bits
the register file (128 bytes now versus 32 bytes are set properly under the new scheme.
before). 3. Eliminate any data memory page switching.
2. A PC latch register (PCLATH) is added to handle Redefine data variables for reallocation.
program memory paging. PA2, PA1 and PA0 bits 4. Verify all writes to STATUS, OPTION, and FSR
are removed from the status register and placed registers since these have changed.
in the option register. 5. Change reset vector to 0000h.
3. Data memory paging is redefined slightly. The
STATUS register is modified.
4. Four new instructions have been added:
RETURN, RETFIE, ADDLW, and SUBLW. Two
instructions, TRIS and OPTION, are being
phased out although they are kept for
compatibility with PIC16C5X.
5. OPTION and TRIS registers are made
addressable.
6. Interrupt capability is added. Interrupt vector is
at 0004h.
7. Stack size is increased to 8 deep.
8. Reset vector is changed to 0000h.
9. Reset of all registers is revisited. Five different
reset (and wake-up) types are recognized.
Registers are reset differently.
10. Wake up from SLEEP through interrupt is
added.
11. Two separate timers, the Oscillator Start-up
Timer (OST) and Power-up Timer (PWRT), are
included for more reliable power-up. These
timers are invoked selectively to avoid
unnecessary delays on power-up and wake-up.
12. PORTB has weak pull-ups and interrupt on
change features.
13. T0CKI pin is also a port pin (RA4/T0CKI).
14. FSR is a full 8-bit register.
15. "In system programming" is made possible. The
user can program PIC16CXX devices using only
five pins: VDD, VSS, VPP, RB6 (clock) and RB7
(data in/out).

PIC16F8X
APPENDIX C: WHATS NEW IN THIS APPENDIX D: WHATS CHANGED IN
DATA SHEET THIS DATA SHEET
Heres whats new in this data sheet: Heres whats changed in this data sheet:
1. DC & AC Characteristics Graphs/Tables section 1. Errata information has been included.
for PIC16F8X devices has been added. 2. Option register name has been changed from
2. An appendix on conversion considerations has OPTION to OPTION_REG. This is consistant
been added. This explains differences for cus- with other data sheets and header files, and
tomers wanting to go from PIC16C84 to resolves the conflict between the OPTION com-
PIC16F84 or similar device. mand and OPTION register.
3. Errors have been fixed.
4. The appendix containing PIC16/17 microcon-
trollers has been removed.

PIC16F8X
APPENDIX E: CONVERSION CONSIDERATIONS - PIC16C84 TO PIC16F83/F84 AND
PIC16CR83/CR84
Considerations for converting from the PIC16C84 to and data RAM memory sizes) and the PIC16CR84 and
the PIC16F84 are listed in the table below. These con- PIC16CR83 (ROM versions of Flash devices). Devel-
siderations apply to converting from the PIC16C84 to opment Systems support is available for all of the
the PIC16F83 (same as PIC16F84 except for program PIC16X8X devices.
Difference PIC16C84 PIC16F84
The polarity of the PWRTE bit has PWRTE PWRTE

been reversed. Ensure that the pro-
grammer has this bit correctly set
before programming.
The PIC16F84 (and PIC16CR84) RAM = 36 bytes RAM = 68 bytes

have larger RAM sizes. Ensure that
this does not cause an issue with
your program.
The MCLR pin now has an on-chip MCLR pulse width (low) MCLR pulse width (low)
filter. The input signal on the MCLR = 350ns; 2.0V VDD 3.0V = 1000ns; 2.0V VDD 6.0V
pin will require a longer low pulse to = 150ns; 3.0V VDD 6.0V
generate an interrupt.
Some electrical specifications have IPD (typ @ 2V) = 26A IPD (typ @ 2V) < 1A
been improved (see IPD example).
Compare the electrical specifica- IPD (max @ 4V, WDT disabled) IPD (max @ 4V, WDT disabled)
tions of the two devices to ensure =100A (PIC16C84) =14A (PIC16F84)
that this will not cause a compatibil- =100A (PIC16LC84) =7A (PIC16LF84)
ity issue.
PORTA and crystal oscillator values For crystal oscillator configurations N/A
less than 500kHz operating below 500kHz, the device
may generate a spurious internal
Q-clock when PORTA<0> switches
state.
RB0/INT pin TTL TTL/ST*

(* This buffer is a Schmitt Trigger
input when configured as the exter-
nal interrupt.)
EEADR<7:6> and IDD It is recommended that the N/A

EEADR<7:6> bits be cleared.
When either of these bits is set, the
maximum IDD for the device is
higher than when both are cleared.
Code Protect 1 CP bit 9 CP bits
Recommended value of REXT for REXT = 3k - 100k REXT = 5k - 100k

RC oscillator circuits
GIE bit unintentional enable If an interrupt occurs while the Glo- N/A
bal Interrupt Enable (GIE) bit is
being cleared, the GIE bit may unin-
tentionally be re-enabled by the
users Interrupt Service Routine (the
RETFIE instruction).

PIC16F8X
NOTES:

PIC16F8X
INDEX CALL .......................................................................... 57
CLRF ......................................................................... 58
Numerics CLRW ........................................................................ 58
8.1 Configuration Bits ......................................................... 37 CLRWDT ................................................................... 58
COMF ........................................................................ 59
A DECF ......................................................................... 59
Absolute Maximum Ratings ......................................... 73, 85 DECFSZ .................................................................... 59
ALU ...................................................................................... 7 GOTO ........................................................................ 60
Architectural Overview ......................................................... 7 INCF .......................................................................... 60
Assembler INCFSZ ...................................................................... 61
MPASM Assembler .................................................... 70 IORLW ....................................................................... 61
IORWF ....................................................................... 62
B MOVF ........................................................................ 62
Block Diagram MOVLW ..................................................................... 62
Interrupt Logic ............................................................ 47 MOVWF ..................................................................... 62
On-Chip Reset Circuit ................................................ 41 NOP ........................................................................... 63
RA3:RA0 and RA5 Port Pins ..................................... 21 OPTION ..................................................................... 63
RA4 Pin ...................................................................... 21 RETFIE ...................................................................... 63
RB7:RB4 Port Pins .................................................... 23 RETLW ...................................................................... 64
TMR0/WDT Prescaler ................................................ 30 RETURN .................................................................... 64
Watchdog Timer ......................................................... 50 RLF ............................................................................ 65
Brown-out Protection Circuit .............................................. 46 RRF ........................................................................... 65
SLEEP ....................................................................... 66
C SUBLW ...................................................................... 66
Carry .................................................................................... 7 SUBWF ...................................................................... 67
CLKIN .................................................................................. 9 SWAPF ...................................................................... 67
CLKOUT .............................................................................. 9 TRIS .......................................................................... 67
Code Protection ........................................................... 37, 52 XORLW ..................................................................... 68
Compatibility, upward ........................................................... 3 XORWF ..................................................................... 68
Computed GOTO ............................................................... 18 Section ....................................................................... 53
Configuration Bits ............................................................... 37 Summary Table ......................................................... 54
INT Interrupt ...................................................................... 48
D
INTCON ........................................................... 17, 42, 47, 48
DC Characteristics ................... 75, 76, 77, 78, 87, 88, 89, 90 INTEDG ............................................................................. 48
Development Support ........................................................ 69 Interrupts
Development Tools ............................................................ 69 Flag ............................................................................ 47
Digit Carry ............................................................................ 7 Interrupt on Change Feature ..................................... 23
E Interrupts ............................................................. 37, 47
Electrical Characteristics .............................................. 73, 85 K

External Power-on Reset Circuit ........................................ 43 KeeLoq Evaluation and Programming Tools .................. 71
F L
Family of Devices Loading of PC .................................................................... 18
PIC16C8X .................................................................... 3
FSR .............................................................................. 19, 42 M
Fuzzy Logic Dev. System (fuzzyTECH-MP) ................... 71 MCLR ...................................................................... 9, 41, 42
Memory Organization
G
Data Memory ............................................................. 12
GIE ..................................................................................... 47 Memory Organization ................................................ 11
I Program Memory ....................................................... 11
MP-DriveWay - Application Code Generator ................. 71
I/O Ports ............................................................................. 21
MPLAB C ........................................................................... 71
I/O Programming Considerations ....................................... 25
MPLAB Integrated Development Environment Software ... 70
ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ........... 69
In-Circuit Serial Programming ...................................... 37, 52 O
INDF ................................................................................... 42 OPCODE ........................................................................... 53
Instruction Format .............................................................. 53 OPTION ................................................................. 16, 42, 48
Instruction Set OSC selection .................................................................... 37
ADDLW ...................................................................... 55 OSC1 ................................................................................... 9
ADDWF ...................................................................... 55 OSC2 ................................................................................... 9
ANDLW ...................................................................... 55 Oscillator
ANDWF ...................................................................... 55 HS ........................................................................ 39, 46
BCF ............................................................................ 56 LP ........................................................................ 39, 46
BSF ............................................................................ 56 RC ....................................................................... 39, 40
BTFSC ....................................................................... 56 XT .............................................................................. 39
BTFSS ....................................................................... 57 Oscillator Configurations .................................................... 39

PIC16F8X
P Programming Considerations .................................... 50
Time-out .................................................................... 42
Paging, Program Memory .................................................. 18
PCL .............................................................................. 18, 42 X
PCLATH ....................................................................... 18, 42
XT ...................................................................................... 46
PD .......................................................................... 15, 41, 46
PICDEM-1 Low-Cost PICmicro Demo Board ..................... 70 Z
PICDEM-2 Low-Cost PIC16CXX Demo Board .................. 70 Zero bit ................................................................................. 7
PICDEM-3 Low-Cost PIC16CXXX Demo Board ................ 70
PICMASTER In-Circuit Emulator ..................................... 69
PICSTART Plus Entry Level Development System ........ 69
Pinout Descriptions .............................................................. 9
POR ................................................................................... 43
Oscillator Start-up Timer (OST) ........................... 37, 43
Power-on Reset (POR) .................................. 37, 42, 43
Power-up Timer (PWRT) ..................................... 37, 43
Time-out Sequence .................................................... 46
Time-out Sequence on Power-up .............................. 44
TO .................................................................. 15, 41, 46
Port RB Interrupt ................................................................ 48
PORTA ..................................................................... 9, 21, 42
PORTB ..................................................................... 9, 23, 42
Power-down Mode (SLEEP) .............................................. 51
Prescaler ............................................................................ 29
PRO MATE II Universal Programmer .............................. 69
Product Identification System ........................................... 121
R
RBIF bit ........................................................................ 23, 48
RC Oscillator ...................................................................... 46
Read-Modify-Write ............................................................. 25
Register File ....................................................................... 12
Reset ............................................................................ 37, 41
Reset on Brown-Out ........................................................... 46
S
Saving W Register and STATUS in RAM .......................... 49
SEEVAL Evaluation and Programming System .............. 71
SLEEP .................................................................... 37, 41, 51
Software Simulator (MPLAB-SIM) ...................................... 71
Special Features of the CPU .............................................. 37
Special Function Registers ................................................ 12
Stack .................................................................................. 18
Overflows ................................................................... 18
Underflows ................................................................. 18
STATUS ................................................................... 7, 15, 42
T
time-out .............................................................................. 42
Timer0
Switching Prescaler Assignment ................................ 31
T0IF ............................................................................ 48
Timer0 Module ........................................................... 27
TMR0 Interrupt ........................................................... 48
TMR0 with External Clock .......................................... 29
Timing Diagrams
Time-out Sequence .................................................... 44
Timing Diagrams and Specifications ............................ 80, 92
TRISA ................................................................................. 21
TRISB ........................................................................... 23, 42
W
W ........................................................................................ 42
Wake-up from SLEEP .................................................. 42, 51
Watchdog Timer (WDT) ................................... 37, 41, 42, 50
WDT ................................................................................... 42
Period ......................................................................... 50

PIC16F8X
ON-LINE SUPPORT Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides
Microchip provides on-line support on the Microchip
system users a listing of the latest versions of all of
World Wide Web (WWW) site.
Microchips development systems software products.
The web site is used by Microchip as a means to make Plus, this line provides information on how customers
files and information easily available to customers. To can receive any currently available upgrade kits.The
view the site, the user must have access to the Internet Hot Line Numbers are:
and a web browser, such as Netscape or Microsoft
1-800-755-2345 for U.S. and most of Canada, and
Explorer. Files are also available for FTP download
from our FTP site. 1-602-786-7302 for the rest of the world.
Connecting to the Microchip Internet Web Site 980106
The Microchip web site is available by using your

favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.futureone.com/pub/microchip
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
Users Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
Trademarks: The Microchip name, logo, PIC, PICSTART,
Latest Microchip Press Releases PICMASTER and PRO MATE are registered trademarks of
Technical Support Section with Frequently Asked Microchip Technology Incorporated in the U.S.A. and other
Questions countries. PICmicro, FlexROM, MPLAB and fuzzyLAB are
trademarks and SQTP is a service mark of Microchip in
Design Tips the U.S.A.
Device Errata fuzzyTECH is a registered trademark of Inform Software
Job Postings Corporation. IBM, IBM PC-AT are registered trademarks of
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Links to other useful web sites related to MS-DOS, Microsoft Windows are registered trademarks
Microchip Products of Microsoft Corporation. CompuServe is a registered
trademark of CompuServe Incorporated.
Conferences for products, Development Sys-
All other trademarks mentioned herein are the property of
tems, technical information and more their respective companies.
Listing of seminars and events

PIC16F8X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
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Device: PIC16F8X Literature Number: DS30430C
Questions:
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3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?

PIC16F8X
PIC16F8X PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. -XX X /XX XXX
Examples:
Device Frequency Temperature Package Pattern a) PIC16F84 -04/P 301 = Commercial
Range Range temp., PDIP package, 4 MHz, normal
VDD limits, QTP pattern #301.
Device PIC16F8X(2), PIC16F8XT(3)
b) PIC16LF84 - 04I/SO = Industrial temp.,
PIC16LF8X(2), PIC16LF8XT(3)
SOIC package, 200 kHz, Extended VDD
PIC16F8XA(2), PIC16F8XAT(3)
limits.
PIC16LF8XA(2), PIC16LF8XAT(3)
PIC16CR8X(2), PIC16CR8XT(3) c) PIC16CR84 - 10I/P = ROM program
PIC16LCR8X(2), PIC16LCR8XT(3) memory, Industrial temp., PDIP package,
10MHz, normal VDD limits.
Frequency 04 = 4 MHz
Range 10 = 10 MHz
20 = 20 MHz Note 1: b = blank
(1) 2: F = Standard VDD range
Temperature b = 0C to +70C (Commercial)
LF = Extended VDD range
Range I = -40C to +85C (Industrial)
CR = ROM Version, Standard VDD
Package P = PDIP range
SO = SOIC (Gull Wing, 300 mil body) LCR = ROM Version, Extended VDD
SS = SSOP range
3: T = in tape and reel - SOIC, SSOP
Pattern 3-digit Pattern Code for QTP, ROM (blank otherwise) packages only.
SALES AND SUPPORT

Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office.
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3. The Microchips Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.

Note the following details of the code protection feature on PICmicro MCUs.
The PICmicro family meets the specifications contained in the Microchip Data Sheet.
Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-
edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.
The person doing so may be engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.
Information contained in this publication regarding device Trademarks

applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to The Microchip name and logo, the Microchip logo, FilterLab,
ensure that your application meets with your specifications. KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,
No representation or warranty is given and no liability is PICSTART, PRO MATE, SEEVAL and The Embedded Control
assumed by Microchip Technology Incorporated with respect Solutions Company are registered trademarks of Microchip Tech-
to the accuracy or use of such information, or infringement of nology Incorporated in the U.S.A. and other countries.
patents or other intellectual property rights arising from such
dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
use or otherwise. Use of Microchips products as critical com-
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
ponents in life support systems is not authorized except with
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
express written approval by Microchip. No licenses are con-
MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode
veyed, implicitly or otherwise, under any intellectual property
and Total Endurance are trademarks of Microchip Technology
rights.
Incorporated in the U.S.A.
Serialized Quick Turn Programming (SQTP) is a service mark

of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their

respective companies.
2002, Microchip Technology Incorporated, Printed in the

U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system

certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Companys quality system processes and
procedures are QS-9000 compliant for its
PICmicro 8-bit MCUs, KEELOQ code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchips quality
system for the design and manufacture of
development systems is ISO 9001 certified.

M
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500 Sugar Mill Road, Suite 200B Beijing, 100027, No. China Singapore
Atlanta, GA 30350 Tel: 86-10-85282100 Fax: 86-10-85282104 Microchip Technology Singapore Pte Ltd.
Tel: 770-640-0034 Fax: 770-640-0307 200 Middle Road
China - Chengdu
Boston #07-02 Prime Centre
Microchip Technology Consulting (Shanghai)
2 Lan Drive, Suite 120 Singapore, 188980
Co., Ltd., Chengdu Liaison Office
Westford, MA 01886 Tel: 65-334-8870 Fax: 65-334-8850
Rm. 2401, 24th Floor,
Tel: 978-692-3848 Fax: 978-692-3821 Taiwan
Ming Xing Financial Tower
Chicago No. 88 TIDU Street Microchip Technology Taiwan
333 Pierce Road, Suite 180 Chengdu 610016, China 11F-3, No. 207
Itasca, IL 60143 Tel: 86-28-6766200 Fax: 86-28-6766599 Tung Hua North Road
Tel: 630-285-0071 Fax: 630-285-0075 Taipei, 105, Taiwan
China - Fuzhou
Dallas Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
4570 Westgrove Drive, Suite 160 Co., Ltd., Fuzhou Liaison Office
Addison, TX 75001 Unit 28F, World Trade Plaza
Tel: 972-818-7423 Fax: 972-818-2924 EUROPE
No. 71 Wusi Road
Detroit Fuzhou 350001, China Denmark
Tri-Atria Office Building Tel: 86-591-7503506 Fax: 86-591-7503521 Microchip Technology Nordic ApS
32255 Northwestern Highway, Suite 190 China - Shanghai Regus Business Centre
Farmington Hills, MI 48334 Microchip Technology Consulting (Shanghai) Lautrup hoj 1-3
Tel: 248-538-2250 Fax: 248-538-2260 Co., Ltd. Ballerup DK-2750 Denmark
Kokomo Room 701, Bldg. B Tel: 45 4420 9895 Fax: 45 4420 9910
2767 S. Albright Road Far East International Plaza France
Kokomo, Indiana 46902 No. 317 Xian Xia Road Microchip Technology SARL
Tel: 765-864-8360 Fax: 765-864-8387 Shanghai, 200051 Parc dActivite du Moulin de Massy
Los Angeles Tel: 86-21-6275-5700 Fax: 86-21-6275-5060 43 Rue du Saule Trapu
18201 Von Karman, Suite 1090 China - Shenzhen Batiment A - ler Etage
Irvine, CA 92612 91300 Massy, France
Tel: 949-263-1888 Fax: 949-263-1338 Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Co., Ltd., Shenzhen Liaison Office
New York Rm. 1315, 13/F, Shenzhen Kerry Centre, Germany
150 Motor Parkway, Suite 202 Renminnan Lu Microchip Technology GmbH
Hauppauge, NY 11788 Shenzhen 518001, China Gustav-Heinemann Ring 125
Tel: 631-273-5305 Fax: 631-273-5335 Tel: 86-755-2350361 Fax: 86-755-2366086 D-81739 Munich, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
San Jose Hong Kong
Microchip Technology Inc. Microchip Technology Hongkong Ltd. Italy
2107 North First Street, Suite 590 Unit 901-6, Tower 2, Metroplaza Microchip Technology SRL
San Jose, CA 95131 223 Hing Fong Road Centro Direzionale Colleoni
Tel: 408-436-7950 Fax: 408-436-7955 Kwai Fong, N.T., Hong Kong Palazzo Taurus 1 V. Le Colleoni 1
Tel: 852-2401-1200 Fax: 852-2401-3431 20041 Agrate Brianza
Toronto
Milan, Italy
6285 Northam Drive, Suite 108 India Tel: 39-039-65791-1 Fax: 39-039-6899883
Mississauga, Ontario L4V 1X5, Canada Microchip Technology Inc.
Tel: 905-673-0699 Fax: 905-673-6509 India Liaison Office United Kingdom
Divyasree Chambers Arizona Microchip Technology Ltd.
1 Floor, Wing A (A3/A4) 505 Eskdale Road
No. 11, OShaugnessey Road Winnersh Triangle
Bangalore, 560 025, India Wokingham
Tel: 91-80-2290061 Fax: 91-80-2290062 Berkshire, England RG41 5TU
Tel: 44 118 921 5869 Fax: 44-118 921-5820
01/18/02

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PIC16F8X

18-pin Flash/EEPROM 8-Bit Microcontrollers

Operating speed: DC - 10 MHz clock input

1998 Microchip Technology Inc. DS30430C-page 1

To Our Valued Customers

DS30430C-page 2 1998 Microchip Technology Inc.

1998 Microchip Technology Inc. DS30430C-page 3

DS30430C-page 4 1998 Microchip Technology Inc.

2.1 Flash Devices

2.2 Quick-Turnaround-Production (QTP)

1998 Microchip Technology Inc. DS30430C-page 5

DS30430C-page 6 1998 Microchip Technology Inc.

1998 Microchip Technology Inc. DS30430C-page 7

FIGURE 3-1: PIC16F8X BLOCK DIAGRAM

5 Direct Addr 7 Indirect TMR0

OSC2/CLKOUT MCLR VDD, VSS

DS30430C-page 8 1998 Microchip Technology Inc.

OSC1/CLKIN 16 16 I ST/CMOS (3) Oscillator crystal input/external clock source input.

1998 Microchip Technology Inc. DS30430C-page 9

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

1. MOVLW 55h Fetch 1 Execute 1

DS30430C-page 10 1998 Microchip Technology Inc.

Registers (SFRs). The operation of the SFRs that Stack Level 8

4.1 Program Memory Organization

Peripheral Interrupt Vector 0004h

1998 Microchip Technology Inc. DS30430C-page 11

DS30430C-page 12 1998 Microchip Technology Inc.

7Fh FFh 7Fh FFh

Note 1: Not a physical register. Note 1: Not a physical register.

1998 Microchip Technology Inc. DS30430C-page 13

Value on Value on all

OPTION_ 1111 1111 1111 1111

87h Unimplemented location, read as '0' ---- ---- ---- ----

88h EECON1 EEIF WRERR WREN WR RD ---0 x000 ---0 q000

DS30430C-page 14 1998 Microchip Technology Inc.

FIGURE 4-1: STATUS REGISTER (ADDRESS 03h, 83h)

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

1998 Microchip Technology Inc. DS30430C-page 15

FIGURE 4-1: OPTION_REG REGISTER (ADDRESS 81h)

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

000 1:2 1:1

DS30430C-page 16 1998 Microchip Technology Inc.

FIGURE 4-1: INTCON REGISTER (ADDRESS 0Bh, 8Bh)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

1998 Microchip Technology Inc. DS30430C-page 17

4.3.2 PROGRAM MEMORY PAGING

The PIC16F83 and PIC16CR83 have 512 words of pro-

DS30430C-page 18 1998 Microchip Technology Inc.

FIGURE 4-1: DIRECT/INDIRECT ADDRESSING

bank select location select bank select location select

Note 1: PIC16F83 and PIC16CR83 devices.

1998 Microchip Technology Inc. DS30430C-page 19

DS30430C-page 20 1998 Microchip Technology Inc.

WR Note: I/O pin has protection diodes to VSS only.

TRIS Latch TTL

Note: I/O pins have protection diodes to VDD and VSS.

1998 Microchip Technology Inc. DS30430C-page 21

Name Bit0 Buffer Type Function