ST 62T62C

ST62T52C
ST62T62C/E62C
8-BIT OTP/EPROM MCUs WITH A/D CONVERTER,
SAFE RESET, AUTO-RELOAD TIMER AND EEPROM
3.0 to 6.0V Supply Operating Range

8 MHz Maximum Clock Frequency
-40 to +125C Operating Temperature Range
Run, Wait and Stop Modes
5 Interrupt Vectors
Look-up Table capability in Program Memory
Data Storage in Program Memory:
User selectable size
Data RAM: 128 bytes
Data EEPROM: 64 bytes (none on ST62T52C) PDIP16
User Programmable Options
9 I/O pins, fully programmable as:
Input with pull-up resistor
Input without pull-up resistor
Input with interrupt generation
Open-drain or push-pull output
Analog Input PSO16
5 I/O lines can sink up to 30mA to drive LEDs or
TRIACs directly
8-bit Timer/Counter with 7-bit programmable
prescaler
8-bit Auto-reload Timer with 7-bit programmable
prescaler (AR Timer)
Digital Watchdog
SSOP16
Oscillator Safe Guard
Low Voltage Detector for Safe Reset
8-bit A/D Converter with 4 analog inputs
On-chip Clock oscillator can be driven by Quartz
Crystal Ceramic resonator or RC network
User configurable Power-on Reset
One external Non-Maskable Interrupt
ST626x-EMU2 Emulation and Development CDIP16W
System (connects to an MS-DOS PC via a
parallel port) (See end of Datasheet for Ordering Information)
DEVICE SUMMARY
EPROM OTP
DEVICE EEPROM
(Bytes) (Bytes)
ST62T52C 1836 -
ST62T62C 1836 64
ST62E62C 1836 64
Rev. 2.7
November 1999 1/78

1
Table of Contents Document
Page
ST62T52C/ST62T62C/E62C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3.4 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3.5 Data Window Register (DWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3.6 Data RAM/EEPROM Bank Register (DRBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3.7 EEPROM Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.4 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.4.1 Option Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.4.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.4.3 . EEPROM Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . 18
3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1.1 Main Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1.2 Low Frequency Auxiliary Oscillator (LFAO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.3 Oscillator Safe Guard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2.1 RESET Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2.2 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2.3 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.4 LVD Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.5 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.6 MCU Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3 DIGITAL WATCHDOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3.1 Digital Watchdog Register (DWDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.4.1 Interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.4.2 Interrupt Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.4.3 Interrupt Option Register (IOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.4.4 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.5 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.5.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.5.2 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.5.3 Exit from WAIT and STOP Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.1.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.1.2 Safe I/O State Switching Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.1.3 ARTimer alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.2 TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.2.1 Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.2.2 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.2.4 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.3 AUTO-RELOAD TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.3.1 AR Timer Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.3.2 Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.3.3 AR Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.4 A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5 SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.5 A/D CONVERTER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.6 TIMER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.7 SPI CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.8 ARTIMER ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
ST62P52C/ST62P62C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
1.2.1 Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
1.2.2 Listing Generation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
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ST6252C/ST6262B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
1.2 ROM READOUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
1.3.1 Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
1.3.2 Listing Generation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
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ST62T52C ST62T62C/E62C
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST62T52C and ST62T62C devices is low cost fined in the programmable option byte of the
members of the ST62xx 8-bit HCMOS family of mi- OTP/EPROM versions.
crocontrollers, which is targeted at low to medium
complexity applications. All ST62xx devices are OTP devices offer all the advantages of user pro-
based on a building block approach: a common grammability at low cost, which make them the
core is surrounded by a number of on-chip periph- ideal choice in a wide range of applications where
erals. frequent code changes, multiple code versions or
last minute programmability are required.
The ST62E62C is the erasable EPROM version of
the ST62T62C device, which may be used to em- These compact low-cost devices feature a Timer
ulate the ST62T52C and ST62T62C devices as comprising an 8-bit counter and a 7-bit program-
well as the ST6252C and ST6262B ROM devices. mable prescaler, an 8-bit Auto-Reload Timer,
EEPROM data capability (except ST62T52C), an
OTP and EPROM devices are functionally identi- 8-bit A/D Converter with 4 analog inputs and a Dig-
cal. The ROM based versions offer the same func- ital Watchdog timer, making them well suited for a
tionality selecting as ROM options the options de- wide range of automotive, appliance and industrial
applications.
Figure 1. Block Diagram
8-BIT
PORT A PA4..PA 5 / Ain
A/D CONVERTER
TEST/VPP TEST
PB0, PB2..PB3 / 30 mA Sink
PORT B PB6 / ARTimin / 20 mA Sink
PB7 / ARTimout / 20 mA Sink
NMI INTERRUPT
DATA ROM
USER PORT C PC2..PC3 / Ain
SELECTABLE
PROGRAM
MEMORY
DATA RAM AUTORELOAD
1836 byte s OTP 128 Bytes
(ST62T52C, T62C) TIMER
1836 byte s EPROM
(ST62E62C)
DATA EEPROM
64 Bytes TIMER
(ST62T62C/E6 2C)
PC
STACK LEVEL 1
STACK LEVEL 2 DIGITAL
STACK LEVEL 3 8 BIT CORE WATCHD OG
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
POWER OSCILLATOR RESET

SUPPLY
VDD VSS OSCin OSCout RESET
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1.2 PIN DESCRIPTIONS
VDD and VSS. Power is supplied to the MCU via Mout are either Port B I/O bits or the Input and
these two pins. VDD is the power connection and Output pins of the ARTimer.
VSS is the ground connection. Reset state of PB2-PB3 pins can be defined by op-
tion either with pull-up or high impedance.
OSCin and OSCout. These pins are internally
connected to the on-chip oscillator circuit. A quartz PB0, PB2-PB3, PB6-PB7 scan also sink 30mA for
crystal, a ceramic resonator or an external clock direct LED driving.
signal can be connected between these two pins.
The OSCin pin is the input pin, the OSCout pin is PC2-PC3. These 2 lines are organized as one I/O
the output pin. port (C). Each line may be configured under soft-
ware control as input with or without internal pull-
RESET. The active-low RESET pin is used to re- up resistor, interrupt generating input with pull-up
start the microcontroller. resistor, analog input for the A/D converter, open-
drain or push-pull output.
TEST/VPP. The TEST must be held at VSS for nor-
mal operation. If TEST pin is connected to a Figure 2. ST62T52C, E62C and T62C Pin
+12.5V level during the reset phase, the
Configuration
EPROM/OTP programming Mode is entered.
NMI. The NMI pin provides the capability for asyn-
chronous interruption, by applying an external non PB0 1 16 PC2/Ain
maskable interrupt to the MCU. The NMI input is
falling edge sensitive. It is provided with an on-chip VPP/TEST 2 15 PC3/Ain
pullup resistor (if option has been enabled), and
Schmitt trigger characteristics. PB2 3 14 NMI
PA4-PA5. These 2 lines are organized as one I/O PB3 4 13 RESET

port (A). Each line may be configured under soft-
ware control as inputs with or without internal pull- ARTIMin/PB6 5 12 OSCout
up resistors, interrupt generating inputs with pull- ARTIMout/PB7 OSCin
up resistors, open-drain or push-pull outputs, ana- 6 11
log inputs for the A/D converter. VDD
7 PA5/Ain
10
PB0, PB2-PB3, PB6-PB7. These 5 lines are or- VSS 8 9 PA4/Ain
ganized as one I/O port (B). Each line may be con-
figured under software control as inputs with or
without internal pull-up resistors, interrupt generat-
ing inputs with pull-up resistors, open-drain or
push-pull outputs. PB6/ARTIMin and PB7/ARTI-
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1.3 MEMORY MAP

1.3.1 Introduction Briefly, Program space contains user program
code in OTP and user vectors; Data space con-
The MCU operates in three separate memory tains user data in RAM and in OTP, and Stack
spaces: Program space, Data space, and Stack space accommodates six levels of stack for sub-
space. Operation in these three memory spaces is routine and interrupt service routine nesting.
described in the following paragraphs.
Figure 3. Memory Addressing Diagram
PROGRAM SPACE DATA SPACE
0000h 000h
RAM / EEPROM
BANKING AREA
0-63 03Fh
040h
DATA READ-ONLY
PROGRAM MEMORY WINDOW
MEMORY 07Fh
080h X REGISTER
081h Y REGISTER
082h V REGISTER
083h W REGISTER
084h
RAM
0C0h DATA READ-ONLY

MEMORY
0FF0h WINDOW SELECT
DATA RAM
INTERRUPT & BANK SELECT
RESET VECTORS
0FFFh 0FFh ACCUMULATOR
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MEMORY MAP (Contd)

1.3.2 Program Space
Program Space comprises the instructions to be Figure 4. ST62T52C/T62C Program
executed, the data required for immediate ad- Memory Map
dressing mode instructions, the reserved factory
test area and the user vectors. Program Space is 0000h
addressed via the 12-bit Program Counter register
(PC register).
1.3.2.1 Program Memory Protection
The Program Memory in OTP or EPROM devices
can be protected against external readout of mem-
ory by selecting the READOUT PROTECTION op-
tion in the option byte.
RESERVED *
In the EPROM parts, READOUT PROTECTION
option can be disactivated only by U.V. erasure
that also results into the whole EPROM context
erasure.
Note: Once the Readout Protection is activated, it
is no longer possible, even for STMicroelectronics,
087Fh
to gain access to the OTP contents. Returned
parts with a protection set can therefore not be ac- 0880h
cepted.
USER
PROGRAM MEMORY
1836 BYTES
(OTP/EPROM)
0F9Fh
0FA0h
0FEFh
RESERVED *
0FF0h
0FF7h INTERRUPT VECTORS
0FF8h
RESERVED
0FFBh
0FFCh
NMI VECTOR
0FFDh
0FFEh USER RESET VECTOR
0FFFh
(*) Reserved areas should be filled with 0FFh
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MEMORY MAP (Contd)

1.3.3 Data Space Table 2. ST62T52C, T62C and ST62E62C Data
Memory Space
Data Space accommodates all the data necessary
for processing the user program. This space com- 000h
RAM / EEPROM banks
prises the RAM resource, the processor core and 03Fh
peripheral registers, as well as read-only data 040h
such as constants and look-up tables in DATA ROM WINDOW AREA
OTP/EPROM.
07Fh
1.3.3.1 Data ROM X REGISTER 080h
Y REGISTER 081h
All read-only data is physically stored in program V REGISTER 082h
memory, which also accommodates the Program W REGISTER 083h
Space. The program memory consequently con- 084h
tains the program code to be executed, as well as DATA RAM 60 BYTES
0BFh
the constants and look-up tables required by the PORT A DATA REGISTE R 0C0h
application. PORT B DATA REGISTE R 0C1h
PORT C DATA REGISTER 0C2h
The Data Space locations in which the different
RESERVED 0C3h
constants and look-up tables are addressed by the
PORT A DIRECTION REGISTER 0C4h
processor core may be thought of as a 64-byte
PORT B DIRECTION REGISTER 0C5h
window through which it is possible to access the
PORT C DIRECTI ON REGISTER 0C6h
read-only data stored in OTP/EPROM.
RESERVED 0C7h
1.3.3.2 Data RAM/EEPROM INTERRUPT OPTION REGISTE R 0C8h*
In ST62T52C, T62C and ST62E62C devices, the DATA ROM WINDOW REGISTER 0C9h*
data space includes 60 bytes of RAM, the accu- 0CAh
RESERVED
mulator (A), the indirect registers (X), (Y), the short 0CBh
direct registers (V), (W), the I/O port registers, the PORT A OPTION REGISTER 0CCh
peripheral data and control registers, the interrupt PORT B OPTION REGISTER 0CDh
option register and the Data ROM Window register PORT C OPTION REGISTE R 0CEh
(DRW register). RESERVED 0CFh
A/D DATA REGISTER 0D0h
Additional RAM and EEPROM pages can also be A/D CONTROL REGISTER 0D1h
addressed using banks of 64 bytes located be- TIMER PRESCALER REGISTER 0D2h
tween addresses 00h and 3Fh. TIMER COUNTE R REGISTE R 0D3h
TIMER STATUS CONTROL REGISTER 0D4h
1.3.4 Stack Space AR TIMER MODE CONTROL REGISTER 0D5h
AR TIMER STATUS/CONT ROL REGISTE R1 0D6h
Stack space consists of six 12-bit registers which AR TIMER STATUS/CONT ROL REGISTE R2 0D7h
are used to stack subroutine and interrupt return WATCHDOG REGISTER 0D8h
addresses, as well as the current program counter AR TIMER RELOAD/CAPTU RE REGISTE R 0D9h
contents. AR TIMER COMPARE REGISTER 0DAh
AR TIMER LOAD REGISTER 0DBh
Table 1. Additional RAM / EEPROM Banks
OSCILLATOR CONTROL REGISTER 0DCh*
Device RAM EEPROM MISCELLANEOUS 0DDh
ST62T52C 1 x 64 bytes - 0DEh
RESERVED
0E7h
ST62T62C 1 x 64 bytes 1 x 64 bytes
DATA RAM/EEP ROM REGISTER 0E8h*
RESERVED 0E9h
EEPROM CONTROL REGISTER 0EAh
0EBh
RESERVED
0FEh
ACCUMULATOR 0FFh
* WRITE ONLY REGISTER
9/78
8
MEMORY MAP (Contd)

1.3.5 Data Window Register (DWR) Data Window Register (DWR)
The Data read-only memory window is located from Address: 0C9h Write Only
address 0040h to address 007Fh in Data space. It
allows direct reading of 64 consecutive bytes locat- 7 0
ed anywhere in program memory, between ad-
dress 0000h and 0FFFh (top memory address de- - - DWR5 DWR4 DWR3 DWR2 DWR1 DWR0
pends on the specific device). All the program
memory can therefore be used to store either in-
structions or read-only data. Indeed, the window Bits 6, 7 = Not used.
can be moved in steps of 64 bytes along the pro-
gram memory by writing the appropriate code in the Bit 5-0 = DWR5-DWR0: Data read-only memory
Data Window Register (DWR). Window Register Bits. These are the Data read-
only memory Window bits that correspond to the
The DWR can be addressed like any RAM location upper bits of the data read-only memory space.
in the Data Space, it is however a write-only regis-
ter and therefore cannot be accessed using single- Caution: This register is undefined on reset. Nei-
bit operations. This register is used to position the ther read nor single bit instructions may be used to
64-byte read-only data window (from address 40h address this register.
to address 7Fh of the Data space) in program Note: Care is required when handling the DWR
memory in 64-byte steps. The effective address of register as it is write only. For this reason, the
the byte to be read as data in program memory is DWR contents should not be changed while exe-
obtained by concatenating the 6 least significant cuting an interrupt service routine, as the service
bits of the register address given in the instruction routine cannot save and then restore the registers
(as least significant bits) and the content of the previous contents. If it is impossible to avoid writ-
DWR register (as most significant bits), as illustrat- ing to the DWR during the interrupt service routine,
ed in Figure 5 below. For instance, when address- an image of the register must be saved in a RAM
ing location 0040h of the Data Space, with 0 load- location, and each time the program writes to the
ed in the DWR register, the physical location ad- DWR, it must also write to the image register. The
dressed in program memory is 00h. The DWR reg- image register must be written first so that, if an in-
ister is not cleared on reset, therefore it must be terrupt occurs between the two instructions, the
written to prior to the first access to the Data read- DWR is not affected.
only memory window area.
Figure 5. Data read-only memory Window Memory Addressing
DATA ROM 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PROGRAM SPACE ADDRESS

WINDOW REGISTER 7 6 READ
5 4 3 2 1 0
CONTENTS
5 4 3 2 1 0 DATA SPACE ADDRESS
(DWR) :
0 1 40h-7Fh
IN INSTRUCTION
Example:
DWR=28h 1 0 1 0 0 0
DATA SPACE ADDRESS
:
0 1 0 1 1 0 0 1 59h
ROM
1 0 1 0 0 0 0 1 1 0 0 1
ADDRESS:A19h
VR01573C
10/78
9
MEMORY MAP (Contd)

1.3.6 Data RAM/EEPROM Bank Register tion. The DRBR register is not modified when an
(DRBR) interrupt or a subroutine occurs.
Address: E8h Write only Notes :
Care is required when handling the DRBR register
7 0
as it is write only. For this reason, it is not allowed
DRBR DRBR to change the DRBR contents while executing in-
- - - - - -
4 0 terrupt service routine, as the service routine can-
not save and then restore its previous content. If it
is impossible to avoid the writing of this register in
Bit 7-5 = These bits are not used interrupt service routine, an image of this register
Bit 4 - DRBR4. This bit, when set, selects RAM must be saved in a RAM location, and each time
Page 2. the program writes to DRBR it must write also to
Bit 3-1. Not used the image register. The image register must be
written first, so if an interrupt occurs between the
Bit 0. DRBR0. This bit, when set, selects EEP- two instructions the DRBR is not affected.
ROM page 0.
In DRBR Register, only 1 bit must be set. Other-
The selection of the bank is made by programming wise two or more pages are enabled in parallel,
the Data RAM Bank Switch register (DRBR regis- producing errors.
ter) located at address E8h of the Data Space ac-
cording to Table 1. No more than one bank should Care must also be taken not to change the
be set at a time. E PROM page (when available) when the parallel
writing mode is set for the E PROM, as defined in
The DRBR register can be addressed like a RAM EECTL register.
Data Space at the address E8h; nevertheless it is
a write only register that cannot be accessed with Table 3. Data RAM Bank Register Set-up
single-bit operations. This register is used to select
the desired 64-byte RAM bank of the Data Space. DRBR ST62T52C ST62T62C
The bank number has to be loaded in the DRBR 00 None None
register and the instruction has to point to the se- 01 Not available EEPROM page 0
lected location as if it was in bank 0 (from 00h ad-
dress to 3Fh address). 02 Not Available Not Available
This register is not cleared during the MCU initiali- 08 Not available Not available
zation, therefore it must be written before the first 10h RAM Page 2 RAM Page 2
access to the Data Space bank region. Refer to other Reserved Reserved
the Data Space description for additional informa-
11/78
10
MEMORY MAP (Contd)

1.3.7 EEPROM Description (PMODE). In BMODE, one byte is accessed at a
EEPROM memory is located in 64-byte pages in time, while in PMODE up to 8 bytes in the same
data space. This memory may be used by the user row are programmed simultaneously (with conse-
program for non-volatile data storage. quent speed and power consumption advantages,
the latter being particularly important in battery
Data space from 00h to 3Fh is paged as described powered circuits).
in Table 4 . EEPROM locations are accessed di-
rectly by addressing these paged sections of data General Notes:
space. Data should be written directly to the intended ad-
The EEPROM does not require dedicated instruc- dress in EEPROM space. There is no buffer mem-
tions for read or write access. Once selected via the ory between data RAM and the EEPROM space.
Data RAM Bank Register, the active EEPROM When the EEPROM is busy (E2BUSY = 1)
page is controlled by the EEPROM Control Regis- EECTL cannot be accessed in write mode, it is
ter (EECTL), which is described below. only possible to read the status of E2BUSY. This
Bit E20FF of the EECTL register must be reset prior implies that as long as the EEPROM is busy, it is
to any write or read access to the EEPROM. If no not possible to change the status of the EEPROM
bank has been selected, or if E2OFF is set, any ac- Control Register. EECTL bits 4 and 5 are reserved
cess is meaningless. and must never be set.
Programming must be enabled by setting the Care is required when dealing with the EECTL reg-
E2ENA bit of the EECTL register. ister, as some bits are write only. For this reason,
the EECTL contents must not be altered while ex-
The E2BUSY bit of the EECTL register is set when ecuting an interrupt service routine.
the EEPROM is performing a programming cycle.
Any access to the EEPROM when E2BUSY is set If it is impossible to avoid writing to this register
is meaningless. within an interrupt service routine, an image of the
register must be saved in a RAM location, and
Provided E2OFF and E2BUSY are reset, an EEP- each time the program writes to EECTL it must
ROM location is read just like any other data loca- also write to the image register. The image register
tion, also in terms of access time. must be written to first so that, if an interrupt oc-
Writing to the EEPROM may be carried out in two curs between the two instructions, the EECTL will
modes: Byte Mode (BMODE) and Parallel Mode not be affected.
Table 4. Row Arrangement for Parallel Writing of EEPROM Locations

Dataspace
addresses.
Banks 0 and 1.
Byte 0 1 2 3 4 5 6 7
ROW7 38h-3Fh
ROW6 30h-37h
ROW5 28h-2Fh
ROW4 20h-27h
ROW3 18h-1Fh
ROW2 10h-17h
ROW1 08h-0Fh
ROW0 00h-07h
Up to 8 bytes in each row may be programmed simultaneously in Parallel Write mode.

The number of available 64-byte banks (1 or 2) is device dependent.
Note: The EEPROM is disabled as soon as STOP instruction is executed in order to achieve the lowest
power-consumption.
12/78
11
MEMORY MAP (Contd)

Additional Notes on Parallel Mode: EEPROM Control Register (EECTL)
If the user wishes to perform parallel program- Address: EAh Read/Write
ming, the first step should be to set the E2PAR2 Reset status: 00h
bit. From this time on, the EEPROM will be ad-
dressed in write mode, the ROW address will be 7 0
latched and it will be possible to change it only at
E2O E2PA E2PA E2BU E2E
the end of the programming cycle, or by resetting D7
FF
D5 D4
R1 R2 SY NA
E2PAR2 without programming the EEPROM. Af-
ter the ROW address is latched, the MCU can only
see the selected EEPROM row and any attempt Bit 7 = D7: Unused.
to write or read other rows will produce errors. Bit 6 = E2OFF: Stand-by Enable Bit. WRITE ONLY.
The EEPROM should not be read while E2PAR2 If this bit is set the EEPROM is disabled (any access
is set. will be meaningless) and the power consumption of
the EEPROM is reduced to its lowest value.
As soon as the E2PAR2 bit is set, the 8 volatile
ROW latches are cleared. From this moment on, Bit 5-4 = D5-D4: Reserved. MUST be kept reset.
the user can load data in all or in part of the ROW. Bit 3 = E2PAR1: Parallel Start Bit. WRITE ONLY.
Setting E2PAR1 will modify the EEPROM regis- Once in Parallel Mode, as soon as the user software
ters corresponding to the ROW latches accessed sets the E2PAR1 bit, parallel writing of the 8 adja-
after E2PAR2. For example, if the software sets cent registers will start. This bit is internally reset at
E2PAR2 and accesses the EEPROM by writing to the end of the programming procedure. Note that
addresses 18h, 1Ah and 1Bh, and then sets less than 8 bytes can be written if required, the un-
E2PAR1, these three registers will be modified si- defined bytes being unaffected by the parallel pro-
multaneously; the remaining bytes in the row will gramming cycle; this is explained in greater detail in
be unaffected. the Additional Notes on Parallel Mode overleaf.
Note that E2PAR2 is internally reset at the end of Bit 2 = E2PAR2: Parallel Mode En. Bit. WRITE
the programming cycle. This implies that the user ONLY. This bit must be set by the user program in
must set the E2PAR2 bit between two parallel pro- order to perform parallel programming. If E2PAR2
gramming cycles. Note that if the user tries to set is set and the parallel start bit (E2PAR1) is reset,
E2PAR1 while E2PAR2 is not set, there will be no up to 8 adjacent bytes can be written simultane-
programming cycle and the E2PAR1 bit will be un- ously. These 8 adjacent bytes are considered as a
affected. Consequently, the E2PAR1 bit cannot be row, whose address lines A7, A6, A5, A4, A3 are
set if E2ENA is low. The E2PAR1 bit can be set by fixed while A2, A1 and A0 are the changing bits, as
the user, only if the E2ENA and E2PAR2 bits are illustrated in Table 4. E2PAR2 is automatically re-
also set. set at the end of any parallel programming proce-
Notes: The EEPROM page shall not be changed dure. It can be reset by the user software before
through the DRBR register when the E2PAR2 bit starting the programming procedure, thus leaving
is set. the EEPROM registers unchanged.
Bit 1 = E2BUSY: EEPROM Busy Bit. READ ON-
LY. This bit is automatically set by the EEPROM
control logic when the EEPROM is in program-
ming mode. The user program should test it before
any EEPROM read or write operation; any attempt
to access the EEPROM while the busy bit is set
will be aborted and the writing procedure in
progress will be completed.
Bit 0 = E2ENA: EEPROM Enable Bit. WRITE ON-
LY. This bit enables programming of the EEPROM
cells. It must be set before any write to the EEP-
ROM register. Any attempt to write to the EEP-
ROM when E2ENA is low is meaningless and will
not trigger a write cycle.
13/78
12
1.4 PROGRAMMING MODES

1.4.1 Option Bytes EXTCNTL is low, STOP mode is not available with
The two Option Bytes allow configuration capabili- the watchdog active.
ty to the MCUs. Option bytes content is automati- PB2-3 PULL. When set this bit removes pull-up at
cally read, and the selected options enabled, when reset on PB2-PB3 pins. When cleared PB2-PB3
the chip reset is activated. pins have an internal pull-up resistor at reset.
It can only be accessed during the programming D4. Reserved. Must be cleared to 0.
mode. This access is made either automatically WDACT. This bit controls the watchdog activation.
(copy from a master device) or by selecting the When it is high, hardware activation is selected.
OPTION BYTE PROGRAMMING mode of the pro- The software activation is selected when WDACT
grammer. is low.
The option bytes are located in a non-user map. DELAY. This bit enables the selection of the delay
No address has to be specified. internally generated after the internal reset (exter-
nal pin, LVD, or watchdog activated) is released.
EPROM Code Option Byte (LSB) When DELAY is low, the delay is 2048 cycles of
the oscillator, it is of 32768 cycles when DELAY is
7 0 high.
PRO- EXTC- PB2-3 DE- OSCIL. Oscillator selection. When this bit is low,
- WDACT OSCIL OSGEN
TECT NTL PULL LAY the oscillator must be controlled by a quartz crys-
tal, a ceramic resonator or an external frequency.
When it is high, the oscillator must be controlled by
EPROM Code Option Byte (MSB) an RC network, with only the resistor having to be
externally provided.
15 8 OSGEN. Oscillator Safe Guard. This bit must be
ADC NMI set high to enable the Oscillator Safe Guard.
- - - - - LVD
SYNCHRO PULL When this bit is low, the OSG is disabled.
The Option byte is written during programming ei-
D15-D13. Reserved. Must be cleared. ther by using the PC menu (PC driven Mode) or
ADC SYNCHRO. When set, an A/D conversion is automatically (stand-alone mode).
started upon WAIT instruction execution, in order 1.4.2 Program Memory
to reduce supply noise. When this bit is low, an
A/D conversion is started as soon as the STA bit of EPROM/OTP programming mode is set by a
the A/D Converter Control Register is set. +12.5V voltage applied to the TEST/VPP pin. The
programming flow of the ST62T62C is described
D11. Reserved, must be set to one. in the User Manual of the EPROM Programming
D10. Reserved, must be cleared. Board.
NMI PULL. NMI Pull-Up. This bit must be set high The MCUs can be programmed with the
to configure the NMI pin with a pull-up resistor. ST62E6xB EPROM programming tools available
When it is low, no pull-up is provided. from STMicroelectronics.
LVD. LVD RESET enable.When this bit is set, safe
Table 5. ST62T52C/T62C Program Memory Map
RESET is performed by MCU when the supply
voltage is too low. When this bit is cleared, only Device Address Description
power-on reset or external RESET are active.
0000h-087Fh Reserved
PROTECT. Readout Protection. This bit allows the 0880h-0F9Fh User ROM
protection of the software contents against piracy. 0FA0h-0FEFh Reserved
When the bit PROTECT is set high, readout of the 0FF0h-0FF7h Interrupt Vectors
OTP contents is prevented by hardware.. When 0FF8h-0FFBh Reserved
this bit is low, the user program can be read. 0FFCh-0FFDh NMI Interrupt Vector
0FFEh-0FFFh Reset Vector
EXTCNTL. External STOP MODE control.. When
EXTCNTL is high, STOP mode is available with
watchdog active by setting NMI pin to one. When Note: OTP/EPROM devices can be programmed
with the development tools available from STMi-
croelectronics (ST62E6X-EPB or ST626X-KIT).
14/78
13
PROGRAMMING MODES (Contd)

1.4.3 . EEPROM Data Memory ternal programmer. Any STMicroelectronics tool
used for the program memory (OTP/EPROM) can
EEPROM data pages are supplied in the virgin also be used to program the EEPROM data mem-
state FFh. Partial or total programming of EEP- ory.
ROM data memory can be performed either
through the application software or through an ex-
15/78
14
2 CENTRAL PROCESSING UNIT

2.1 INTRODUCTION
The CPU Core of ST6 devices is independent of the Indirect Registers (X, Y). These two indirect reg-
I/O or Memory configuration. As such, it may be isters are used as pointers to memory locations in
thought of as an independent central processor Data space. They are used in the register-indirect
communicating with on-chip I/O, Memory and Pe- addressing mode. These registers can be ad-
ripherals via internal address, data, and control dressed in the data space as RAM locations at ad-
buses. In-core communication is arranged as dresses 80h (X) and 81h (Y). They can also be ac-
shown in Figure 6; the controller being externally cessed with the direct, short direct, or bit direct ad-
linked to both the Reset and Oscillator circuits, dressing modes. Accordingly, the ST6 instruction
while the core is linked to the dedicated on-chip pe- set can use the indirect registers as any other reg-
ripherals via the serial data bus and indirectly, for ister of the data space.
interrupt purposes, through the control registers.
Short Direct Registers (V, W). These two regis-
2.2 CPU REGISTERS ters are used to save a byte in short direct ad-
dressing mode. They can be addressed in Data
space as RAM locations at addresses 82h (V) and
The ST6 Family CPU core features six registers and
83h (W). They can also be accessed using the di-
three pairs of flags available to the programmer.
rect and bit direct addressing modes. Thus, the
These are described in the following paragraphs.
ST6 instruction set can use the short direct regis-
Accumulator (A). The accumulator is an 8-bit ters as any other register of the data space.
general purpose register used in all arithmetic cal-
Program Counter (PC). The program counter is a
culations, logical operations, and data manipula-
12-bit register which contains the address of the
tions. The accumulator can be addressed in Data
next ROM location to be processed by the core.
space as a RAM location at address FFh. Thus the This ROM location may be an opcode, an oper-
ST6 can manipulate the accumulator just like any
and, or the address of an operand. The 12-bit
other register in Data space.
length allows the direct addressing of 4096 bytes
in Program space.
Figure 6ST6 Core Block Diagram
0,01 TO 8MHz
RESET
OSCin OSCout
INTERRUPTS
CONTROLLER
DATA SPACE
CONTROL
FLAG SIGNALS DATA
OPCODE VALUES ADDRESS /READ LINE
2 RAM/EEPR OM
PROGRAM
DATA
ROM/EPRO M ADDRESS
256 ROM/EPROM
DECODER
A-DATA B-DATA
DEDICAT IONS
ACCUMULATOR
Program Counter
12 and FLAGS
6 LAYER STACK ALU
RESULTS TO DATA SPACE (WRITE LINE)
VR01811
16/78
15
CPU REGISTERS (Contd)

However, if the program space contains more than a RETI instructions occurs. As the NMI mode is
4096 bytes, the additional memory in program automatically selected after the reset of the MCU,
space can be addressed by using the Program the ST6 core uses at first the NMI flags.
Bank Switch register.
Stack. The ST6 CPU includes a true LIFO hard-
The PC value is incremented after reading the ad- ware stack which eliminates the need for a stack
dress of the current instruction. To execute relative pointer. The stack consists of six separate 12-bit
jumps, the PC and the offset are shifted through RAM locations that do not belong to the data
the ALU, where they are added; the result is then space RAM area. When a subroutine call (or inter-
shifted back into the PC. The program counter can rupt request) occurs, the contents of each level are
be changed in the following ways: shifted into the next higher level, while the content
- JP (Jump) instructionPC=Jump address of the PC is shifted into the first level (the original
contents of the sixth stack level are lost). When a
- CALL instructionPC= Call address subroutine or interrupt return occurs (RET or RETI
- Relative Branch Instruction.PC= PC +/- offset instructions), the first level register is shifted back
into the PC and the value of each level is popped
- Interrupt PC=Interrupt vector back into the previous level. Since the accumula-
- ResetPC= Reset vector tor, in common with all other data space registers,
is not stored in this stack, management of these
- RET & RETI instructionsPC= Pop (stack) registers should be performed within the subrou-
- Normal instructionPC= PC + 1 tine. The stack will remain in its deepest position
if more than 6 nested calls or interrupts are execut-
Flags (C, Z). The ST6 CPU includes three pairs of ed, and consequently the last return address will
flags (Carry and Zero), each pair being associated be lost. It will also remain in its highest position if
with one of the three normal modes of operation: the stack is empty and a RET or RETI is executed.
Normal mode, Interrupt mode and Non Maskable In this case the next instruction will be executed.
Interrupt mode. Each pair consists of a CARRY
flag and a ZERO flag. One pair (CN, ZN) is used Figure 7ST6 CPU Programming Mode
during Normal operation, another pair is used dur- l
ing Interrupt mode (CI, ZI), and a third pair is used

in the Non Maskable Interrupt mode (CNMI, ZN- INDEX b7 X REG. POINTER b0
SHORT
MI). REGISTER DIRECT
b7 Y REG. POINTER b0
ADDRESSING
The ST6 CPU uses the pair of flags associated MODE
b7 V REGISTER b0
with the current mode: as soon as an interrupt (or
a Non Maskable Interrupt) is generated, the ST6 b7 W REGISTER b0
CPU uses the Interrupt flags (resp. the NMI flags)
b7 ACCUM ULATO R b0
instead of the Normal flags. When the RETI in-
struction is executed, the previously used set of
flags is restored. It should be noted that each flag b11 PROGRAM COUNTER b0
set can only be addressed in its own context (Non
Maskable Interrupt, Normal Interrupt or Main rou-
tine). The flags are not cleared during context
switching and thus retain their status. SIX LEVELS
STACK REGISTER
The Carry flag is set when a carry or a borrow oc-
curs during arithmetic operations; otherwise it is
cleared. The Carry flag is also set to the value of
the bit tested in a bit test instruction; it also partici-
pates in the rotate left instruction. NORMAL FLAGS C Z
The Zero flag is set if the result of the last arithme-

INTERRUPT FLAGS C Z
tic or logical operation was equal to zero; other-
wise it is cleared.
NMI FLAGS C Z
Switching between the three sets of flags is per- VA000423
formed automatically when an NMI, an interrupt or
17/78
16
3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES
3.1 CLOCK SYSTEM

The MCU features a Main Oscillator which can be Figure 8. Oscillator Configurations
driven by an external clock, or used in conjunction
with an AT-cut parallel resonant crystal or a suita- CRYSTAL/RES ONATOR CLOCK
ble ceramic resonator, or with an external resistor CRYSTAL/RESON ATOR option
(RNET). In addition, a Low Frequency Auxiliary Os-
cillator (LFAO) can be switched in for security rea-
sons, to reduce power consumption, or to offer the ST6xxx
benefits of a back-up clock system.
The Oscillator Safeguard (OSG) option filters OSCin OSCout
spikes from the oscillator lines, provides access to
the LFAO to provide a backup oscillator in the
event of main oscillator failure and also automati-
cally limits the internal clock frequency (f INT) as a
function of VDD, in order to guarantee correct oper- CL1n C L2
ation. These functions are illustrated in Figure 9.,
Figure 10., Figure 11. and Figure 12..
Figure 8. illustrates various possible oscillator con- EXTERNAL CLOCK
figurations using an external crystal or ceramic res- CRYSTAL/RESON ATOR option
onator, an external clock input, an external resistor
(RNET), or the lowest cost solution using only the
ST6xxx
LFAO. CL1 an CL2 should have a capacitance in the
range 12 tST6_CLK1o 22 pF for an oscillator fre-
quency in the 4-8 MHz range. OSCin OSCout
The internal MCU clock frequency (fINT) is divided
by 12 to drive the Timer, the A/D converter and the NC
Watchdog timer, and by 13 to drive the CPU core,
as may be seen in Figure 11..
With an 8MHz oscillator frequency, the fastest ma- RC NETW ORK
RC NETW ORK option
chine cycle is therefore 1.625s.
A machine cycle is the smallest unit of time needed
to execute any operation (for instance, to increment ST6xxx
the Program Counter). An instruction may require
two, four, or five machine cycles for execution. OSCin OSCout
3.1.1 Main Oscillator
NC
The oscillator configuration may be specified by se-
lecting the appropriate option. When the CRYS- RNET
TAL/RESONATOR option is selected, it must be
used witha quartz crystal, a ceramic resonator or an
external signalprovided onthe OSCinpin. When the
RC NETWORK option is selected, the system clock INTEGRA TED CLOCK
is generated by an external resistor. CRYSTAL/RESON ATOR option
OSG ENABLED option
The main oscillator can be turned off (when the
OSG ENABLED option is selected) by setting the
OSCOFF bit of the ADC Control Register. The ST6xxx
Low Frequency Auxiliary Oscillator is automatical-
ly started. OSCin OSCout
NC
18/78
17
CLOCK SYSTEM (Contd)

Turning on the main oscillator is achieved by re- tions: it filters spikes from the oscillator lines which
setting the OSCOFF bit of the A/D Converter Con- would result in over frequency to the ST62 CPU; it
trol Register or by resetting the MCU. Restarting gives access to the Low Frequency Auxiliary Os-
the main oscillator implies a delay comprising the cillator (LFAO), used to ensure minimum process-
oscillator start up delay period plus the duration of ing in case of main oscillator failure, to offer re-
the software instruction at fLFAO clock frequency. duced power consumption or to provide a fixed fre-
3.1.2 Low Frequency Auxiliary Oscillator quency low cost oscillator; finally, it automatically
(LFAO) limits the internal clock frequency as a function of
supply voltage, in order to ensure correct opera-
The Low Frequency Auxiliary Oscillator has three tion even if the power supply should drop.
main purposes. Firstly, it can be used to reduce
power consumption in non timing critical routines. The OSG is enabled or disabled by choosing the
Secondly, it offers a fully integrated system clock, relevant OSG option. It may be viewed as a filter
without any external components. Lastly, it acts as whose cross-over frequency is device dependent.
a safety oscillator in case of main oscillator failure. Spikes on the oscillator lines result in an effectively
This oscillator is available when the OSG ENA- increased internal clock frequency. In the absence
BLED option is selected. In this case, it automati- of an OSG circuit, this may lead to an over fre-
cally starts one of its periods after the first missing quency for a given power supply voltage. The
edge from the main oscillator, whatever the reason OSG filters out such spikes (as illustrated in Figure
(main oscillator defective, no clock circuitry provid- 9.). In all cases, when the OSG is active, the max-
ed, main oscillator switched off...). imum internal clock frequency, fINT, is limited to
fOSG, which is supply voltage dependent. This re-
User code, normal interrupts, WAIT and STOP in- lationship is illustrated in Figure 12..
structions, are processed as normal, at the re-
duced fLFAO frequency. The A/D converter accura- When the OSG is enabled, the Low Frequency
cy is decreased, since the internal frequency is be- Auxiliary Oscillator may be accessed. This oscilla-
low 1MHz. tor starts operating after the first missing edge of
the main oscillator (see Figure 10.).
At power on, the Low Frequency Auxiliary Oscilla-
tor starts faster than the Main Oscillator. It there- Over-frequency, at a given power supply level, is
fore feeds the on-chip counter generating the POR seen by the OSG as spikes; it therefore filters out
delay until the Main Oscillator runs. some cycles in order that the internal clock fre-
quency of the device is kept within the range the
The Low Frequency Auxiliary Oscillator is auto- particular device can stand (depending on VDD),
matically switched off as soon as the main oscilla- and below fOSG: the maximum authorised frequen-
tor starts. cy with OSG enabled.
ADCR Note. The OSG should be used wherever possible
Address: 0D1h Read/Write as it provides maximum safety. Care must be tak-
en, however, as it can increase power consump-
7 0 tion and reduce the maximum operating frequency
ADCR ADCR ADCR ADCR ADCR OSC ADCR ADCR to fOSG.
7 6 5 4 3 OFF 1 0 Warning: Care has to be taken when using the
OSG, as the internal frequency is defined between
Bit 7-3, 1-0= ADCR7-ADCR3, ADCR1-ADCR0: a minimum and a maximum value and is not accu-
ADC Control Register . These bits are not used. rate.
Bit 2 = OSCOFF. When low, this bit enables main For precise timing measurements, it is not recom-
oscillator to run. The main oscillator is switched off mended to use the OSG and it should not be ena-
when OSCOFF is high. bled in applications that use the SPI or the UART.
3.1.3 Oscillator Safe Guard It should also be noted that power consumption in
The Oscillator Safe Guard (OSG) affords drastical- Stop mode is higher when the OSG is enabled
ly increased operational integrity in ST62xx devic- (around 50A at nominal conditions and room
es. The OSG circuit provides three basic func- temperature).
19/78
18

Figure 9. OSG Filtering Principle
(1)
(2)
(3)
(4)
(1) Maximum Frequency for the device to work correctly

(2) Actual Quartz Crystal Frequency at OSCin pin
(3) Noise from OSCin
(4) Resulting Internal Frequency VR001932
Figure 10. OSG Emergency Oscillator Principle
Main
Oscillator
Emergency
Oscillator
Internal
Frequency
VR001933
20/78
19

Figure 11. Clock Circuit Block Diagram
POR
: 13 Core
OSG
TIMER 1
MAIN M fINT Watchdog

OSCILLATOR U : 12
X
LFAO
:1
Main Oscillator off
Figure 12. Maximum Operating Frequency (fMAX) versus Supply Voltage (VDD)
Maximum FREQU ENCY (MHz)
7 4
FUNCTIONALITY IS NOT
3
6
fOSG
GUARANTEED
IN THIS AREA
5
fOSG Min (at 85C)
4 2
3
fOSG Min (at 125C)
2
1
1
2.5 3 3.6 4 4.5 5 5.5 6
SUPPLY VOLTAGE (VDD )

VR01807J
Notes:
1. In this area, operation is guaranteed at the area is guaranteed at the quartz crystal frequency.
quartz crystal frequency. When the OSG is enabled, access to this area is
2. When the OSG is disabled, operation in this prevented. The internal frequency is kept a fOSG.
area is guaranteed at the crystal frequency. When 4. When the OSG is disabled, operation in this
the OSG is enabled, operation in this area is guar- area is not guaranteed
anteed at a frequency of at least fOSG Min. When the OSG is enabled, access to this area is
3. When the OSG is disabled, operation in this prevented. The internal frequency is kept at fOSG.
21/78
20
3.2 RESETS
The MCU can be reset in four ways: is executed immediately following the internal de-
by the external Reset input being pulled low; lay.
by Power-on Reset; To ensure correct start-up, the user should take
care that the VDD Supply is stabilized at a suffi-
by the digital Watchdog peripheral timing out. cient level for the chosen frequency (see recom-
by Low Voltage Detection (LVD) mended operation) before the reset signal is re-
3.2.1 RESET Input leased. In addition, supply rising must start from
0V.
The RESET pin may be connected to a device of
the application board in order to reset the MCU if As a consequence, the POR does not allow to su-
required. The RESET pin may be pulled low in pervise static, slowly rising, or falling, or noisy
RUN, WAIT or STOP mode. This input can be (presenting oscillation) VDD supplies.
used to reset the MCU internal state and ensure a An external RC network connected to the RESET
correct start-up procedure. The pin is active low pin, or the LVD reset can be used instead to get
and features a Schmitt trigger input. The internal the best performances.
Reset signal is generated by adding a delay to the
external signal. Therefore even short pulses on Figure 13. Reset and Interrupt Processing
the RESET pin are acceptable, provided VDD has
completed its rising phase and that the oscillator is RESET
running correctly (normal RUN or WAIT modes).
The MCU is kept in the Reset state as long as the
RESET pin is held low.
NMI MASK SET
If RESET activation occurs in the RUN or WAIT INT LATCH CLEARED
( IF PRESENT )
modes, processing of the user program is stopped
(RUN mode only), the Inputs and Outputs are con-
figured as inputs with pull-up resistors and the
main Oscillator is restarted. When the level on the SELECT
NMI MODE FLAGS
RESET pin then goes high, the initialization se-
quence is executed following expiry of the internal
delay period.
If RESET pin activation occurs in the STOP mode, PUT FFEH
ON ADDRESS BUS
the oscillator starts up and all Inputs and Outputs
are configured as inputs with pull-up resistors.
When the level of the RESET pin then goes high,
the initialization sequence is executed following
expiry of the internal delay period. YES
IS RESET STILL
3.2.2 Power-on Reset PRESENT?
The function of the POR circuit consists in waking

up the MCU by detecting around 2V a dynamic NO
(rising edge) variation of the VDD Supply. At the
beginning of this sequence, the MCU is configured LOAD PC
FROM RESET LOCATIONS
in the Reset state: all I/O ports are configured as FFE/FFF
inputs with pull-up resistors and no instruction is
executed. When the power supply voltage rises to
a sufficient level, the oscillator starts to operate,
whereupon an internal delay is initiated, in order to FETCH INSTRUCTION
allow the oscillator to fully stabilize before execut-
ing the first instruction. The initialization sequence VA000427
22/78
21
RESETS (Contd)
3.2.3 Watchdog Reset ues, allowing hysteresis effect. Reference value in
The MCU provides a Watchdog timer function in case of voltage drop has been set lower than the
order to ensure graceful recovery from software reference value for power-on in order to avoid any
upsets. If the Watchdog register is not refreshed parasitic Reset when MCU starts running and
before an end-of-count condition is reached, the sinking current on the supply.
internal reset will be activated. This, amongst oth- As long as the supply voltage is below the refer-
er things, resets the watchdog counter. ence value, there is a internal and static RESET
command. The MCU can start only when the sup-
The MCU restarts just as though the Reset had ply voltage rises over the reference value. There-
been generated by the RESET pin, including the fore, only two operating mode exist for the MCU:
built-in stabilisation delay period. RESET active below the voltage reference, and
3.2.4 LVD Reset running mode over the voltage reference as
shown on the Figure 14., that represents a power-
The on-chip Low Voltage Detector, selectable as up, power-down sequence.
user option, features static Reset when supply
voltage is below a reference value. Thanks to this Note: When the RESET state is controlled by one
feature, external reset circuit can be removed of the internal RESET sources (Low Voltage De-
while keeping the application safety. This SAFE tector, Watchdog, Power on Reset), the RESET
RESET is effective as well in Power-on phase as pin is tied to low logic level.
in power supply drop with different reference val-
Figure 14. LVD Reset on Power-on and Power-down (Brown-out)
VDD
VUp
Vdn
RESET
RESET
time
VR02106A
3.2.5 Application Notes

No external resistor is required between VDD and Direct external connection of the pin RESET to
the Reset pin, thanks to the built-in pull-up device. VDD must be avoided in order to ensure safe be-
haviour of the internal reset sources (AND.Wired
structure).
23/78
22
RESETS (Contd)
3.2.6 MCU Initialization Sequence Figure 15. Reset and Interrupt Processing
When a reset occurs the stack is reset, the PC is
RESET
loaded with the address of the Reset Vector (locat-
ed in program ROM starting at address 0FFEh). A
jump to the beginning of the user program must be
coded at this address. Following a Reset, the In- JP JP:2 BYTES/4 CYCLES
terrupt flag is automatically set, so that the CPU is RESET
in Non Maskable Interrupt mode; this prevents the VECTOR
initialisation routine from being interrupted. The in-

itialisation routine should therefore be terminated
by a RETI instruction, in order to revert to normal
mode and enable interrupts. If no pending interrupt
is present at the end of the initialisation routine, the INITIALIZATION
MCU will continue by processing the instruction ROUTINE RETI: 1 BYTE/2 CYCLES
immediately following the RETI instruction. If, how- RETI
ever, a pending interrupt is present, it will be serv-
iced. VA00181
Figure 16. Reset Block Diagram
VDD
ST6
fOSC CK INTERNA L
RESET
RPU COUNTER
AND. Wired
RESD1)
RESET RESET
RESET
POWER ON RESET
WATCHD OG RESET
LVD RESET
VR02107A
1) Resistive ESD protection. Value not guaranteed.
24/78
23
RESETS (Contd)
Table 6. Register Reset Status
Register Address(es) Status Comment
Oscillator Control Register 0DCh fINT = fOSC; user must set bit3 to 1
EEPROM Control Register 0EAh EEPROM enabled (if available)
Port Data Registers 0C0h to 0C2h I/O are Input with pull-up
Port Direction Register 0C4h to 0C6h I/O are Input with pull-up
Port Option Register 0CCh to 0CEh I/O are Input with pull-up
Interrupt Option Register 0C8h Interrupt disabled
TIMER Status/Control 0D4h 00h TIMER disabled
AR TIMER Mode Control Register 0D5h AR TIMER stopped

AR TIMER Status/Control 1 Register 0D6h
AR TIMER Status/Control 2Register 0D7h
AR TIMER Compare Register 0DAh
Miscellaneous Register 0DDh
X, Y, V, W, Register 080H TO 083H

Accumulator 0FFh
Data RAM 084h to 0BFh
Data RAM Page REgister 0E8h
Data ROM Window Register 0C9h Undefined
EEPROM 00h to F3h As written if programmed
A/D Result Register 0D0h
AR TIMER Load Register 0DBh
AR TIMER Reload/Capture Register 0D9h
TIMER Counter Register 0D3h FFh
TIMER Prescaler Register 0D2h 7Fh Max count loaded
Watchdog Counter Register 0D8h FEh
A/D Control Register 0D1h 40h A/D in Standby
25/78
24
3.3 DIGITAL WATCHDOG

The digital Watchdog consists of a reloadable When the Watchdog is disabled, low power Stop
downcounter timer which can be used to provide mode is available. Once activated, the Watchdog
controlled recovery from software upsets. cannot be disabled, except by resetting the MCU.
The Watchdog circuit generates a Reset when the In the HARDWARE option, the Watchdog is per-
downcounter reaches zero. User software can manently enabled. Since the oscillator will run con-
prevent this reset by reloading the counter, and tinuously, low power mode is not available. The
should therefore be written so that the counter is STOP instruction is interpreted as a WAIT instruc-
regularly reloaded while the user program runs tion, and the Watchdog continues to countdown.
correctly. In the event of a software mishap (usual- However, when the EXTERNAL STOP MODE
ly caused by externally generated interference), CONTROL option has been selected low power
the user program will no longer behave in its usual consumption may be achieved in Stop Mode.
fashion and the timer register will thus not be re-
loaded periodically. Consequently the timer will Execution of the STOP instruction is then gov-
decrement down to 00h and reset the MCU. In or- erned by a secondary function associated with the
der to maximise the effectiveness of the Watchdog NMI pin. If a STOP instruction is encountered
function, user software must be written with this when the NMI pin is low, it is interpreted as WAIT,
concept in mind. as described above. If, however, the STOP in-
struction is encountered when the NMI pin is high,
Watchdog behaviour is governed by two options, the Watchdog counter is frozen and the CPU en-
known as WATCHDOG ACTIVATION (i.e. ters STOP mode.
HARDWARE or SOFTWARE) and EXTERNAL
STOP MODE CONTROL (see Table 7 ). When the MCU exits STOP mode (i.e. when an in-
terrupt is generated), the Watchdog resumes its
In the SOFTWARE option, the Watchdog is disa- activity.
bled until bit C of the DWDR register has been set.
Table 7. Recommended Option Choices

Functions Required Recommended Options
Stop Mode & Watchdog EXTERNAL STOP MODE & HARDWARE WATCHDOG
Stop Mode SOFTWARE WATCHDOG
Watchdog HARDWARE WATCHDOG
26/78
25
DIGITAL WATCHDOG (Contd)

The Watchdog is associated with a Data space Figure 17. Watchdog Counter Control
register (Digital WatchDog Register, DWDR, loca-
tion 0D8h) which is described in greater detail in
Section 3.3.1 Digital Watchdog Register (DWDR).
This register is set to 0FEh on Reset: bit C is
cleared to 0, which disables the Watchdog; the D0 C
timer downcounter bits, T0 to T5, and the SR bit
are all set to 1, thus selecting the longest Watch-
dog timer period. This time period can be set to the D1 SR
WATCHDOG CONTROL REGISTER

users requirements by setting the appropriate val-
ue for bits T0 to T5 in the DWDR register. The SR
WATCHDOG COUNTER
RESET
bit must be set to 1, since it is this bit which gen- D2 T5
erates the Reset signal when it changes to 0;
clearing this bit would generate an immediate Re-
set. D3 T4
It should be noted that the order of the bits in the
DWDR register is inverted with respect to the as-
sociated bits in the down counter: bit 7 of the D4 T3
DWDR register corresponds, in fact, to T0 and bit
2 to T5. The user should bear in mind the fact that
these bits are inverted and shifted with respect to D5 T2
the physical counter bits when writing to this regis-
ter. The relationship between the DWDR register
bits and the physical implementation of the Watch- D6 T1
dog timer downcounter is illustrated in Figure 17..
Only the 6 most significant bits may be used to de- D7 T0
fine the time period, since it is bit 6 which triggers
the Reset when it changes to 0. This offers the
user a choice of 64 timed periods ranging from
3,072 to 196,608 clock cycles (with an oscillator 28 OSC 12
frequency of 8MHz, this is equivalent to timer peri-
ods ranging from 384s to 24.576ms). VR02068A
27/78
26

3.3.1 Digital Watchdog Register (DWDR) 3.3.2 Application Notes
Address: 0D8h Read/Write The Watchdog plays an important supporting role
Reset status: 1111 1110b in the high noise immunity of ST62xx devices, and
should be used wherever possible. Watchdog re-
7 0 lated options should be selected on the basis of a
trade-off between application security and STOP
T0 T1 T2 T3 T4 T5 SR C mode availability.
When STOP mode is not required, hardware acti-
Bit 0 = C: Watchdog Control bit vation without EXTERNAL STOP MODE CON-
If the hardware option is selected, this bit is forced TROL should be preferred, as it provides maxi-
high and the user cannot change it (the Watchdog mum security, especially during power-on.
is always active). When the software option is se- When STOP mode is required, hardware activa-
lected, the Watchdog function is activated by set- tion and EXTERNAL STOP MODE CONTROL
ting bit C to 1, and cannot then be disabled (save should be chosen. NMI should be high by default,
by resetting the MCU). to allow STOP mode to be entered when the MCU
When C is kept low the counter can be used as a is idle.
7-bit timer. The NMI pin can be connected to an I/O line (see
This bit is cleared to 0 on Reset. Figure 18.) to allow its state to be controlled by
software. The I/O line can then be used to keep
Bit 1 = SR: Software Reset bit NMI low while Watchdog protection is required, or
This bit triggers a Reset when cleared. to avoid noise or key bounce. When no more
processing is required, the I/O line is released and
When C = 0 (Watchdog disabled) it is the MSB of the device placed in STOP mode for lowest power
the 7-bit timer. consumption.
This bit is set to 1 on Reset. When software activation is selected and the
Bits 2-7 = T5-T0: Downcounter bits Watchdog is not activated, the downcounter may
be used as a simple 7-bit timer (remember that the
It should be noted that the register bits are re-
bits are in reverse order).
versed and shifted with respect to the physical
counter: bit-7 (T0) is the LSB of the Watchdog The software activation option should be chosen
downcounter and bit-2 (T5) is the MSB. only when the Watchdog counter is to be used as
a timer. To ensure the Watchdog has not been un-
These bits are set to 1 on Reset.
expectedly activated, the following instructions
should be executed within the first 27 instructions:
jrr 0, WD, #+3
ldi WD, 0FDH
28/78
27

These instructions test the C bit and Reset the Figure 18. A typical circuit making use of the
MCU (i.e. disable the Watchdog) if the bit is set EXERNAL STOP MODE CONTROL feature
(i.e. if the Watchdog is active), thus disabling the
Watchdog.
In all modes, a minimum of 28 instructions are ex-
ecuted after activation, before the Watchdog can
SWITCH
generate a Reset. Consequently, user software
should load the watchdog counter within the first NMI
27 instructions following Watchdog activation
(software mode), or within the first 27 instructions
executed following a Reset (hardware activation).
I/O
It should be noted that when the GEN bit is low (in-
terrupts disabled), the NMI interrupt is active but
cannot cause a wake up from STOP/WAIT modes.
VR02002
Figure 19. Digital Watchdog Block Diagram
RESET
Q
RSFF -27 -2 8 -12
S R DB 1.7 LOAD SET SET
OSCILLATOR
8 CLOCK
DB0
WRITE
RESET
DATA BUS
VA00010
29/78
28
3.4 INTERRUPTS
The CPU can manage four Maskable Interrupt ically reset by the core at the beginning of the non-
sources, in addition to a Non Maskable Interrupt maskable interrupt service routine.
source (top priority interrupt). Each source is asso- Interrupt request from source #1 can be config-
ciated with a specific Interrupt Vector which con- ured either as edge or level sensitive by setting ac-
tains a Jump instruction to the associated interrupt cordingly the LES bit of the Interrupt Option Regis-
service routine. These vectors are located in Pro- ter (IOR).
gram space (see Table 8 ).
Interrupt request from source #2 are always edge
When an interrupt source generates an interrupt sensitive. The edge polarity can be configured by
request, and interrupt processing is enabled, the setting accordingly the ESB bit of the Interrupt Op-
PC register is loaded with the address of the inter- tion Register (IOR).
rupt vector (i.e. of the Jump instruction), which
then causes a Jump to the relevant interrupt serv- Interrupt request from sources #3 & #4 are level
ice routine, thus servicing the interrupt. sensitive.
Interrupt sources are linked to events either on ex- In edge sensitive mode, a latch is set when a edge
ternal pins, or on chip peripherals. Several events occurs on the interrupt source line and is cleared
can be ORed on the same interrupt source, and when the associated interrupt routine is started.
relevant flags are available to determine which So, the occurrence of an interrupt can be stored,
event triggered the interrupt. until completion of the running interrupt routine be-
fore being processed. If several interrupt requests
The Non Maskable Interrupt request has the high- occurs before completion of the running interrupt
est priority and can interrupt any interrupt routine routine, only the first request is stored.
at any time; the other four interrupts cannot inter-
rupt each other. If more than one interrupt request Storage of interrupt requests is not available in lev-
is pending, these are processed by the processor el sensitive mode. To be taken into account, the
core according to their priority level: source #1 has low level must be present on the interrupt pin when
the higher priority while source #4 the lower. The the MCU samples the line after instruction execu-
priority of each interrupt source is fixed. tion.
At the end of every instruction, the MCU tests the
Table 8. Interrupt Vector Map interrupt lines: if there is an interrupt request the
Interrupt Source Priority Vector Address next instruction is not executed and the appropri-
ate interrupt service routine is executed instead.
Interrupt source #0 1 (FFCh-FFDh)
Interrupt source #1 2 (FF6h-FF7h) Table 9. Interrupt Option Register Description
Interrupt source #2 3 (FF4h-FF5h)
SET Enable all interrupts
Interrupt source #3 4 (FF2h-FF3h) GEN
CLEARED Disable all interrupts
Interrupt source #4 5 (FF0h-FF1h)
Rising edge mode on inter-
SET
rupt source #2
3.4.1 Interrupt request ESB
Falling edge mode on inter-
CLEARED
All interrupt sources but the Non Maskable Inter- rupt source #2
rupt source can be disabled by setting accordingly Level-sensitive mode on in-
SET
the GEN bit of the Interrupt Option Register (IOR). terrupt source #1
LES
This GEN bit also defines if an interrupt source, in- Falling edge mode on inter-
cluding the Non Maskable Interrupt source, can re- CLEARED
rupt source #1
start the MCU from STOP/WAIT modes. OTHERS NOT USED
Interrupt request from the Non Maskable Interrupt
source #0 is latched by a flip flop which is automat-
30/78
29
INTERRUPTS (Contd)
3.4.2 Interrupt Procedure MCU
The interrupt procedure is very similar to a call pro- Automatically the MCU switches back to the nor-
cedure, indeed the user can consider the interrupt mal flag set (or the interrupt flag set) and pops
as an asynchronous call procedure. As this is an the previous PC value from the stack.
asynchronous event, the user cannot know the The interrupt routine usually begins by the identify-
context and the time at which it occurred. As a re- ing the device which generated the interrupt re-
sult, the user should save all Data space registers quest (by polling). The user should save the regis-
which may be used within the interrupt routines. ters which are used within the interrupt routine in a
There are separate sets of processor flags for nor- software stack. After the RETI instruction is exe-
mal, interrupt and non-maskable interrupt modes, cuted, the MCU returns to the main routine.
which are automatically switched and so do not
need to be saved. Figure 20. Interrupt Processing Flow Chart
The following list summarizes the interrupt proce- INS TRU CTION
dure:
MCU
FETCH
The interrupt is detected. INS TRU CTION
The C and Z flags are replaced by the interrupt

flags (or by the NMI flags).
EXEC UTE
The PC contents are stored in the first level of IN STRUC TION
the stack.
The normal interrupt lines are inhibited (NMI still LOAD PC FROM
active). WAS
NO INT ERR UP T VEC TOR
THE INS TRU CTION (FFC/FFD)
The first internal latch is cleared. A RE TI ?
Theassociated interrupt vectoris loaded inthe PC. YES
WARNING: In some circumstances, when a YES

IS THE CORE
ALREADY IN
SET
INTER RU PT MASK
?
maskable interrupt occurs while the ST6 core is in NORMAL MODE?
NORMAL mode and especially during the execu- NO

tion of an ldi IOR, 00h instruction (disabling all C LEAR PUSH THE
maskable interrupts): if the interrupt arrives during INT ERR UP T MASK
PC IN TO THE STACK
the first 3 cycles of the ldi instruction (which is a
4-cycle instruction) the core will switch to interrupt
mode BUT the flags CN and ZN will NOT switch to SELECT
PROGRAM FLAGS
the interrupt pair CI and ZI. SELECT
IN TER NA L MODE FLAG
User
User selected registers are saved within the in- POP
THE STACK ED PC
terrupt service routine (normally on a software
stack).
The source of the interrupt is found by polling the NO C HEC K IF THER E IS
AN IN TER RUP T R EQUEST
?
interrupt flags (if more than one source is associ- AN D INTE RRU PT MASK
ated with the same vector). YES

VA000014
The interrupt is serviced.
Return from interrupt (RETI)
31/78
30
INTERRUPTS (Contd)
3.4.3 Interrupt Option Register (IOR) Bit 5 = ESB: Edge Selection bit.
The Interrupt Option Register (IOR) is used to en- The bit ESB selects the polarity of the interrupt
able/disable the individual interrupt sources and to source #2.
select the operating mode of the external interrupt Bit 4 = GEN: Global Enable Interrupt. When this bit
inputs. This register is write-only and cannot be is set to one, all interrupts are enabled. When this
accessed by single-bit operations. bit is cleared to zero all the interrupts (excluding
Address: 0C8h Write Only NMI) are disabled.
Reset status: 00h When the GEN bit is low, the NMI interrupt is ac-
tive but cannot cause a wake up from STOP/WAIT
7 0 modes.
- LES ESB GEN - - - - This register is cleared on reset.
3.4.4 Interrupt Sources
Bit 7, Bits 3-0 = Unused. Interrupt sources available on the
ST62E62C/T62C are summarized in the Table 10
Bit 6 = LES: Level/Edge Selection bit. with associated mask bit to enable/disable the in-
When this bit is set to one, the interrupt source #1 terrupt request.
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
Table 10. Interrupt Requests and Mask Bits
Address Interrupt
Peripheral Register Mask bit Masked Interrupt Source
Register vector
GENERAL IOR C8h GEN All Interrupts, excluding NMI
TIMER TSCR1 D4h ETI TMZ: TIMER Overflow Vector 4
A/D CONVERTER ADCR D1h EAI EOC: End of Conversion Vector 4
OVIE OVF: AR TIMER Overflow
AR TIMER ARMC D5h CPIE CPF: Successful compare Vector 3
EIE EF: Active edge on ARTIMin
Port PAn ORPA-DRPA C0h-C4h ORPAn-DRPAn PAn pin Vector 1
Port PBn ORPB-DRPB C1h-C5h ORPBn-DRPBn PBn pin Vector 1
Port PCn ORPC-DRPC C2h-C6h ORPCn-DRPCn PCn pin Vector 2
32/78
31
INTERRUPTS (Contd)
Figure 21. Interrupt Block Diagram
FROM REGISTER PORT A,B,C

SINGLE BIT ENABLE
PBE
V DD
PORT A FF
CLK Q 0
PORT B PBE
CLR
Bits
INT #1 (FF6,7)
I Start MUX
1
RESTART FROM
IOR REG. C8H, bit 6 STOP/WAIT
PORT C FF
PBE CLK Q INT #2 (FF4,5)
Bits
CLR
SPIDIV Register
I 2 Start
SPINT bit IOR REG. C8H, bit 5
SPIE bit
OVF
SPIMOD Register OVIE
CPF INT #3 (FF2,3)
AR TIMER
CPIE
EF
EIE
TMZ
TIMER1 INT #4 (FF0,1)
VDD ETI
EOC
ADC EAI
FF NMI (FFC,D)
NMI CLK Q
CLR
I 0 Start
Bit GEN (IOR Register)
VA0426K
33/78
32
3.5 POWER SAVING MODES
The WAIT and STOP modes have been imple- of the processor core prior to the WAIT instruction,
mented in the ST62xx family of MCUs in order to but also on the kind of interrupt request which is
reduce the products electrical consumption during generated. This is described in the following para-
idle periods. These two power saving modes are graphs. The processor core does not generate a
described in the following paragraphs. delay following the occurrence of the interrupt, be-
3.5.1 WAIT Mode cause the oscillator clock is still available and no
stabilisation period is necessary.
The MCU goes into WAIT mode as soon as the 3.5.2 STOP Mode
WAIT instruction is executed. The microcontroller
can be considered as being in a software frozen If the Watchdog is disabled, STOP mode is availa-
state where the core stops processing the pro- ble. When in STOP mode, the MCU is placed in
gram instructions, the RAM contents and peripher- the lowest power consumption mode. In this oper-
al registers are preserved as long as the power ating mode, the microcontroller can be considered
supply voltage is higher than the RAM retention as being frozen, no instruction is executed, the
voltage. In this mode the peripherals are still ac- oscillator is stopped, the RAM contents and pe-
tive. ripheral registers are preserved as long as the
power supply voltage is higher than the RAM re-
WAIT mode can be used when the user wants to tention voltage, and the ST62xx core waits for the
reduce the MCU power consumption during idle occurrence of an external interrupt request or a
periods, while not losing track of time or the capa- Reset to exit the STOP state.
bility of monitoring external events. The active os-
cillator is not stopped in order to provide a clock If the STOP state is exited due to a Reset (by acti-
signal to the peripherals. Timer counting may be vating the external pin) the MCU will enter a nor-
enabled as well as the Timer interrupt, before en- mal reset procedure. Behaviour in response to in-
tering the WAIT mode: this allows the WAIT mode terrupts depends on the state of the processor
to be exited when a Timer interrupt occurs. The core prior to issuing the STOP instruction, and
same applies to other peripherals which use the also on the kind of interrupt request that is gener-
clock signal. ated.
If the WAIT mode is exited due to a Reset (either This case will be described in the following para-
by activating the external pin or generated by the graphs. The processor core generates a delay af-
Watchdog), the MCU enters a normal reset proce- ter occurrence of the interrupt request, in order to
dure. If an interrupt is generated during WAIT wait for complete stabilisation of the oscillator, be-
mode, the MCUs behaviour depends on the state fore executing the first instruction.
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33
POWER SAVING MODE (Contd)

3.5.3 Exit from WAIT and STOP Modes tered will be completed, starting with the
execution of the instruction which follows the
The following paragraphs describe how the MCU STOP or the WAIT instruction, and the MCU is
exits from WAIT and STOP modes, when an inter- still in the interrupt mode. At the end of this rou-
rupt occurs (not a Reset). It should be noted that tine pending interrupts will be serviced in accord-
the restart sequence depends on the original state
of the MCU (normal, interrupt or non-maskable in- ance with their priority.
terrupt mode) prior to entering WAIT or STOP In the event of a non-maskable interrupt, the
mode, as well as on the interrupt type. non-maskable interrupt service routine is proc-
essed first, then the routine in which the WAIT or
Interrupts do not affect the oscillator selection. STOP mode was entered will be completed by
3.5.3.1 Normal Mode executing the instruction following the STOP or
WAIT instruction. The MCU remains in normal
If the MCU was in the main routine when the WAIT interrupt mode.
or STOP instruction was executed, exit from Stop
or Wait mode will occur as soon as an interrupt oc- Notes:
curs; the related interrupt routine is executed and,
on completion, the instruction which follows the To achieve the lowest power consumption during
STOP or WAIT instruction is then executed, pro- RUN or WAIT modes, the user program must take
viding no other interrupts are pending. care of:
3.5.3.2 Non Maskable Interrupt Mode configuring unused I/Os as inputs without pull-up
(these should be externally tied to well defined
If the STOP or WAIT instruction has been execut- logic levels);
ed during execution of the non-maskable interrupt
routine, the MCU exits from the Stop or Wait mode placing all peripherals in their power down
as soon as an interrupt occurs: the instruction modes before entering STOP mode;
which follows the STOP or WAIT instruction is ex-
ecuted, and the MCU remains in non-maskable in- When the hardware activated Watchdog is select-
terrupt mode, even if another interrupt has been ed, or when the software Watchdog is enabled, the
generated. STOP instruction is disabled and a WAIT instruc-
tion will be executed in its place.
3.5.3.3 Normal Interrupt Mode
If all interrupt sources are disabled (GEN low), the
If the MCU was in interrupt mode before the STOP MCU can only be restarted by a Reset. Although
or WAIT instruction was executed, it exits from setting GEN low does not mask the NMI as an in-
STOP or WAIT mode as soon as an interrupt oc- terrupt, it will stop it generating a wake-up signal.
curs. Nevertheless, two cases must be consid-
ered: The WAIT and STOP instructions are not execut-
If the interrupt is a normal one, the interrupt rou- ed if an enabled interrupt request is pending.
tine in which the WAIT or STOP mode was en-
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4 ON-CHIP PERIPHERALS
4.1 I/O PORTS

The MCU features Input/Output lines which may be also written by user software, in conjunction
be individually programmed as any of the following with the related option registers, to select the dif-
input or output configurations: ferent input mode options.
Input without pull-up or interrupt Single-bit operations on I/O registers are possible
Input with pull-up and interrupt but care is necessary because reading in input
mode is done from I/O pins while writing will direct-
Input with pull-up, but without interrupt ly affect the Port data register causing an unde-
Analog input sired change of the input configuration.
Push-pull output The Data Direction registers (DDRx) allow the
data direction (input or output) of each pin to be
Open drain output
set.
The lines are organised as bytewise Ports.
The Option registers (ORx) are used to select the
Each port is associated with 3 registers in Data different port options available both in input and in
space. Each bit of these registers is associated output mode.
with a particular line (for instance, bits 0 of Port A
All I/O registers can be read or written to just as
Data, Direction and Option registers are associat-
ed with the PA0 line of Port A). any other RAM location in Data space, so no extra
RAM cells are needed for port data storage and
The DATA registers (DRx), are used to read the manipulation. During MCU initialization, all I/O reg-
voltage level values of the lines which have been isters are cleared and the input mode with pull-ups
configured as inputs, or to write the logic value of and no interrupt generation is selected for all the
the signal to be output on the lines configured as pins, thus avoiding pin conflicts.
outputs. The port data registers can be read to get
the effective logic levels of the pins, but they can
Figure 22. I/O Port Block Diagram
RESET VDD
SIN CONTROLS
DATA VDD
DIRECTION
REGISTE R
INPUT /OUTPUT
DATA
REGISTE R
SHIFT
REGIST ER
OPTION
REGISTE R
SOUT
TO INTERRU PT
TO ADC
VA00413
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35
I/O PORTS (Contd)

4.1.1 Operating Modes 4.1.1.2 Interrupt Options
Each pin may be individually programmed as input All input lines can be individually connected by
or output with various configurations. software to the interrupt system by programming
This is achieved by writing the relevant bit in the the OR and DR registers accordingly. The inter-
Data (DR), Data Direction (DDR) and Option reg- rupt trigger modes (falling edge, rising edge and
isters (OR). Table 11 illustrates the various port low level) can be configured by software as de-
configurations which can be selected by user soft- scribed in the Interrupt Chapter for each port.
ware. 4.1.1.3 Analog Input Options
4.1.1.1 Input Options Some pins can be configured as analog inputs by
Pull-up, High Impedance Option. All input lines programming the OR and DR registers according-
can be individually programmed with or without an ly. These analog inputs are connected to the on-
internal pull-up by programming the OR and DR chip 8-bit Analog to Digital Converter. ONLY ONE
registers accordingly. If the pull-up option is not pin should be programmed as an analog input at
selected, the input pin will be in the high-imped- any time, since by selecting more than one input
ance state. simultaneously their pins will be effectively short-
ed.
Table 11. I/O Port Option Selection
DDR OR DR Mode Optio n
0 0 0 Input With pull-up, no interrupt
0 0 1 Input No pull-up, no interrupt
0 1 0 Input With pull-up and with interrupt
0 1 1 Input Analog input (when available)
1 0 X Output Open-drain output (20mA sink when available)
1 1 X Output Push-pull output (20mA sink when available)
Note: X = Dont care
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I/O PORTS (Contd)

4.1.2 Safe I/O State Switching Sequence outputs, it is advisable to keep a copy of the data
Switching the I/O ports from one state to another register in RAM. Single bit instructions may then
should be done in a sequence which ensures that be used on the RAM copy, after which the whole
no unwanted side effects can occur. The recom- copy register can be written to the port data regis-
mended safe transitions are illustrated in Figure ter:
23.. All other transitions are potentially risky and SET bit, datacopy
should be avoided when changing the I/O operat- LD a, datacopy
ing mode, as it is most likely that undesirable side- LD DRA, a
effects will be experienced, such as spurious inter-
rupt generation or two pins shorted together by the Warning: Care must also be taken to not use in-
analog multiplexer. structions that act on a whole port register (INC,
Single bit instructions (SET, RES, INC and DEC) DEC, or read operations) when all 8 bits are not
should be used with great caution on Ports Data available on the device. Unavailable bits must be
registers, since these instructions make an implicit masked by software (AND instruction).
read and write back of the entire register. In port
input mode, however, the data register reads from
The WAIT and STOP instructions allow the
the input pins directly, and not from the data regis-
ST62xx to be used in situations where low power
ter latches. Since data register information in input
mode is used to set the characteristics of the input consumption is needed. The lowest power con-
sumption is achieved by configuring I/Os in input
pin (interrupt, pull-up, analog input), these may be
unintentionally reprogrammed depending on the mode with well-defined logic levels.
state of the input pins. As a general rule, it is better The user must take care not to switch outputs with
to limit the use of single bit instructions on data heavy loads during the conversion of one of the
registers to when the whole (8-bit) port is in output analog inputs in order to avoid any disturbance to
mode. In the case of inputs or of mixed inputs and the conversion.
Figure 23. Diagram showing Safe I/O State Transitions
Interrupt Input
pull-up 010* 011 Analog
Input
pull-up (Reset 000 001 Input
state)
Output 100 101

Output
Open Drain Open Drain
Output 110 111

Output
Push-pull Push-pull
Note *. xxx = DDR, OR, DR Bits respectively
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37
I/O PORTS (Contd)

Table 12. I/O Port Option Selections
MODE AVAILABLE ON (1) SCHEMATIC
Input
PA4-PA5
Reset state(
PB0, PB6-PB7
PC2-PC3
Data in
Reset state if PULL-UP PB2-PB3,
option disabled Interrupt
Input PA4-PA5
Reset state PB0,,PB6-PB7
PC2-PC3
Data in
Reset state if PULL-UP
option enabled PB2-PB3 Interrupt
Input PA4-PA5
with pull up PB0, PB2-PB3,PB6-PB7
Data in
with interrupt PC2-PC3
Interrupt
PA4-PA5
Analog Input
PC2-PC3 ADC
PA4-PA5
Open drain output
PC2-PC3
5mA
Data out
Open drain output
PB0, PB2-PB3,PB6-PB7
30mA
PA4-PA5
Push-pull output
PC2-PC3
5mA
Data out
Push-pull output
PB0, PB2-PB3,PB6-PB7
30mA
Note 1. Provided the correct configuration has been selected.
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38
I/O PORTS (Contd)

4.1.3 ARTimer alternate functions ARTIMin/PB6 is connected to the AR Timer input.
It is configured through the port registers as any
When bit PWMOE of register ARMC is low, pin standard pin of port B. To use ARTIMin/PB6 as AR
ARTIMout/PB7 is configured as any standard pin Timer input, it must be configured as input through
of port B through the port registers. When PW- DDRB.
MOE is high, ARTMout/PB7 is the PWM output, in-
dependently of the port registers configuration.
Figure 24. Peripheral Interface Configuration of AR Timer
PID
ARTIMin
ARTIMin DR
AR TIMER
PID
OR
PWMOE
1 ARTIMout
ARTIMout MUX
0 DR
VR01661G
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39
4.2 TIMER
The MCU features an on-chip Timer peripheral, The prescaler input is the internal frequency (fINT)
consisting of an 8-bit counter with a 7-bit program- divided by 12. The prescaler decrements on the
mable prescaler, giving a maximum count of 215. rising edge. Depending on the division factor pro-
Figure 25. shows the Timer Block Diagram. The grammed by PS2, PS1 and PS0 bits in the TSCR
content of the 8-bit counter can be read/written in (see Table 13.), the clock input of the timer/coun-
the Timer/Counter register, TCR, which can be ad- ter register is multiplexed to different sources. For
dressed in Data space as a RAM location at ad- division factor 1, the clock input of the prescaler is
dress 0D3h. The state of the 7-bit prescaler can be also that of timer/counter; for factor 2, bit 0 of the
read in the PSC register at address 0D2h. The prescaler register is connected to the clock input of
control logic device is managed in the TSCR reg- TCR. This bit changes its state at half the frequen-
ister as described in the following paragraphs. cy of the prescaler input clock. For factor 4, bit 1 of
the PSC is connected to the clock input of TCR,
The 8-bit counter is decrement by the output (ris- and so forth. The prescaler initialize bit, PSI, in the
ing edge) coming from the 7-bit prescaler and can TSCR register must be set to allow the prescaler
be loaded and read under program control. When (and hence the counter) to start. If it is cleared, all
it decrements to zero then the TMZ (Timer Zero)bit the prescaler bits are set and the counter is inhib-
in the TSCR is set. If the ETI (Enable Timer Inter- ited from counting. The prescaler can be loaded
rupt) bit in the TSCR is also set, an interrupt re- with any value between 0 and 7Fh, if bit PSI is set.
quest is generated. The Timer interrupt can be The prescaler tap is selected by means of the
used to exit the MCU from WAIT mode. PS2/PS1/PS0 bits in the control register.
Figure 26. illustrates the Timers working principle.
Figure 25. Timer Block Diagram
DATA BUS
8 8 8
6 8-BIT b7 b6 b5 b4 b3 b2 b1 b0
5
COUNTER
4 STATUS/CONTROL
PSC SELECT
3 REGISTER
2 1 OF 7
fINT 1 TMZ ETI D5 D4 PSI PS2 PS1 PS0
12
0
3
INTERRUPT
LINE
VR02070A
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40
TIMER (Contd)
4.2.1 Timer Operation zero, the TMZ bit in the TSCR register is set to
The Timer prescaler is clocked by the prescaler one.
clock input (fINT 12). 4.2.3 Application Notes
The user can select the desired prescaler division TMZ is set when the counter reaches zero; howev-
ratio through the PS2, PS1, PS0 bits. When the er, it may also be set by writing 00h in the TCR
TCR count reaches 0, it sets the TMZ bit in the register or by setting bit 7 of the TSCR register.
TSCR. The TMZ bit can be tested under program The TMZ bit must be cleared by user software
control to perform a timer function whenever it when servicing the timer interrupt to avoid unde-
goes high. sired interrupts when leaving the interrupt service
4.2.2 Timer Interrupt routine. After reset, the 8-bit counter register is
loaded with 0FFh, while the 7-bit prescaler is load-
When the counter register decrements to zero with ed with 07Fh, and the TSCR register is cleared.
the ETI (Enable Timer Interrupt) bit set to one, an This means that the Timer is stopped (PSI=0)
interrupt request associated with Interrupt Vector and the timer interrupt is disabled.
#3 is generated. When the counter decrements to
Figure 26. Timer Working Principle
7-BIT PRESCALER
CLOCK BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6
0 1 2 3 4 5 6 7 PS0
8-1 MULTIPLEXER PS1
PS2
BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7
8-BIT COUNTER
VA00186
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41
TIMER (Contd)
A write to the TCR register will predominate over PSI=0 both counter and prescaler are not run-
the 8-bit counter decrement to 00h function, i.e. if a ning.
write and a TCR register decrement to 00h occur Bit 2, 1, 0 = PS2, PS1, PS0: Prescaler Mux. Se-
simultaneously, the write will take precedence, lect. These bits select the division ratio of the pres-
and the TMZ bit is not set until the 8-bit counter caler register.
reaches 00h again. The values of the TCR and the
PSC registers can be read accurately at any time. Table 13. Prescaler Division Factors
PS2 PS1 PS0 Divided by
4.2.4 Timer Registers 0 0 0 1
Timer Status Control Register (TSCR) 0 0 1 2
Address: 0D4h Read/Write 0 1 0 4
0 1 1 8
7 0
1 0 0 16
TMZ ETI D5 D4 PSI PS2 PS1 PS0 1 0 1 32
1 1 0 64
1 1 1 128
Bit 7 = TMZ: Timer Zero bit
A low-to-high transition indicates that the timer
count register has decrement to zero. This bit Timer Counter Register (TCR)
must be cleared by user software before starting a Address: 0D3h Read/Write
new count.
7 0
Bit 6 = ETI: Enable Timer Interrup
When set, enables the timer interrupt request D7 D6 D5 D4 D3 D2 D1 D0
(vector #3). If ETI=0 the timer interrupt is disabled.
If ETI=1 and TMZ=1 an interrupt request is gener-
ated. Bit 7-0 = D7-D0: Counter Bits.
Bit 5 = D5: Reserved
Must be set to 1. Prescaler Register PSC
Bit 4 = D4 Address: 0D2h Read/Write
Do not care. 7 0
Bit 3 = PSI: Prescaler Initialize Bit
D7 D6 D5 D4 D3 D2 D1 D0
Used to initialize the prescaler and inhibit its count-
ing. When PSI=0 the prescaler is set to 7Fh and
the counter is inhibited. When PSI=1 the prescal- Bit 7 = D7: Always read as 0.
er is enabled to count downwards. As long as Bit 6-0 = D6-D0: Prescaler Bits.
43/78
42
4.3 AUTO-RELOAD TIMER

The Auto-Reload Timer (AR Timer) on-chip pe- the prescaler and counter contents are frozen.
ripheral consists of an 8-bit timer/counter with When TEN is set, the AR counter runs at the rate
compare and capture/reload capabilities and of a of the selected clock source. The counter is
7-bit prescaler with a clock multiplexer, enabling cleared on system reset.
the clock input to be selected as f INT, fINT/3 or an The AR counter may also be initialized by writing
external clock source. A Mode Control Register, to the ARLR load register, which also causes an
ARMC, two Status Control Registers, ARSC0 and immediate copy of the value to be placed in the AR
ARSC1, an output pin, ARTIMout, and an input counter, regardless of whether the counter is run-
pin, ARTIMin, allow the Auto-Reload Timer to be ning or not. Initialization of the counter, by either
used in 4 modes: method, will also clear the ARPSC register, where-
Auto-reload (PWM generation), upon counting will start from a known value.
Output compare and reload on external event 4.3.2 Timer Operating Modes
(PLL), Four different operating modes are available for
Input capture and output compare for time meas- the AR Timer:
urement. Auto-reload Mode with PWM Generation. This
Input capture and output compare for period mode allows a Pulse Width Modulated signal to be
measurement. generated on the ARTIMout pin with minimum
The AR Timer can be used to wake the MCU from Core processing overhead.
WAIT mode either with an internal or with an exter- The free running 8-bit counter is fed by the pres-
nal clock. It also can be used to wake the MCU calers output, and is incremented on every rising
from STOP mode, if used with an external clock edge of the clock signal.
signal connected to the ARTIMin pin. A Load reg- When a counter overflow occurs, the counter is
ister allows the program to read and write the automatically reloaded with the contents of the Re-
counter on the fly. load/Capture Register, ARCC, and ARTIMout is
4.3.1 AR Timer Description set. When the counter reaches the value con-
The AR COUNTER is an 8-bit up-counter incre- tained in the compare register (ARCP), ARTIMout
mented on the input clocks rising edge. The coun- is reset.
ter is loaded from the ReLoad/Capture Register, On overflow, the OVF flag of the ARSC0 register is
ARRC, for auto-reload or capture operations, as set and an overflow interrupt request is generated
well as for initialization. Direct access to the AR if the overflow interrupt enable bit, OVIE, in the
counter is not possible; however, by reading or Mode Control Register (ARMC), is set. The OVF
writing the ARLR load register, it is possible to flag must be reset by the user software.
read or write the counters contents on the fly. When the counter reaches the compare value, the
The AR Timers input clock can be either the inter- CPF flag of the ARSC0 register is set and a com-
nal clock (from the Oscillator Divider), the internal pare interrupt request is generated, if the Compare
clock divided by 3, or the clock signal connected to Interrupt enable bit, CPIE, in the Mode Control
the ARTIMin pin. Selection between these clock Register (ARMC), is set. The interrupt service rou-
sources is effected by suitably programming bits tine may then adjust the PWM period by loading a
CC0-CC1 of the ARSC1 register. The output of the new value into ARCP. The CPF flag must be reset
AR Multiplexer feeds the 7-bit programmable AR by user software.
Prescaler, ARPSC, which selects one of the 8 The PWM signal is generated on the ARTIMout
available taps of the prescaler, as defined by pin (refer to the Block Diagram). The frequency of
PSC0-PSC2 in the AR Mode Control Register. this signal is controlled by the prescaler setting
Thus the division factor of the prescaler can be set and by the auto-reload value present in the Re-
to 2n (where n = 0, 1,..7). load/Capture register, ARRC. The duty cycle of
The clock input to the AR counter is enabled by the the PWM signal is controlled by the Compare Reg-
TEN (Timer Enable) bit in the ARMC register. ister, ARCP.
When TEN is reset, the AR counter is stopped and
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AUTO-RELOAD TIMER (Contd)

Figure 27. AR Timer Block Diagram
DATA BUS
DDRB7
DRB7
AR COMPARE
REGISTER
8
PB7/
ARTIMout
CPF
COMPARE R
S
8
PWMOE
f INT OVF OVF

M
7-Bit 8-Bit OVIE
f INT /3 U
AR PRESCALER AR COUNTER LOAD
X TCLD
CC0-CC1 PS0-PS2 EIE

EF
AR TIMER
8
INTERRUPT
CPF
CPIE
8 8
PB6/
ARTIMin
SL0-SL1
AR AR
EF
SYNCHRO RELOAD/CAPTURE LOAD
REGISTER REGISTER
8 8
DATA BUS
VR01660A
45/78
44

It should be noted that the reload values will also The ARTC counter is initialized by writing to the
affect the value and the resolution of the duty cycle ARRC register and by then setting the TCLD (Tim-
of PWM output signal. To obtain a signal on ARTI- er Load) and the TEN (Timer Clock Enable) bits in
Mout, the contents of the ARCP register must be the Mode Control register, ARMC.
greater than the contents of the ARRC register. Enabling and selection of the clock source is con-
The maximum available resolution for the ARTI- trolled by the CC0, CC1, SL0 and SL1 bits in the
Mout duty cycle is: Status Control Register, ARSC1. The prescaler di-
Resolution = 1/[255-(ARRC)] vision ratio is selected by the PS0, PS1 and PS2
bits in the ARSC1 register.
Where ARRC is the content of the Reload/Capture
register. The compare value loaded in the Com- In Auto-reload Mode, any of the three available
pare Register, ARCP, must be in the range from clock sources can be selected: Internal Clock, In-
(ARRC) to 255. ternal Clock divided by 3 or the clock signal
present on the ARTIMin pin.
Figure 28. Auto-reload Timer PWM Function
COUNTER
255
COMPARE
VALUE
RELOAD
REGISTER
000
t
PWM OUTPUT
t
VR001852
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45

Capture Mode with PWM Generation. In this the count is incremented on every clock rising
mode, the AR counter operates as a free running edge.
8-bit counter fed by the prescaler output. The Each counter overflow sets the ARTIMout pin. A
counter is incremented on every clock rising edge. match between the counter and ARCP (Compare
An 8-bit capture operation from the counter to the Register) resets the ARTIMout pin and sets the
ARRC register is performed on every active edge compare flag, CPF. A compare interrupt request is
on the ARTIMin pin, when enabled by Edge Con- generated if the related compare interrupt enable
trol bits SL0, SL1 in the ARSC1 register. At the bit, CPIE, is set. A PWM signal is generated on
same time, the External Flag, EF, in the ARSC0 ARTIMout. The CPF flag must be reset by user
register is set and an external interrupt request is software.
generated if the External Interrupt Enable bit, EIE, Initialization of the counter is as described in the
in the ARMC register, is set. The EF flag must be previous paragraph. In addition, if the external AR-
reset by user software. TIMin input is enabled, an active edge on the input
Each ARTC overflow sets ARTIMout, while a pin will copy the contents of the ARRC register into
match between the counter and ARCP (Compare the counter, whether the counter is running or not.
Register) resets ARTIMout and sets the compare Notes:
flag, CPF. A compare interrupt request is generat-
ed if the related compare interrupt enable bit, The allowed AR Timer clock sources are the fol-
CPIE, is set. A PWM signal is generated on ARTI- lowing:
Mout. The CPF flag must be reset by user soft- AR Timer Mode Clock Sources
ware.
Auto-reload mode fINT, fINT/3, ARTIMin
The frequency of the generated signal is deter- Capture mode fINT, fINT/3
mined by the prescaler setting. The duty cycle is
Capture/Reset mode fINT, fINT/3
determined by the ARCP register.
External Load mode fINT, fINT/3
Initialization and reading of the counter are identi-
cal to the auto-reload mode (see previous descrip- The clock frequency should not be modified while
tion). the counter is counting, since the counter may be
Enabling and selection of clock sources is control- set to an unpredictable value. For instance, the
led by the CC0 and CC1 bits in the AR Status Con- multiplexer setting should not be modified while
trol Register, ARSC1. the counter is counting.
The prescaler division ratio is selected by pro- Loading of the counter by any means (by auto-re-
gramming the PS0, PS1 and PS2 bits in the load, through ARLR, ARRC or by the Core) resets
ARSC1 Register. the prescaler at the same time.
In Capture mode, the allowed clock sources are Care should be taken when both the Capture inter-
the internal clock and the internal clock divided by rupt and the Overflow interrupt are used. Capture
3; the external ARTIMin input pin should not be and overflow are asynchronous. If the capture oc-
used as a clock source. curs when the Overflow Interrupt Flag, OVF, is
high (between counter overflow and the flag being
Capture Mode with Reset of counter and pres-
caler, and PWM Generation. This mode is identi- reset by software, in the interrupt routine), the Ex-
cal to the previous one, with the difference that a ternal Interrupt Flag, EF, may be cleared simul-
capture condition also resets the counter and the taneusly without the interrupt being taken into ac-
count.
prescaler, thus allowing easy measurement of the
time between two captures (for input period meas- The solution consists in resetting the OVF flag by
urement on the ARTIMin pin). writing 06h in the ARSC0 register. The value of EF
is not affected by this operation. If an interrupt has
Load on External Input. The counter operates as
a free running 8-bit counter fed by the prescaler. occured, it will be processed when the MCU exits
from the interrupt routine (the second interrupt is
latched).
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46

4.3.3 AR Timer Registers ARSC0 register is also set, an interrupt request is
AR Mode Control Register (ARMC) generated.
Address: D5h Read/Write Bit 1-0 = ARMC1-ARMC0: Mode Control Bits 1-0.
These are the operating mode control bits. The fol-
Reset status: 00h lowing bit combinations will select the various op-
erating modes:
7 0
ARMC1 ARMC0 Operating Mode
TCLD TEN PWMOE EIE CPIE OVIE ARMC1 ARMC0
0 0 Auto-reload Mode
0 1 Capture Mode
The AR Mode Control Register ARMC is used to Capture Mode with Reset
program the different operating modes of the AR 1 0
of ARTC and ARPSC
Timer, to enable the clock and to initialize the Load on External Edge
counter. It can be read and written to by the Core 1 1
Mode
and it is cleared on system reset (the AR Timer is
disabled).
AR Timer Status/Control Registers ARSC0 &
Bit 7 = TLCD: Timer Load Bit. This bit, when set, ARSC1. These registers contain the AR Timer sta-
will cause the contents of ARRC register to be tus information bits and also allow the program-
loaded into the counter and the contents of the ming of clock sources, active edge and prescaler
prescaler register, ARPSC, are cleared in order to multiplexer setting.
initialize the timer before starting to count. This bit ARSC0 register bits 0,1 and 2 contain the interrupt
is write-only and any attempt to read it will yield a
flags of the AR Timer. These bits are read normal-
logical zero.
ly. Each one may be reset by software. Writing a
Bit 6 = TEN: Timer Clock Enable. This bit, when one does not affect the bit value.
set, allows the timer to count. When cleared, it will
AR Status Control Register 0 (ARSC0)
stop the timer and freeze ARPSC and ARTSC.
Address: D6h Read/Clear
Bit 5 = PWMOE: PWM Output Enable. This bit,
when set, enables the PWM output on the ARTI- 7 0
Mout pin. When reset, the PWM output is disabled.
Bit 4 = EIE: External Interrupt Enable. This bit, D7 D6 D5 D4 D3 EF CPF OVF
when set, enables the external interrupt request.
When reset, the external interrupt request is Bits 7-3 = D7-D3: Unused
masked. If EIE is set and the related flag, EF, in
Bit 2 = EF: External Interrupt Flag. This bit is set by
the ARSC0 register is also set, an interrupt re-
quest is generated. any active edge on the external ARTIMin input pin.
The flag is cleared by writing a zero to the EF bit.
Bit 3 = CPIE: Compare Interrupt Enable. This bit,
when set, enables the compare interrupt request. Bit 1 = CPF: Compare Interrupt Flag. This bit is set
if the contents of the counter and the ARCP regis-
If CPIE is reset, the compare interrupt request is
ter are equal. The flag is cleared by writing a zero
masked. If CPIE is set and the related flag, CPF, in
to the CPF bit.
the ARSC0 register is also set, an interrupt re-
quest is generated. Bit 0 = OVF: Overflow Interrupt Flag. This bit is set
by a transition of the counter from FFh to 00h
Bit 2 = OVIE: Overflow Interrupt. This bit, when
set, enables the overflow interrupt request. If OVIE (overflow). The flag is cleared by writing a zero to
the OVF bit.
is reset, the compare interrupt request is masked.
If OVIE is set and the related flag, OVF in the
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47

AR Status Control Register 1(ARSC1) AR Load Register ARLR. The ARLR load register
Address: D7h Read/Write is used to read or write the ARTC counter register
on the fly (while it is counting). The ARLR regis-
7 0 ter is not affected by system reset.
AR Load Register (ARLR)
PS2 PS1 PS0 D4 SL1 SL0 CC1 CC0
Address: DBh Read/Write
Bist 7-5 = PS2-PS0: Prescaler Division Selection 7 0
Bits 2-0. These bits determine the Prescaler divi-
sion ratio. The prescaler itself is not affected by D7 D6 D5 D4 D3 D2 D1 D0
these bits. The prescaler division ratio is listed in the
following table: Bit 7-0 = D7-D0: Load Register Data Bits. These
are the load register data bits.
Table 14. Prescaler Division Ratio Selection
PS2 PS1 PS0 ARPSC Division Ratio
AR Reload/Capture Register. The ARRC re-
0 0 0 1 load/capture register is used to hold the auto-re-
0 0 1 2 load value which is automatically loaded into the
0 1 0 4 counter when overflow occurs.
0 1 1 8 AR Reload/Capture (ARRC)
1 0 0 16 Address: D9h Read/Write
1 0 1 32
7 0
1 1 0 64
1 1 1 128 D7 D6 D5 D4 D3 D2 D1 D0
Bit 4 = D4: Reserved. Must be kept reset.

Bit 3-2 = SL1-SL0: Timer Input Edge Control Bits 1- Bit 7-0 = D7-D0: Reload/Capture Data Bits. These
0. These bits control the edge function of the Timer are the Reload/Capture register data bits.
input pinfor external synchronization. If bit SL0 is re-
set, edge detection is disabled; if set edge detection AR Compare Register. The CP compare register
is enabled. If bit SL1 is reset, the AR Timer input pin is used to hold the compare value for the compare
is rising edge sensitive; if set, it is falling edge sen- function.
sitive.
AR Compare Register (ARCP)
SL1 SL0 Edge Detection
Address: DAh Read/Write
X 0 Disabled
0 1 Rising Edge 7 0
1 1 Falling Edge
D7 D6 D5 D4 D3 D2 D1 D0
Bit 1-0 = CC1-CC0: Clock Source Select Bit 1-0.

These bits select the clock source for the AR Timer Bit 7-0 = D7-D0: Compare Data Bits. These are
through the AR Multiplexer. The programming of the Compare register data bits.
the clocksources is explained in the following Table
15 :
Table 15. Clock Source Selection.
CC1 CC0 Clock Source
0 0 Fint
0 1 Fint Divided by 3
1 0 ARTIMin Input Clock
1 1 Reserved
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48
4.4 A/D CONVERTER (ADC)

The A/D converter peripheral is an 8-bit analog to sion to allow stabilisation of the A/D converter.
digital converter with analog inputs as alternate I/O This action is also needed before entering WAIT
functions (the number of which is device depend- mode, since the A/D comparator is not automati-
ent), offering 8-bit resolution with a typical conver- cally disabled in WAIT mode.
sion time of 70us (at an oscillator clock frequency During Reset, any conversion in progress is
of 8MHz). stopped, the control register is reset to 40h and the
The ADC converts the input voltage by a process ADC interrupt is masked (EAI=0).
of successive approximations, using a clock fre-
quency derived from the oscillator with a division Figure 29. ADC Block Diagram
factor of twelve. With an oscillator clock frequency
less than 1.2MHz, conversion accuracy is de-
creased. INTERRUPT
CLOCK
Selection of the input pin is done by configuring Ain CONVERTER RESET
the related I/O line as an analog input via the Op- AVSS
tion and Data registers (refer to I/O ports descrip- AVDD
tion for additional information). Only one I/O line
must be configured as an analog input at any time.
The user must avoid any situation in which more
than one I/O pin is selected as an analog input si- CONTROL REGISTER RESULT REGISTER
multaneously, to avoid device malfunction.
8 8
The ADC uses two registers in the data space: the
ADC data conversion register, ADR, which stores CORE CORE
the conversion result, and the ADC control regis- CONTROL SIGNALS VA00418
ter, ADCR, used to program the ADC functions.
A conversion is started by writing a 1 to the Start
bit (STA) in the ADC control register. This auto- 4.4.1 Application Notes
matically clears (resets to 0) the End Of Conver- The A/D converter does not feature a sample and
sion Bit (EOC). When a conversion is complete, hold circuit. The analog voltage to be measured
the EOC bit is automatically set to 1, in order to should therefore be stable during the entire con-
flag that conversion is complete and that the data version cycle. Voltage variation should not exceed
in the ADC data conversion register is valid. Each 1/2 LSB for the optimum conversion accuracy. A
conversion has to be separately initiated by writing low pass filter may be used at the analog input
to the STA bit. pins to reduce input voltage variation during con-
The STA bit is continuously scanned so that, if the version.
user sets it to 1 while a previous conversion is in When selected as an analog channel, the input pin
progress, a new conversion is started before com- is internally connected to a capacitor Cad of typi-
pleting the previous one. The start bit (STA) is a cally 12pF. For maximum accuracy, this capacitor
write only bit, any attempt to read it will show a log- must be fully charged at the beginning of conver-
ical 0. sion. In the worst case, conversion starts one in-
The A/D converter features a maskable interrupt struction (6.5 s) after the channel has been se-
associated with the end of conversion. This inter- lected. In worst case conditions, the impedance,
rupt is associated with interrupt vector #4 and oc- ASI, of the analog voltage source is calculated us-
curs when the EOC bit is set (i.e. when a conver- ing the following formula:
sion is completed). The interrupt is masked using 6.5s = 9 x Cad x ASI
the EAI (interrupt mask) bit in the control register.
(capacitor charged to over 99.9%), i.e. 30 k in-
The power consumption of the device can be re- cluding a 50% guardband. ASI can be higher if Cad
duced by turning off the ADC peripheral. This is has been charged for a longer period by adding in-
done by setting the PDS bit in the ADC control reg- structions before the start of conversion (adding
ister to 0. If PDS=1, the A/D is powered and en- more than 26 CPU cycles is pointless).
abled for conversion. This bit must be set at least
one instruction before the beginning of the conver-
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A/D CONVERTER (Contd)

Since the ADC is on the same chip as the micro- the noise during the conversion. But the first con-
processor, the user should not switch heavily load- version step is performed before the execution of
ed output signals during conversion, if high preci- the WAIT when most of clocks signals are still en-
sion is required. Such switching will affect the sup- abled . The key is to synchronize the ADC start
ply voltages used as analog references. with the effective execution of the WAIT. This is
The accuracy of the conversion depends on the achieved by setting ADC SYNC option. This way,
quality of the power supplies (V DD and VSS). The ADC conversion starts in effective WAIT for maxi-
user must take special care to ensure a well regu- mum accuracy.
lated reference voltage is present on the VDD and Note: With this extra option, it is mandatory to ex-
VSS pins (power supply voltage variations must be ecute WAIT instruction just after ADC start instruc-
less than 5V/ms). This implies, in particular, that a tion. Insertion of any extra instruction may cause
suitable decoupling capacitor is used at the VDD spurious interrupt request at ADC interrupt vector.
pin. A/D Converter Control Register (ADCR)
The converter resolution is given by:: Address: 0D1h Read/Write
7 0
V DD V SS
---------
------------------- EAI EOC STA PDS D3 D2 D1 D0
256
Bit 7 = EAI: Enable A/D Interrupt. If this bit is set to

The Input voltage (Ain) which is to be converted 1 the A/D interrupt is enabled, when EAI=0 the
must be constant for 1s before conversion and interrupt is disabled.
remain constant during conversion.
Bit 6 = EOC: End of conversion. Read Only. This
Conversion resolution can be improved if the pow-
read only bit indicates when a conversion has
er supply voltage (VDD ) to the microcontroller is been completed. This bit is automatically reset to
lowered.
0 when the STA bit is written. If the user is using
In order to optimise conversion resolution, the user the interrupt option then this bit can be used as an
can configure the microcontroller in WAIT mode, interrupt pending bit. Data in the data conversion
because this mode minimises noise disturbances register are valid only when this bit is set to 1.
and power supply variations due to output switch- Bit 5 = STA: Start of Conversion. Write Only. Writ-
ing. Nevertheless, the WAIT instruction should be ing a 1 to this bit will start a conversion on the se-
executed as soon as possible after the beginning
lected channel and automatically reset to 0 the
of the conversion, because execution of the WAIT
EOC bit. If the bit is set again when a conversion is
instruction may cause a small variation of the VDD in progress, the present conversion is stopped and
voltage. The negative effect of this variation is min-
a new one will take place. This bit is write only, any
imized at the beginning of the conversion when the
attempt to read it will show a logical zero.
converter is less sensitive, rather than at the end
of conversion, when the less significant bits are Bit 4 = PDS: Power Down Selection. This bit acti-
determined. vates the A/D converter if set to 1. Writing a 0 to
this bit will put the ADC in power down mode (idle
The best configuration, from an accuracy stand- mode).
point, is WAIT mode with the Timer stopped. In-
deed, only the ADC peripheral and the oscillator Bit 3-0 = D3-D0. Not used
are then still working. The MCU must be woken up
from WAIT mode by the ADC interrupt at the end
A/D Converter Data Register (ADR)
of the conversion. It should be noted that waking
up the microcontroller could also be done using Address: 0D0h Read only
the Timer interrupt, but in this case the Timer will
be working and the resulting noise could affect 7 0
conversion accuracy.
D7 D6 D5 D4 D3 D2 D1 D0
One extra feature is available in the ADC to get a
better accuracy. In fact, each ADC conversion has
to be followed by a WAIT instruction to minimize Bit 7-0 = D7-D0: 8 Bit A/D Conversion Result.
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5 SOFTWARE
5.1 ST6 ARCHITECTURE

The ST6 software has been designed to fully use bits of the opcode with the byte following the op-
the hardware in the most efficient way possible code. The instructions (JP, CALL) which use the
while keeping byte usage to a minimum; in short, extended addressing mode are able to branch to
to provide byte efficient programming capability. any address of the 4K bytes Program space.
The ST6 core has the ability to set or clear any
register or RAM location bit of the Data space with An extended addressing mode instruction is two-
a single instruction. Furthermore, the program byte long.
may branch to a selected address depending on
Program Counter Relative. The relative address-
the status of any bit of the Data space. The carry
bit is stored with the value of the bit when the SET ing mode is only used in conditional branch in-
structions. The instruction is used to perform a test
or RES instruction is processed.
and, if the condition is true, a branch with a span of
-15 to +16 locations around the address of the rel-
5.2 ADDRESSING MODES ative instruction. If the condition is not true, the in-
struction which follows the relative instruction is
The ST6 core offers nine addressing modes, executed. The relative addressing mode instruc-
which are described in the following paragraphs. tion is one-byte long. The opcode is obtained in
Three different address spaces are available: Pro- adding the three most significant bits which char-
gram space, Data space, and Stack space. Pro- acterize the kind of the test, one bit which deter-
gram space contains the instructions which are to mines whether the branch is a forward (when it is
be executed, plus the data for immediate mode in- 0) or backward (when it is 1) branch and the four
structions. Data space contains the Accumulator, less significant bits which give the span of the
the X,Y,V and W registers, peripheral and In- branch (0h to Fh) which must be added or sub-
put/Output registers, the RAM locations and Data tracted to the address of the relative instruction to
ROM locations (for storage of tables and con- obtain the address of the branch.
stants). Stack space contains six 12-bit RAM cells
used to stack the return addresses for subroutines Bit Direct. In the bit direct addressing mode, the
and interrupts. bit to be set or cleared is part of the opcode, and
the byte following the opcode points to the ad-
Immediate. In the immediate addressing mode, dress of the byte in which the specified bit must be
the operand of the instruction follows the opcode set or cleared. Thus, any bit in the 256 locations of
location. As the operand is a ROM byte, the imme- Data space memory can be set or cleared.
diate addressing mode is used to access con-
stants which do not change during program execu- Bit Test & Branch. The bit test and branch ad-
tion (e.g., a constant used to initialize a loop coun- dressing mode is a combination of direct address-
ter). ing and relative addressing. The bit test and
branch instruction is three-byte long. The bit iden-
Direct. In the direct addressing mode, the address tification and the tested condition are included in
of the byte which is processed by the instruction is the opcode byte. The address of the byte to be
stored in the location which follows the opcode. Di- tested follows immediately the opcode in the Pro-
rect addressing allows the user to directly address gram space. The third byte is the jump displace-
the 256 bytes in Data Space memory with a single ment, which is in the range of -127 to +128. This
two-byte instruction. displacement can be determined using a label,
which is converted by the assembler.
Short Direct. The core can address the four RAM
registers X,Y,V,W (locations 80h, 81h, 82h, 83h) in Indirect. In the indirect addressing mode, the byte
the short-direct addressing mode. In this case, the processed by the register-indirect instruction is at
instruction is only one byte and the selection of the the address pointed by the content of one of the in-
location to be processed is contained in the op- direct registers, X or Y (80h,81h). The indirect reg-
code. Short direct addressing is a subset of the di- ister is selected by the bit 4 of the opcode. A regis-
rect addressing mode. (Note that 80h and 81h are ter indirect instruction is one byte long.
also indirect registers).
Inherent. In the inherent addressing mode, all the
Extended. In the extended addressing mode, the information necessary to execute the instruction is
12-bit address needed to define the instruction is contained in the opcode. These instructions are
obtained by concatenating the four less significant one byte long.
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51
5.3 INSTRUCTION SET
The ST6 core offers a set of 40 basic instructions Load & Store. These instructions use one, two or
which, when combined with nine addressing three bytes in relation with the addressing mode.
modes, yield 244 usable opcodes. They can be di- One operand is the Accumulator for LOAD and the
vided into six different types: load/store, arithme- other operand is obtained from data memory using
tic/logic, conditional branch, control instructions, one of the addressing modes.
jump/call, and bit manipulation. The following par-
agraphs describe the different types. For Load Immediate one operand can be any of
the 256 data space bytes while the other is always
All the instructions belonging to a given type are immediate data.
presented in individual tables.
Table 16. Load & Store Instructions
Flags
Instruction Addressing Mode Bytes Cycles
Z C
LD A, X Short Direct 1 4 *
LD A, Y Short Direct 1 4 *
LD A, V Short Direct 1 4 *
LD A, W Short Direct 1 4 *
LD X, A Short Direct 1 4 *
LD Y, A Short Direct 1 4 *
LD V, A Short Direct 1 4 *
LD W, A Short Direct 1 4 *
LD A, rr Direct 2 4 *
LD rr, A Direct 2 4 *
LD A, (X) Indirect 1 4 *
LD A, (Y) Indirect 1 4 *
LD (X), A Indirect 1 4 *
LD (Y), A Indirect 1 4 *
LDI A, #N Immediate 2 4 *
LDI rr, #N Immediate 3 4 * *
Notes:
X,Y. Indirect Register Pointers, V & W Short Direct Registers
# . Immediate data (stored in ROM memory)
rr. Data space register
. Affected
* . Not Affected
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52
INSTRUCTION SET (Contd)

Arithmetic and Logic. These instructions are tent or an immediate value in relation with the ad-
used to perform the arithmetic calculations and dressing mode. In CLR, DEC, INC instructions the
logic operations. In AND, ADD, CP, SUB instruc- operand can be any of the 256 data space ad-
tions one operand is always the accumulator while dresses. In COM, RLC, SLA the operand is always
the other can be either a data space memory con- the accumulator.
Table 17. Arithmetic & Logic Instructions
Flags
Z C
ADD A, (X) Indirect 1 4
ADD A, (Y) Indirect 1 4
ADD A, rr Direct 2 4
ADDI A, #N Immediate 2 4
AND A, (X) Indirect 1 4
AND A, (Y) Indirect 1 4
AND A, rr Direct 2 4
ANDI A, #N Immediate 2 4
CLR A Short Direct 2 4
CLR r Direct 3 4 * *
COM A Inherent 1 4
CP A, (X) Indirect 1 4
CP A, (Y) Indirect 1 4
CP A, rr Direct 2 4
CPI A, #N Immediate 2 4
DEC X Short Direct 1 4 *
DEC Y Short Direct 1 4 *
DEC V Short Direct 1 4 *
DEC W Short Direct 1 4 *
DEC A Direct 2 4 *
DEC rr Direct 2 4 *
DEC (X) Indirect 1 4 *
DEC (Y) Indirect 1 4 *
INC X Short Direct 1 4 *
INC Y Short Direct 1 4 *
INC V Short Direct 1 4 *
INC W Short Direct 1 4 *
INC A Direct 2 4 *
INC rr Direct 2 4 *
INC (X) Indirect 1 4 *
INC (Y) Indirect 1 4 *
RLC A Inherent 1 4
SLA A Inherent 2 4
SUB A, (X) Indirect 1 4
SUB A, (Y) Indirect 1 4
SUB A, rr Direct 2 4
SUBI A, #N Immediate 2 4
Notes:
X,Y.Indirect Register Pointers, V & W Short Direct RegistersD. Affected
# . Immediate data (stored in ROM memory)* . Not Affected
rr. Data space register
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53
INSTRUCTION SET (Contd)

Conditional Branch. The branch instructions Control Instructions. The control instructions
achieve a branch in the program when the select- control the MCU operations during program exe-
ed condition is met. cution.
Bit Manipulation Instructions. These instruc- Jump and Call. These two instructions are used
tions can handle any bit in data space memory. to perform long (12-bit) jumps or subroutines call
One group either sets or clears. The other group inside the whole program space.
(see Conditional Branch) performs the bit test
branch operations.
Table 18. Conditional Branch Instructions
Flags
Instruction Branch If Bytes Cycles
Z C
JRC e C=1 1 2 * *
JRNC e C=0 1 2 * *
JRZ e Z=1 1 2 * *
JRNZ e Z=0 1 2 * *
JRR b, rr, ee Bit = 0 3 5 *
JRS b, rr, ee Bit = 1 3 5 *
Notes :
b. 3-bit address rr. Data space register
e. 5 bit signed displacement in the range -15 to +16<F128M> . Affected. The tested bit is shifted into carry.
ee. 8 bit signed displacement in the range -126 to +129 * . Not Affected
Table 19. Bit Manipulation Instructions

Flags
Z C
SET b,rr Bit Direct 2 4 * *
RES b,rr Bit Direct 2 4 * *
Notes:
b. 3-bit address; * . Not<M> Affected
rr. Data space register;
Table 20. Control Instructions

Flags
Z C
NOP Inherent 1 2 * *
RET Inherent 1 2 * *
RETI Inherent 1 2
STOP (1) Inherent 1 2 * *
WAIT Inherent 1 2 * *
Notes:
1. This instruction is deactivated<N>and a WAI T is automatically executed instead of a STOP if the watchdog function is selected.
. Affected
*. Not Affected
Table 21. Jump & Call Instructions

Instruction Flags
Addressing Mode Bytes Cycles
Z C
CALL abc Extended 2 4 * *
JP abc Extended 2 4 * *
Notes:
abc. 12-bit address;
* . Not Affected
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54
Opcode Map Summary. The following table contains an opcode map for the instructions used by the ST6
LOW LOW
0 1 2 3 4 5 6 7
0000 0001 0010 0011 0100 0101 0110 0111
HI HI
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 LD
0 e abc e b0,rr,ee e # e a,(x) 0
0000 0000
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 4 LDI
1 e abc e b0,rr,ee e x e a,nn 1
0001 0001
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 CP
0010 0010
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC 4 CPI
3 e abc e b4,rr,ee e a,x e a,nn 3
0011 0011
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 ADD
0100 0100
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 4 ADDI
5 e abc e b2,rr,ee e y e a,nn 5
0101 0101
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 INC
6 e abc e b6,rr,ee e # e (x) 6
0110 0110
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC
7 e abc e b6,rr,ee e a,y e # 7
0111 0111
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 LD
8 e abc e b1,rr,ee e # e (x),a 8
1000 1000
2 RNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC
9 e abc e b1,rr,ee e v e # 9
1001 1001
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 AND
A e abc e b5,rr,ee e # e a,(x) A
1010 1010
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC 4 ANDI
B e abc e b5,rr,ee e a,v e a,nn B
1011 1011
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 SUB
C e abc e b3,rr,ee e # e a,(x) C
1100 1100
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 4 SUBI
D e abc e b3,rr,ee e w e a,nn D
1101 1101
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 DEC
E e abc e b7,rr,ee e # e (x) E
1110 1110
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC
F e abc e b7,rr,ee e a,w e # F
1111 1111
Abbreviations for Addressing Modes: Legend:

dir Direct # Indicates Ill egal Instructions Cycle
sd Short Direct e 5 Bit Displacement 2 JRC Mnemonic
imm Immediate b 3 Bit Address Operand e
inh Inherent rr 1byte dataspace address
Bytes 1 prc
ext Extended nn 1 byte immediate data
b.d Bit Direct abc 12 bit address
Addressing Mode
bt Bit Test ee 8 bit Displacement
pcr Program Counter Relative
ind Indirect
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55
Opcode Map Summary (Continued)

LOW LOW
8 9 A B C D E F
1000 1001 1010 1011 1100 1101 1110 1111
HI HI
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 LDI 2 JRC 4 LD
0 e abc e b0,rr e rr,nn e a,(y) 0
0000 0000
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 3 imm 1 prc 1 ind
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 LD
1 e abc e b0,rr e x e a,rr 1
0001 0001
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 COM 2 JRC 4 CP
2 e abc e b4,rr e a e a,(y) 2
0010 0010
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 prc 1 ind
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 CP
3 e abc e b4,rr e x,a e a,rr 3
0011 0011
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 RETI 2 JRC 4 ADD
4 e abc e b2,rr e e a,(y) 4
0100 0100
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 ADD
5 e abc e b2,rr e y e a,rr 5
0101 0101
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 STOP 2 JRC 4 INC
6 e abc e b6,rr e e (y) 6
0110 0110
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 INC
7 e abc e b6,rr e y,a e rr 7
0111 0111
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 JRC 4 LD
8 e abc e b1,rr e # e (y),a 8
1000 1000
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 prc 1 ind
2 RNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 LD
9 e abc e b1,rr e v e rr,a 9
1001 1001
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 RCL 2 JRC 4 AND
A e abc e b5,rr e a e a,(y) A
1010 1010
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 AND
B e abc e b5,rr e v,a e a,rr B
1011 1011
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 RET 2 JRC 4 SUB
C e abc e b3,rr e e a,(y) C
1100 1100
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 SUB
D e abc e b3,rr e w e a,rr D
1101 1101
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 WAIT 2 JRC 4 DEC
E e abc e b7,rr e e (y) E
1110 1110
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 DEC
F e abc e b7,rr e w,a e rr F
1111 1111
Abbreviations for Addressing Modes: Legend:

dir Direct # Indicates Ill egal Instructions Cycle
sd Short Direct e 5 Bit Displacement 2 JRC Mnemonic
imm Immediate b 3 Bit Address Operand e
inh Inherent rr 1byte dataspace address
Bytes 1 prc
ext Extended nn 1 byte immediate data
b.d Bit Direct abc 12 bit address
Addressing Mode
bt Bit Test ee 8 bit Displacement
pcr Program Counter Relative
ind Indirect
57/78
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6 ELECTRICAL CHARACTERISTICS
6.1 ABSOLUTE MAXIMUM RATINGS

This product contains devices to protect the inputs Power Considerations.The average chip-junc-
against damage due to high static voltages, how- tion temperature, Tj, in Celsius can be obtained
ever it is advisable to take normal precaution to from:
avoid application of any voltage higher than the Tj=TA + PD x RthJA
specified maximum rated voltages.
Where:TA = Ambient Temperature.
For proper operation it is recommended that VI
and VO be higher than VSS and lower than V DD. RthJA =Package thermal resistance (junc-
Reliability is enhanced if unused inputs are con- tion-to ambient).
nected to an appropriate logic voltage level (VDD PD = Pint + Pport.
or VSS).
Pint =IDD x VDD (chip internal power).
Pport =Port power dissipation (determined
by the user).
Symbol Parameter Value Unit

VDD Supply Voltage -0.3 to 7.0 V
(1)
VI Input Voltage V SS - 0.3 to VDD + 0.3 V
VO Output Voltage V SS - 0.3 to VDD + 0.3 (1) V
IV DD Total Current into VDD (source) 80 mA
IVSS Total Current out of VSS (sink) 100 mA
Tj Junction Temperature 150 C
TSTG Storage Temperature -60 to 150 C
Notes:
- Stresses above those listed as absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
- (1) Within these limits, clamping diodes are guarantee to be not conductive. Voltages outside these limits are authorised as long as injection
current is kept within the specification.
58/78
57
6.2 RECOMMENDED OPERATING CONDITIONS

Value
Symbol Parameter Test Conditio ns Unit
Min. Typ. Max.
6 Suffix Version -40 85
TA Operating Temperature 1 Suffix Version 0 70 C
3 Suffix Version -40 125
fOSC = 4MHz, 1 & 6 Suffix 3.0 6.0
Operating Supply Voltage fOSC = 4MHz, 3 Suffix 3.0 6.0
V
(Except ST626xB ROM devices) fosc= 8MHz , 1 & 6 Suffix 3.6 6.0
fosc= 8MHz , 3 Suffix 4.5 6.0
VDD
fOSC = 4MHz, 1 & 6 Suffix 3.0 6.0
Operating Supply Voltage fOSC = 4MHz, 3 Suffix 3.0 6.0
V
(ST626xB ROM devices) fosc= 8MHz , 1 & 6 Suffix 4.0 6.0
fosc= 8MHz , 3 Suffix 4.5 6.0
VDD = 3.0V, 1 & 6 Suffix 0 4.0
Oscillator Frequency 2) VDD = 3.0V , 3 Suffix 0 4.0
MHz
(Except ST626xB ROM devices) VDD = 3.6V , 1 & 6 Suffix 0 8.0
VDD = 3.6V , 3 Suffix 0 4.0
fOSC
VDD = 3.0V, 1 & 6 Suffix 0 4.0
Oscillator Frequency 2) VDD = 3.0V , 3 Suffix 0 4.0
MHz
(ST626xB ROM devices) VDD = 4.0V , 1 & 6 Suffix 0 8.0
VDD = 4.0V , 3 Suffix 0 4.0
IINJ+ Pin Injection Current (positive) VDD = 4.5 to 5.5V +5 mA
IINJ- Pin Injection Current (negative) VDD = 4.5 to 5.5V -5 mA
Notes:
1. Care must be taken in case of negative current injection, where adapted impedance must be respected on analog sources to not affect the
A/D conversion. For a -1mA injection, a maximum 10 K is recommended.
2.An oscillator frequency above 1MHz is recommended for reliable A/D results
Figure 30. Maximum Operating FREQUENCY (Fmax) Versus SUPPLY VOLTAGE (VDD)
Maximum FREQUENCY (MHz)
1 & 6 Suffix version

8
FUNCTIONAL ITY IS NOT
1 & 6 Suffix 3 Suffix version
7 GUARANTE ED IN
version
THIS AREA
6
4
3 Suffix version
3
1
2.5 3 3.6 4 4.5 5 5.5 6
SUPPLY VOLTAGE (VDD)
All devices except ST626xB ROM devices

ST626xB ROM devices
The shaded area is outside the recommended operating range; device functionality is not guaranteed under these conditions.
59/78
58
6.3 DC ELECTRICAL CHARACTERISTICS
(TA = -40 to +125C unless otherwise specified)

Value
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
VIL Input Low Level Voltage
VDD x 0.3 V
All Input pins
VIH Input High Level Voltage
VDD x 0.7 V
All Input pins
Hysteresis Voltage (1) VDD= 5V 0.2

V Hys V
All Input pins VDD= 3V 0.2
Vup LVD Threshold in power-on 4.1 4.3

V dn LVD threshold in powerdown 3.5 3.8
Low Level Output Voltage VDD= 5.0V; IOL = +10A 0.1
All Output pins VDD= 5.0V; IOL = + 3mA 0.8
VOL VDD= 5.0V; IOL = +10A 0.1 V
Low Level Output Voltage
VDD= 5.0V; IOL = +7mA 0.8
30 mA Sink I/O pins
VDD= 5.0V; IOL = +15mA 1.3
High Level Output Voltage VDD= 5.0V; IOH = -10A 4.9
VOH V
All Output pins VDD= 5.0V; IOH = -3.0mA 3.5
All Input pins 40 100 350
R PU Pull-up Resistance
RESET pin 150 350 900
Input Leakage Current VIN = VSS (No Pull-Up configured)
0.1 1.0
IIL All Input pins but RESET VIN = VDD
A
IIH Input Leakage Current VIN = VSS -8 -16 -30
RESET pin VIN = VDD 10
Supply Current in RESET VRESET=VSS
7 mA
Mode fOSC=8MHz
Supply Current in
VDD=5.0V fINT=8MHz 7 mA
RUN Mode (2)
Supply Current in WAIT
IDD VDD=5.0V fINT=8MHz 2.5 mA
Mode (3)
Supply Current in STOP ILOAD=0mA
20 A
Mode, with LVD disabled(3) VDD=5.0V
500
Mode, with LVD enabled(3) VDD=5.0V
Retention EPROM Data Retention TA = 55C 10 years
Notes:
(1) Hysteresis voltage between switching levels
(2) All peripherals running
(3) All peripherals in stand-by
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59
DC ELECTRICAL CHARACTERISTICS (Contd)

(TA = -40 to +85C unless otherwise specified))
Value
Min. Typ. Max.
Vup LVD Threshold in power-on Vdn +50 mV 4.1 4.3 V
V dn LVD threshold in powerdown 3.6 3.8 Vup -50 mV V
VDD= 5.0V; IOL = +10A 0.1
Low Level Output Voltage
VDD= 5.0V; IOL = + 5mA 0.8
All Output pins
VDD= 5.0V; IOL = + 10mAv 1.2
VOL VDD= 5.0V; IOL = +10A 0.1 V
Low Level Output Voltage VDD= 5.0V; IOL = +10mA 0.8
30 mA Sink I/O pins VDD= 5.0V; IOL = +20mA 1.3
VDD= 5.0V; IOL = +30mA 2.0
High Level Output Voltage VDD= 5.0V; IOH = -10A 4.9
VOH V
All Output pins VDD= 5.0V; IOH = -5.0mA 3.5
IDD 10 A
Mode, with LVD disabled(*) VDD=5.0V
Note:
(*) All Peripherals in stand-by.
6.4 AC ELECTRICAL CHARACTERISTICS

Value
Min. Typ. Max.
tREC Supply Recovery Time (1) 100 ms
TA = 25C 5 10
TWEE EEPROM Write Time TA = 85C 10 20 ms
TA = 125C 20 30
Endurance
(2) EEPROM WRITE/ERASE Cycle QA LOT Acceptance (25C) 300,000 1 million cycles
Retention EEPROM Data Retention TA = 55C 10 years

fLFAO Internal frequency with LFAO active 200 400 800 kHz
VDD = 3V 1
Internal Frequency with OSG VDD = 3.6V 1
fOSG fOSC MHz
enabled 2) VDD = 4.5V 2
VDD = 6V 2
VDD=5.0V (Except 626xB ROM)
R=47k 4 5 5.8 MHz
R=100k 2.7 3.2 3.5 MHz
Internal frequency with RC oscilla- R=470k 800 850 900 kHz
fRC
tor and OSG disabled2) 3) VDD=5.0V (626xB ROM)
R=10k 2.4 3.1 3.8 MHz
R=27k 1.8 2.2 2.5 MHz
R=100k 800 980 1200 kHz
CIN Input Capacitance All Inputs Pins 10 pF
C OUT Output Capacitance All Outputs Pins 10 pF
Notes:
1. Period for which VDD has to be connected at 0V to allow internal Reset function at next power-up.
2 An oscillator frequency above 1MHz is recommended for reliable A/D results.
3. Measure performed with OSCin pin soldered on PCB, with an around 2pF equivalent capacitance.
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6.5 A/D CONVERTER CHARACTERISTICS

Value
Min. Typ. Max.
Res Resolution 8 Bit
fOSC > 1.2MHz 2
ATOT Total Accuracy (1) (2) LSB
fOSC > 32kHz 4
fOSC = 8MHz (TA < 85C) 70
tC Conversion Time s
fOSC = 4 MHz 140
Conversion result when
ZIR Zero Input Reading 00 Hex
VIN = VSS
Conversion result when
FSR Full Scale Reading FF Hex
VIN = VDD
Analog Input Current During
AD I VDD= 4.5V 1.0 A
Conversion
ACIN Analog Input Capacitance 2 5 pF
Notes:
1. Noise at VDD, VSS <10mV
2. With oscillator frequencies less than 1MHz, the A/D Converter accuracy is decreased.
6.6 TIMER CHARACTERISTICS

Value
Min. Typ. Max.
fIN Input Frequency on TIMER Pin

IINT MHz
----------
4
VDD = 3.0V 1 s
tW Pulse Width at TIMER Pin
VDD >4.5V 125 ns
6.7 SPI CHARACTERISTICS
6.8 ARTIMER ELECTRICAL CHARACTERISTICS

62/78
Figure 31. Vol versus Iol on all I/O port at Vdd=5V
6 T = -40C
Vol (V)
T = 25C
4
T = 95C
2 T = 125C
0
0 10 20 30 40
Iol (mA)
This curves represents typical variations and is given for guidance only
Figure 32. Vol versus Iol on all I/O port at T=25C
8
6 Vdd = 3.0V
Vol (V)
Vdd = 4.0V
4
Vdd = 5.0V
2 Vdd = 6.0V
0
0 10 20 30 40
Iol (mA)
Figure 33. Vol versus Iol for High sink (30mA) I/Oports at T=25C
5
4
Vdd = 3.0V
Vol (V)
3 Vdd = 4.0V
2 Vdd = 5.0V
1 Vdd = 6.0V
0
0 10 20 30 40
Iol (mA)
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Figure 34. Vol versus Iol for High sink (30mA) I/O ports at Vdd=5V
5
4
T= -40C
Vol (V)
3 T= 25C
2 T= 95C
T= 125C
1
0
0 10 20 30 40
Iol (mA)
Figure 35. Voh versus Ioh on all I/O port at 25C
6
4 Vdd = 3.0V
Voh (V)
Vdd = 4.0V
2
Vdd = 5.0V
0 Vdd = 6.0V
-2
0 10 20 30 40
Ioh (mA)
Figure 36. Voh versus Ioh on all I/O port at Vdd=5V
4 T= -40C
Voh (V)
T= 25C
2
T= 95C
0 T= 125C
-2
0 10 20 30 40
Ioh (mA)
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Figure 37. Idd WAIT versus Vcc at 8 Mhz for OTP devices
2.5
Idd WAIT (mA)
2 T = -40C
1.5 T = 25C
1 T = 95C
0.5 T = 125C
0
3V 4V 5V 6V
Vdd
Figure 38. Idd STOP versus Vcc for OTP devices
8
Idd STOP (A)
6 T= -40C
4 T= 25C
2 T= 95C
0 T= 125C
-2
3V 4V 5V 6V
Vdd
Figure 39. Idd STOP versus Vcc for ROM devices
1.5
Idd STOP (A)
T = -40C
1
T = 25C
0.5 T = 95C
T = 125C
0
-0.5
3V 4V 5V 6V
Vdd
65/78
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Figure 40. Idd WAIT versus Vcc at 8Mhz for ROM devices
2.5
Idd WAIT (mA)
2 T = -40C
1.5 T = 25C
1 T = 95C
0.5 T = 125C
0
3V 4V 5V 6V
Vdd
Figure 41. Idd RUN versus Vcc at 8 Mhz for ROM and OTP devices
6
Idd RUN (mA)
T = -40C
T = 25C
4
T = 95C
T = 125C
2
0
3V 4V 5V 6V
Vdd
Figure 42. LVD thresholds versus temperature
4.2
4.1
Vthresh.
4
Vup
Vdn
3.9
3.8
3.7
-40C 25C 95C 125C
Temp
66/78
65
Figure 43. RC frequency versus Vcc for ROM ST626xB only
10
Frequency
MHz
R=10K
1
R=27K
R=100K
0.1
3 3.5 4 4.5 5 5.5 6
VDD (volts)
Figure 44. RC frequency versus Vcc (Except for ST626xB ROM devices)
10
Frequency
R=47K
MHz
1 R=100K
R=470K
0.1
3 3.5 4 4.5 5 5.5 6
VDD (volts)
67/78
66
7 GENERAL INFORMATION
7.1 PACKAGE MECHANICAL DATA

Figure 45. 16-Pin Plastic Dual In Line Package (B), 300-mil Width
mm inches
Dim.
Min Typ Max Min Typ Max
A 5.33 0.210
A1 0.38 0.015
A2 2.92 3.30 4.95 0.115 0.130 0.195
b 0.36 0.56 0.014 0.022
b2 1.52 1.78 0.060 0.070
c 0.20 0.25 0.36 0.008 0.010 0.014
D 18.67 19.18 19.69 0.735 0.755 0.775
e 2.54 0.100
E1 6.10 6.35 7.11 0.240 0.250 0.280
L 2.92 3.30 3.81 0.115 0.130 0.150
Number of Pins
PDIP16
N 16
Figure 46. 16-Pin Ceramic Side-Brazed Dual In-Line Package
mm inches
Dim.
A 3.78 0.149
A1 0.38 0.015
B 0.36 0.46 0.56 0.014 0.018 0.022
B1 1.14 1.37 1.78 0.045 0.054 0.070
C 0.20 0.25 0.36 0.008 0.010 0.014
D 19.86 20.32 20.78 0.782 0.800 0.818
D1 17.78 0.700
E1 7.04 7.49 7.95 0.277 0.295 0.313
e 2.54 0.100
G 6.35 6.60 6.86 0.250 0.260 0.270
G1 9.47 9.73 9.98 0.373 0.383 0.393
G2 1.02 0.040
L 2.92 3.30 3.81 0.115 0.130 0.150
S 1.27 0.050
CDIP16W
4.22 0.166
Number of Pins
N 16
68/78
67
PACKAGE MECHANICAL DATA (Contd)

Figure 47. 16-Pin Plastic Small Outline Package (M), 300-mil Width
mm inches
Dim.
A 2.35 2.65 0.0926 0.1043
A1 0.10 0.0040
B 0.33 0.51 0.013 0.020
C 0.32 0.0125
D 10.10 10.50 0.3977 0.4133
E 7.40 7.60 0.2914 0.2992
e 1.27 0.050
H 10.01 10.64 0.394 0.419
h 0.25 0.74 0.010 0.029
K 0 8 0 8
L 0.41 1.27 0.016 0.050
SO16 G 0.10 0.004

Number of Pins
N 16
Figure 1. 16-Pin Plastic Shrink Small Outline Package, 0.209 Width
mm inches
Dim.
A 1.73 1.86 1.99 0.068 0.073 0.078
A1 0.05 0.13 0.21 0.002 0.005 0.008
B 0.25 0.38 0.010 0.015
C 0.09 0.20 0.004 0.008
D 6.07 6.20 6.33 0.239 0.244 0.249
E 7.65 7.80 7.90 0.301 0.307 0.311
E1 5.20 5.30 5.38 0.205 0.209 0.212
e 0.65 0.026
G 0.076 0.003
K 0 4 8 0 4 8
L 0.63 0.75 0.95 0.025 0.030 0.037
SSOP16 Number of Pins

N 16
THERMAL CHARACTERISTIC
Value
Min. Typ. Max.
PDIP16 55
RthJA Thermal Resistance C/W
PSO16 75
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68
7.2 ORDERING INFORMATION
Table 22. OTP/EPROM VERSION ORDERING INFORMATION

Program
Sales Type EEPROM (Bytes) Temperature Range Package
Memory (Bytes)
ST62E62CF1 1836 EPROM 64 0 to +70C CDIP16W
ST62T52CM6 -40 to + 85C
1836 OTP None PSO16
ST62T52CM3 -40 to + 125C
ST62T62CM6 -40 to + 85C
1836 OTP 64 PSO16
ST62T62CM3 -40 to + 125C
ST62T52CB6 -40 to + 85C
1836 OTP None PDIP16
ST62T52CB3 -40 to + 125C
ST62T62CB6 -40 to + 85C
1836 OTP 64 PDIP16
ST62T62CB3 -40 to + 125C
ST62T52CN6 -40 to + 85C
1836 OTP None SSOP16
ST62T52CN3 -40 to + 125C
ST62T62CN6 -40 to + 85C
1836 OTP 64 SSOP16
ST62T62CN3 -40 to + 125C
70/78
69
ST62P52C
ST62P62C
8-BIT FASTROM MCUs WITH A/D CONVERTER,
SAFE RESET, AUTO-RELOAD TIMER AND EEPROM

5 Interrupt Vectors
Data RAM: 128 bytes
Data EEPROM: 64 bytes (none on ST62T52C)
Input with pull-up resistor PDIP16
Analog Input
TRIACs directly
prescaler
8-bit Auto-reload Timer with 7-bit programmable PSO16
Digital Watchdog
Crystal Ceramic resonator or RC network SSOP16
ST626x-EMU2 Emulation and Development (See end of Datasheet for Ordering Information)
parallel port)
DEVICE SUMMARY
ROM
DEVICE EEPROM
(Bytes)
ST62P52C 1836 -
ST62P62C 1836 64
Rev. 2.7
November 1999 71/78

70
ST62P52C ST62P62C
1.1 INTRODUCTION 1.2.2 Listing Generation and Verification
The ST62P52C and ST62P62C are the Factory When STMicroelectronics receives the users
Advanced Service Technique ROM (FASTROM) ROM contents, a computer listing is generated
version of ST62T52C and ST62T62C OTP devic- from it. This listing refers exactly to the ROM con-
es. tents and options which will be used to produce
They offer the same functionality as OTP devices, the specified MCU. The listing is then returned to
selecting as FASTROM options the options de- the customer who must thoroughly check, com-
fined in the programmable option byte of the OTP plete, sign and return it to STMicroelectronics. The
version. signed listing forms a part of the contractual agree-
ment for the production of the specific customer
1.2 ORDERING INFORMATION MCU.
The following section deals with the procedure for The STMicroelectronics Sales Organization will be
transfer of customer codes to STMicroelectronics. pleased to provide detailed information on con-
tractual points.
1.2.1 Transfer of Customer Code
Customer code is made up of the ROM contents
and the list of the selected FASTROM options. Table 1. ROM Memory Map for ST62P52C/P62C
The ROM contents are to be sent on diskette, or
by electronic means, with the hexadecimal file Device Address Description
generated by the development tool. All unused 0000h-087Fh Reserved
bytes must be set to FFh. 0880h-0F9Fh User ROM
0FA0h-0FEFh Reserved
The selected options are communicated to STMi- 0FF0h-0FF7h Interrupt Vectors
croelectronics using the correctly filled OPTION 0FF8h-0FFBh Reserved
LIST appended. 0FFCh-0FFDh NMI Interrupt Vector
Table 2. FASTROM version Ordering Information
Sales Type ROM EEPROM (Bytes) Temperature Range Package
ST62P52CM1/XXX 0 to +70C
ST62P52CM6/XXX 1836 Bytes None -40 to + 85C
ST62P52CM3/XXX (*) -40 to + 125C
PSO16
ST62P62CM1/XXX 0 to +70C
ST62P62CM6/XXX 1836 Bytes 64 -40 to + 85C
ST62P62CM3/XXX (*) -40 to + 125C
ST62P52CB1/XXX 0 to +70C
ST62P52CB6/XXX 1836 Bytes None -40 to + 85C
ST62P52CB3/XXX (*) -40 to + 125C
PDIP16
ST62P62CB1/XXX 0 to +70C
ST62P62CB6/XXX 1836 Bytes 64 -40 to + 85C
ST62P62CB3/XXX (*) -40 to + 125C
ST62P52CN1/XXX 0 to +70C
ST62P52CN6/XXX 1836 Bytes None -40 to + 85C
ST62P52CN3/XXX (*) -40 to + 125C
SSOP16
ST62P62CN1/XXX 0 to +70C
ST62P62CN6/XXX 1836 Bytes 64 -40 to + 85C
ST62P62CN3/XXX (*) -40 to + 125C
(*) Advanced information
72/78
71
ST62P52C ST62P62C
ST62P52C and ST62P62C FASTROM MICROCONTROLLER OPTION LIST
Customer .. .. . .... . ... .. .. ... ... . .

Address .. .. . .... . ... .. .. ... ... . .
. .. . .. .. .. . . .... . .. .. . .. .
Contact .. .. . .... . ... .. .. ... ... . .
Phone No .. .. . .... . ... .. .. ... ... . .
Reference .. .. . .... . ... .. .. ... ... . .
STMicroelectronics references
Device: [ ] ST62P52C [ ] ST62P62C
Package: [ ] Dual in Line Plastic [ ] Small Outline Plastic with condionning:
[ ] Standard (Stick)
[ ] Tape & Reel
[ ] Shrink Small Outline Plastic
Temperature Range: [ ] 0C to + 70C [ ] - 40C to + 85C [ ] - 40C to + 125C
Oscillator Source Selection: [ ] Crystal Quartz/Ceramic resonator

[ ] RC Network
Watchdog Selection: [ ] Software Activation
[ ] Hardware Activation
Power on Reset Delay [ ] 32768 cycle delay
[ ] 2048 cycle delay
Readout Protection: [ ] Disabled
[ ] Enabled
External STOP Mode Control [ ] Enabled
[ ] Disabled
PB2-PB3 Pull-Up at RESET [ ] Enabled
[ ] Disabled
LVD Reset [ ] Enabled
[ ] Disabled
ADC Synchro [ ] Enabled
[ ] Disabled
Oscillator Safe Guard [ ] Enabled
[ ] Disabled
Comments : Supply Operating Range in the application:

Oscillator Fequency in the application:
Notes .. .. . .... . ... .. .. ... ... . .

Signature .. .. . .... . ... .. .. ... ... . .
Date .. .. . .... . ... .. .. ... ... . .
73/78
72
ST62P52C ST62P62C
Notes:
74/78
73
ST6252C
ST6262B
8-BIT ROM MCUs WITH A/D CONVERTER,
SAFE RESET AUTO-RELOAD TIMER, ROM AND EEPROM

5 Interrupt Vectors
Data RAM: 128 bytes
Data EEPROM: 64 bytes (none on ST62T52C)
Input with pull-up resistor PDIP16
Analog Input
TRIACs directly
prescaler
8-bit Auto-reload Timer with 7-bit programmable PSO16
Digital Watchdog
Crystal Ceramic resonator or RC network SSOP16
ST626x-EMU2 Emulation and Development (See end of Datasheet for Ordering Information)
parallel port)
DEVICE SUMMARY
ROM
DEVICE EEPROM LVD & OSG
(Bytes)
ST6252C 1836 - Yes

ST6262B 1836 64 No
Rev. 2.7
November 1999 75/78

74
ST6252C ST6262B
1.1 INTRODUCTION 1.2 ROM READOUT PROTECTION
The ST6252C and ST6262B are mask pro- If the ROM READOUT PROTECTION option is
grammed ROM version of ST62T52C and selected, a protection fuse can be blown to pre-
ST62T62C OTP devices. vent any access to the program memory content.
They offer the same functionality as OTP devices, In case the user wants to blow this fuse, high volt-
selecting as ROM options the options defined in age must be applied on the TEST pin.
the programmable option byte of the OTP version,
except the LVD & OSG options that are not availa-
ble on the ST6262B ROM device. Figure 2. Programming Circuit
Figure 1. Programming wave form
0.5s min
TEST
5V 47mF
15 100nF
14V typ
10
VSS
5
VDD
TEST PROTECT
150 s typ
TEST 14V
100nF
100mA ZPD15
max 15V
VR02003
4mA typ
t
VR02001
Note: ZPD15 is used for overvoltage protection
76/78
75
ST6252C ST6262B
ST6252C and ST6262B MICROCONTROLLER OPTION LIST

Customer .. .. . .... . ... .. .. ... ... . .
Address .. .. . .... . ... .. .. ... ... . .
. .. . .. .. .. . . .... . .. .. . .. .
Contact .. .. . .... . ... .. .. ... ... . .
Phone No .. .. . .... . ... .. .. ... ... . .
Reference .. .. . .... . ... .. .. ... ... . .
STMicroelectronics references
Device: [ ] ST6252C [ ] ST6262B
Package: [ ] Dual in Line Plastic [ ] Small Outline Plastic with condionning:
[ ] Standard (Stick)
[ ] Tape & Reel
[ ] Shrink Small Outline Plastic
Temperature Range: [ ] 0C to + 70C [ ] - 40C to + 85C [ ] - 40C to + 125C
Special Marking: [ ] No [ ] Yes _ _ _ _ _ _ _ _ _ _ _
Authorized characters are letters, digits, ., -, / and spaces only.
Maximum character count: DIP16: 9
SO16: 5
Oscillator Source Selection: [ ] Crystal Quartz/Ceramic resonator
[ ] RC Network
Watchdog Selection: [ ] Software Activation
[ ] Hardware Activation
Power on Reset Delay [ ] 32768 cycle delay
[ ] 2048 cycle delay
ROM Readout Protection: [ ] Disabled (Fuse cannot be blown)
[ ] Enabled (Fuse can be blown by the customer)
Note: No part is delivered with protected ROM.
The fuse must be blown for protection to be effective.
External STOP Mode Control [ ] Enabled [ ] Disabled
PB2-PB3 Pull-Up at RESET [ ] Enabled [ ] Disabled
LVD Reset* [ ] Enabled [ ] Disabled
ADC Synchro* [ ] Enabled [ ] Disabled
Oscillator Safe Guard* [ ] Enabled [ ] Disabled
*ST6252C only
Comments : Supply Operating Range in the application:

Oscillator Fequency in the application:
Notes .. .. . .... . ... .. .. ... ... . .

Signature .. .. . .... . ... .. .. ... ... . .
Date .. .. . .... . ... .. .. ... ... . .
77/78
76
ST6252C ST6262B
1.3 ORDERING INFORMATION from it. This listing refers exactly to the mask which
will be used to produce the specified MCU. The
The following section deals with the procedure for listing is then returned to the customer who must
transfer of customer codes to STMicroelectronics. thoroughly check, complete, sign and return it to
1.3.1 Transfer of Customer Code STMicroelectronics. The signed listing forms a
part of the contractual agreement for the creation
Customer code is made up of the ROM contents of the specific customer mask.
and the list of the selected mask options. The
ROM contents are to be sent on diskette, or by The STMicroelectronics Sales Organization will be
electronic means, with the hexadecimal file gener- pleased to provide detailed information on con-
ated by the development tool. All unused bytes tractual points.
must be set to FFh.
Table 1. ROM Memory Map for ST6252C/62B
The selected mask options are communicated to
Device Address Description
STMicroelectronics using the correctly filled OP-
TION LIST appended. 0000h-087Fh Reserved
0880h-0F9Fh User ROM
1.3.2 Listing Generation and Verification 0FA0h-0FEFh Reserved
0FF0h-0FF7h Interrupt Vectors
When STMicroelectronics receives the users
0FF8h-0FFBh Reserved
ROM contents, a computer listing is generated
0FFCh-0FFDh NMI Interrupt Vector
Table 2. ROM version Ordering Information
Sales Type ROM EEPROM (Bytes) Temperature Range Package
ST6252CB1/XXX 0 to +70C
ST6252CB6/XXX -40 to + 85C PDIP16
ST6252CB3/XXX -40 to + 125C
1836 Bytes None
ST6252CM1/XXX 0 to +70C
ST6252CM6/XXX -40 to + 85C PSO16
ST6252CM3/XXX -40 to + 125C
ST6252CN1/XXX 0 to +70C
ST6252CN6/XXX -40 to + 85C SSOP16
ST6252CN3/XXX -40 to + 125C
ST6262BB1/XXX 0 to +70C
ST6262BB6/XXX -40 to + 85C PDIP16
ST6262BB3/XXX -40 to + 125C
1836 Bytes 64
ST6262BM1/XXX 0 to +70C
ST6262BM6/XXX -40 to + 85C PSO16
ST6262BM3/XXX -40 to + 125C
ST6262BN1/XXX 0 to +70C
ST6262BN6/XXX -40 to + 85C SSOP16
ST6262BN3/XXX -40 to + 125C
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
1999 STMicroelectronics - All Rights Reserved.
Purchase of I2 C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an
I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
STMicroelectronics Group of Companies
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain
Sweden - Switzerland - United Kingdom - U.S.A.
http:// www.st.com
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ST62T52C

3.0 to 6.0V Supply Operating Range

November 1999 1/78

POWER OSCILLATOR RESET

VDD VSS OSCin OSCout RESET

1.2 PIN DESCRIPTIONS

PA4-PA5. These 2 lines are organized as one I/O PB3 4 13 RESET

1.3 MEMORY MAP

PROGRAM SPACE DATA SPACE

0C0h DATA READ-ONLY

MEMORY MAP (Contd)

(*) Reserved areas should be filled with 0FFh

MEMORY MAP (Contd)

MEMORY MAP (Contd)

DATA ROM 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PROGRAM SPACE ADDRESS

MEMORY MAP (Contd)

MEMORY MAP (Contd)

Table 4. Row Arrangement for Parallel Writing of EEPROM Locations

Up to 8 bytes in each row may be programmed simultaneously in Parallel Write mode.

MEMORY MAP (Contd)

1.4 PROGRAMMING MODES

PROGRAMMING MODES (Contd)

2 CENTRAL PROCESSING UNIT

CPU REGISTERS (Contd)

ing Interrupt mode (CI, ZI), and a third pair is used

The Zero flag is set if the result of the last arithme-

3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES

3.1 CLOCK SYSTEM

CLOCK SYSTEM (Contd)

CLOCK SYSTEM (Contd)

(1) Maximum Frequency for the device to work correctly

Figure 10. OSG Emergency Oscillator Principle

CLOCK SYSTEM (Contd)

MAIN M fINT Watchdog

Main Oscillator off

Maximum FREQU ENCY (MHz)

SUPPLY VOLTAGE (VDD )

The function of the POR circuit consists in waking

3.2.5 Application Notes

initialisation routine from being interrupted. The in-

Figure 16. Reset Block Diagram

1) Resistive ESD protection. Value not guaranteed.

AR TIMER Mode Control Register 0D5h AR TIMER stopped

Miscellaneous Register 0DDh

X, Y, V, W, Register 080H TO 083H

3.3 DIGITAL WATCHDOG

Table 7. Recommended Option Choices

DIGITAL WATCHDOG (Contd)

WATCHDOG CONTROL REGISTER

DIGITAL WATCHDOG (Contd)

DIGITAL WATCHDOG (Contd)

Figure 19. Digital Watchdog Block Diagram

The C and Z flags are replaced by the interrupt

Theassociated interrupt vectoris loaded inthe PC. YES

WARNING: In some circumstances, when a YES

NORMAL mode and especially during the execu- NO

ated with the same vector). YES

FROM REGISTER PORT A,B,C

Bit GEN (IOR Register)