Design-for-Test: Scan and ATPG

Achieving High Test

Coverage
 Objectives

Upon completion of this module, you will be able to:

Initiate an initial ATPG run

Apply FastScan pattern types to relevant circuits
Apply techniques to achieve high test coverage
Use ModelSim to simulate and verify the following Verilog
testbenches:

Serial and parallel

Chaintest

Pattern sample
Save patterns in various formats: ASCII, Verilog, and WGL
Read in and perform fault simulation on an external pattern
Optimize patterns for quality and cost
Create patterns for At-speed ATPG

Transition fault patterns

Path delay patterns

5-2 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 ATPG Run
For initial run, use fault sampling to provide the following:

Quick estimate of coverage for a large circuit.

Creates a smaller pattern set for simulation.
Detects problems early.
Use The SET FAult Sampling command to specify a
percentage (between 0 and 100) of the total faults you want
processed.

ATPG> SET FAult Sampling 1

ATPG> CREate PAtterns -Auto
ATPG> REPort STatistics
ATPG> SAVe PAtterns <FILENAME1.v> -Verilog -Parallel
ATPG> SET PAttern Filtering SAMple 2
ATPG> SAVe PAtterns <FILENAME2.v> -Verilog -Serial

5-3 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 Using an External Fault List
Use the LOAd FAults command to place faults from an
external file into the internal fault list.

Retains original faults

in the fault list.

ATPG> LOAd FAults <-FILENAME> -Retain

ATPG>SET Fault Protection ON
ATPG> REPort STatistics //verify initial coverage (optional)
ATPG> CREate Patterns -Auto
ATPG> REPort STatistics //shows total coverage

5-4 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 Adding NOfaults
Use the ADD NOfault command to place nofault settings on
the following:

Pin pathnames.

Pin names of:
specified instances.
Modules.
Issue the ADD NOfaults command in setup mode before
using the ADD FAults command.

Specified pin pathnames and pins names will not
become fault sites.

If design was previously flattened, using the ADD NOfault
command will delete the flattened model.

The tool loses all information added after flattening,

such as ATPG functions and constraints.

5-5 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 FastScans Test Pattern Types
FastScan generates the following test pattern types:

Basic Scan
Used on full-scan design circuitry

Clock Sequential
Used to propagate values through non-scan latches and DFFs
with limited sequential depth

RAM Sequential
Used to propagate values through RAM

Multi Load
Used on RAM/ROM designs that contain non-scan cells

MacroTest
Used to test the cell array of small embedded memories

Clock PO
Used on circuitry where a clock signal passes through
combinational logic to a primary output

5-6 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 Basic Scan Patterns
The following apply to basic scan patterns:

Generated by default.

Use appropriate test procedures to define control
and observation of scan cells.

Independent from each other.

5-7 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 Basic Scan Patterns (Cont.)
Basic scan patterns contain the following events:
1. Load scan chain
2. Force primary inputs (PI)
3. Measure primary outputs (PO)
4. Pulse capture clock
Capture
5. Unload values from scan cells Cycle
Load next pattern

Measure PO

capture clock
Force PI

Pulse
Load Scan Chain

.
CLK

SE
PIs X

X
PO

5-8 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 Basic Scan Pattern Operation
Load Initialization procedure first. LOAD

Load values into the scan cells. FORCE PI

1. Force SE to 1 (scan enable). MEASURE PO

PULSE CAPTURE
2. Force SI (scan chain input pin). CLK.

3. Pulse shift clock.

4. Repeat steps 2 and 3 until all scan cells are loaded.
1st Shift
1st Shift
A
Y SE
B

SI

CLK
011 1 SO
SI D Q D Q D Q

1
SE 1
CLK

5-9 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 Basic Scan Pattern Operation (Cont.)
Load values into the scan cells. LOAD

1. Force SE to 1. FORCE PI
MEASURE PO
2. Force SI.
PULSE CAPTURE
3. Pulse shift clock. CLK.

4. Repeat steps 2 and 3 until all scan cells are loaded.

2nd Shift 1st 2nd

Shift Shift
A
Y
B SE

SI

CLK
011 1 1 SO
SI D Q D Q D Q

1 1
SE 1
CLK

5-10 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 Basic Scan Pattern Operation (Cont.)
Load values into the scan cells.
LOAD
1. Force SE to 1. FORCE PI
2. Force SI. MEASURE PO
3. Pulse shift clock. PULSE CAPTURE
CLK.
4. Repeat steps 2 and 3 until all scan cells are loaded.

3rd Shift 1st 2nd 3rd

Shift Shift Shift
A
Y
B SE

SI

CLK
011 0 1 1 SO
SI D Q D Q D Q

0 1 1 LOAD
SE 1
CLK

5-11 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 Basic Scan Pattern Operation (Cont.)
Force primary inputs. LOAD

Force normal primary inputs. FORCE PI

Force SE to 0 (exits shift mode). MEASURE PO

Now all internal values can be predicted. PULSE CAPTURE

CLK.

1
A 1 1 1 1
1 Y
SE
B 1 0 1 1
A

Force PI
Q SO
SI D Q D Q D

0 1 1
SE
0
CLK

5-12 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 Basic Scan Pattern Operation (Cont.)
Measure primary outputs.
LOAD

Measure 1 on Y. FORCE PI
MEASURE PO
PULSE CAPTURE
CLK.

1
A 1 1 1 1
1 1 Y
SE
B 1 0 1 1
A

D Q SO
SI D Q D Q
Y
0 1 1

Measure PO
SE
0

Force PI
CLK

5-13 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 Basic Scan Pattern Operation (Cont.)
Pulse Capture Clock.
LOAD

Loads scan cells with functional inputs FORCE PI
to observe circuit status. MEASURE PO Capture
Cycle
PULSE CAPTURE
CLK.

1
A 1 1 1 1
CLK
1 1 Y SE
B 1 0 1 1
A

B
Q SO
SI D Q D Q D
Y
1 1 1

Pulse capture
Measure PO
SE
0

Force PI

CLK
CLK

Capture Cycle

5-14 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 Basic Scan Pattern Operation (Cont.)
LOAD/UNLOAD
Unload the scan chain.
FORCE PI

As new data is being shifted into the scan chain during
MEASURE PO
load serially, the previous internal circuit state is being shifted out
PULSE CAPTURE
serially and measured at scan out (SO). CLK.

LOAD/
UNLOAD

1st 2nd 3rd

Shift Shift Shift
A
Y
B SE

LOAD
SI

CLK
101 1 0 1 111
SI D Q D Q D Q
SO SO UNLOAD
1 0 1
SE
1
CLK Measure_sco
Previous internal state
of scan cells measured
at scan out

5-15 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 Clock Sequential Patterns
The following apply to Clock Sequential patterns:

Test through scan-based designs that contain limited non-scan
sequential logic or non-scan latches.

FastScan reports non-scan logic as tie-x by default.

To enable, set the sequential depth to a number greater than 1.
SETUP> SET PAttern Type -SEquential 2

Clock sequential depth -1 defines the number of non-scan cells
connected in series that FastScan can test through.
Do not set the depth greater than 5.

5-16 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 Clock Sequential Patterns (Cont.)
Clock sequential patterns contain the following events:
1. Load scan chains.
2. Apply clock sequential cycle.
a. Force PIs.
b. Pulse clock.
c. Repeat a and b up to N times, where N is the sequential depth -1.
3. Apply capture cycle.
a. Force PIs.
b. Measure PO.
c. Pulse capture clock.
4. Unload values from scan cells.

5-17 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 Clock Sequential Patterns (Cont.)

Clock sequential

Measure PO
Force PI
Force PI

Capture pulse
A
Y

pulse
B Load Scan Chain

Non-scan
logic CLK

D Q SO
SI D Q D Q
SE

SE PIs X
CLK
PO X
SETUP> SET PAttern Type -Sequential 2

Clock Sequential Capture Cycle

Clock sequential depth Cycle

5-18 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 Clock Sequential Pattern Operation
Load values into the scan cells.

Unknown

A Load Scan Chain

Y
B
1st 2nd

CLK
D Q SO
00 SI D Q D Q
0 X 0
1
SE SE
CLK

Initialized Unknown Initialized

5-19 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 Clock Sequential Pattern Operation (Cont.)
Apply clock sequential cycle.
a. Force primary inputs.

Force PIs

Clock sequential
1

pulse
A0 0 Load Scan Chain
Y
B1
1

Known input 0 CLK

X
1 SE
SO
SI D Q D Q D Q
0 X 0 A X

0 B X
SE
CLK
Clock Sequential
Cycle

5-20 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 Clock Sequential Pattern Operation (Cont.)
Apply clock sequential cycle.
b. Pulse clock.
c. Repeat a and b up to N times, where N
is the sequential depth 1.

Force PIs

Clock sequential
A0 0 1 1

pulse
Y Load Scan Chain
B1

1
X CLK
X
1 SO
SI D Q D Q D Q SE
0 1 X
A X
0
SE B X
CLK

Clock Sequential
Clock sequential pulse Cycle

captures data into

non-scan cell.

5-21 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 Clock Sequential Pattern Operation (Cont.)
Apply capture cycle.
a. Force PI.

Clock sequential

Measure PO
Force PI
Force PI

Capture pulse
1
1 1 1
A1 1 1 Y
B1

pulse
1 Load Scan Chain

CLK

D Q SO
SI D Q D Q
SE
0 1 X
0 PIs X
SE
CLK
PO X

Clock Sequential Capture Cycle

Cycle

5-22 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 Clock Sequential Pattern Operation (Cont.)
Apply capture cycle.
a. Force PI.
b. Measure PO.

Clock sequential

Measure PO
Force PI
Force PI

Capture pulse
1
1 1 1
A1 1 1

pulse
Y Load Scan Chain
B1
1

CLK

SO SE
SI D Q D Q D Q
0 1 X
PIs X
0
SE
CLK PO X

Clock Sequential Capture Cycle

Cycle

5-23 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 Clock Sequential Pattern Operation (Cont.)
Apply capture cycle.
a. Force PI.
b. Measure PO.
c. Pulse capture clock.

Clock sequential

Measure PO
Force PI
Force PI

Capture pulse
1
1 1 1
A1 1 1 Y
B1

pulse
1 Load Scan Chain

CLK

D Q D Q SO
SI D Q
SE
1 1 1
0 PIs X
SE
CLK
PO X

Clock Sequential Capture Cycle

Cycle

5-24 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 Clock Sequential Pattern Operation (Cont.)
Unload values from scan cells.

As new data is being shifted into the scan chain during
load, the previous internal circuit state is being shifted
out and measured at scan out (SO).

A Load Scan Chain

Y
B 1st 2nd

CLK
10 D Q D Q D Q
11
SI
SO
1 X 0
1
SE
SE
CLK
SI

5-25 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 RAM Sequential Patterns
The following applies to RAM Sequential patterns:

Targets faults associated with address and data lines.

Automatically determines writes and reads to test logic around
memories.

Single patterns with multiple loads.
Load events include: two address writes and a read.

5-26 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 RAM Sequential Patterns (Cont.)
Clock sequential patterns contain the following events:
1. Write to 1st address.
a. Load scan cells.
b. Force primary inputs.
c. Pulse write line(s).
2. Write to 2nd address.
Repeat steps a through c for a different address.
3. Read 1st address.
Load scan cells.
Force primary inputs.
Pulse read lines.
4. Capture read values.
Load scan cells.
Force primary inputs.
Measure primary outputs.
Pulse capture clock.
5. Unload values from scan cells.
5-27 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 RAM Sequential Patterns (Cont.)
Do the following to generate RAM sequential patterns:
SETUP>ADD CLks 0 CLK
SETUP>ADD WRite Controls 0 RAMCLK
ADDR[0]
SETUP>ADD REad Controls 0 RAMCLK
D_OUT[0]
S-a- 0 D_OUT[1]
DQ .
X ADDR[1] .
U1 ATPG>SET PAttern Type -RAM_sequential ON
RAM DQ

D_IN[0]
Scan_Out

IN1 D_IN[1]
RE Targets for RAM_
WE sequential patterns
CLK CLK
Scan_In
RAMCLK

Targets for RAM_

sequential patterns

5-28 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 RAM Sequential Patterns (Cont.)
RAM must be stable during LOAD/UNLOAD events.
If the scan clock is used for RAM, read enable (RE)
and write enable (WE) must be off during shift.

ADDR[0]

D_OUT[0]
DQ
D_OUT[1]
ADDR[1]
U1
RAM DQ

D_IN[0]
Scan_Out

IN1 D_IN[1]
RE
Inserted test logic
WE
holds WE and RE off
CLK CLK during shift.
Scan_In
RAMCLK
SE

5-29 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 RAM Sequential Patterns Example: Tests For Stuck-At-0 at
the Output of U1
Do the following to test for S-a-0
ADDR[0]
Write data to 1 st address.
D_OUT[0]
S-a- 0 D_OUT[1]
DQ ADDR [0] = 1
X ADDR[1] ADDR [1] = 1
U1
RAM DQ Data In = 00
D_IN[0] Address = 11
Scan_Out

Write different data to 2 nd address.
IN1 D_IN[1] ADDR [0] = 1
RE ADDR [1] = 0 (target S-a-0)
WE
Data In = 11
CLK CLK Address = 01
Scan_In
RAMCLK
Read 1st address.

Capture read values.
Correct captured data will read 00
(ADDR [1] = 1)
If U1 is S-a-0, captured data
will read 11
(ADDR [1] is stuck-at-0)

5-30 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 RAM Sequential Pattern Operation
1
ADDR[0]
Write to 1st Address. 1
D_OUT[0]
S-a-0 DQ
a. Load scan chain. X
D_OUT[1]
X
1 ADDR[1]
U1 1
b. Force PI. RAM DQ
0 X
c. Pulse write lines. 1 D_IN[0]
Scan_Out
0
1 IN1 D_IN[1]
0
RE
WE
0 1
CLK CLK

Pulse write
Scan_In
RAMCLK

Force PI
RAM CLK

SE
SI X X

CLK
IN1 X
Load Scan Chain

Address = 11 Data = 00
5-31 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 RAM Sequential Pattern Operation (Cont.)
1
Write to 2nd address. 1 ADDR[0]
D_OUT[0]
a. Load scan chain. S-a-0 D_OUT[1] DQ

X ADDR[1] X
0 0
b. Force PI. U1
RAM DQ
1 X
c. Pulse write lines. 0 D_IN[0]
Scan_Out
1
0 IN1 D_IN[1]
0
RE
WE
CLK 0 1
Scan_In CLK
RAMCLK

Pulse write
Force PI
RAM
CLK
Load Scan Chain
SE
SI X X
CLK
IN1 X

Write to 1st address Write to 2 nd address

5-32 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 RAM Sequential Pattern Operation (Cont.)
Read 1st address. 1
ADDR[0] 0
1
a. Load scan chain. S-a-0
D_OUT[0]
D_OUT[1]
DQ

b. Force PI. 1 X ADDR[1] 0 X

U1 1
RAM DQ
c. Pulse read lines. x
D_IN[0]
X
x
Scan_Out
x IN1 x
D_IN[1]
1
RE
WE
CLK 1 0
CLK
Scan_In
RAMCLK

Pulse read
A 1 causes Data is now valid

Force PI
RE =1 at memory output
WE =0
RAM
CLK
Load Scan Chain Load Scan Chain
SE
SI X X X
CLK
IN1 X
Write to 1st address Write to 2nd address Read to 1 st address

5-33 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 RAM Sequential Pattern Operation (Cont.)
Capture read values. x
x
ADDR[0] 0
0
a. Load scan cells. S-a-0
D_OUT[0]
D_OUT[1]
DQ

X 0
b. Force primary inputs. x x ADDR[1] 0
U1
RAM DQ
c. Measure primary outputs. x
D_IN[0]
x
d. Pulse capture clock. Scan_Out
x
x IN1 D_IN[1]
RE
WE
CLK x x
CLK
Scan_In

Pulse capture
RAMCLK

Measure PO
Force PI

clock
RAM
CLK
Load Scan Chain Load Scan Chain Load Scan Chain
SE
SI X X X X X X
CLK
IN1 X X

PO X
Write to 1st address Write to 2nd address Read 1st address Capture read values
5-34 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 Saving Patterns
Save ATPG patterns in the following formats:

Reuse, debugging, and diagnostics.
ASCII ATPG > SAVe PAtterns <Filename> -Ascii
Binary ATPG > SAVe PAtterns <Filename> -Binary
These pattern formats can be read back into FastScan. Can also read WGL and STIL files
back into FastScan too.

Time-based verification.
Verilog ATPG > SAVe PAtterns <Filename> -Verilog
VHDL ATPG > SAVe PAtterns <Filename> -VHdl
Allows user to independently verify test patterns with circuit timing.

Manufacturing test (ATE).
WGL ATPG > SAVe PAtterns <Filename> -Wgl
STIL ATPG > SAVe PAtterns <Filename> -STil
TI-TDL ATPG > SAVe PAtterns <Filename> -TItdl
...
Use .gz or .Z filename extension to save compressed files.

5-35 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 Quality and Cost

The goal of test generation is to

Coverage create high quality test.

Quality.
High quality test detects
manufacturing defects; therefore,
Test time fewer defective parts shipped to
customers.
Trend Reload

Cost.
Escapes The time it takes to test one chip
has a major impact on
production costs.
Tester Pattern
capacity volume
limit

5-36 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 Quality
To adequately test ICs for various
types of possible defects, use the
following fault models:

Stuck-at.
Functional
circuitry opens
Defects
circuitry shorts
Path delay.
At-Speed
Transition.
Defects
IDDQ
IDDQ.
Defects
CMOS stuck-on slow transistors Using a combination of fault
CMOS stuck-open resistive bridges
bridging models ensures high test quality.

Poor test quality can adversely
affect production schedules and
costs.

5-37 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 Cost
ATE (tester) time is a recurring cost for each chip.

Scan test application time is equal to the pattern count
times the shift cycle period.

Reload is extremely slow but may be necessary if pattern
count exceeds tester memory.

Patterns are often truncated to avoid reloads but pattern
quality is often impacted.
The following factors affect tester costs:

Number of scan channels.

Amount of required memory.

Number of clocks.

Required test frequency.

5-38 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 At-Speed ATPG

Checks the amount of time it takes for a device to change

logic states
Detects timing failures that occur when a circuit operates
correctly at a slow clock rate, but then fails when run at
clock speed

5-39 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 At-Speed ATPG (Cont.)

Traditional functional testing for At-speed defects.

Long development time.

Required detailed circuit knowledge.

Difficult to fault grade.
At-speed ATPG.

Patterns are automatically generated.

Simpler.

Easier to diagnose.

5-40 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 The Transition Fault Model
The transition fault model:

Detects gross pin-to-pin delay effects.

Requires no timing information.

Paths are randomly chosen.

Behaves as a stuck-at fault for a brief period of time.
Includes two fault models:

Slow-to-rise.
Models a pin slow to change from 0 to 1.

Slow-to-fall.
Models a pin that is slow to change from 1 to 0.
Requires two clock pulses for detection:

One for launch.

One for capture.

5-41 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 The Path Delay Fault Model
Models defects in circuit paths.
Associated with testing AC performance of critical path.

Critical paths are user-defined.

Typically measure the amount of time it takes to get from point A
to point B.

Longest path or paths are usually defined as critical, because
timing violations more likely to occur.
Path is defined by a timing analysis too.
Identified by path topology.

Launch point: PI or state element.

Capture point: PO or state element.
Difference between transition and path delay:

Transition random observation points.

Path delay specific observation point.

5-42 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 At-Speed Test

Scan Chains

10 10

Test Path

Goal = test the path for a 1 to 0 transition

FastScan automatically determines appropriate values
to load scan chain and perform test.

5-43 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 At-Speed Test (Cont.)

1 1
1
1

Define the initial path values.

5-44 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 At-Speed Test (Cont.)

1
1 1
1 1
1

Define other values to sensitize path.

5-45 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 At-Speed Test (Cont.)

1
1 0 1
1 1

0
0

Define other values to cause launch event.

Now load all defined values into the scan chain.

5-46 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 At-Speed Test (Cont.)

11
1 0
1 10
1
10
0
0

Pulse clock in functional mode to cause launch.

Causes the values to propagate through the path.

5-47 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 At-Speed Test (Cont.)

10
10

Pulse clock in functional mode to capture value

if transition propagated in time.

5-48 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 Transition Fault Patterns
FastScan uses the following transition fault patterns:
Launch-off shift.

Capture
Launch


Allows FastScan to switch scan enable At-speed
(requires additional clock routing of SE). SHIFT SHIFT Capture
Applies combinational ATPG. CLK

SE

Broadside.

Capture
Launch
Scan enable timing is not critical.
Applies clock sequential ATPG. SHIFT SHIFT Capture

Activated when clock-sequential depth CLK

is > 2.
Tests functional paths/logic. SE

5-49 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 Creating Transition Fault Patterns: Launch-Off Shift
Use the following commands to create launch-off shift
transition fault patterns:
ATPG> SET FAult Type Transition
ATPG> SET PAttern Type -Sequential 0 // default
ATPG> CREate PAtterns -Auto

It is recommended to use Broadside transition fault patterns.

5-50 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 Creating Transition Fault Patterns: Broadside
Use the following commands to create broadside transition
fault patterns:
ATPG> SET FAult Type Transition -no_shift_launch
ATPG> SET PAttern Type -Sequential 2
ATPG> CREate PAtterns -Auto

5-51 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 Timing for At-Speed Test (Cont.)
FastScan uses the following timeplates for skewed clocks:

tp_early
Used in launch-shift capture
Used in broadside capture

tp_late
Used in launch-shift load/unload and shift
Used in broadside clock-sequential
100 ns 100 ns 100 ns

20 ns

tp_late tp_early
tp_late

timeplate tp_late = procedure load_unload = timeplate tp_early = procedure capture =

force_pi 0 ; scan_group grp1 ; force_pi 0 ; timeplate tp_early ;
measure_po 10 ; timeplate tp_late ; measure_po 8 ; cycle =
pulse CLOCK 90 5; cycle = pulse CLOCK 10 5; force_pi ;
period 100 ; force CLOCK 0 ; period 100 ; measure_po ;
end; force scan_en 1 ; end; pulse_capture_clock ;
end ; end;
apply shift 7; end;
end;
5-52 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 Path Delay Pattern Flow
PATH "path0" =
PIN /p5/pic1/inst_reg_8/DFF1/Q + ; Static Timing
PIN /p5/pic1/inst_reg_8/BUF1/IN + ;
PIN /p5/pic1/inst_reg_8/BUF1/OUT + ;
Analysis Tool
PIN /p5/pic1/inst_reg_8/Q + ;
PIN /p5/pic1/U888/B + ;
PIN /p5/pic1/U888/UP1/IN1 + ;
PIN /p5/pic1/U888/UP1/OUT + ;
PIN /p5/pic1/U888/Z + ;
PIN /p5/pic1/U953/B + ;
PIN /p5/pic1/U953/UP1/IN1 + ; Critical Paths
PIN /p5/pic1/U953/UP1/OUT - ;
PIN /p5/pic1/U953/Z - ;
PIN /p5/pic1/U966/F - ;
PIN /p5/pic1/U966/UP3/IN1 - ;
PIN /p5/pic1/U966/UP3/OUT - ;
PIN /p5/pic1/U966/UP4/IN2 - ;
PIN /p5/pic1/U966/UP4/OUT + ;
PIN /p5/pic1/U966/UP5/IN + ; FastScan
PIN /p5/pic1/U966/UP5/OUT + ;
PIN /p5/pic1/U966/Z + ;
PIN /p5/pic1/U1054/D + ;
PIN /p5/pic1/U1054/UP1/IN3 + ;
PIN /p5/pic1/U1054/UP1/OUT - ;
PIN /p5/pic1/U1054/Z - ;
PIN /p5/pic1/pc_reg_2/D - ;
PIN /p5/pic1/pc_reg_2/INV1/IN - ;
Path delay
PIN /p5/pic1/pc_reg_2/INV1/OUT + ; Patterns
PIN /p5/pic1/pc_reg_2/INV2/IN + ;
PIN /p5/pic1/pc_reg_2/INV2/OUT - ;
PIN /p5/pic1/pc_reg_2/MUX1/IN1 - ;
PIN /p5/pic1/pc_reg_2/MUX1/OUT - ;
PIN /p5/pic1/pc_reg_2/MUX2/IN0 - ;
PIN /p5/pic1/pc_reg_2/MUX2/OUT - ;
PIN /p5/pic1/pc_reg_2/DFF1/D1 - ;
END
. ;
.
.

5-53 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 Path Delay Patterns

Path delay patterns contain the

following events:

Load scan chains.

Force PIs.

Pulse clock.

Force PIs.

Measure POs.

Pulse clock.

Unload scan chains.
100 ns 100 ns 20 ns 20 ns 100 ns

load load unload

capture
launch
5-54 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 Creating Path Delay Patterns
Do the following to create path delay patterns:
ATPG> SET PAttern Type -Sequential 2
ATPG> SET FAult Type path_delay
ATPG> LOAd PAths <path filename>
ATPG> CREate PAtterns

5-55 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 Optimizing Quality and Cost
Pattern optimization:

Patterns must fit within tester memory.

If patterns do not fit into tester memory, truncation is necessary.

Use the ORDer PAttern command to reorder the pattern set from
highest fault detection to least fault detection.
If truncating you will get the most productive patterns first.

ATPG> CREate PAtterns

ATPG> ORDer PAttern 3

5-56 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 Optimizing Quality and Cost
Always utilize compression and fault hierarchy when
optimizing your test pattern set.

GENERATE Path
Netlist Critical Path Patterns List
Grade for transition coverage

GENERATE Critical Path

Additional Transition Patterns Patterns
Grade for stuck-at coverage Transition
Patterns
Stuck-at
GENERATE Patterns
Additional Stuck-at Patterns

5-57 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation
 ATE Characteristics
Know the following ATE characteristics before you work on
your design:

When using DFTAdvisor, consider the following:
The number of scan channels available to the tester.
The number of clocks that the tester can support.

When using FastScan, consider the following:
The frequency of the tester.
The maximum number of timeplates that the tester can support
(restrictions might effect pattern types: At-speed and clock PO).
The memory depth of the tester.

5-58 Design-for-Test: Scan and ATPG: Achieving High Test Coverage Copyright 2006 Mentor Graphics Corporation