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    Segregated Questions

    Uploaded by

    deepa
    This document contains questions related to scan-based testing, ATPG, simulation, and JTAG topics. It includes questions about DRC issues during scan insertion and EDT, compression ratio decisions, test coverage targets, optimal test patterns, capture pulse control, NCP usage, improving test coverage, simulation mismatches, TAP controller functionality, and the advantages of using JTAG.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd

    Segregated Questions

    Uploaded by

    deepa
    297 views1 page
    This document contains questions related to scan-based testing, ATPG, simulation, and JTAG topics. It includes questions about DRC issues during scan insertion and EDT, compression ratio decisions, test coverage targets, optimal test patterns, capture pulse control, NCP usage, improving test coverage, simulation mismatches, TAP controller functionality, and the advantages of using JTAG.

    Original Description:

    dft

    Original Title

    Segregated Questions (1)

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    This document contains questions related to scan-based testing, ATPG, simulation, and JTAG topics. It includes questions about DRC issues during scan insertion and EDT, compression ratio decisions, test coverage targets, optimal test patterns, capture pulse control, NCP usage, improving test coverage, simulation mismatches, TAP controller functionality, and the advantages of using JTAG.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    297 views1 page

    Segregated Questions

    Uploaded by

    deepa
    This document contains questions related to scan-based testing, ATPG, simulation, and JTAG topics. It includes questions about DRC issues during scan insertion and EDT, compression ratio decisions, test coverage targets, optimal test patterns, capture pulse control, NCP usage, improving test coverage, simulation mismatches, TAP controller functionality, and the advantages of using JTAG.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 1

    Scan Based Qns

    1. What all DRC’s you got during scan insertion and how you handled that?
    2. Have you done any test point insertion during scan insertion and what was that?
    3. How many scan pins was there in your block and what was the chain length before
    compression?
    4. Have you done EDT? How did you decide the compression ratio or maximum internal chain
    length?
    5. Why are we going for synthesis after doing EDT?
    6. The actual compression achieved will be less than the specified compression factor. Why?
    7. Deciding factors of scan design?
    8. Scan length, Scan chains, hierarchical scan concept?

    ATPG

    1. Why do we use terminal lock up?


    2. How have you handled OCC flops during compression?
    3. What was the targeted test coverage for your block and were you able to get that?
    4. What is the optimal input pattern set for AND gate to detect all stuck-at faults?
    5. How were you getting a capture pulse in an at-speed test?
    6. How can we control the maximum number of capture pulses that we get from OCC?
    7. What is NCP? Why do we use this?
    8. At-speed coverage is always less than STUCK-at coverage. Why?
    9. How did you improve test coverage and what was the initial test coverage?
    10.What happens if you are getting DRC’s during ATPG, can we resolve it here and what is the
    impact of this on test coverage and ATPG run time?
    11.What was the ATPG run time for your block and how many patterns were generated?
    12.Two flops will have the same values during shift. What's the effect of it?
    13.Have you got any DRC’s during EDT and how you handled that?

    Simulation

    1. Why do we need simulation?


    2. EDT bypass is passing. EDT chain patterns are failing. What could be the reasons?
    3. Have you got any simulation mismatches?
    4. Setup violations are there in your design. Which patterns would fail? (s@ or @speed?)
    5. Hold violations are there. Which patterns would fail?
    6. How did you debug the mismatches in serial and parallel simulation for scan and chain test?
    7. Why were we doing parallel simulation?
    8. Is it necessary to run a serial simulation?
    9. Are the serial and parallel patterns the same or different?
    10. What is timing and no timing simulation or zero delay and with delay simulation?
    11. What is X mismatch and binary mismatch in simulation?

    JTAG
    1. What are the advantages of JTAG and why are we using JTAG?
    2. What is a TAP controller?

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