Deepa PPT 49
Deepa PPT 49
Deepa PPT 49
B.Deepa (17Q61D5708)
M.TECH (VLSI )
Contents
ABSTRACT
INTRODUCTION
LITERATURE REVIEW
EXISTING SYSTEM
PROPOSED SYSTEM
RESULTS
SYNTHESIS REPORTS
COMPARISON TABLE
IMPROVEMENTS OBSERVED
CONCLUSION
ABSTRACT
In this paper we design DLAU, which is a scalable
accelerator architecture for large-scale deep learning networks for
CNN structure using DLAU controller.
The DLAU accelerator employs three pipelined processing
units to improve the throughput and utilizes techniques to explore
locality for deep learning applications.
INTRODUCTION
In the past few years, machine learning has become
pervasive in various research fields, applications and
achieved satisfactory products.
The emergence of deep learning speeded up the
development of machine learning and artificial intelligence.
Consequently, deep learning has become a research hot
spot in research organizations.
In general, deep learning uses a multilayer neural
network model to extract high-level features which are a
combination of low-level abstractions to find the
distributed data features, in order to solve complex
problems in machine learning.
EXCITSING SYSTEM
TMMU , PSAU & AFAU
TMMU is in charge of multiplication and
accumulation operations.
PSAU is responsible for the accumulation operation.
PSAU architecture, which accumulates the part sum
produced by TMMU.
If the part sum is the final result, PSAU will write the
value to output buffer and send results to AFAU in a
pipeline manner.
Conc………………
Finally, AFAU implements the activation function
using piecewise linear interpolation .
This method has been widely applied to implement
activation functions with negligible accuracy loss. In
activation function implementation of sigmoid
function is done.
PROPOSED SYSTEM
Description
In order to explore the locality of the deep learning
application, we employ tile techniques to partition the
large scale input data.
The DLAU architecture can be configured to operate
different sizes of tile data to leverage the trade-offs
between speedup and hardware costs.
Consequently the FPGA based accelerator is more
scalable to accommodate different machine learning
applications.
DLAU Controller
Description
The DLAU accelerator is composed of three fully
pipelined processing units, including TMMU, PSAU,
and AFAU.
Different network topologies such as CNN, DNN, or
even emerging neural networks can be composed from
these basic modules.
Consequently the scalability of FPGA based
accelerator is higher than ASIC based accelerator.
CNN (Convolution with laplacian filter stage 1)
if(enable) begin output1 <= 0;
output2 <= 0; output3 <= 0;
output4 <= 0; output5 <= 0;
done <= 1'b0; end
else begin
output1 <= {1'b1, ~(input2)} + 5'b00001;
output2 <= {1'b1, ~(input4)} + 5'b00001;
output3 <= {2'b00, input5} << 2;
output4 <= {1'b1, ~(input6)} + 5'b00001;
output5 <= {1'b1, ~(input8)} + 5'b00001;
done <= 1'b1;
FSM diagram for AFAU
RESULTS
SYNTHESIS REPORT
Area Utilization Power Utilization
COMPARISON TABLE
IMPROVEMENTS OBSERVED
CONCLUSION
In current design scenario we have seen Author () have proposed
DLAU with CNN architecture with 2x2 and 4x4 as separate
models
Our design criteria improvises a novel concept of CNN structure
for both 2x2 and 4x4 for each internal modules utilized in design.
This proposed structure utilized only 2 L-Filters, 3 adders and 1
max-pooling circuits where as for exitisng scenario we need to
provide at least 2 filters and 8 adders with one max-pooling
modules.
We propose the design of deep learning accelerator unit using
FSM which can reduce power consumption and speed up device.
THANK YOU