NXP Questions & Answers

By
Siva Sreeramdas
VLSI Design Flow
Specifications

Architectural Design

RTL Coding & Functional

Verification

Logic Synthesis

Logic verification & test

DFT Insertion

Physical Design

Fabrication
 SCAN
• We can control the inputs and observe the output nodes in a planned
manner.
• Replacing all the flipflops with scan flops.
• Scan chains are inserted into the design to shift the test data into and out
of the chip.
• This is done by making every point in the chip controllable and observable.
• Purpose is to test the stuckat faults and also to test path in manufacturing devices
for delay.

D MUX
Q
SI
FF
SE
CLK
 ATPG DRC’s
Bypass mode Violations:
Error message :
Scan chain blocked at gate N (G) after tracing C Cells
1. T3

010 CLK Q 0X0 1X1 CLK Q SSS

SSS SI SSS SI
000 D SFF 000 D SFF
111 SHIFT 111 SHIFT
000 RST 000 RST

• In the above case I added cutpoint on Q output

add_primary_inputs –internal /…/…/…/Q -name clk_cut
add_clock 0 cclk_cut
2. BB
010 CLK Q SSS
ZZZ ZZZ ZZZ SI
000 D
111 SHIFT SFF
000 RST
By reading the BB modules issue got resolved
Compression mode:
3. K19

P Q 010 0
A FF 1
D

1
Programming register

• Here above one cell advance data is detected at EDT decompressor output
during chain index.

Expected 0 0 0 0 0 1 0 1 1 0 1 1 0
Simulated 0 0 0 0 1 0 1 1 0 1 1 0 0
4. F8
• To debug this F violation, we need to turn off the edt finder in the shell.
EX: set_edt_finder off
set_system_mode analysis
• The above violation will turn in to T3 or T5, K19 etc.. Which is easy to
debug.

5. E8
• Multiple clocks are used to shift master of scan chain causing E8 violation.
• Two clocks leads to clock skew on the tester.
 Lockup Latch
• They are mainly used to reduce the clock skew.
• When ever there is any domain crossover happens this lockup latch are
used.
• This lockup latches are used to fix the hold time issues in shift mode.
• With out lockup latch, it is difficult for the STA team to close the timing in
scan chains.
• This lockup latch induce half cycle delay.
• Always use –ve flop followed by +ve flop during intersection.

D1 Q1 D Q D2 Q2

FF1 L FF2

CLK1 EN
CLK2
 Waveforms

CLK

D1

Q1

L_D

L_Q/D2

Q2
 Simulations
Zero delay
• Zero delay is used to validate the scan structure
Timing
• Timing is to cross check, all the gate elements are meeting the timing or not.

Zero delay Debug

1. Simulated x expected 0
• I have loaded the failing register in the shell from the log file, when I trace back I
noticed a 4x1 mux that is giving logic 1 output.
• In GLS for the same failing register, input conditions are same as ATPG but output is X.
• So by creating a verilog module with UDP, the issue got resolved.

2. Simulated x expected 0
• ram_wrap registers are failing, I have masked all the registers .
• By added cell_constraints on the output of this ram_wrap to TX.
• Rerun the atpg for pattern generation and simulated the patterns, later this issue got
fixed.
3. Simulated 1 expected 0
• In the log file tool will show you the exact failing register and particular
time and also the cycle in which it is failing.
• I have opened the failing register in the visualizer and also in the
waveform.
• I trace backed the pin into the combinational logic and analyzed what
values it is simulating.
• I analyzed do there is any logic in between that it is not able to propagate
the value.
• I have added the forces in the output pin in the cmd file.

Timing Debug
Simulated x expected 0
• For timing related failures, open the failing pattern both in zero delay and
also in the timing and compare both the waveforms and debug.
Zero delay

CLK

SE

Timing

CLK

SE

• Clock is coming earlier, so I have added dead cycles in procedure capture

and procedure clock sequential before and after the capture pulse.
• Zero delay simulation is done with pre layout netlist.
• Timing simulations are done with post layout netilst.
• There are two corners.
• Min, here we are looking for hold violation which is best case.
• Max, we are looking for setup violation which is worst case.
 Coverage
• Different Fault categories
Untestable
• Unused
• Blocked
• Tied
• Redundant
Testable
Detected
• Det_simulation
• Det_implication
Posdet
• Posdet-testeable – PT
AU
• Tied cells
• Au.seq
• Pin constraints
Undetected
• UC
• UO
Approach
• Load the flat model
• Read the latest faults
• Verify the coverage is same after reading the faults.
• Load the cell in the visualizer
• identify which type of fault is present in the pins.
• Trace back or forward to get coverage improvement.
• Apply the coverage improvement changes in corresponding files.
• Set_system_mode setup –force
• Set_system_mode analysis
• reset_au_faults
• create patterns
• Report_statistics
• Verify the coverage you got with the previous coverage.
 atspeed
• Atspeed testing is mainly used to test the timing related defects.
• In order to test the timing related defects we require two patterns, one for
Launching and other for Capturing.
• There are two approach in which we test the atspeed patterns.
1. LOC
2. LOS
LOC

CLK

SE

• We don’t have control on the value what we are launching.

• Pattern count and runtime increases and coverage decreases.
LOS
----- -----
CLK

SE

• We have control on the value what we are launching,

• Coverage increases and pattern count and runtime decreases.
• Disadvantage with LOS is capture should happen at atspeed.
 Netlist
netlist

Pre layout post layout

• Pre layout netlist is used for zero delay simulations.

• Post layout netlist which we get from PD team, which includes addition of
buffers, inverters and STA analysis
• Post layout netlist is released along with SDF files.
• This PD netlist should undergo again for chain tracing and pattern
generation.
 Verification

Verification

Functional Formal
(Logic verification test)

cadence synopsis
(conformal) (formality)
Cadence
• Golden netlist means synthesized netlist -> functional mode
• Revised netlist means scan inserted netlist -> test mode
Synopsis
• Referenced netlist which is synthesized netlist - > functional mode
• Implemented netlist which is scan netilst -> test mode
Functional Verification
• Verifying that a design has the desired functionality, it was intended to
have.
• It is about creating the write all possible combinations of test to verify the
SoC.

Formal Verification
• It doesn't care if your SoC is going to be a USD or any.
• It understands the SoC as a normal block with inputs and outputs and
flops.
• The combo logic between flops is matters.
• It include gate-level simulation, Static timing analysis, and formal
equivalence checking
• These are tools aimed at verifying that the synthesis tool created a valid
and equivalent netlist to the original RTL.
 Compression
• It is mainly used to reduce the test application time and test data volume.
• As the test time is reduced test cost is also reduced.

EDT Decompressor

Compactor
Compressed Compacted
stimuli ATE responce
Decompressor
• Consists of ring generator and phase shifters
• Decompressor drives scan chain input
• Output of ring generator is connected to input of scan chain through
phase shifters

Compactor
• It consists of masking logic and xor tree.
• Compactor drives the scan chain output
• Masking logic consist of pattern mask register, decoder and AND gates
before xor.
• Masking logic can handle any number of X’s.

• Compression Ratio = No. of scan chains

N0. of scan channels
Thank You