Compression Notes
Compression Notes
Compression Notes
1. what is compression?
LSSD LSSD
• If the control pin used to select bypass or compression mode is shared with
the edt_bypass pin, the bypass chains must be active when the edt_bypass pin
is at 1, and the scan chains must be active when the edt_bypass pin is at 0.
• Test procedure file for the EDT logic must set up the mux select, so the
shortened internal scan chains can be traced.
Inserting bypass chains with a scan insertion tool ensures that lockup cells and
multiplexers used for bypass mode operation are fully integrated into the
design netlist to allow more effective design routing.
Test patterns:
A set of test patterns are stored on the ATE and each test patterns applies data
to the input of decompressor and hold the responses and observed on the
output of compactor.
Functional input and output pins are directly controlled(forced)and
observed(measured) by the tester.
10.what is the use of bypass logic?
I. debug the compressed test patterns.
ii.more effective design routing.
11. What is the internal flow and external flow of the design?
Because the clock used in the EDT logic is different than the scan clock, lockup
cells can be inserted automatically between the EDT logic and the scan chains
as needed. The tool inserts lockup cells as part of the EDT logic and never
modifies the design core.
You set the EDT clock to pulse before scan chain shift clock with the
pulse_edt_before_shift_clocks switch of the set_edt_option command.
By default edt and scan chain shift clocks are pulsed simultaneously.
• Makes creating EDT logic for a design in the RTL stage easier because scan
chain clocking information is not required. For more information on creating
EDT logic at the RTL stage, see “Integrating Compression at the RTL Stage” on
page 305.
• Removes the need for lockup cells between scan chains and the EDT logic
because correct timing is ensured by the clock sequence. Only a single lockup
cell between pairs of bypass scan chains is necessary. For more information,
see “Understanding LockupCells” on page 269.
• Simplifies clock routing because the lockup cells used for bypass scan chains
are driven by the EDT clock instead of a system clock. This eliminates the need
to route systemclocks to the EDT logic.
To use this functionality, the shift speed must be able to support two
independent clock pulses in one shift cycle, which may increase test time.
Compressed ATPG test patterns can be written out in ASCII and binary
formats, and can read back into the tool.
When you create patterns with compression, the captured data is
stored with respect to the internal scan chains and the load data is stored with
respect to the external scan channels. The load data in the pattern file is in
compressed format—the same form it is fed to the decompressor.
Uncompressed patterns, you can use this formats primarily debugging
simulation mismatch archiving.
14.compression which type of faults it support?
i.stuck_at..
ii.transition.
iii.iddq.
iv.path delay.
15. What is the post synthesis EDT ip creation and EDT pattern generation
flow?
EDT IP generation:
By default the tool writes out the RTL files in the same format as original
netlist. You can use either pre_synthesis flow or post_synthesis flow to
generate EDT IP and create TCD file