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Interview Questions Related To Scan, ATPG, EDT and Simulation

This document contains 38 interview questions related to topics in digital design test such as scan insertion, automatic test pattern generation (ATPG), embedded deterministic test (EDT), and simulation. The questions cover areas like the blocks and design features the candidate has worked with, how scan insertion and EDT were performed, techniques for improving test coverage, resolving issues found during ATPG and simulation, and purposes of different types of simulation.

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Siva Sreeramdas
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2K views

Interview Questions Related To Scan, ATPG, EDT and Simulation

This document contains 38 interview questions related to topics in digital design test such as scan insertion, automatic test pattern generation (ATPG), embedded deterministic test (EDT), and simulation. The questions cover areas like the blocks and design features the candidate has worked with, how scan insertion and EDT were performed, techniques for improving test coverage, resolving issues found during ATPG and simulation, and purposes of different types of simulation.

Uploaded by

Siva Sreeramdas
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Interview Questions Related to Scan,ATPG,EDT and simulation

1. What have you done so far in DFT?


2. How many blocks was there in your last project and what were the flop counts?
3. How many blocks have you handled in the last project,how many clocks was there in
your block,how were you controlling the clock and how many OCC was there?
4. What were the clock frequencies for stuck-at and TDF?
5. What all DRC’s you got during scan insertion and how you handled that?
6. Have you done any test point insertion during scan insertion and what was that?
7. How many scan pins was there in your block and what was the chain length before
compression?
8. Have you done EDT ?How did you decide the compression ratio or maximum internal
chain length?
9. Why do we use terminal lock up?
10. Why are we going for synthesis after doing EDT?
11. Have you got any DRC’s during EDT and how you handled that?
12. How have you handled OCC flops during compression?
13. What was the targeted test coverage for your block and were you able to get that?
14. What is the optimal input pattern set for AND gate to detect all stuck-at faults ?
15. How were you getting a capture pulse in an at-speed test?
16. How can we control the maximum number of capture pulses that we get from OCC?
17. What is NCP?Why do we use this?
18. What is a wrapper cell?
19. Have you used a Wrapper cell and why?
20. Atspeed coverage is always less than STUCK-at coverage. Why?
21. How did you improve test coverage and what was the initial test coverage?
22. What happens if you are getting DRC’s during ATPG ,Can we resolve it here and what
is the impact of this on test coverage and ATPG run time?
23. What was the ATPG run time for your block and how many patterns were generated?
24. Two flops will have the same values during shift. What's the effect of it?
25. Why do we need simulation?
26. EDT bypass is passing. EDT chain patterns are failing. What could be the reasons?
27. Have you got any simulation mismatches?
28. Setup violations are there in your design. Which patterns would fail? (s@ or @speed?)
29. Hold violations are there. Which patterns would fail?
30. How did you debug the mismatches in serial and parallel simulation for scan and chain
test?
31. Why were we doing parallel simulation?
32. Is it necessary to run a serial simulation?
33. Are the serial and parallel patterns the same or different?
34. What is timing and no timing simulation or zero delay and with delay simulation?
35. Why do we go for parallel simulation?
36. What is X mismatch and binary mismatch in simulation?
37. What are the advantages of JTAG and why are we using JTAG?
38. What is a TAP controller?

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