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Design For Test (DFT) Course Module - 1 JTAG and Scan Insertion Course Duration: 6 Weekends (Sundays)

This document outlines a 12-week course on design for test (DFT) that is divided into two modules. The first module covers JTAG and scan insertion over 6 weeks, including topics like boundary scan, scan architectures, scan design rules, and compression techniques. The second module covers ATPG and simulations over another 6 weeks, with topics such as fault models, ATPG algorithms, transition fault testing, and diagnosis flows. The course is intended to provide experienced training on DFT topics from product company employees.

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Siva Sreeramdas
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
101 views

Design For Test (DFT) Course Module - 1 JTAG and Scan Insertion Course Duration: 6 Weekends (Sundays)

This document outlines a 12-week course on design for test (DFT) that is divided into two modules. The first module covers JTAG and scan insertion over 6 weeks, including topics like boundary scan, scan architectures, scan design rules, and compression techniques. The second module covers ATPG and simulations over another 6 weeks, with topics such as fault models, ATPG algorithms, transition fault testing, and diagnosis flows. The course is intended to provide experienced training on DFT topics from product company employees.

Uploaded by

Siva Sreeramdas
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Design for Test (DFT) Course

MODULE -1
JTAG and Scan Insertion
Course Duration: 6 weekends (Sundays)

WEEK -1

 Full ASIC flow – DFT


 DFT Basics
 Boundary scan / JTAG basics
 Boundary scan cell operation in detail
 JTAG operation
 TAP controller state machine
WEEK -2

 Understanding of SCAN in depth


 Types of Scan architecture
 Scan architecture overview
WEEK -3

 Test cases assignments review


 Assessment on Boundary scan
WEEK -4

 Scan design rules


 Design Rule Checking (DRC)
 DRC Fixing with examples
WEEK -5

 Full scan insertion and stitching without compression


 Multiple clock domains in SoC
 Handling multiple clock domains during shift and capture
WEEK -6

 Basics and Need of Compression


 Compression techniques
 Scan insertion with compression
 On-chip clocking for at-speed testing
 Hierarchical Scan Design
WEEK -7

 Test cases assignments review


 Assessment on Scan Insertion
MODULE -2
ATPG and Simulations
Course Duration: 6 weekends (Sundays)

WEEK -1

 DFT Overview – ATPG


 Understanding of Defects and Faults
 Types of fault models
 Basic concepts of ATPG
 ATPG algorithm
 Different types of ATPG
WEEK -2

 Stuck-at fault model (In detail)


 Understanding of ATPG constraints
 ATPG DRC analysis
 ATPG for Stuck-at fault model
 Coverage improvement techniques
WEEK -3

 At speed fault model (In detail)


 Understanding Transition fault ATPG
 ATPG setup for transition fault model
 ATPG for Transition fault model
WEEK -4

 Introduction to Diagnosis
 Diagnosis Flow
 Analyzing failure logs
 Chain Failure Diagnosis
 Successful results
WEEK -5

 Test cases assignments review


 Assessment on ATPG & Simulations
WEEK -6
Preparation for Interviews & guidance
Course Duration: 12 Weeks [Saturday and Sunday’s]
Trainer: Experienced Top Product based company Employee’s

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