Scan IMP Questions

Created by:-Er.Manjeet Singh

1. What is DFT 33. what is test point Insertion? Can you tell and
2. What are two pillars of DFT explain one TestPoint Insertion scenario?
3. What are penalties of DFT 34. what is the use of clock gaters in design?
35. Draw the internal diagram of clock gating cell?
4. What is rule of 10
36. what is use of latch in clock gating cell?
5. What are the levels of Testing. 37. How glitches can be remove through latch?
6. Difference between verification & testing 38. Draw the muxed flip flop and explain?
7. Draw ex-or gate using nand gate find total no. Of 39. Take three scan flop and stitch it and explain the
stuck@, TDF,PDF scan operation
8. Why we need scan,Why we convert normal D FF 40. How you will decide the number of scan chains
to scan FF for your core?
41. what are Manufactured defects?
9. Why scan frequency is less than functional
42. what is clock latency?
frequency 43. what is lockup latch and why we use it?
10. Take 3 FF explain scan operation. 44. will latency effect data shifting in scan chain?
11. Explain scan styles 45. consider two flop of .2sec and 0.3 sec latency
12. Explain scan types how do you connect the flops in scan chain?
13. What will happen if I do testing with normal D ff 46. Implement a 2 by 1 Mux through gates?
14. What is the importance of testmode & scan 47. what all information you will ask from designer
for smooth scan insertion?
mode.
48. what all ctls you read while scan insertion?
15. Take two input OR gate and AND gate target 49. which one is better having single or multiple scan
stuck at 0, stuck at 1 for each node & generate clock?
patterns 50. In which path we insert the lockkup latch, data or
16. Draw the waveform of muxed scan cell operation clock path?
17. What are the major concerns of scan design? 51. How you will resolve the combinational feedback
loop issue in design if present?
18. Why clock should not be driven as data?
52. why we don't connect the capture flop's clock to
19. Why data should not drive as clock? the lockup latch?
20. Explain why reset must be controlled from 53. why we use flop trays in design?
primary input? 54. what is the purpose of DFT?
21. If there are any shift registers present in design, 55. what work around you can do if you don't have
then do you convert it into scannable flop, give scan equivalent for some flops in design while
reason scan insertion?
56. Different types of faults?
22. What is meant by lockup latch? When to use
57. Explain ASIC Flow?
lockup latch, Illustrate with example. 58. What is difference between ASIC and FPGA?
23. How do you do the continuity test for the scan 59. What is problem if we do not have DFT?
chain? What are the vectors are used for chain 60. What is meaning of defect , fault and error?
test. 61. What is YIELD? What is DPPM?
24. Explain atleast 3 DRC’s with example. 62. What is test coverage & fault coverage
25. Why bus contention should be avoided during 63. Why achieving good test coverage is important?
64. Who all are major DFT Tool vendors and what
shift operation in the scan chain? what is the
all are the names of DFT tools?
recommended solution for bus contention. 65. Explain the inputs needed for carrying out scan
26. Why bi directional i/o ports are trouble during insertion for a design?
shift operation? Illustrate with example. 66. What is scan chain balancing and what is the
27. Why tri-state buses should be fixed? What is the need of it?
recommended solution for fixing the violation. 67. Why need terminal lockup latchs?
68. How do you differentiate shift and capture?
28. How do you fix derived clocks, explain with
69. What is the impact of having latches in the
example. design?
29. Why latch is not converted into scannable flop? 70. Can latches is a part of scan chains, explain?
Why it should be transparent when clocks are 71. What is scan? What are the difference between
off? full scan and partial scan?
30. Explain scan insertion steps? 72. What are the benefits of scan?
31. what are the basic things that needs to take care 73. What is scan chain and scan group?
for Scan Insertion? 74. What is observability and controllability?
32. what are the DRC Violations that u have faced 75. What is the use of shift enable and test mode
during Scan Insertion and how did you fix those ? signal?
76. What are the inputs and outputs for scan?
 Scan IMP Questions
Created by:-Er.Manjeet Singh

77. How do you take care negative-edge flops during

scan insertion?
78. If design having multiple clock domains, how do
you take care during scan insertion?
79. What are the the advantages and disadvantages of
clock mixing and non-clock mixing?
80. Explain following figure

81. Where are negative edge flops place in scan

chain? Can negative edge flops be in between
scan chains, if explain what precautions to be
taken care?

82. What is CTL and why need to use during scan

insertion?
83. If IP is already scan inserted, how do you taken
care during scan insertion?
84. How to avoid hold issue when scan chain is
stitched from positive edge to negative edge flop?
85. How asynchronous and synchronous are handled
for scan?
86. Can we have the shift frequency same as
functional frequency?
87. How to solve setup and hold violations in a
design?
88. Give three clocks DRC rules and how to fix
them?
89. What you mean by scan chain reordering?
90. Apart from the conventional mux FF scan
architecture, there are many others like the Level
Sensitive scan and the clocked scan etc. How are
these better or worse than the muxed FF
technique?
91. I have three types of flops in my design. 1.clock
domain positive edge 2.clock domain negative
edge 3.RCO_clock domain positive edge only. Is
it feasible/possible to put them in one scan chain?
92. In scan chains if some flip flops are +ve edge
triggered and remaining flip flops are -ve edge
triggered how it behaves?
93. Give the formula for area over head.
94. How much % of chip area is allotted for DFT.
95. Explain do file & test proc file
 EDT IMP Questions
Created by: Er. Manjeet Singh

1. Why we don’t go for high compression like 90- 34. Draw & explain EDT wave form.
100%. 35. Difference between ASIC & FPGA.
2. Draw & explain decompressor block. 36. Tools used for EDT insertion in Mentor &
3. Draw & explain compactor block. Synopsis.
4. How will you decide compression ratio. 37. Commonly used Compression Technique.
5. Explain SDC file. 38. Find C.R.
6. What is bypass mode in EDT.
7. What is EDT, why we use it.
8. Drc’s faced during EDT insertion.
9. What is EDT clock state during capture.
10. What is EDT update state during load_unload
11. Estimate the compression ratio for following
specification.
1. The design consist of 10k FF ,10 input ,10
Output
2. How many FF needed to keep in each chain 39. Find C.R.
to achieve a)20% b)100% c)50%
12. Take one example & explain how edt reduces
TAT.
13. What is meant by masking or X blocking, explain
types of masking.
14. Explain fault aliasing.
15. Explain fault collapsing.
16. How to share EDT clock & scan clock.
17. Explain pipeline stage used in compactor.
18. What are lockup cells. 40. EDT works on edt clock & scan works on scan
19. What are the advantages of EDT. clock,draw a diagram showing both clock.
20. What is the reason for increase in pattern count 41. Why only x-or gate used in compactor & phase
for compressed mode. shifter.
21. The actual compression achieved will be less 42. I have 330 internal core chains to each
than the specified compression why ? edt_channel & there are 7 edt channels.while
22. Explain k-17,k-18,k-19 violation. performing simulation the log file reporting that a
23. How are x’s handled in EDT , what is their flop is producing x instead of 1 in edt channel 2.
effect. How to fix this.
24. How do you control the ‘AND ‘ logic which is 43. Is it possible to reconvert the scan FF to normal
used to prevent ‘x’ from propagating to x-or FF .
logic. 44. Which reset is preferred active low or active
25. Is decompressor a combinational or sequential high.
block. 45. What is the off state for active low reset.
26. Write & explain test procedure file used in EDT. 46. What is the off state for active high reset.
27. What are the input & output files of EDT 47. What is scan sysnthesis.
insertion. 48. What is scan configuration.
28. Does coverage increase or decrease with increase 49. Whether RTL drc’s & DFT drc’s are same.
in compression. 50. What is spyglass.
29. How the compression technique factor affect the
number of scan chain? Is number of clock
domain also a factor.
30. What do you mean by TDV.
31. How many cycles required for loading of 3
patterns through 100 FF in normal mode &
pipeline mode.
32. ATE costs depend on.
33. Explain F9,F10 violation.
 ATPG IMP Questions
Created By: Er.Manjeet Singh

1. What is pattern optimization. 31. What is atpg effectiveness.

2. What is pattern retargeting. 32. What is robust /non-robust path delay
3. How to reduce power dissipation as faults
DFT engineer 33. What does do file contain
4. How to share EDT clock & scan clock 34. How many fault site are there for 2 i/p
5. How to test BB. AND gate
6. How to test reset. 35. What is pseudo random pattern
7. How to improve coverage. generator.
8. Drc’s result in low coverage. 36. What is iddq test.
9. Why stuck@ coverage is more than 37. Have you ever seen condition statements
transition coverage. in spf.
10. Difference Between LOC & LOS 38. If we have cover all transition faults
11. Difference Between stuck@ and along a critical path already ,then should
transition fault model. we check path delay.
12. What are the input & output files of 39. What are the advantages of modular
atpg. atpg.
13. Explain Fault classes. 40. What is hierarchical & flattened atpg.
14. Explain Fault Models. 41. What is sequential depth, how
15. Difference Between combinational & increasing sequential depth helps in
sequential atpg improving coverage.
16. Difference Between transition & path 42. On what basis we select LOC & LOS.
delay. 43. What are the techniques to reduce
17. What spf/test procedure file contains. pattern count with out loosing coverage.
18. Explain fault collapsing. 44. Why we have both transition & path
19. Drc’s faced during atpg delay fault model
20. What is test coverage & fault coverage. 45. Are the fault on reset of flops are
21. Why we measure po before capture detected.
clock. 46. How to toggle reset to get coverage.
22. Explain abort limit & possible credit 47. What is scan chain tracing.
limit. 48. Can you write atpg run script
23. What command you used for fixing the 49. Can you write atpg test procedure file.
clock,set,reset violation during scan 50. What are the tools you used for atpg.
24. What are the steps for converting the 51. How 2 pulses are generated for
library from synopsis to mentor. transition faults
25. What are the commands for creating 52. How will you increase transition test
user defined scan ports. coverage.
26. What is the command for creating the 53. How DFT vectors are different from
no. of scan chains. functional vectors.
27. Commands for setting the abort limit & 54. Explain T3,T4,T5 violation
possible credit limit. 55. Explain P27,P6,P8,P11 violation.
28. Generate Loc pattern for 2 i/p or gate.
29. What are different atpg modes.
30. What is atpg , why we use it.
 Simulations IMP Questions
Created by: Er. Manjeet Singh

1. What is simulation. 30. How can you tell if the patterns were
2. Explain 3 steps of simulation. generated for an EDT design or fastscan
3. What we do in simulation, what is the design.
use of simulation in DFT. 31. What commands should you look for in
4. Difference between serial & Parallel the logfile to see, if there are any
simulation. internal defined clock or pin.
5. Which simulation we use for debugging 32. Explain (i).po.name (ii).chain.name
the mismatch. (iii).v.0.vec (iv).v.cfg (v).v (vi)-
6. What are chain patterns. voptargs (vii)-novoptargs
7. What are basic patterns. 33. Difference between two dft libraries.
8. What are clock sequential patterns. 34. What values we are comparing during
9. What is psd flow. simulation debug.
10. Explain debugDB switch 35. Difference between simulation &
11. Which patterns we are going to deliver Emulation.
to tester (ATE) 36. What are ram sequential patterns.
12. Explain the steps for chain pattern 37. Whether debugging process for
debug. compressed & Bypassed pattern is same.
13. Explain the steps for scan pattern debug. 38. What is setup time & hold time.
14. What is the use of flattened design 39. What violation will occur if setup &
during simulation debug. hold not maintain properly.
15. What are the files we save after atpg. 40. If clock skew is more than half clock
16. Difference between testbench & cycle then how you will avoid the hold
Testvector. violation.
17. Can you write debug_atpg script. 41. If scan chain is broken how you debug.
18. What patterns we load in atpg view 42. What is setup slack equation.
during pattern mismatch debug. 43. What are main causes of simulation
19. What are the two main commands used mismatch.
for simulation debug. 44. Can you write simulation run script used
20. Difference between timing & No timing in questasim.
simulation. 45. How do you design a clock gating
21. What is sdf file. circuit which is glitch free.
22. What is c6 drc violation mismatch. 46. What is critical path , false path & multi
23. What is T24 drc violation mismatch. cycle path.
24. Input/output files for simulation. 47. In your design if you have both setup &
25. How to handle BB during simulations. hold time violation, which one you
26. What pattern buffer does read_patterns resolve first & why.
place the patterns into internal or 48. Adding lockup latch, is it helps to avoid
external. hold time violation.
27. What is preshift & postshift 49. What is difference between RTL & Gate
28. What are the issues you faced during level simulation
notiming simulation. 50. What is the difference between zero
29. What are the issues you faced during delay & unit delay simulation.
timing simulation.