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    Interview Questions-Deepak

    Uploaded by

    Deepak Tiwari
    The document discusses various concepts related to testing digital circuits including scan insertion. It asks about clock skew, synchronous vs asynchronous reset, scan specifications, non-scan flops coverage, hold time violations, scan synthesis, lock-up latches usage scenarios, wrapper flops insertion, dedicated and shared wrapper cells, LOC vs LOS, testability, scan insertion tools and commands, design rule check violations, scan insertion outputs, compression techniques, EDT update signals, JTAG architecture and pins, IDCODE register, INTEST and EXTEST operations, and OCC architecture.

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    © All Rights Reserved
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    Interview Questions-Deepak

    Uploaded by

    Deepak Tiwari
    33 views1 page
    The document discusses various concepts related to testing digital circuits including scan insertion. It asks about clock skew, synchronous vs asynchronous reset, scan specifications, non-scan flops coverage, hold time violations, scan synthesis, lock-up latches usage scenarios, wrapper flops insertion, dedicated and shared wrapper cells, LOC vs LOS, testability, scan insertion tools and commands, design rule check violations, scan insertion outputs, compression techniques, EDT update signals, JTAG architecture and pins, IDCODE register, INTEST and EXTEST operations, and OCC architecture.

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    Interview questions-Deepak

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    The document discusses various concepts related to testing digital circuits including scan insertion. It asks about clock skew, synchronous vs asynchronous reset, scan specifications, non-scan flops coverage, hold time violations, scan synthesis, lock-up latches usage scenarios, wrapper flops insertion, dedicated and shared wrapper cells, LOC vs LOS, testability, scan insertion tools and commands, design rule check violations, scan insertion outputs, compression techniques, EDT update signals, JTAG architecture and pins, IDCODE register, INTEST and EXTEST operations, and OCC architecture.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    33 views1 page

    Interview Questions-Deepak

    Uploaded by

    Deepak Tiwari
    The document discusses various concepts related to testing digital circuits including scan insertion. It asks about clock skew, synchronous vs asynchronous reset, scan specifications, non-scan flops coverage, hold time violations, scan synthesis, lock-up latches usage scenarios, wrapper flops insertion, dedicated and shared wrapper cells, LOC vs LOS, testability, scan insertion tools and commands, design rule check violations, scan insertion outputs, compression techniques, EDT update signals, JTAG architecture and pins, IDCODE register, INTEST and EXTEST operations, and OCC architecture.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 1

    1.

    Explain the concept of clock skew


    2. What is difference between synchronous and asynchronous reset?
    3. What are the scan specification required before scan insertion?
    4. If there are two non-scan flops between two scan flip-flops and after specifying the sequential
    depth, will the non-scan flip flops be included in the coverage?
    5. Explain hold time violation?
    6. What is scan synthesis?
    7. Explain the different scenario where we can use lock-up latches?
    8. Why to insert wrapper flops?
    9. What is dedicated and shared wrapper cell?
    10. What is difference between LOC and LOS ?
    11. How will you make your design testable?
    12. What is scan insertion? Which tool you have used for scan insertion? Explain the command with
    switches you have used during scan insertion?
    13. What is design Rule check? What are the violations you have faced during Scan insertion?
    14. What are the outputs of scan insertion? Explain ?
    15. What is Compression? Which technique you have used? Explain the architecture?
    16. Why EDT update signal required?
    17. What is JTAG? Explain its Architecture? Why RST a optional pin?
    18. What is IDCODE Reg?
    19. Explain INTEST and EXTEST operation in JTAG?
    20. What is OCC? Explain the Architecture?

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