INTEL - interview-1(Interviewer - Jayanth)

1. Can u introduce yourself? and can u brief ur technical skills, your strong areas and
area of interests?
2. What are the things u are aware of physical verification?
3. How can you divide ASIC flow from RTL to GDS(tapeout) into 4 or 5 steps??

4. What exactly is the difference between pre-layout STA and post layout STA?
5. What is the model u use during pre-layout STA and during post layout STA?
6. Why is accuracy less in pre-layout STA and more in post layout STA ?
7. What is the extra information u get after physical synthesis and what is the
information u dont have before physical synthesis?
8. Which part of the digital logic design you are interested in and why?
9. For an xyz STA tool, what are the inputs u are going to give and what are the
outputs u are going to get ?
10. What is the very first thing required for an STA analysis?
11. What do u mean by a synthesis code?
12. Will STA go for the false path analysis also?
13. What are the construction parts so to analyze these setup time and a hold time,
basically what are the list of elements used to get an accurate picture of SETUP and
HOLD?
14. What are the factors which will influence these SETUP and HOLD time?
15. If it is true that because of Crosstalk, there is an increase in delay then it is good for
HOLD time right? Then y u call crosstalk as a disadvantage?
16. What are the different types of power dissipations in a digital ckt?
17. ​Why static power dissipation is dominating as we go on scaling?
18. Tell me about ur project?

INTEL - interview-2(Interviewer - Ashok)

1. Can u quickly brief about yourself for next 5 minutes?

2. How good u are in digital electronics?
3. Can u quickly built xnor gate with muxes?
4. How many 2:1 muxes require to built an xnor gate?
5. There is a triangle, each corner of the triangle have one object. That objects can move
any direction from the corners.What is the probability that any two objects collide each
other?
6. What is SETUP and HOLD times?
7. How will you solve the SETUP violation?

INTEL - interview-3(Interviewer - Saurav)

1. Project details
2. Two separate always blocks a1 and a2. Some condition in a2 should stop the
execution of a1. (Verilog)
3. System verilog concepts - assertions, constraints
4. Oops concepts
5. Fork join
6. Or using mux
7. What is glitch . How to remove it.
8. Make an array with all unique elements
9. Sort an array with min. No. Of comparisons.
10. Perl basics- diff btw single and double quotes.
11. Diff btw latch n flipflop
12. Freeze statement in verilog
13. Automatic task

INTEL - interview-4(Interviewer - Anand)

1.which hdl languages do u know?

2.fibonacci series in verilog you reach a number that 16bit register cannot hold
3.a system which checks if 16bit input is a prime number and gives one bit output as 1
if it prime and 0 if it not prime
4.how approximate multipliers implemented in my project
What was my approach? What was error? How did u achieve that give me an example or
piece of ur design? How accuracy and power are traded in ur design? On what basis u
vary them?
5.how did u implement ur atm project? What is its complexity? What are different states
in it? How state traversal take place? What type of state machine is your project? What
max operating frequency of ur project?
Ki6.aptitude question on train running opposite started at different times, different
speeds, when do they reach destination? Who reaches first? When do they meet togeth
er?
INTEL - interview-5(Interviewer - Anand)

1Q - Projects in details
2Q - Implement verilog code for LCM of two 16 bit numbers
3Q - Aptitude Q based on Speed time distance (two trains with different speed and
starting with different delay with both different distances reaching same point)

INTEL - interview-6

Introduce yourself
Explain any project
What you like analog or digital?
What will happen if we connect Q output to D input of flip flop?
What is setup time?
What will happen if it violates?
Hardware if we multiply 16bit with 12?

INTEL - interview 7
1.Tell me about yourself
2Different types of amplifiers
3.Gain of common source
4.Differential amplifier
5.Gain of differential amplifier
6.Oscillator
7.Draw inverter and Vout vs Vin curve
8.If pmos is weak and nMOS is weak , the curve will move to which side.
9.In a pass transistor 1 can be passed through NMOS or not.
10.If pmos is replaced by nMOS and nMOS is replaced by pmos , what will happen?
11.What is noise margin? What is VIL, VOL , VIH, VOH
relation between VIH AND VOH … which one should be greater.
12.Draw FSM . 1011010110 … detect 0110 and explain.
13.what is setup time and hold time?
14.Two flip flops are there… one is launch and another is capture… delay between two
flop is 40ps and delay in clock path is 10ps .. clock period is 100ps … setup time is 5ps
and hold time is 3ps.. do setup check and hold time check.
15. Different types of encoding.
16. How is gray coding different from binary coding

QUALCOMM

1. Introduce yourself.
2. How much do you rate yourself in perl, TCL and Python?
3. Did you use any automation packages in python?
4. How familiar are you with verilog?
5. Difference between tasks and functions
6. What is asynchronous and synchronous RESET? How to declare them in always
block?
7. Draw the circuit diagram of D-flip flop with synchronous and asynchronous reset
8. Design and gate using 2:1 mux
9. How to do STA when two FSMs operating at different frequencies exchange data
between themselves?
10. What is SETUP and HOLD time? Why do we need them?
11. How does SETUP and HOLD time depend on the Vdd?
12. How SETUP and HOLD times of a cell can be changed?
13. For a Flip flop if Vdd changes will setup and hold slack change? If yes, why?
14. What is the difference between a basic processor and a DSP processor?
15. What is meant by clock speed?
16. What are ​static, auto, volatile and register​ keywords in C?
17. Write a program to calculate number of 1s in a given binary number, in C
18. What are voltage regulators?
19. What is a schmitt trigger?
20. Layout, DRC
21. How to calculate the power consumed by a circuit?
22. Explain any one of the SoC protocols you know.
23. In detailed discussion about all the projects.

INTEL

Interview – 1:​ (Interviewer: Mr. Suresh)

1. Tell me about yourself.
2. Blocking and Non-Blocking assignments.
3. Latch and flip flops.
4. Setup and hold time definitions.
5. What is the difference between mealy and moore machines?
6. If I have to design 16-state FSM, how many registers will it take?
7. Difference between half adder and full adder. Which one will be faster?
8. What is insertion and transportation delay.?
9. Verilog code for asynchronous reset D - flip flop.
10. How to generate clock in the code?
11. Unix command to list all the files in the directory.x
12. Unix command to search for a particular word in the list.

Interview – 2:​ (Interviewer: Mr. Divakar)

1. Tell me about yourself.
2. How MOSFET works?
3. What are the regions in which MOSFET works? Conditions for each region.
4. Current equation for linear region. What is the meaning of all the variables used
in the formula?
5. What is the application of the cut-off and saturation region?
6. Can we use MOSFET as an amplifier?
7. What is pinch off?
8. What is the depletion region?
9. What is metastability?
10. What are types of ASIC flow? Explain both traditional and physical ASIC flow.
11. What are inputs for physical synthesis?
12. What are setup and hold violations? How to remove them?
13. What is the difference between Initial and Always block? Is Initial block
synthesizable?
14. What is skew? What is a positive and negative skew?
15. What is latency?
16. Difference between latch and flip flop.
17. What is inheritance.? What are types?
18. What is polymorphism?
19. How does Johnson counter works? Is it synchronous or an asynchronous
counter?
20. What are the inputs required to store data in RAM?
21. What is static and dynamic power?
22. What is leakage power? How to reduce it?
23. Difference between task and function.
24. Inter and intra statement delay.
25. What are === and == operators?
26. a=b?c:d and
If (b) a=b
else a=d
Then what is the difference between them? If the input b=x, then what will be the
output of both statements?

Interview – 3:​ (Interviewer: Ms. Kamya)

1. Projects
2. What are interrupts? What are some types? Who will setup these priorities for
interrupts?
3. What are the things packets can have?
4. What are headers, payload and trailers?
5. How much will you rate yourself in perl and python?
6. What are types of memories? Examples of volatile and non volatile memories.
7. How SRAM and DRAM? Which is faster? Which one will you prefer?
8. What makes DRAM slow?
9. How do you differentiate between cache memory and RAM? Which one will you
put near the CPU and why?
10. Will you be 100% available during internship? If daily deliverables are not
completed then we may ask you to work for some extended hours. Are you comfortable
with that?
11. Where did you worked before? For how much duration and what was your job
profile?

Interview – 4:​ (Interviewers: Srinivas(HR), Divakar and CK) (Whatsapp video call)
1. Tell me about yourself.
2. What are your strengths?
3. Are you interested in working at Intel?
4. If we give you an internship, what will you take away after the completion of the
internship?
5. What will be your motivation to work in intel?
6. In a particular scenario, 3 of your seniors give you work. How will you tackle it?
7. Will it be okay with you if sometimes you have to work for extended hours if work
is not completed?
8. How does the keyboard works?
9. How does the CPU know the particular instructions?
10. Data types in python.
INTEL
1.How to fix IR drop without using straps
2.How to fix setup violation without using buffer
3.What is tie high and tie low
4.What is antenna effect
5.How to make latch to flipflop

Intel (ARUN KUMAR)

1.What are the subjects you read in ongoing sem?
2.In which subjects do you have good command?
3.Define your subject low power IC design?
4.What are the leakages in MOSFET?
5.Name different leakages in and how can we avoid it?
6.Why there is tunneling leakage current?
7.How you can avoid Gate leakage current?
8.What is power gating?
9.What is clock gating?
10.How can you apply power gating?
11.How can you apply clock gating?
12.Give practical example of power gating.
13.What are the effects of applying gating. Any disadvantage?
14.What do you do study in ASIC subject?
15.How logical synthesis is done?
16.Did you do any Timing Analysis?
17.What are different types of Timing Analysis?
18.Define STA?
19.What tool did you use in doing STA ?
20 .What tool is used in doing logical synthesis?
21.Did you do physical synthesis?
22.What are the files required for timing analysis?
23.What does all these files contain?
24.What is setup and hold time?
25.What is DFT?
26.Why do we do DFT?
27.How do we do it?
28.If there are 5 millions transistors in your IC how will you test it?
29.Is there any other method of doing the testing?
30.What is Boundary Scan?
31.What is the best way of testing an IC?
32.What is BIST?
33.What is LBIST?
34.Name any IC in which BIST is there.
35.What is MBIST?
36.ASIC physical flow.
37.What are different types of validation?
38.How leakage power is different than dynamic power?
39.Is leakage power is only there in mosfet?
40.What is subthreshold leakage?
41.Area of Interest ...and other questions.

Intel
Panel name: Anand
1.which hdl languages do u know?
2.fibonacci series in verilog you reach a number that 16bit register cannot hold
3.a system which checks if 16bit input is a prime number and gives one bit output as 1
if it prime and 0 if it not prime
4.how approximate multipliers implemented in my project
What was my approach? What was error? How did u achieve that give me an example or
piece of ur design? How accuracy and power are traded in ur design? On what basis u
vary them?
5.how did u implement ur atm project? What is its complexity? What are different states
in it? How state traversal take place? What type of state machine is your project? What
max operating frequency of ur project?
6.aptitude question on train running opposite started at different times, different
speeds, when do they reach destination? Who reaches first? When do they meet
together?

Explain projs
Find output of a given verilog code
Why bist is used,it's advantages
Diff between CMOS and domino logic, compare power dissipation in the two
Various power reduction techniques
Basics of verilog - blocking and non blocking
Complete pd flow
Uvm structure. Why uvm ?
System verilog tesbench structure
Flags of perl n tcl

What's difference between blocking and non blocking

Difference between latch and FF
Difference between mealy and moore
OOP concepts
Verification environment
System Verilog concepts on data types
Basic structure of a verilog code
Python basics
Perl basics
Questions on projects
Setup and hold
Power dissipation concepts

1. What are the different types of amplifier

2. Their gain formula
3. Why -ve is coming in gain formula
4. Inv charac
5.how graph varies with size of tran chages
6.some qus from ptl logic
7.FSM drawing nd code for 2 different sequences
8.what is set up nd hold
9.2 sums from STA

INTEL ( INTERVIEWER - AAKASH MEHTA )

1. Introduction
2. Project related questions
3. What is nmos pmos
4. Region of Operation
5. Cs amplifier gain output input impedance pole zero
6. Cd Cg gain formulae
7. Cascode gain details
8. Why we go to telescopic amp and folded amp
9. Opamp gain eq
10. Differential amplifier gain pole eq
11. Inverter working
 12. Load effect on circuit
13. Pass transitor logic and transmission gate
14. Draw any gate using that logic
15. Sequence detector 1101
16. Setup hold time
17. Single and multicycle Data and cloak path
18. Timing arc and constraint
19. Problem on sta setup slack and hold slack calculation
20. What is the effect when we consider negative edge for capturing data

INTEL (INTERVIEWER - NARASIMHAN IYENGAR)

1.Project
2.Explain the run on vcs
3.Other options in -debug
4.Difference between blocking and non blocking
5.Glitch propagation in blocking and non blocking
6.Packages in system verilog
7.Local and global data type in packages
8.Perl pattern substitutions
9.Make flip flop using latch
10.Mutlicycle path
11.False path

INTEL - Interviewer (Kamya )

1. Project
2. Synchronous counter
3. L1,L2,L3 level cache memory
4. Difference between SRAM and DRAM
5. Interrupts
6. RISC and CISC processor
7. I2C protocol
8. Microprocessor
MEDIATEK (SR6 - 12PM (20MAY))

1. Draw CMOS ckt from Equation

2. A=50MHz B=100MHz
What will be freq & duty cycle of A.B & A+B. Draw the waveform.
3. Draw & explain region of operation of CMOS inverter
4. What is setup & hold timing.
5. How will you remove hold & setup violation(different method)
6. CS amplifier Ids vs vgs.. Ids vs Vds

INTEL - interviewer (Ashish)

1. Project details
2. ASIC flow, what is synthesis and why we do mapping after optimization?
3. design not/buffer gate using ex-or and mux
4. Set-up and hold violations, how to fix them
5. Do you know any Low power techniques, why we need of low power how can we
apply them in big circuits
6. Asynchronous or synchronous reset which one do you prefer and why?
7. After tape out if you find any set-up or hold violation how to rectify them
8. What is multi-Vt, how you can use it to avoid set-up or hold violations
9. Lvt , rvt, hvt how you use it in circuits (critical path or subcritical path)
10. Power sources in circuit(static and dynamic), which one you will try to reduce if
we consider an example of mobile phone
11. Explain Clock gating, if we are using AND gate then do you think any glitch will be
there? If yes how to avoid it
12. If a single gate drives N number of inverters, and that gate is not sufficient to
drive them all then which one buffer or inverter do you prefer in between so that it
will drive the N number of gates? How many can you add those gates to boost
the drive strength?
13. What is FF/latch
14. Explain skew, jitter, margin, latency
15. Explain metastability, CMOS structure
16. Brief about yourself
MediaTek Interview: (20 May, Panel : SR6)
1. Draw CMOS ckt from Equation
2. A=25MHz B=100MHz
What will be the freq & duty cycle of A.B & A+B. Draw the waveform.
3. Draw & explain region of operation of CMOS inverter
4. What is setup & hold timing.
5. How will you remove hold & setup violation(different method)

Qualcomm Interview:
1. Difference between FF and latch
2. Can we implement FF using latch
3. Can we implement memory using FF
4. Why hold & setup time required @circuit level
5. Difference in Cmos & nmos logic @(power, area, delay), what should be preferred?
6. ASIC design flow: specs to GDSII
7. Blocking vs non-blocking
8. STA: how to hold violation if there is no setup violation
9. About projects

Intel Interview:
1. Project Briefing
2. Asic setup & hold time
3. Optimize code for given case:
a. Suppose we have two 3-bit numbers a & b, if a>4 then multiply b by 4.
b. frequency divider (f to f/4).
4. AND gate using MUX
5. Verilog: interchange 2 var. without using 3rd variable
6. Fork join,any,none
7. Task vs function
8. SV : assertion,coverage
9. How to verify any design?
10. Transportation delay, insertion delay, proportion delay
11. Mealy moore
12. Latch flip-flop
13. What is Crosstalk, Metastability, Antenna Effect? How to resolve it?
14. What is Fanout? Is high fanout good or bad? Why?
15. Different Power Dissipation in design. How to reduce them?
16. Noise Margin.
16. Puzzle:
There are three boxes, one contains only apples, one contains only oranges, and one
contains both apples and oranges. The boxes have been incorrectly labeled such that
no label identifies the actual contents of the box it labels. Opening just one box, and
without looking in the box, you take out one piece of fruit. By looking at the fruit, how
can you immediately label all of the boxes correctly?

Intel Interview- (Jayanth and Ashok)

Questions asked by Interviewer Jayanth and Ashok
1.Explain about projects
2.What is the meaning of alpha=0.4 in low power
3. Is task and function synthesiable . If yes what is the hardware architecture?
4. What is latch and flip flop
5. What is blocking and non blocking
6. Difference between Mealy and moore
7. Trade off PTA
8. ASIC flow
9. What is formal verification
10.setup and hold fix
11.aptitude questions
12. What constraints contain?
13. What is the use of quartus prime.
14. For formal verification which tool do you use
15. What is interrupt in microprocessor?
16. How many address lines do you require?
17. Difference between combinational and sequential
18. Why latch will take less power compared to flipflop
19. If you have an AOI ckt in data path you can't decrease the delay in data path in set
up. What are other aspects to decrease the delay without using buffer?
20. Difference between structural and behavioral modelling.
21. Difference between task and function.
22.Interrupt in microprocessor

Intel
How much of 64KB memory are required to build 1MB memory?
Full case and parallel case in verilog

Difference between asic and fpga

What are Trade of parameter in lpic? Area speed and power
If setup or hold violates what will be output
What is synthesis.
Tool used for synthesis
How to fix IR drop without using straps
How to fix setup violation without using buffer
What is tie high and tie low
What is antenna effect
How to make latch to flipflop

What is verilog A and verilog Ams

Serial protocols
Thermometer coding
Gray coding
Setup and hold how to resolve
LRC circuit
What is amplification

Interviewer : sourav

1. Project details
2. Two separate always blocks a1 and a2. Some condition in a2 should stop the
execution of a1. (Verilog)
3. System verilog concepts - assertions, constraints
4. Oops concepts
5. Fork join
6. Or using mux
7. What is glitch? How to remove it.
8. Make an array with all unique elements
9. Sort an array with min. No. Of comparisons.
10. Perl basics- diff btw single and double quotes
11. Diff btw latch n flipflop
12. Freeze statement in verilog
13. Automatic task

1. Counter basics.
2.PLL Working. Use of PLL in generating clock.
3.how to implement different functions in look up table.
4.Difference between FPGA processor and microprocessor.
4.asic flow
5.multi cycle path, false path.
6.explain synthesis in detail.
7.basics of MOSFET
8.explain project in detail.
9.clock gating.
10.blocking and non blocking- find the output of code.
11.fsm and sequence detector.
12.sequence generator.
13.latch and flip flop.different types of flipflop and its excitation tables.
14.Setup and hold time. How to rectify if violated.
15.simple aptitude questions.

1.Difference between Fpga and asic

2. How to rectify setup and hold violation aftet the fabrication of the chip
3. Difference between functions and tasks
4. How to design a synchronous counter using functions
5. Design a 64k 8-bit ram using 4k 4-bit ram
6. If there are three bikers at three corners of a triangle what is the probability of their
collision. Where do you come across such a condition in digital circuits and design it.
7. How does delay of a circuit vary with temperature
8. What happens to delay if W and L are increased
9. What are the inputs and outputs of synthesis
10. Different constraints applied to a reg to Reg path
11. What happens to delay if a buffer is replaced by two inverters

1.all projects
2.Memory leakage in C
3.How will u avoid setup violation of 1ns by optimising only comb circuit
4.Ver n Sys Ver differences
5.How will u write a test plan and how will u give test cases?
6.Sys ver test bench components
7.Comb sequential differences , Synch n Asynch counter differences, Synch reset n
Asynch reset
8. Perl(pattern matching) Tcl Python differences
9.FIFO read n write n depth
10. Machine learning and Data science basic questions

MediaTek Interview Questions:

1.Introduce yourself
2.Que about academic details
3.whether you did any STA related course or project
4.what u have done in that project
5.whether you get any violations in that
6. How to remove setup and hold violations
7.Explain Asic flow and files used in that(eg. .sdc .lib .lef etc)
9. Write verilog code for ff getting input from 2input AND gate(then he asked to hold the
paper in front of the camera so that he could see it)
10. How will you add synchronous and asynchronous reset in that code
11.difference between synchronous reset and asynchronous reset ..how it will affect the
ckt
12.draw two FF and combinational logic in between ...take ur own values for all the
factors.. Write equations for setup and hold slack and calculate it(again show all the
details what u have taken)
13.what is uncertainty
14.how it will effect setup and hold
15. Is uncertainty good for setup and also for hold
16. Is it good to have uncertainty in ckt
17. Due to which factors uncertainty happens
18.explain clock skew, clock latency, jitter
19. What is multicycle path...why do we need that
20.If data path delay ie AT is more while calculating setup slack, is it good to add one
more FF in between so that data path delay will reduce
21.what is false path
22. Is there any commands related to false path, multicycle path and clock generation in
any of the file... Name that file and commands
23. how do u set clock frequency using command
24.Logical question
Mediatek
1. What u have idea on physical design.
2. did u do any project in it.
3. How u prepared scripts
4. Utilization factor
5. Normal buffers and Clock tree buffers
6. Have u used any macros.
7. Setup and hold time.
8. Other than setup and hold, what u have observed.
9. How do u do any optimization
10. Nand Vs nor. Which is better and how u decide that. Explain the reasons.
11. What are universal gates

Samsung semiconductor
1)Tell me about your college life.
2) name VLSI industries you know.
3) What is SanDisk?
4) why some industries are fabless, some fab
6) What you learnt in Mtech
7) What is latest research going in VLSI nowadays
8) Verilog Questions
9) Show me your Project code ( shared screen and shown code)( skype Interview)
Asked to draw logic diagram of the part of code( also draw diagram using Universal
gate)
10) How will you make Priority encoder in verilog?( It must be efficient design)
10) ASIC flow of it in detail
11) ASIC files
12) Optimization for your completed projects. How it would be done
13) STA violations
14) SV testbench to verify projects.( Basics) ( not so deep)( standard flow )
15) 4 bit full adder verilog code. Draw its Gate level diagram.
16) in it he saw XOR gate, asked it in detail
17) How to implement it (4 bit parallel adder) ( take photos by phone and send on skype
to show him written code) using EDA tools.
( Flow of tools to perform verilog coding)( same asic flow)
18) verilog indeep( statements) ( assign, blocking, Non blocking uses)
19).how will you swap two variables without using temporary variable.
20) Asked how was your interview and comment on it.