8/21/12 ASIC interview Question & Answer: ASIC Timing Interview Questions

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ASIC interview Question &

Answer
A blog to collect the interview questions and answer for ASIC related positions

Thursday, January 14, 2010

ASIC Timing Interview Questions
1)

The digital circuit is shown with logic delay (dly3) and two clock buffer
delays (dly1, dly2).

How will you fix setup timing viloations occuring at pin B?

Answer:

Use the following formula:

Tc2q + Tdly3 <= Tsk + Tp - Tsu

Since Tp ( clock frequency is fixed 1/Tp = f ), Tc2q (clock to Q) and Tsu

(setup time) are fixed, the setup timing violations are caused by Tdly3. In
order to fix the setup violations, we can reduce Tdly3.

How will you fix the hold violations occuring at pin B?

Answer:

Labels Use the following formula:

ASIC Flow (1)
Tc2q + Tdly3 >= Tsk + Thd
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8/21/12 ASIC interview Question & Answer: ASIC Timing Interview Questions

ASIC Gate (3) Tc2q + Tdly3 - Tsk >= Thd

ASIC Logic (4)
ASIC SystemVerilog (10) Since Tc2q (clock to Q) and Thd (hold time) are fixed, the hold time
ASIC timing (2) violations are caused by the Tdly3. We can increase the Tdly3. For
ASIC Verification (1) example, add buffer to the path. We should not mess up with the clock
C++ (2) skew. It would affect too many paths.
Design Complier (1)
M emory Interface (1)
Networking (2) 2) If there's a timing violation in the chip, how could you verify it as setup
perl (9) violation or hold time?
PLL (1)
Previous Interview Questions (1) Answer:
PrimeTime (1)
SVA (2) If the test engineer slow the clock speed, the chip passed the tested. It's a
Verilog Interview Questions (6) setup time problem. If the problem did not changes, it could be hold time
issue.

Blog Archive Setup violations occurs when the data path is too slow compared to
the clock speed.
▼ 2010 (49)
The designer can fix the setup violations by reducing the delay in the data
► November (1)
path. Designer can also reduce the clock speed to fix the setup violation,
► October (2)
but it is going to be a poor design technique.
► June (2)
► May (2)
Hold violations occurs when data is too fast when compared to the
► April (7)
clock speed. If hold violations are not fixed before the chip is made, lot of
► February (12) problem occurs unlike setup violation where the clock speed can be
▼ January (23) reduced. To fix hold violations, designer can add more delay to the data
ASIC Gate Interview Questions path.
Part#3
Asic Flow 3) what's timing constraint?
Prime Time Questions
Design Constraints and Synthesis Timing Constraints:
Questions
CAM related Questions Timing constraints are how the designer tells the STA tool about the
Network Questions & Answer timing behavior of the ASIC. The three minimum constraints are defining
Basic OPP questions, SystemVerilog the clock, input delay, and output delay. There are four types of timing
Interview Quest...
paths are available. They are :
System Verilog Interview Questions
2
Clock Domain Crossing Timing Q&A Input to Register (Sync),
Ethernet Questions Register to Register (Sync),
Memory Interface Questions Register to Output (Sync) and
ASIC Timing Interview Questions Input to Output(Async). Each path has a start and endpoint
ASIC Logic Interview Questions
Part #4
ASIC Gate Interview Questions Part When the clocks are defined, all Register to Register paths are assumed to
#2 be constrained in one clock cycle. A path originates from either an Input
ASIC Logic Interview Questions port or a Register clock pin, while an end point is either an Output port or
Part # 3 a Register data pin. All start and end point must be timing constrained.
ASIC Logic Interview Questions
Part # 2

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8/21/12 ASIC interview Question & Answer: ASIC Timing Interview Questions

ASIC Logic Interview Questions

Part # 1
Verilog Interview Question Part # 5
Verilog Interview Questions Part
#4 Posted by Roy Chan at 11:06 PM
Verilog Interview Questions Part Labels: ASIC timing
#3
Verilog Interview Questions Part
#2 2 comments:
Verilog Interview Questions Part
#1
ASIC Gate Interview Questions Part
franma November 8, 2010 6:02 AM
#1 Hi

I read this post 2 times. It is very useful.

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Roy Chan Jonathan.
Specialties in ASIC Design and Reply
Verification from front-end to back-
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verification (testbench development, Maxim Zap September 22, 2011 8:33 AM
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