PD Evaluation Test

Physical Design Evaluation Test
1. A boat takes 90 minutes less to travel 36 miles downstream than to travel the same distance
upstream. If the speed of the boat in still water is 10 mph, find the speed of the stream.
2. Anu can do a work in 6 days and Binu alone in 9 days. Anu and Binu undertook to do it for
Rs.4500. With help of Minu, they completed the work in 3 days. How much is to be paid to Minu
and Anu?
3. In an election between two candidates, one got 55% of the total valid votes, 20% of the votes
were invalid. If the total number of votes was 7500, the number of valid votes that the other
candidate got, was:
4. A tank is filled by three pipes with uniform flow. The first two pipes operating simultaneously fill
the tank in the same time during which the tank is filled by the third pipe alone. The second pipe
fills the tank 5 hours faster than the first pipe and 4 hours slower than the third pipe. The time
required by the first pipe is:
5. A rectangular carpet has an area of 60 sq.m. If its diagonal and longer side together equal 5
times the shorter side, the length of the carpet is:
6. The length of a rectangular plot is 20 metres more than its breadth. If the cost of fencing the
plot @ 26.50 per meter is Rs. 5300, what is the length of the plot in meters?
7. What is the difference between Mealy and Moore state machines?
8. Draw the circuit of frequency divider (Divide by 2) using D-FF.
9. Draw the circuit of D-FF using NAND Gate.
10. What Is Race-around Problem? How Can You Rectify it ?
11. What is the command to find hidden files in the current directory ?
12. Define piping and explain with an example in Unix.
13. Write down the command to search and replace a pattern into VI editor.
14. Why is NAND gate preferred over NOR gate for fabrication ?
15. What is the fundamental difference between a MOSFET and BJT ?
16. What is effect in CMOS inverter if I will interchange the NMOS and PMOS?
17. What is Latch up in CMOS, how to resolve it ?
18. What is threshold voltage and channel length, what are the challenges in lower node
technology?
19. Explain about setup time and hold time, what will happen if there is setup time and hold time
violation and which will have high priority ?
20. Explain these terminology : DEF, SPEF, SDF, UPF , LEF
21. Draw the circuit diagram of 2-input NOR and NAND gate using CMOS logic.
22. List out all the inputs for PD and explain the information associated to it.
23. What is sanity check and explain the significance of it with ICC command.
24. Explain the PD flow with flow diagram with importance of each stages.
25. What is importance of SDC file, Write 5 SDC commands and explain the uses of it.
26. List out all Pre Placed cells and explain its uses.
27. Write down the guidelines to place the Macros into Core area, Why Macro can’t be flip by 90
degree and how to find the channel .
28. Write down inputs for PT and which net-list will be used for PT, what is command to fix the
timing violation.
29. What is difference between Placement and Place_Opt Explain the commands Place_opt,
Psynopt and refine_placement.
30. What the report we need to check after placement write it’s command also.
31. Write down the differences between STA and Dynamic timing analysis.
32. How to do power planning and to do it’s analysis.
33. What is signoff and what are the checks we do in this stage.
34. List the Logical DRCs and its SDC command.
35. List down commands t extract spef and command to generate sdf fil
36. List down detailed steps in physical verification. List down differences between lvs and drc
37. List down differences between functional and timing Eco.
38. What is congestion, Cell density and pin density and how to resolve congestion?
39. Write a command to see the report of only all negative slack in setup and hold check?
40. Explain the Blockage and its type also write the command to create a partial blockage.
41. What is propagation delay and transition delay in clock.
42. What is clock latency delay, clock source delay and clock network delay.
43. Explain the NDR and Default routing, write down its advantage and disadvantage?
44. Explain source, sink, float and exclude pins in CTS.
45. What is Keep out margin and Bounds please explain with command.
46. Write down all the stages after that we can do the STA analysis.
47. Explain the clock exceptions and write its commands.
48. What is level shifter, Isolation cells and write its uses and type.
49. What is intrachip variation and interchip variation how to consider this in analysis .
50. Explain in detail CRPR , OCV , AOCV and POCV.
51. What we do in PRE-CTS stage, write down all specification which we set before CLOCK_OPT?
52. Write down the steps of routing and explain them.
53. What is cross talk, how it comes and write down the methods to avoid the crosstalk.
54. How to fix setup and hold violations, list out all the possible ways.
55. Explain the variant of cell present in library in terms of VT and Drive Strength, also list out its
advantage and disadvantage in terms of PPA.
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