CMOS Basic

Topics for this presentation
1. How CMOS Works ?

2. Drain Current Equation
3. Pinch Off Voltage
4. Latchup Concept
5. CMOS Capacitance with graph Cap vs Vt
SUJIT KUMAR
HOW CMOS WORKS ?
• The term CMOS stands for “Complementary Metal Oxide Semiconductor”.
CMOS technology is one of the most popular technology in the computer
chip design industry and broadly used today to form integrated circuits in
numerous and varied applications.
• The main advantage of CMOS over NMOS and BIPOLAR technology is the
much smaller power dissipation. Unlike NMOS or BIPOLAR circuits, a
Complementary MOS circuit has almost no static power dissipation.
• Power is only dissipated in case the circuit actually switches. This allows
integrating more CMOS gates on an IC than in NMOS or bipolar technology,
resulting in much better performance.
• Complementary Metal Oxide Semiconductor transistor consists of P-
channel MOS (PMOS) and N-channel MOS (NMOS).
NMOS :
• NMOS is built on a p-type substrate with n-type source and drain diffused
on it. In NMOS, the majority carriers are electrons. When a high voltage is
applied to the gate, the NMOS will conduct. Similarly, when a low voltage is
applied to the gate, NMOS will not conduct. NMOS are considered to be
faster than PMOS, since the carriers in NMOS, which are electrons, travel
twice as fast as the holes.
PMOS :
•P- channel MOSFET consists P-type
Source and Drain diffused on an N-
type substrate. Majority carriers are
holes. When a high voltage is applied
to the gate, the PMOS will not
conduct. When a low voltage is
applied to the gate, the PMOS will
conduct. The PMOS devices are
more immune to noise than NMOS
devices.
CMOS Working Principle :

In CMOS technology, both N-type and
P-type transistors are used to design
logic functions. The same signal
which turns ON a transistor of one
type is used to turn OFF a transistor
of the other type.
• In CMOS logic gates a collection of n-type MOSFETs is arranged in a pull-
down network between the output and the low voltage power supply rail
(Vss or quite often ground). Instead of the load resistor of NMOS logic
gates, CMOS logic gates have a collection of p-type MOSFETs in a pull-up
network between the output and the higher-voltage rail (often named Vdd).
• Thus, if both a p-type and n-type transistor have their gates connected to
the same input, the p-type MOSFET will be ON when the n-type MOSFET
is OFF, and vice-versa. The networks are arranged such that one is ON
and the other OFF for any input pattern.
• CMOS offers relatively high speed, low power dissipation, high noise
margins in both states, and will operate over a wide range of source and
input voltages (provided the source voltage is fixed).
Drain Current Equation
• The general expression for the drain current equals the total charge in the
inversion layer divided by the time the carriers need to flow from the source
to the drain :
• Where Qinv is the inversion layer charge per unit area, W is the gate width,
L is the gate length and tr is the transit time. If the velocity of the carriers is
constant between source and drain, the transit time equals :
• where the velocity, v, equals the product of the mobility and the electric field:
• The constant velocity also implies a constant electric field so that the field
equals the drain-source voltage divided by the gate length. This leads to the
following expression for the drain current:
• We now assume that the charge density in the inversion layer is constant
between source and drain. We also assume that the charge density in the
inversion layer equals minus the product of the capacitance per unit area
and the gate-to-source voltage minus the threshold voltage:
• The inversion layer charge is zero if the gate voltage is lower than the
threshold voltage. Replacing the inversion layer charge density in the
expression for the drain current yields the linear model:
• Drain current saturation :
• The drain current is still zero if the gate voltage is less than the threshold
voltage :
Pinch Off Voltage
• The MOSFET is a device that controls a current between two contacts
(Source and Drain) using a voltage contact (Gate). The device uses a
surface effect to create a n-type region in a p-type substrate (or the
converse).
• When we apply an appropriate voltage to the gate, a channel is formed

between the source and drain. In effect, we have created a pipe between
the source and drain, so that charges can move from the source to the
drain.
• Next, we apply a voltage between
the source and drain. This will
cause charge movement between
the source and drain. But, it will
also change the shape of the
channel.
• Now, the channel begins to deplete
towards the drain end. This is
because the drain is at a positive
potential, and negative charges
from the channel closest to the
drain are being pulled into the
drain.
• As we increase the voltage VDS, a
point will be reached when the
channel is completely pinched off.
• The gate voltage was responsible
for the channel. And, so as long as
there was no pinch off, the gate
controlled the flow of charges from
the source to the drain through the
channel.
• Once pinch off occurs, our pipe no longer connects the source to the drain.
The gate loses control over the flow of charges between the source and the
drain.
• So, now the flow of charges between the source and the drain is controlled
only by the voltage VDS.
• So, in conclusion, pinch off in an FET is when the gate loses control over the
flow of charges between source and drain.
Latch up concept
• Latchup refers to short circuit formed between power and ground rails in an
IC leading to high current and damage to the IC.
• latch up is the phenomenon of low impedance path between power rail and
ground rail due to interaction between parasitic pnp and npn transistors.
• In a latch-up conduction, the current flows from VDD to GND directly via the
two transistors, causing the dangerous condition of a short circuit. The
resistors are bypassed and thus excessive current flows from VDD to
Ground.
• Latchup prevention/protection
includes putting a high resistance in
the path so as to limit the current.
This can be done in 2 ways.
• Surrounding PMOS and NMOS
transistors with an insulating oxide
layer. This breaks parasitic structure.
• Latchup Protection Technology
circuitry which shuts off the device
when latchup is detected.

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Topics for this presentation

1. How CMOS Works ?

CMOS Working Principle :

• Drain current saturation :

• When we apply an appropriate voltage to the gate, a channel is formed

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