Field Effect Transistor

Introduction
• The FET is a device in which the flow of current through the
conducting region is controlled by an electric field. Hence the name
Field Effect Transistor (FET). As current conduction is only by
majority carriers, FET is said to be a unipolar device.
• Based on the construction, the FET can be classified into two types
as Junction FET(JFET) and Metal Oxide Semiconductor FET(MOSFET)
or Insulated Gate FET (IGFET) or Metal Oxide Silicon
Transistor(MOST).
• Depending upon the majority carriers, JFET has been classified into
two types, namely, (1) N-channel JFET with electrons as the
majority carriers, and (2) P-Channel JFET with holes as the majority
carriers.
 Construction of n-channel JFET
• It consists of a N-type bar which is made of silicon. Ohmic contacts
(terminals), made at the two ends of the bar, are called Source and
Drain.
• Source (S): This terminal is connected to the negative pole of the
battery. Electrons which are the majority carriers in the N-type bar
enter the bar through this terminal.
• Drain (D) This terminal is connected to the positive pole of the
battery. The majority carriers leave the bar through this terminal.
• Gate(G): Heavily doped P-type silicon is diffused on both sides of
the N-type silicon bar by which PN junctions are formed. These
layers are joined together and called Gate G.
• Channel: The region BC of the N-type bar between the depletion
region is called the channel. Majority carriers move from the
source to drain when a potential difference VDS is applied between
the source and drain.
• As indicated earlier, the JFET is a three-terminal device with one terminal
capable of controlling the current between the other two.
• The major part of the structure is the n -type material, which forms the
channel between the embedded layers of p -type material.
• The top of the n -type channel is connected through an ohmic contact to a
terminal referred to as the drain (D) , whereas the lower end of the same
material is connected through an ohmic contact to a terminal referred to as
the source (S).

• The two p-type materials are

connected together and to the gate
(G) terminal.
• In the absence of any applied
potentials the JFET has two p–n
junctions under no-bias conditions.
 Characteristic of N Channel JFET

• We know that there is a channel of n-

type semiconductor material in n
channel JFET.
• The gate region of the n channel JFET is
a highly doped p-type region.
• A voltage is applied across the channel
i.e. between drain and source terminal.
• First, let us plot the values of the drain
to source current for different applied
drain to source voltages.
• At first case, we will short circuit the
gate terminal with the source terminal
and ground them commonly.
• Now we will slowly increase the drain
circuit voltage VDD from zero.
• After a certain drain voltage the depletion
layer towards drain terminal touches each
other.
• At that point the curve gets very nearly
horizontal.
• At that drain voltage the depletion layers
do not perfectly touch to block the channel
rather there will be a narrow opening
between the layers through which the
drain current continues to flow.
• If we further increase the drain voltage the
depletion layer will try to increase its
thickness further but they in no way can
touch each other rather the depletion layer
more towards source terminal get closure
and increases the effective length of the
narrow channel opening.
• This phenomenon is known as channel
modulation.
Pinch off Voltage (VP). It is the minimum drain-source voltage at which the
drain current essentially becomes constant.
• Due to this phenomenon, the effective resistance of the channel gets increased and
that increment is almost proportional to increment of drain voltage.
• As a result, the drain current becomes almost constant. The drain current to drain to
source voltage curve gets its horizontal portion. The voltage after which the drain
current becomes almost constant is known as pinch-off voltage.
• The drain current at pinch-off voltage when get terminal is in ground potential, is
denoted as IDSS and known as Shorted Gate Drain Current.

• Now if we go on increasing the drain

voltage after a certain value of drain to
source voltage, the depletion layers get
broken down and drain current gets
suddenly rises. This region of the
characteristic is called breakdown region.
• The portion of the curve when drain current
increases with increasing drain to source
voltage is known as linear region or ohmic
region and the portion of the curve when
drain current remains almost constant is
known as constant current or active region.
• Now we will open the gate terminal from grounded source terminal
and apply certain negative voltage at gate terminal (VGS<0).
• In this situation the junction between gate region and channel gets
more quick reverse biasing and hence the drain current for same drain
to source voltage becomes lower.
• The entire curve against drain
current and drain to source
voltage for applied negative gate
voltage, is shifted below the
zero gate voltage curve.
• If we apply more negative
voltage at gate terminal the
curve will shift more downwards
as shown in the figure of the
characteristic of an n channel
JFET.
 Condition for VGS<0

In Fig. a negative voltage of 1V is applied between the gate and source terminals for a
low level of VDS . The effect of the applied negative-bias VGS is to establish depletion
regions similar to those obtained with VGS =0 V, but at lower levels of VDS .
Therefore, the result of applying a negative bias to the gate is to reach the saturation
level at a lower level of VDS , as shown in Fig. b for VGS = -1 V. The resulting saturation
level for ID has been reduced and in fact will continue to decrease as VGS is made more
and more negative.
 Transfer Characteristic of N-Channel JFET

• The transfer characteristic is drawn between gate voltage and drain

current by keeping drain to source voltage at pinch-off voltage.
• When the gate is in zero potential the maximum drain current flowing
through the transistor is shorted gate drain current (IDSS).

• As the reverse gate-source voltage is

increased, the cross-sectional area of the
channel decreases. This in turn decreases the
drain current.
• At some reverse gate-source voltage, the
depletion layers extend completely across the
channel.
• In this condition, the channel is cut off and the
drain current reduces to zero.
• The gate voltage at which the channel is cut
off (i.e. channel becomes non-conducting) is
called gate-source cut off voltage VGS (off).
 Expression for Drain Current (ID)

Relation between output and input quantities

of JFET is not a linear relationship as it is linear
in case if BJT. The relation between ID and VGS
is defined by Shockley’s equation.
 Operation of N-channel JFET
• When no voltage is applied between drain and
source, and gate and source, the thickness of
the depletion regions round the PN junction is
uniform as shown in Figure.

• In this case, the PN junctions are reverse biased

and hence the thickness of the depletion region
increases.
• As Vgs is decreased from zero, the reverse bias
voltage across the PN junction is increased and
hence, the thickness of the depletion region in
the channel also increases until the two
depletion regions make contact with each
other.
• In this condition, the channel is said to be cut-
off. The value of Vgs which is required to cut-off
the channel is called the cut-off voltage VC.
• Drain is positive with respect to the source with VGS = 0. Now the
majority carriers (electrons) flow through the N-channel from
source to drain. Therefore the conventional current ID flows from
drain to source.
• The magnitude of the current will depend upon the following
factors:
As VDS is increased, the cross-sectional area of the channel will be reduced. At
a certain value VP of VDS, the crosssectional area at B becomes minimum. At
this voltage, the channel is said to be pinched off and the drain voltage VP is
called the pinch-off voltage.
As a result of the decreasing cross-section of the channel with the
increase of VDS, the following results are obtained.
• When the gate is maintained at a negative voltage less than the negative
cut-off voltage, the reverse voltage across the junction is further
ncreased. Hence for a negative value of Vgs, the curve of ID versus VDS is
similar to that for Vgs = 0, but the values of VP and BVDGO are lower, as
shown in Figure.
• From the curves, it is seen that above the pinch-off voltage, at a constant
value of VDS, ID increases with an increase of Vgs. Hence, a JFET is suitable
for use as a voltage amplifier, similar to a transistor amplifier.
• It can be seen from the curve that for voltage VDS = VP, the drain current is
not reduced to zero. If the drain current is to be reduced to zero, the
ohmic voltage drop along the channel should also be reduced to zero.
• Further, the reverse biasing to the gate-source PN junction essential for
pinching off the channel would also be absent.
• The drain current ID is controlled by the
electric field that extends into the channel
due to reverse biased voltage applied to the
gate; hence, this device has been given the
name Field Effect Transistor.
Metal Oxide Semiconductor Field Effect Transistor
(MOSFET)
• As well as the JFET, there is another type of Field Effect Transistor
available whose Gate input is electrically insulated from the main
current carrying channel and is therefore called an Insulated Gate
Field Effect Transistor (IGFET) or Metal Oxide Semiconductor
Field Effect Transistor (MOSFET).

• The IGFET or MOSFET is a voltage

controlled field effect transistor that
differs from a JFET in that it has a
“Metal Oxide” Gate electrode.
• This is electrically insulated from the
main semiconductor n-channel or p-
channel by a very thin layer of
insulating material usually silicon
dioxide.
 MOSFET
• The isolation of the controlling Gate makes the input resistance of
the MOSFET extremely high, in the Mega-ohms (MΩ) region
thereby making it almost infinite.
• As the Gate terminal is electrically isolated from the main current
carrying channel between the drain and source, “NO current flows
into the gate” .
• There are two basic forms of MOSFET: (i) Depletion MOSFET and (ii)
Enhancement MOSFET.
• In a depletion MOSFET, the controlling electric field reduces the
number of majority carriers available for conduction, whereas in
the enhancement MOSFET, application of electric field causes an
increase in the majority carrier density in the conducting regions of
the transistor.
 Types of MOSFET

MOSFET

Depletion-type Enhancement -
MOSFET Type MOSFET

N-channel P-channel N-channel P-Channel

DMOSFET DMOSFET EMOSFET EMOSFET
 Basic structure of D-MOSFET
• The n-channel depletion-type MOSFET is provided in Figure.
• A slab of p-type material is formed from a silicon base and is referred to as
the substrate. It is the foundation upon which the device will be constructed.
• The source and drain terminals are connected through metallic contacts to n-
doped regions linked by an n-channel.

• The gate is also connected to a metal

contact surface but remains insulated from
the n-channel by a very thin silicon
dioxide (SiO2) layer.
• There is no direct electrical connection
Between G and Channel of the MOSFET.
 Working of D-MOSFET
VGS=0 V, VDS Some Positive Value
• As gate-to-source voltage is set to zero volts and a voltage VDS is applied across the
drain-to-source terminals.
• The result is an attraction for the positive potential at the drain by the free electrons
of the n-channel and a current similar to that established through the channel of the
JFET. In fact, the resulting current with VGS=0 V continues to be labelled IDSS.
Characteristics of DMOSFET
 Working of D-MOSFET
VGS is negative
• The gate-source voltage VGS has been set at a negative
voltage such as VGS=-1 V.
• The negative potential at the gate will tend to pressure
electrons toward the p-type substrate (like charges repel)
and attract holes from the p-type substrate (opposite
charges attract).
• Depending on the magnitude of the negative bias
established by VGS, a level of recombination between
electrons and holes will occur that will reduce the
number of free electrons in the n-channel available for
conduction.
• The more negative the bias, the higher the rate of
recombination. The resulting level of drain current is
therefore reduced with increasing negative bias for VGS.
• For VGS = -1V, -2 V, and so on, to the pinch-off level of -
6 V.
• The resulting levels of drain current and the plotting of
the transfer curve proceeds like to JFET.
Characteristics of D-MOSFET
 Working of D-MOSFET
VGS is Positive
• For positive values of VGS, the positive gate will draw additional electrons
(free carriers) from the p-type substrate due to the reverse leakage current
and establish new carriers through the collisions resulting between
accelerating particles.
• As the VGS continues to increase in the positive direction, the drain current
will increase at a rapid rate for the reasons listed above.
• Due to the rapid rise, the user must be aware of the maximum drain current
rating since it could be exceeded with a positive gate voltage.
• As revealed above, the application of a positive gate-to-source voltage has
“enhanced” the level of free carriers in the channel compared to that
encountered with VGS=0V.
Characteristics of MOSFET
 ENHANCEMENT-TYPE MOSFET (E-MOSFET)
Basic structure of E-MOSFET
• In construction of the n-channel enhancement-type
MOSFET, A slab of p-type material is formed from a
silicon base and is again referred to as the substrate.
• As with the depletion-type MOSFET, the substrate is
sometimes internally connected to the source
terminal.
• The source and drain terminals are connected through
metallic contacts to n-doped regions, but note in the
absence of a channel between the two n-doped
regions.
• The SiO2 layer is still present to isolate the gate
metallic platform from the region between the drain
and source, but now it is simply separated from a
section of the p-type material.
• In summary, therefore, the construction of an
enhancement-type MOSFET is quite similar to that of
the depletion-type MOSFET, except for the absence
of a channel between the drain and source terminals.
 Working of E-MOSFET
VGS=0 V, VDS Some Positive Value

• As VGS=0V, so channel is created between source and drain, net flow of

carries is absent so that current from drain to source is 0A.
• Quite different from the depletion-type MOSFET and JFET, where ID = IDSS.
• It is not sufficient to have a large accumulation of carriers (electrons) at the
drain and the source (due to the n-doped regions) if a path fails to exist
between the two.
• With VDS some positive voltage, VGS at 0V, and terminal SS directly
connected to the source, there are in fact two reverse-biased p – n junctions
between the n -doped regions and the p -substrate to oppose any significant
flow between drain and source.
 Working of E-MOSFET
VGS and VDS both are positive
• The +ve VGS attract the electrons from
substrate and form a conductive channel
between S and D.
• The value of VGS at which sufficient
amount of electrons accumulated near the
SiO2 layer to make it as conductive layer, is
known as threshold voltage Vth.
• Since the channel is nonexistent with VGS
=0 V and “enhanced” by the application of
a positive gate-to-source voltage, this type
of MOSFET is called an enhancement-type
MOSFET.
• Both depletion- and enhancement type
MOSFETs have enhancement-type regions,
but the label was applied to the latter since
it is its only mode of operation.
 Working of E-MOSFET
VGS is fixed at some Positive value and VDS is increasing
If VGS is held fixed at some value and VDS is increased, the voltage VDG will drop and
the gate will become less and less positive with respect to the drain. This reduction in
gate-to-drain voltage will in turn reduce the attractive forces for free carriers (electrons)
in this region of the induced channel, causing a reduction in the effective channel width.
Eventually, the channel will be reduced to the point of pinch-off and a saturation
condition will be established.
In other words, any further increase in VDS at the fixed value of VGS will not affect the
saturation level of ID until breakdown conditions are encountered.
VDS(sat) = VGS-Vth
ID = K(VGS-Vth)2
Characteristics of E-MOSFET
 Use of FET as Voltage Variable Resistor
• FET is operated in the constant-current portion of its output
characteristics for the linear applications.
• In the region before pinch-off, where VDS is small, the drain to source
resistance rd can be controlled by the bias voltage VGS.
• The FET is useful as a Voltage Variable Resistor (VVR) or Voltage
Dependent Resistor (VDR).
• In JFET, the drain-to-source conductance gd =ID/VDS for small values of VDS ,
which may also be expressed as,

• where gdo is the value of drain conductance when the bias voltage Vgs is
zero.
 Biasing of FET

• For the proper functioning of a linear FET amplifier, it is necessary

to maintain the operating point Q stable in the central portion of
the pinch off region.
• The Q-point should be independent of device parameter variations
and ambient temperature changes.
• This can be achieved by suitably selecting the gate to source voltage
(Vgs) and drain current(ID) which is referred to as biasing.
• The Q-point, the quiescent point or operating point for a self-biased
JFET is established by determining the value of drain current ID for a
desired value of gate-to-source voltage, Vgs, or vice-versa.
• If the data sheet of JFET includes a transfer characteristics curve,
then the Q-point may be determined by using the procedure given
below.
• The following analytical method or graphical method can be used
for the design of self bias circuit.
 Biasing of FET

• For the proper functioning of a linear FET amplifier, it is necessary

to maintain the operating point Q stable in the central portion of
the pinch off region.
• The Q-point should be independent of device parameter variations
and ambient temperature changes.
• This can be achieved by suitably selecting the gate to source voltage
(Vgs) and drain current(ID) which is referred to as biasing.
• The Q-point, the quiescent point or operating point for a self-biased
JFET is established by determining the value of drain current ID for a
desired value of gate-to-source voltage, Vgs, or vice-versa.
 Self-bias
• Figure shows the self-bias circuit for an N-channel FET.
• When the drain voltage VDD is applied, a drain current ID flows even
in the absence of gate voltage (VG).
• The voltage drop across resistor Rs produced by the drain current is
given by Vs = ID*Rs.
• This voltage drop reduces the gate to source reverse voltage
required for FET operation. The feedback resistor Rs prevents any
variation in FET drain current.
 Self-bias
• When drain current increases, the voltage drop across Rs increases.
• The increased voltage drop increases the reverse gate to source
voltage, which decreases the effective width of the channel and
hence, reduces the drain current.
• Now the reduced drain current decreases the gate to source voltage
which, in turn, increases the effective width of channel thereby
increasing the value of drain current.
 Voltage divider bias
• Resistors R1 and R2 connected on the gate side forms a voltage
divider. The gate voltage,

If the gate voltage VGG is very large as

compared to gate to source Vgs, the drain
current is approximately constant. In
practice, the voltage divider bias is less
effective with JFET than BJT.
This is because, in BJT, VBE=0.7 (silicon)
with only minor variations from one
transistor to another. But in a JFET, the
Vgs can vary several volts from one JFET
to another.
 FET small signal model
• Field-effect transistor amplifiers provide an excellent voltage gain with the
added feature of a high input impedance.
• They are also low-power-consumption configurations with good frequency
range and minimal size and weight.
• JFETs and depletion MOSFETs can be used to design amplifiers having
similar voltage gains. The depletion MOSFET circuit, however, has a much
higher input impedance than a similar JFET configuration.
• The FET can be used as a linear amplifier or as a digital device in logic
circuits. In fact, the enhancement MOSFET is quite popular in digital
circuitry, especially in CMOS circuits that require very low power
consumption.
• FET devices are also widely used in high-frequency applications and in
buffering (interfacing) applications.
 FET small signal model

• The ac analysis of a JFET configuration requires that a small-signal

ac model for the JFET be developed.
• A major component of the ac model will reflect the fact that an ac
voltage applied to the input gate-to-source terminals will control
the level of current from drain to source.
• The gate-to-source voltage controls the drain-to-source (channel)
current of a JFET.
• The change in drain current that will result from a change in
gate-to-source voltage can be determined using the
transconductance factor gm in the following manner:
Mathematical Definition of gm
 JFET equivalent circuit

• The control of Id by Vgs is included as a current source gmVgs

connected from drain to source as shown in Figure.
• The current source has its arrow pointing from drain to source to
establish a 180° phase shift between output and input voltages as
will occur in actual operation.

The input impedance is represented by the

open circuit at the input terminals and the
output impedance by the resistor rd from drain
to source.
Note that the gate-to-source voltage is now
represented by Vgs (lowercase subscripts) to
distinguish it from dc levels.
In addition, note that the source is common to
both input and output circuits, whereas the
gate and drain terminals are only in “touch”
through the controlled current source gmVgs.
• In situations where rd is ignored (assumed sufficiently large in relation to
other elements of the network to be approximated by an open circuit), the
equivalent circuit is simply a current source whose magnitude is controlled
by the signal Vgs and parameter gm —clearly a voltage-controlled current
source.