Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET)

The metal-oxide semiconductor field-effect transistor (MOSFET) is

actually a four-terminal device. In addition to the drain, gate and source,
there is a substrate, or body, contact. Generally, for practical applications,
the substrate is connected to the source terminal. If this is the case (and it
usually is), the MOSFET may be considered a standard three-terminal
device, with the drain, gate and source the terminals of interest.

Like all FET structures, the MOSFET uses the field effect to operate the
attraction or repulsion of charge carriers through an applied voltage but
this device has a twist that has allowed it to become the predominant
technology for silicon based FETs. The MOSFET structure has dominated
primarily due to the availability of a high quality oxide (SiO2, or silicon
dioxide) for the silicon system. As we will see, this oxide acts as an insulator
and provides electrical isolation between the gate and an active (conduction)
channel between the source and drain, thus providing the required
input/output isolation.

Now, we get into an interesting part as you go through this next

segment, keep in mind that its okay to share your head in
bewilderment initially and that we will be going into detail about all
this!

Recall back to our discussion of BJTs and the definition of the two possible
flavors that depended on device construction and bipolar operation:

the npn BJT, where electrons are the majority carrier and holes are the
minority carrier; and
the pnp BJT, where holes are the majority carrier and electrons are the
minority carrier.

As mentioned above in our discussion of JFETs, we have the same sort of

situation with FETs, but now we only have to define the device in terms of a
majority carrier type (unipolar operation). Specifically for MOSFETS we
have:

the n-channel MOSFET, called the NMOS, where the majority carrier type
is electrons; and
the p-channel MOSFET, or PMOS, where the majority carrier type is
holes.

Okay, thats pretty reasonable. But for MOSFETs (and some other FET
structures) there is another twist. Due to the insulator layer that exists
between the gate and the substrate, we can modify the device structure to
allow two modes. This will become clearer below when device schematics are
presented and in subsequent discussions when we investigate individual
configurations right now just hang on, were in definition mode.

In the depletion mode, a channel region of a material type

corresponding to the majority carrier (i.e., n-type material for NMOS and
p-type material for PMOS) is physically implanted at the time of
fabrication to connect the source and drain. Recall that an active (a.k.a.
conduction or inversion) channel is required for current to flow between
the source and drain, so the depletion MOSFET is in a normally on
condition until the field effect is used to turn it off. To turn a depletion
type MOS transistor off, or interrupt current flow between the source and
drain, appropriate bias conditions must be generated in order to deplete
the channel region of charge carriers, thereby removing the conduction
path between source and drain.
Conversely, in the enhancement mode, the conduction channel is
created through the field effect. Enhancement mode operation is
characterized by the requirement that appropriate biasing conditions be
applied to create a conduction channel between the source and drain
diffusions. In this mode of operation, the transistor exists in a normally
off state until the conduction channel is created and current can flow
between the source and drain.

Can you see the handwriting on the wall?

Having two possible majority carrier types and two possible modes of
operation as defined above, we come up with four possible MOSFET device
types:

depletion NMOS depletion PMOS

enhancement NMOS enhancement PMOS

The schematic for each of these devices, as well as a general operational

discussion, is presented below. Note that these are slightly different
representations than what is presented in your text, but all physical
properties are unchanged. Each figure illustrates the particular device
regions, as well as materials and doping types for the silicon regions. Two
symbols are also provided for each figure the first is used by your author
(and the one we will generally use), but dont get upset if the other version
shows up in other texts or references. Also, please keep in mind that these
schematics are for illustrative purposes only and are not intended to be a
true representation of the actual fabrication techniques, relative geometries
of the device, or absolute placement of the different structural regions.
The n-channel depletion MOSFET (depletion NMOS)

The depletion NMOS device is formed from a p-type substrate with

physically implanted n-type source, drain and channel regions. The dielectric
material covers the area between the source and drain to provide electrical
isolation as mentioned earlier and allows the field-effect operation to occur.
For a gate-to-source voltage (vGS) greater than or equal to zero, the channel
is active and, if a sufficiently large drain-to-source voltage (vDS) is applied,
electrons will move through the channel from the source to the drain, for a
positive drain current (iD > 0).

OK, this is totally goofed up, right? Lets back up for a minute and
see whats going on

vGS > 0 means that the implanted channel will remain unchanged (vGS=0)
or that even more majority carriers will be attracted to the channel at the
Si/SiO2 interface. Charges cannot move through the insulator (ideally), so
a positive applied gate bias has the effect of attracting more negative
charges from the substrate to the channel. Note that since the gate is
isolated from the source (and the channel) by the oxide layer, the gate
current is negligibly small and may be considered to be zero.
Now, if we have a conduction channel and apply a large enough positive
vDS (remember that this means the potential at the drain is higher than
that of the source), electrons in the channel (and source region) will be
attracted to the drain. The channel size is increased, resulting in an
increased drain current (within limits, of course). Physically whats
happening is that the extra majority carriers increase the channel
conductivity or, equivalently, reduce the channel resistivity (remember
=1/?).
But since conventional current directions are defined with respect to the
movement of positive charges, we have a net positive current flow
 (negative charges moving opposite positive current has the same effect
as positive charges moving with positive current).

Clear as mud?!?!? Breathe deeply and go through it again

Now, lets look at what happens when vGS goes negative. For a negative vGS,
the potential at the gate is less positive than that of the source. Usually the
source is grounded, so this means that the gate potential is negative, or that
negative charges are piled up along the gate contact. Since like charges
repel, the negative charges on the gate push electrons out of the channel
region and into the substrate, thereby depleting the majority carriers in the
channel. When vGS reaches a specific magnitude known as the threshold
voltage VT (also referred to as pinch-off in your text). At this threshold
value, the channel is considered to be completely depleted of majority
carriers and the drain current magnitude is reduced to zero for any applied
vDS.

A comment here before we go any further. Please do not confuse the

threshold voltage of the MOSFET with the thermal voltage (VT=26mV
at room temperature if n=1, remember?) Your text uses the same
notation for both parameters, but they have nothing to do with each
other!

The p-channel depletion MOSFET (depletion PMOS)

The depletion PMOS device is complementary to the depletion NMOS

except the n-type and p-type silicon designations are interchanged. This
device operates exactly as discussed above, with the following modifications:

The conduction channel exists for vGS < 0, with the conductivity
increasing for negative vGS (more holes are attracted to the channel
region. For a negative vDS of sufficient magnitude, current flows through
the channel and iD is nonzero.
 Please note: there are two ways of looking at the drain current iD
(remember were dealing with holes as the majority carrier now). For a
negative vDS, the drain is at a lower potential than the source and holes
will move through the channel from the source to the drain. In the
graphic above and Figure 6.2(b) of your text, the direction of the current
is shown as out of the drain contact with the notation for the current
shown as iD < 0. (youll see why in a little while). This is exactly the
same thing as a positive current into the drain contact. Be sure you are
comfortable that these two representations mean exactly the
same thing!
To deplete the channel in a PMOS device, a positive vGS is applied since
the positive gate will repel the holes in the channel. The channel is again
pinched off at a threshold voltage VT, but instead of being a negative as
for the depletion NMOS, it is now positive with a magnitude that depends
on specific material and structural parameters. Above the threshold
voltage magnitude, iD is once again zero regardless of the vDS applied.

The n-channel enhancement MOSFET (enhancement NMOS)

As shown above, the enhancement NMOS device differs from the

depletion NMOS by the absence of the implanted channel. As stated earlier,
this type of device is normally off and requires the creation of a conduction
channel to allow current to flow. For the NMOS structure, this is achieved by
applying a positive vGS of sufficient magnitude (vGS > VT). The positive gate
potential attracts electrons from the substrate to the Si/SiO2 interface under
the oxide layer. This process continues until enough electrons have been
accumulated between the source and drain to increase the conductivity to a
point that a conduction channel is formed. Note that no appreciable drain
current can flow until the vGS magnitude exceeds the threshold voltage VT.

The remainder of device operation is as discussed for the depletion NMOS.

Once the channel has been created, a positive vDS will result in a drain
current iD.
The p-channel enhancement MOSFET (enhancement PMOS)

By this time, the functionality of the enhancement PMOS device should

come as no surprise. Because it does not have a built-in channel and holes
are the majority carriers, a negative vGS with a magnitude greater than VT
must be applied to create the conduction channel. Once the channel is
created and drain current can flow, a negative vDS of appropriate magnitude
results in a negative current with a direction as shown above (or a positive
current with an opposite direction).

These discussions get a little shorter each time dont they?

To summarize: The operation of a MOSFET device is based on the variation

of charge carriers in a channel that exists at the oxide-semiconductor
interface between the source and drain diffusion regions. The control of
charge carriers in the channel is not a function of dopants, as for the BJT,
but instead is achieved through modulation of an applied gate bias. In
enhancement mode, the MOSFET is on, or operating with an active channel,
when a high density of majority carriers is attracted to the oxide-
semiconductor interface. Variation in applied gate bias provides the
mechanism for modulation of the current flow between the source and drain
contacts. An analogous discussion may be developed for the depletion type
structure, with the difference between the two modes of operation
dependent upon gate bias polarity. Using a PMOS device as an example:
where a negative gate bias is required for enhancement mode operation to
attract positive charge carriers to the oxide-semiconductor interface and
create an active channel, a positive gate bias is used for depletion mode
operation to repel positive carriers and remove the connection between
source and drain.
Finally, Figure 6.5 (reproduced to
the right) illustrates sketches of
the iD-vGS characteristics for
enhancement and depletion mode
MOSFETs. Note that it is assumed
that a vDS of appropriate polarity
and magnitude has been applied
to generate iD. The characteristic
curves intersect the vGS axis at
the threshold voltage VT.
Although it may not be readily
apparent, keep in mind the |VT| is
dependent upon several physical
factors and is determined during
device fabrication.

The remainder of this section of our studies is going to have to do with the
terminal characteristics of the MOSFETs under consideration. Before we start
though, I would like to explicitly state a couple of things that were implicit in
the device introductions above:

Just as we defined the normal flow of current in the BJT as being from the
collector to emitter (assuming conventional current direction please
refer to the modified version of Figure 4.2(a) in Section C2 for
clarification), the normal current flow in a MOSFET is defined as being
from the drain to the source.
This next one may be a little harder to see. If you look at a horizontal
slice of the device that encompasses drain, substrate and source, you can
see that we effectively have two back-to-back diodes between the drain
and source. This results in a similar situation to our discussion of the BJT
and means that appropriate external voltages must be applied to bias the
device and allow current to flow.

Were going to be talking about the enhancement mode and depletion mode
devices in detail next, but as a general overview

Current flow in a MOS device is a

function of several material,
structural, and bias parameters,
including (some of which are
illustrated in the sketch to the
right for an enhancement mode
device): the channel length L,
which is the separation distance
between the source and drain; the channel width W, charge mobilities
within the active channel region (n for electrons or p for holes); the
capacitance of the oxide layer C ox, which is modeled as a parallel plate
capacitor and is in turn a function of oxide layer thickness (tox) and
permittivity (); the applied gate potential V GS; drain to source bias VDS; and
the threshold voltage V T. Although the MOSFET structure is inherently less
sensitive to doping considerations when compared to a conventional bipolar
junction transistor, the threshold voltage is dependent on the impurity
concentration of the channel region. Additionally, since several breakdown
mechanisms associated with MOS structures are contingent on the maximum
electric field in the drain space charge region, doping criteria may become
important to reduce these effects (were not going to be getting into
threshold voltage variations too much, but I just wanted to briefly present a
little of whats going on).

Enhancement Mode MOSFET Terminal Characteristics

Schematics of the enhancement mode MOSFET devices are given above and
are illustrated by Figures 6.3 and 6.4 in your text (note that there is an error
in the text narrative when referencing the texts figures). To briefly review:

Enhancement mode devices have no built in channel (i.e., the device is

normally off).
A threshold voltage, determined by physical and fabrication parameters,
exists for the MOSFET (VT > 0 for NMOS, VT < 0 for PMOS).
Generally, the source is grounded and is common to both gate and drain.
An active channel is created between drain and source (the transistor is
turned on) through the application of a gate voltage of appropriate
polarity and magnitude (vGS VT > 0 for NMOS, vGS - VT < 0 for PMOS).
Current flow between the drain and source is a function of both vGS and
vDS.

A representation of
the generic terminal
characteristics of an
enhancement mode
NMOS is shown to the
right (note that this
is a modified version
of Figure 6.8 of your
text). Analogous to
the BJT forward
characteristic curves of Section C4, once the device has been turned on (vGS
> VT), current may flow between drain and source with an applied vDS,
generating individual curves for different values of vGS-VT. Also similar to the
BJT, the MOSFET has different operational regions, depending upon external
biases. The delineation of the two regions for the MOSFET (triode and
saturation) is determined by the relationship between the applied drain-to-
source voltage, the applied gate-to-source voltage and the threshold
voltage, which occurs when vDS=vGS-VT, as illustrated above.

If vDS < vGS-VT, the transistor is operating in the triode region. As shown in
the expanded view of Figure 6.6 of your text, the relationship between iD
and vDS is approximately linear when operating in the triode region. This
allows the MOSFET to be operated as a linear resistor whose resistance is
controlled by vGS. In the triode region, the potentials at all three terminals
strongly affect the drain current (hence the name), and the drain current
obeys the relationship:

[ 2
i D = K 2(v GS VT )v DS v DS], where K =
1
2
n C ox
W
L
, (Equations 6.2 & 6.3)

with the parameters n, Cox, W and L as defined earlier.

If we now hold vGS constant (lets look at a single curve at first), and
increase vDS, things start to change. Bear with me for a few minutes the
following discussion is slightly different from your text, but (I hope) will
serve to clarify whats going on. Lets look at the applied vDS as a distributed
quantity along the channel with respect to the grounded source, voltage in
the channel varies from zero (when measured at the source) to vDS (when
measured at the drain). Now, if we simultaneously consider the effect of vGS,
we can see that both sources are trying to do the same thing (attract
electrons) and are essentially opposing each other. Since the gate-to-source
voltage controls the channel depth, and vGS and vDS are essentially
competing for available charges, the channel does not have a uniform depth
for any vDS > 0. In fact, the effective gate-to-source voltage decreases from
the applied vGS at the source, to vGS-vDS at the drain and the channel takes
on a tapered shape.

Another way of looking at this effect is to consider the gate-to-drain voltage

(vGD). This is just another way of looking at vGS-vDS, since:

v GD = v G v D = (v G v S ) (v D v S ) = v GS v DS .

However you want to look at it, when the difference between vGS and vDS
becomes less than VT, the depth of the active channel becomes zero and the
channel is constrained or pinched off. This means that further increases in
vDS have little effect on iD (ideally, no effect).
The condition vDS > vGS-VT, defines the normal active, or saturation
region of operation on the iD-vDS curves, with the boundary between the
triode and saturation regions (called the knee) defined by vDS=vGS-VT. If we
could have an ideal device, the curves in the saturation region would be
perfectly horizontal (i.e., absolutely no change in iD with changes in vDS).
Using the saturation condition in Equation 6.2 and simplifying yields the
expression for the drain current of an ideal MOSFET in saturation,

2
v
i D = K [v GS VT ]
2
= KV GS 1 .
T
2
(Equations 6.4 and 6.6)
VT

However, since we insist on dealing with reality, the characteristic curves

actually have a nonzero slope. This slope is accounted for by adding a linear
factor (1+vDS), where is a MOSFET parameter known as the channel
length modulation parameter (just like for the JFET).

i D = K [v GS VT ] (1 + v DS )
2
(Equation 6.5)

Often, the term |vDS| << 1, so the expression of Equation 6.4 (or 6.6) will
suffice to define the drain current. However, the parameter does serve to
define an important device parameter. If the straight-line characteristics of
the iD-vDS curves are extrapolated backwards, they intercept the vDS axis at
a common point, labeled -VA in the figure above. VA is a positive voltage for
the enhancement NMOS that is similar to the Early voltage in the BJT. If
the device were ideal, would be zero and VA would be infinite. Practical
devices generally have values on the order of 10-3V-1, with corresponding
VA values of several hundred volts.

The final term illustrated in the figure above is the incremental output
resistance, rO. For a constant vGS, we can operate along one of the
parametric curves of the figure and, in the saturation region; the
instantaneous relationship between id and vds (ac quantities) defines rO in
terms of a partial derivative

1
i
rO = d . (Equation 6.12, Modified)
v ds

Using the expanded expression of Equation 6.5, this partial turns out to be

1 1 V
rO = = A , (Equations 6.13 & 6.15, Modified)
K (VGS VT ) I D I D
2
where ID is the bias current associated with the constant value of vGS
(denoted VGS).

The figure to the right

provides a possible
representation of the
terminal characteristics
of an enhancement
PMOS. Note that this is
complementary to the
NMOS in every
respect, except the
signs of the axes have
been switched (vDS is now vDS, iD is now iD), the parameter is negative
(iD/vDS < 0), and the curves for increasing current magnitudes correspond
to more negative gate voltages. Since vGS and vDS are both negative, the
expressions for currents in the triode and saturation regions are the same as
for the enhancement NMOS. Keep in mind that these relationships give you
current magnitudes and that, while the current flows into the drain for the
NMOS, it flows out of the drain for the PMOS.

Depletion Mode MOSFET Terminal Characteristics

Schematics of the depletion mode MOSFET devices were given earlier and
are illustrated by Figures 6.1 and 6.2 in your text. Following the same
strategy as our discussion of enhancement mode devices, we will briefly
review depletion mode device characteristics:

Depletion mode devices have a built in channel (i.e., the device is

normally on).
A threshold voltage, determined by physical and fabrication parameters,
exists for the MOSFET (VT < 0 for NMOS, VT > 0 for PMOS).
Generally, the source is grounded and is common to both gate and drain.
The active channel is depleted between drain and source (the transistor is
turned off) through the application of a gate voltage of appropriate
polarity and magnitude (VGS VT < 0 for NMOS, VGS - VT > 0 for PMOS).
Current flow between the drain and source is a function of both vGS and
vDS. However, in the depletion mode, current can flow for both positive
and negative values of vGS for both NMOS and PMOS devices until the
cutoff condition is reached.
In keeping with our
previous presentations
of device terminal
characteristics, a set of
generic curves for the
depletion NMOS is
presented to the right.
This figure is based on
Figure 6.9 of your text,
but has been modified
to allow the same presentation as for the enhancement mode devices.

The equations that define the operation of the depletion mode MOSFET are
very similar to those we developed for enhancement mode. However, since
we can have a current when vGS = 0, we can define the drain-source
saturation current, also known as the zero-gate drain current, IDSS.
Using Equation 6.4 with vGS = 0, we define IDSS=KVT2. If desired, this
parameter may be introduced into Equation 6.4 for the representation

2
v
i D = I DSS 1 GS . (Equation 6.11)
VT

Finally (literally!), we
have the depletion
PMOS. Everything
weve talked about so
far still holds, so well
just take a quick look
at some characteristic
curves for the sake of
completeness.

Small-Signal Model of the MOSFET

The last thing were going

to do in this section is
introduce the small signal
model for the MOSFET. The
schematic for the small
signal model is given in
Figure 6.12 of your text and
is reproduced to the right.
Notice that this model is
directly analogous to the model derived for the BJT (with the appropriate
analogies substituted), but that the FET has no gate current (implying an
infinite differential input resistance). Remember that lower case symbols
with lower case subscripts mean that were dealing only with ac quantities.
Everything in the figure has been defined except for the transconductance
parameter, gm. Using the same method as we used for the BJT, we find

i d
gm = = 2K (VGS VT )(1 + v DS ) 2K (VGS VT ) (Equation 6.15, Mod.)
v gs v gs =VGS

where the final approximation was made by assuming that is small.

Well, wasnt that just too much fun!

Now that you fought your way through all the words and pictures, the table
below provides a summary of MOSFET characteristics:

NMOS PMOS
Enhancement Depletion Enhancement Depletion
Mode Mode Mode Mode
VT >0 <0 <0 >0
1 W 1 W
n C ox p C ox
K 2 L 2 L
Normally Off On Off On
To turn device on vGS > VT vGS < VT
(= VA-1) >0 <0
To operate in
triode region vDS < vGS - VT vDS > vGS - VT
Drain current in
triode region iD = K[2(vGS VT)vDS vDS2]
To operate in
saturation region vDS > vGS - VT vDS < vGS - VT
Drain current in
saturation region iD = K(vGS VT)2(1 + vDS)
1 |V |
rO = A
Output resistance | | ID ID
Transconductance g m = 2 K (VGS VT )(1 + v DS ) 2 K (VGS VT )