VLSI DESIGN AND ANALYSIS

DEPT. OF ELECTRONICS

MODULE II BASIC ELECTRICAL PROPERTIES OF MOS AND CMOS CIRCUITS

A MOS transistor is a majority-carrier device, in which the current in a conducting channel between the source and the drain is modulated by a voltage applied to the gate.

Symbols

Figure 1 : symbols of various types of transistors.

An MOS transistor is termed as a majority-carrier device, in which the current conduction in a conducting channel between the source and drain is modulated by a voltage applied at the gate. In nMOS the majority carrier are electrons. A positive voltage applied on the gate with respect to the substrate enhances the number of electrons in the channel and hence increases the conductivity of the channel. If gate voltage is less than a threshold voltage Vt , the channel is cutoff (very low current between source & drain). In PMOS (p-type MOS transistor) majority carriers are holes. Applied voltage is negative with respect to substrate. Symbol Definitions Vt: the threshold voltage of an nMOS or a pMOS transistor. Vtn: the threshold voltage of an nMOS transistor. Vtp: the threshold voltage of a pMOS transistor. Vds: the voltage difference between the drain and the source for an nMOS or a pMOS transistor. Vdsn: the voltage difference between the drain and the source for an nMOS transistor. Vdsp: the voltage difference between the drain and the source for a pMOS transistor.
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Vgs: the voltage difference between the gate and the source for an nMOS or a pMOS transistor. Vgsn: the voltage difference between the gate and the source for an nMOS transistor. Vgsp: the voltage difference between the gate and the source for a pMOS transistor. Ids: the current between the drain and the source for an nMOS or a pMOS transistor. Idsn: the current between the drain and the source for an nMOS transistor. Idsp: the current between the drain and the source for a pMOS transistor. Vin: the input voltage. Vinp: the input voltage for a pMOS transistor. Vinn: the input voltage for an nMOS transistor. Vout: the output voltage. Vdd: power supply. Vss: ground. Four modes of transistors Enhancement mode nMOS transistor: Vtn > 0 If Vgs > Vtn, the transistor starts to conduct. The number of electrons in the channel increases so that Idsn increases accordingly. If Vgs < Vtn, the transistor is cut off and Ids is almost zero. Depletion mode nMOS transistor: Vtn < 0 (in the textbook it is referred as -Vtn and Vtn > 0) Even if Vgs = 0 > Vtn, the transistor is on. If Vgs < Vtn < 0, the transistor is cut off. Enhancement mode pMOS transistor: Vtp < 0 (in the textbook it is referred as -Vtp and Vtp > 0) If Vgs < Vtp < 0, the transistor starts to conduct. The number of holes in the channel increases so that Idsp increases accordingly. If Vgs > Vtp, the transistor is cut off.
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Depletion mode pMOS transistor: Vtp > 0 Even if Vgs = 0 < Vtp, the transistor is on. If Vgs > Vtp > 0, the transistor is cut off. Conduction characteristics of MOS transistors

Devices that are normally cut-off with zero gate bias are classified as "enhancement- mode "devices. Devices that conduct with zero gate bias are called "depletion-mode"devices. Enhancement-mode devices are more popular in practical use. The n-channel transistors and pchannel transistors are the duals of each other; that is , the voltage polarities required for correct operation are the opposite. Most CMOS integrated circuits at present use enhancement mode transistors. nMOS ENHANCEMENT TRANSISTOR Structure of an n-channel enhancement-type transistor is shown in figure. which is formed on a p-type substrate of moderate doping level. As shown in the figure, the source and the drain regions made of two isolated islands of n+-type diffusion. These two diffusion regions are connected via metal to the external conductors.

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The depletion regions are mainly formed in the more lightly doped p-region. Thus, the source and the drain are separated from each other by two diodes.

OPERATION OF nMOS TRANSISTOR With zero gate bias, i.e. Vgs = 0, Ids = 0 because the source and the drain are effectively insulated from each other by the two reversed-bias pn junctions (indicated as the diode symbol in Figure 3). Accumulation mode: With positive gate bias with respect to the source and substrate (generally denoted by Vgs > 0), an electric field E across the substrate is established such that electrons are attracted to the gate and holes are repelled from the gate.(See Figure 4 (a)) Depletion mode: If Vg Vtn, a depletion channel under the gate free of charges is established.(See Figure 4 (b)) Inversion mode: If Vgs > Vtn, an inversion channel (region) consisting of electrons is established just under the gate oxide and a depletion channel (region) is also established just under the inversion region.(See Figure 4 (c)) Hence the term n-channel is applied to the nMOS structure.

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Electrically, a MOS device acts as a voltage-controlled switch. It conducts initially when Vgs = Vt. Vgs establishes a conducting channel, while Vds is responsible for sweeping the electrons from the source to the drain. Thus, establish a current flow between the drain and the source. The electric field established by Vgs is orthogonal to the electric field established by Vds. When Vgs Vt and Vds = 0, the width of the n-type channel at the source end is equal to that at the drain end. This is due to Vgs = Vgd (See Figure 5 (a)). Nonsaturated (resistive or linear) mode: when Vgs - Vt > Vds > 0, the width of the n-type channel at the source end is larger than that at the drain end. This is due to Vgs Vgd > Vt. (See Figure 5 (b)) Saturated mode: When Vds > Vgs - Vt > 0, the n-type channel no longer reaches the drain. That is, the channel is pinched off. This is due to Vgs > Vt and Vgd < Vt. (See Figure 5 (c)) In nonsaturated mode, Ids is a function of gate and drain voltage, while in saturated mode, Ids is a function of gate voltage. In saturated mode, the movement of electrons in the channel is brought about under the influence of positive drain voltage. After the electrons leave the channel and inject into the drain depletion region, they are accelerated toward the drain. Because the voltage across the pinched-off channel tends to remain fixed at Vgs - Vt, the drifting speed of electrons in the channel is controlled by Vgs - Vt, but almost independent of Vds. This is what saturation means.

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For a fixed Vds and Vgs, the factors that influence Ids are: The distance between source and drain. The channel width Vt The thickness of gate oxide. The dielectric constant of the gate oxide. The carrier mobility. Normal conduction characteristics of a MOS transistor are: Cut-off region: Ids 0 Non-saturated region: The channel is weakly inverted. Ids is dependent on the gate and drain voltage with respect to the substrate. Saturated region: The channel is strongly inverted. Ids is ideally independent of Vds.
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pMOS ENHANCEMENT TRANSISTOR A reversal of n-type and p-type regions yields a p-channel channel transistor. (See Figure 6)

For a pMOS enhancement transistor; (1) Vg < 0 (2) Holes are major carrier (3) Vd < 0 , which sweeps holes from the source through the channel to the drain .

MOS EQUATIONS BASIC DC EQUATIONS Three MOS operating regions are: 1. Cutoff or subthreshold region 2. Linear region 3. Saturation region. The following equation describes all these three regions

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Where is MOS transistor gain and it is given by =/tox(W/L) , again is the mobility of the charge carrier , is the permittivity of the oxide layer. ,toxis the thickness of the oxide layer. ,W is the width of the transistor.( shown in diagram) L is the channel length of the transistor.(shown in diagram)

V-I CHARACTERISTICS OF MOS The graph of Id and Vds for a given Vgs is given below:

Figure : VI Characteristics of MOSFET

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THRESHOLD VOLTAGE (

The voltage at which an MOS device begins to conduct ("turn on"). The threshold voltage is a function of (1) Gate conductor material (2) Gate insulator material (3) Gate insulator thickness (4) Impurity at the silicon-insulator interface (5) Voltage between the source and the substrate Vsb (6) Temperature Threshold voltage equations:

Where,

And

Vt-mos is the ideal threshold voltage for an ideal MOS capacitor Vfb is the flat-band voltage k: Boltzmanns constant = 1.38 * 10-23 J/oK. q: electronic charge = 1.602 * 10-19 Coulomb. T: Temperature (oK). NA: the density of carriers in the doped substrate. Ni: the density of carriers in the undoped substrate.
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si: the permittivity of silicon = 1.06 * 10-12 (F/cm) Cox: the gate-oxide capacitance, which is inversely proportional to the gate oxide thickness (tox). Qfc: the fixed charge due to surface states that arise due to imperfections in the silicon-oxide interface and doping. ms: the work function difference between the gate material and the silicon substrate. Two common techniques for the adjustment of Vt are: Affecting Qfc by varying the doping concentration at the silicon-insulator interface through ion implantation. Affecting Cox by using different insulating material for the gate. A layer of silicon nitride (Si3N4) combined with a layer of silicon oxide can effectively increase the relative permittivity of gate insulator from 3.9 to 6. BODY EFFECT When connecting several devices in series as shown in Figure below, the source-tosubstrate of each individual devices may be different. For example, Vsb2 > Vsb1 = 0. As Vsb (Vsource - Vsubstrate) is increased, the density of the trapped carriers in the depletion layer also increases. The overall effect is an increase in the threshold voltage, Vt (Vt2 > Vt1).

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THE PASS TRANSISTOR Unlike bipolar transistors, the isolated nature of the gate allows MOS transistors to be used as switches in series with lines carrying logic levels in a way similar to the use of relay contacts. This application of the MOS device is called pass transistor and switching logic arrays can be formed- for example, an AND array as in fig. below.

THE nMOS INVERTER A basic requirement of producing a complete range of logic circuits is the inverter. This is needed for restoring logic levels, for Nand and Nor gates, and for sequential and memory circuits of various forms. The basic inverter circuit requires a transistor with source connected to ground and a load resistor of some sort connected from the drain to the positive supply rail . The output is taken from the drain and the input applied between gate and ground. Resistors are not conveniently produced on silicon substrate; even modest values occupy excessively larger areas so that some other form of load resistance is required. A convenient way to solve this problem is to use a depletion mode transistor as the load as shown below;

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With no current drawn from the output, the currents Ids for both transistors must be equal. For the depletion mode transistor, the gate is connected to the source so it is always on and only the characteristics curve Vgs=0 is relevant. In this condition the depletion mode transistor is called pull-up (pu)and the enhancement mode device is called pull down(pd)

To obtain transfer characteristics superimpose the Vgs =0 depletion mode characteristics with for the enhancement mode device corresponds to minimum voltage across the depletion mode transistor. The point of intersection of the curves as in fig above give points on the transfer characteristics as in fig below;

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As Vin exceeds the p.d threshold voltage current begins to flow. The output voltage Vout thus decreases and subsequent increase in Vin causes the p.d transistor to come out of saturation and become resistive. Note that p.u transistor is initially resistive as p.d turns on. During transition, the slope of the transfer characteristics determines the gain;

The point at which Vout= Vin is denoted as Vinv. DETERMINATION OF PULL-UP TO PULL-DOWN RATIO FOR AN nMOS INVERTER DRIVEN BY ANOTHER nMOS INVERTER Consider the arrangement shown in fig; which an inverter is driven from the output of another similar inverter. Consider the depletion mode transistor for which =0 under all conditions, and further assume that in order to cascade inverters without degradation of levels.

For equal margins of the inverter threshold, V inv = 0.5 saturation and,

. At this point both transistors are in

In the depletion mode;

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And in the enhancement mode;

Equating (since the currents are the same) we have;

Where Wp.d, Lp.d, Wp.u and Lp.u are the width pength of p.u and p.d transistors respectively.

Substitute the typical values as follows,

For an inverter directly driven by an inverter.

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PULL-UP TO PULL-DOWN RATIO FOR AN nMOS INVERTER DRIVEN THROUGH ONE OR MORE TRANSISTOR Consider the arrangement as shown; in which the input to inverter 2 comes from the output of inverter 1 but passes through one or more nMOS transistors used as switches in series(called pass transistors).

The connection of pass transistors in series will degrade the logic 1 level into inverter 2 so that the output will not be a proper logic 0 level the critical condition is when point A is at 0 volts and B is thus at V DD, but the voltage into inverter 2 at point c is now reduced from V DD by the threshold voltage of the series pass transistor. With all pass transistor gates connected to VDD, there is a loss of Vtp , therefore input of inverter 2 is

Vin2= VDD-Vtp

Where Vtp= threshold voltage for pass transistor.

Consider inverter 1 with input = VDD. If the input is at VDD, then the p.d transistor T2 is conducting but with a low voltage across it; therefore, it is in its resistive region represented by R1 in fig below. Meanwhile the p.u transistor T1 is in saturation and is represented as a curren source.

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For p.d transistor, ( Therefore, )

is small and Thus,

may be ignored;

For depletion mode p.u in saturation Vgs=0

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The product

Thus,

Consider inverter 2 when input = VDD-Vtp. As inverter 1

Where,

If inverter 2 is to have the same output voltage under these conditions then Vout 1 = Vout 2. That is

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Taking typical values,

Summarizing for an nmos device, An inverter driven directly from the output of another should have a Z p.u/ Z p.d ratio of >=4/1. An inverter driven through one or more pass transistor should have a Z p.u / Z p.d ratio of >=8/1. THE CMOS INVERTER A complementary CMOS inverter is implemented as the series connection of a p-device and an n-device, as shown in Figure. Note that the source and the substrate (body) of the p device is tied to the VDD rail, while the source and the substrate of the n- device are connected to the ground bus. Thus, the devices do not suffer from any body effect. To derive the DC transfer characteristics for the CMOS inverter, which depicts the variation of the output voltage (Vout) as a function of the input voltage (Vin), one can identify five following regions of operation for the n -transistor and p - transistor.

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Figure: Variation of current in CMOS inverter with Vin

Transfer function The current voltage relation can be written as,

In saturation.
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In both cases the factor K is a technology-dependent parameter such that

The factor W/L is, contributed by the geometry,

THE COMPLEMENTARY CMOS INVERTER-DC CHARACTERISTICS The output voltage Vout is drawn as a function of the input voltage Vin. Table outlines the various regions of operation for the n- and p-transistors of an inverter.

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Find the DC-transfer characteristics of an inverter: Step1: obtain VI characteristics for p- and n-transistor respectively based on the equation dc equations (see Figure (a)) Step2: reflect the VI characteristics for p-transistor about the x-axis (see Figure (b)) Step3: the input/output transfer curve may now be determined by the points of common Vgs intersection in Figure (c).

Solving for Vinn=Vinp and Idsn=Idsp gives the desired transfer characteristics of the inverter. The switching point is typically designed to be at VDD/2. Operation regions of an inverter (see Figure and Table below)
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Region A: defined by , where the n-device is cutoff and the p-device is in the linear region. Vout=VDD because Idsn=-Idsp= 0 Vdsp=Vout-VDD= 0 Vout=VDD Region B: defined by , where the p-device is in the nonsaturated region while the n-device is in saturation. The equivalent circuit in this region can be represented by a resistor for the p-transistor and a current source for the n-transistor as shown in Figure a below;

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Let Idsp=-Idsn, the output voltage Vout can be expressed as

Region C: defined by , where the p- and n-devices are in saturation. Its equivalent circuit is shown in Figure (b) above.

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In this region, we have two current sources in series, which is an unstable condition. Thus a small input voltage has a large effect at the output. The input equation shown in

can be used for defining the gate threshold Vinv , which corresponds to the state where Vout=Vin .

Region D: defined by where the p-device is in saturation while the n-device is in the nonstaturated region. (See Figure (c)above for its equivalent circuit).

Region E: defined by Vin>VDD+Vtp where the p-device is cutoff (Idsp=0) and the n-device is in the linear region.

n/p RATIO The transfer curves of an inverter plotted as a function of n/p are shown in Figure below; Vinv(gate threshold voltage) where Vin = Vout is dependent on n/p. As the ration n/p is decreased, as shown in Figure the transition region shifts from left to right. For the CMOS invert a ratio of n/p = 1 may be desirable since it provides equal current-source and sink capability. Change channel dimension W and L of the p and n devices would change the value and thus would change the ratio n/p for a given process. The inverter transfer curve is also plotted for Wn/ Wp as shown in Figure (b). n T-1.5 => Ids T-1.5. The effective carrier mobility decreases when temperature increases, but n/p ratio is relatively independent of temperature to a good approximation.

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NOISE MARGIN Noise margin allows us to determine the allowable noise voltage on the input of a gate so that the output will not be affected. It is closely related to the input-output voltage characteristics. The LOW noise margin :defined as the difference in magnitude between the maximum LOW output voltage(VOLmax) of the driving gate and the maximum input LOW voltage(VILmax) recognized by the driven gate (Figure ). The HIGH noise margin : defined as the difference in magnitude between the minimum HIGH output voltage (VOHmin) of the driving gate and minimum HIGH voltage (VHmin) recognized by the driven gate.(see Figure below)

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VIH = VIL is desirable. This implies the transfer characteristic should switch abruptly. That is, there should be a high gain in the transition region. For the purpose of calculating noise margins, the transfer characteristics of a typical inverter and the definition of voltage levels VIL, VOL, VIN, VOH are sown in Figure below. The noise margin defined for the inverter shown in Figure below is NML=2.3 V and NMH=1.7V . Note that .

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SWITCHING CHARACTERISTICS Switching characteristics for CMOS inverter

Rise time (tr): The time for a waveform to rise from 10% to 90% of its steady-state value. Fall time (tf): The time for a waveform to fall from 90% to 10% steady-state value Delay time (td): The time difference between input transition (50%) and the 50% output level. (This is the time taken for a logic transition to pass from input to output) High-to-low delay (tdf) Low-to-high delay (tdr) FALL TIME OF THE INVERTER Equivalent circuit for fall-time analysis

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The fall time consists of two intervals tf1=period during which the capacitor voltage, Vout, drops from 0.9VDDto (VDD-Vtn) tf2=period during which the capacitor voltage, Vout, drops from (VDD-Vtn) to 0.1VDD Timing Calculations. tf1can be calculated with the current-voltage equation as shown below, while in saturation.

tf2also can be obtained by the same way. Finally, the fall time can be estimated with,

Similarly, the rise time can be estimated with,

Thus the propagation delay is,

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