MODULE 1

CMOS
TECHNOLOGY

S.ARUNA,
AP/EEE,
KEC
Outline
 Introduction
 Basic CMOS technology: N well, P well, Twin tub, SOI Process
 MOS Transistor Theory
 NMOS and PMOS Enhancement transistor and its Operation
 MOS DC equations
 Second Order Effects
 MOS models
 Small signal AC characteristics
 Complementary CMOS inverter DC characteristics
 Switching Characteristics
 Power dissipation
 Latch up and prevention.
 MOSFETS as switches and Pass Transistors.
Introduction
Integrated circuits: many transistors on one chip.
Very Large Scale Integration (VLSI)
Complementary Metal Oxide Semiconductor (CMOS)
 Fast, cheap, “low-power” transistors circuits
Introduction – Continued…..
 1018 transistors manufactured in 2003

 Modern electronic chips are built mostly on silicon

substrates.

 Silicon is a Group IV semiconducting material

 Crystal lattice: covalent bonds hold each atom to four

neighbours
A Brief History Invention of the Transistor
 Vacuum tubes ruled in first half of 20th century Large, expensive, power-
hungry, unreliable
 1947: first point contact transistor (3 terminal devices)
 Shockley, John Bardeen and Walter Brattain at Bell Labs
 1958: First integrated circuit
 Flip-flop using two transistors, built by Jack Kilby (Nobel Laureate) at
Texas Instruments and Robert Noyce (Fairchild) is also considered as a co-
inventor
 First Planer IC was built in 1961
 2003
 Intel Pentium 4 processor (55 million transistors)
 512 Mbit DRAM (> 0.5 billion transistors)
 53% compound annual growth rate over 45 years
 No other technology has grown so fast so long
 Driven by miniaturization of transistors
 Smaller is cheaper, faster, lower in power!
 Revolutionary effects on society
MOS Integrated Circuits
 1970’s processes usually had only nMOS transistors
Inexpensive, but consume power while idle
 1980s-present: CMOS processes for low idle power

Intel 1101 256-bit Intel 4004 4-bit Proc

SRAM
Moore’s Law
 1965: Gordon Moore plotted transistor on each chip
 Fit straight line on semilog scale
 Transistor counts have doubled every 26 months
 Integration Levels
Name Signification Year Transistors number Logic gates

SSI small-scale integration 1964 1 to 10 1 to 12

MSI medium-scale integration 1968 10 to 500 13 to 99

LSI large-scale integration 1971 500 to 20,000 100 to 9,999

10,000 to
VLSI very large-scale integration 1980 20,000 to 1,000,000
99,999

100,000 and
ULSI ultra-large-scale integration 1984 1,000,000 and more
more
Modern Transistors
•Modern transistors are few microns wide and approximately
0.1 micron or less in length
• Human hair is 80-90 microns in diameter
 Transistor Types
 Bipolar transistors
 npn or pnp silicon structure
 Small current into very thin base layer controls large
currents between emitter and collector
 Base currents limit integration density
 Metal Oxide Semiconductor Field Effect Transistors
 nMOS and pMOS MOSFETS
 Voltage applied to insulated gate controls current
between source and drain
 Low power allows very high integration
nMOS Enhancement Transistor
 Moderately doped p-type silicon substrate.
 Two heavily doped n+ regions (the source and the drain).
 A channel sandwiched between a thin insulating layer of silicon
dioxide (SiO2) and p-substrate.
 A polysilicon gate over the gate oxide (the SiO2 over the channel).
 No DC current flows from gate to channel due to insulating of gate
oxide.
Physical structure of an nMOS Transistor
Operation of nMOS transistor
 With zero gate bias, i.e. Vgs = 0, Ids = 0 because the source and the drain are
effectively insulated from each other by the two reversed-bias pn junctions.
 Accumulation mode: With positive gate bias with respect to the
source and substrate (generally denoted by Vgs > 0), an electric field E across
the substrate is established such that electrons are attracted to the gate and
holes are repelled from the gate.
 Depletion mode: If Vgs = Vtn, a depletion channel under the gate
free of charges is established.

 Inversion mode: If Vgs > Vtn, an inversion channel (region)

consisting of electrons is established just under the gate oxide and a
depletion channel (region) is also established just under the
inversion region.
Hence the term “n-channel” is applied to the nMOS structure.
nMOS Operation - Summary
polysilicon gate
Vg < 0
silicon dioxide insulator
 Gate and body form MOS +
- p-type body
capacitor

(a)
 Operating modes

0 < V g < Vt
 Accumulation depletion region
+
-

 Depletion
(b)

 Inversion
Vg > Vt
inversion region
+
- depletion region

(c)
Cutoff Region
 If Vgs < Vtn , the current flow is essentially zero.
 If Vgs = Vtn , MOS device acts as a voltage controlled switch which
conducts initially.
 When the gate voltage Vgs increases above Vtn, then the electric field
repels more holes from the channel area leaving an excess of
electrons. (Vgs > Vtn , Vds = 0)
 The field also pulls out electrons from the source and drain area
which, by virtue of being the n+ regions, have excess of electrons.
the area between source and drain an inversion layer.
 A conducting channel has been formed between the source and
drain.
Linear Region
 Vds > 0 and (Vgs - Vtn) > Vds, the drain-source current, Ids starts to
flow.
 When the Vds voltage is relatively small, the transistor operates in
the so-called linear region, resistive, nonsaturated or unsaturated.
 In this region of operation the drain current Ids is a quadratic
function of the source-drain voltage, Vds.
 The channel depth at the drain end decreases with the increase of
Vds.
 In this region Ids is a function of both gate and drain voltages.
Saturation Region
 If (Vgs - Vtn) < Vds and Vgd < Vtn , the channel becomes
pinch-off. (Vds = Vsat = (Vgs - Vtn))
 the further increase of the Vds does not result in an increase
of Ids. (Ids is independent of Vds)
 Ids is controlled by the gate voltage.
 The transistor now operates in the saturation mode.
 The depletion region acts as a dielectric.
Normal conduction characteristics of a MOS
transistor:
 “Cut-off” region: Ids 0
 “Non-saturated” region: The channel is weakly inverted. Ids is
dependent on the gate and drain voltage with respect to the
substrate.
 “Saturated” region: The channel is strongly inverted. Ids is
ideally independent of Vds.
For a fixed V and V , the factors that influence I :
ds gs ds
 The distance between source and drain.
 The channel width
 Vt
 The thickness of gate oxide.
 The dielectric constant of the gate oxide.
 The carrier mobility
 PMOS Transistor
 The pMOS transistor (p-type, p-channel) is a complementary
structure to the nMOS transistor.
 The pMOS transistor is built on the n-type substrate which is
donor-doped silicon.
 The source and drain of a pMOS transistor are now p+ diffusion
regions.
 The carriers in the channel are now positive holes. As previously,
their flow is controlled by the gate-substrate voltage.
Operation of MOS Transistors
 The pMOS operates in the dual way. The basic principle of
operation can be stated as follows.
“ The flow of the current between the source and the drain is
controlled by the electric field generated by the gate-substrate
voltage.”
 In order for the drain-source current to exist there must be carriers
existing in the area between the source and drain referred to as the
conducting channel.
 A MOS transistor is a four terminal device.
 In most cases, the substrate and the source of an nMOS are
connected to the ground potential (GND)
MOS DC Equations
 MOS transistor have three regions of Operation
 Cutoff or Subthreshold Region
 Nonsaturation or Linear Region
 Saturation Region

Cutoff Region:
Ids = 0 Vgs ≤ Vt

Nonsaturation , linear or Triode Region:

Saturation Region:
MOS Transistor Theory
Terminal Voltages
 Mode of operation depends on Vg, Vd, Vs Vg
 Vgs = Vg – Vs + +
Vgs Vgd
 Vgd = Vg – Vd - -
 Vds = Vd – Vs = Vgs - Vgd Vs Vd
- +
Vds
 Source and drain are symmetric diffusion terminals
 By convention, source is terminal at lower voltage
 Hence Vds  0
 nMOS body is grounded. First assume source is 0 too.
 Three regions of operation
 Cutoff
 Linear
 Saturation
nMOS Cutoff
No channel
Ids = 0

Vgs = 0 Vgd
+ g +
- -
s d

n+ n+

p-type body
b
 nMOS Linear
Vgs > Vt
 Channel forms Vgd = Vgs
+ g +
- -
s d
 Current flows from d to s n+ n+ Vds = 0

 e- from s to d p-type body

b

 Ids increases with Vds

Vgs > Vt
Vgs > Vgd > Vt
+ g +
- - Ids
 Similar to linear resistor s d
n+ n+
0 < Vds < Vgs-Vt
p-type body
b
nMOS Saturation
 Channel pinches off

 Ids independent of Vds

 We say current saturates

 Similar to current source

Vgs > Vt
g Vgd < Vt
+ +
- -
s d Ids

n+ n+
Vds > Vgs-Vt
p-type body
b
I-V Characteristics
In Linear region, Ids depends on
How much charge is in the channel?
How fast is the charge moving?
Channel Charge
MOS structure looks like parallel plate capacitor while
operating in inversion
Gate – oxide – channel
Qchannel =

gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
channel
tox n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body
Channel Charge
MOS structure looks like parallel plate capacitor while
operating in inversion
Gate – oxide – channel
Qchannel = CV
C =

gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
channel
tox n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body
Channel Charge
MOS structure looks like parallel plate capacitor while
operating in inversion
Gate – oxide – channel
Qchannel = CV
Cox = ox / tox
C = Cg = oxWL/tox = CoxWL
V =

gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
channel
tox n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body
Channel Charge
MOS structure looks like parallel plate capacitor while
operating in inversion
Gate – oxide – channel
Qchannel = CV
Cox = ox / tox
C = Cg = oxWL/tox = CoxWL
V = Vgc – Vt = (Vgs – Vds/2) – Vt

gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
channel
tox n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body
Carrier velocity
Charge is carried by e-
Carrier velocity v proportional to lateral E-field
between source and drain
v =
Carrier velocity
Charge is carried by e-
Carrier velocity v proportional to lateral E-field
between source and drain
v = E  called mobility
E =
Carrier velocity
Charge is carried by e-
Carrier velocity v proportional to lateral E-field
between source and drain
v = E  called mobility
E = Vds/L
Time for carrier to cross channel:
t =
Carrier velocity
Charge is carried by e-
Carrier velocity v proportional to lateral E-field
between source and drain
v = E  called mobility
E = Vds/L
Time for carrier to cross channel:
t = L / v
 nMOS Linear I-V
Now we know
How much charge Qchannel is in the channel
How much time t each carrier takes to cross

I ds 

3: CMOS Transistor
Slide 36
Theory
nMOS Linear I-V
Now we know
How much charge Qchannel is in the channel
How much time t each carrier takes to cross

Qchannel
I ds 
t


3: CMOS Transistor
Slide 37
Theory
 nMOS Linear I-V
Now we know
How much charge Qchannel is in the channel
How much time t each carrier takes to cross

Qchannel
I ds 
t
W  V  V  Vds V
 Cox  gs t  ds
L 2 
W
V  = Cox
  Vgs  Vt  ds Vds L
 2
nMOS Saturation I-V
If Vgd < Vt, channel pinches off near drain
When Vds > Vdsat = Vgs – Vt
Now drain voltage no longer increases current

I ds 
nMOS Saturation I-V
If Vgd < Vt, channel pinches off near drain
When Vds > Vdsat = Vgs – Vt
Now drain voltage no longer increases current

 Vdsat V
I ds   Vgs  Vt   dsat
 2 
nMOS Saturation I-V
If Vgd < Vt, channel pinches off near drain
When Vds > Vdsat = Vgs – Vt
Now drain voltage no longer increases current

 Vdsat V
I ds   Vgs  Vt   dsat
 2 

 Vgs  Vt 
2

2
 nMOS I-V Summary
Shockley 1st order transistor models


 0 Vgs  Vt cutoff

  Vds V V  V
I ds     Vgs  Vt   ds linear
 2 
ds dsat

 
Vgs  Vt 
2
 Vds  Vdsat saturation
2
Example
0.6 m process (Example)
From AMI Semiconductor
tox = 100 Å
2.5
Vgs = 5
  = 350 cm2/V*s
2
Vt = 0.7 V
1.5 Vgs = 4

Ids (mA)
Plot Ids vs. Vds
1
Vgs = 3
Vgs = 0, 1, 2, 3, 4, 5 0.5
Vgs = 2
Use W/L = 4/2  Vgs = 1
0
0 1 2 3 4 5
Vds

W  3.9  8.85  10 14   W  W

  Cox  350   8    120  A /V 2
L  100  10  L  L
pMOS I-V
All dopings and voltages are inverted for pMOS
Mobility p is determined by holes
Typically 2-3x lower than that of electrons n
120 cm2/V*s in AMI 0.6 m process
Thus pMOS must be wider to provide same current
In this class, assume n / p = 2
 MOS Transistor Theory
 The majority carriers of an nMOS transistor: Electrons
 The majority carriers of a pMOS transistor: Holes
Basic CMOS Technology
Lithography
Physical structure
CMOS fabrication sequence
Yield
Design rules
Other processes
Advanced CMOS process
Process enhancements
Technology scaling
N-Well Process
 Step 1: Si Substrate
 Step 2: Oxidation
 Step 3: Photoresist Coating
 Step 4: Masking
 Step 5: Removal of Photoresist
 Step 6: Acid Etching
 Step 7: Removal of Photoresist
 Step 8: Formation of n-well
 Step 9: Removal of SiO
2
 Step 10: Polysilicon Deposition
 Step 11: N-Diffusion
 Step 12: P-Diffusion
 Step 13: Contact Cuts
 Step 14: Matallization
N-Well Process
Advantages of n-well Process
n-well CMOS are superior to p-well because of
lower substrate bias effects on transistor threshold
voltage.
Lower parasitic capacitances associated with
source and drain region
Latch-up problems can be considerably reduced by
using a low resistivity epitaxial p-type substrate
However n-well process degrades the performance
of poorly performing p-type transistor
Silicon-on Insulator Process
Advantages:
 No wells  denser transistor structures
 Lower substrate capacitances
 Reduced Source and Drain to Substrate Capacitance.
 Absence of Latchup.
 Lower Passive current.
 Denser Layout  Low cost.
SOI Process
Second Order Effects
Threshold Voltage
Body Effect
Subthreshold region
Channel-length Modulation
Mobility Variation
Fowler-Nordheim Tunneling
Drain Punchthrough
Impact Ionization - Hot Electrons
Threshold Voltage
 The voltage applied between the gate and the source of a MOS device below
which the drain-to-source current Ids “effectively” drops to zero.
 Vt is a function of the following parameters:
 Gate conduction material
 Gate insulation material
 Gate insulator thickness
 Channel doping
 Impurities at the silicon-insulator interface
 Voltage between the source and the substrate, Vsb.

V t  Vt- mos  Vfb

Drain Punch through
Vd is very high with respect to source, depletion region around drain
may extend to source causing current flow I ds independent of Vgs
Good for I/O protection circuit.

Subthreshold region
Cut-off = subthreshold region
Ids » 0 (Subthreshold region)
But the finite value of Ids may be used to construct very low power
circuits.
Body Effect
 When connecting several devices in series as shown in Figure, the
source-to-substrate of each individual devices may be different. For
example, Vsb2 > Vsb1 = 0.
 As Vsb (Vsource - Vsubstrate) is increased, the density of the trapped carriers in
the depletion layer also increases. The overall effect is an increase in the
threshold voltage, Vt (Vt2 > Vt1).

• Body effect is defined as the

threshold voltage (Vt ) is not constant
with respect to the voltage difference
between substrate and source of
MOS transistor.

• It is also known as substrate bias

effect.
Channel Length Modulation

GND VDD VDD

Source Gate Drain
Depletion Region
Width: Ld

L
n+ Leff n+

p GND bulk Si
Channel Length Mod I-V
 Shorter Leff gives more current Ids (A)
400
Ids increases with Vds Vgs = 1.8
300
Even in saturation
Vgs = 1.5
200

Vgs = 1.2
100
Vgs = 0.9
Vgs = 0.6
0
0 0.3 0.6 0.9 1.2 1.5 1.8 Vds

  = channel length modulation coefficient

not feature size
Empirically fit to I-V characteristics
Mobility
Impact Ionization-hot electrons:
 When the length of the transistor is reduced, the electric
field at the drain increases.

 The field can be come so high that electrons are imparted

with enough energy we can term them as hot.

 These hot electrons impact the drain, dislodging holes that

are then swept toward the negatively charged substrate and
appear as a substrate current.

 This effect is known as Impact Ionization.

Drain Punch through
When drain is at high enough voltage with respect to
source, the depletion region may extend to source,
causing current flow irrespective of gate voltage.

This is called as punch through condition

MOS Transistors as switches
MOS transistors are modelled as controlled
switches.
Voltage at gate controls path from source to
drain
Pass Transistors
Transistors can be used as Switches.
Switch Model of CMOS Transistor
|V GS|

Ron

|VGS| > |VT|

|VGS| < |VT|
 CMOS Inverter
 A CMOS inverter is series connection of a p-device and an n-
device
CMOS Inverter
VIN =0 VIN =VDD
VDD VDD

Rp

Vout Vout

CL
CL
Rn
The Complementary CMOS Inverter
-DC Characteristics
 Region A

defined by 0 < Vin < Vtn

n-device is cutoff
p-device is in the linear region.
 

Vout=VDD
because Idsn= -Idsp= 0
V =V -V = 0 c V =V
dsp out DD out DD
 Region B
defined by Vtn < Vin < VDD/2
n-device is saturation region
p-device is in the non saturation region.

Idsn for the n-device by setting Vgs = Vin . So

[V n 
Idsn  n in 2 tn n  [ n
]
V 2] W
tox Ln
Idsp for the p-device by setting Vgs = Vin –VDD, Vds = Vout –VDD,
⎡ (Vout Vdd )2 p  W
Idsp (V V V )(V p  [ p ]
p in dd tp out dd
2 tox Lp
( ) V )
Substituting Idsp = -Idsn we have

Vdd
V (V V ) (V V ) 2[V 2
out in tp in tp 2 in tp dd   V
in ]V
tn
p
Region C
defined by Vin = VDD/2
I  p

VGS  Vtp 
2

n-device is in saturation region dsp 2

p-device is in saturation region p
I dsp   V
in  VDD  Vtp  ; Vin  Vtp  VDD
2

2
n
VDS increases, IDS also I dsn  Vin  Vtn 2 ; Vin  Vtn
2
increases
I dsp   I dsn
So region C is finite slope
  n  

 p Vtn   VDD  Vtp 
  p  
   
Vin 
  
 p 1  n 
  p 

assume p   n andVtp  Vtn
VDD
Vin 
2
 Region D
Defined by Vdd /2 < Vin < Vdd - Vtp
p-device saturation,
n-device linear
The two currents are
[Vin Vdd
Idsp p V ]2 tp

2
 out
2 ]
Idsn  n[(Vin V
2
Vtn)Vout
□ With Idsp = - Idsn we have

p
V (V V ) (V V )  (V
out in tn in in tn 2 dd Vtp
n
2
Region E
Defined by Vin Vdd - Vtn
p-device cut off,
n-device linear

Idsn=-Idsp =0
Vgsp= Vin - Vdd which is more positive than Vtp and Hence
Vout = 0
Summary
Region Conditon p n output
A 0 < Vin < Vtn Non - Sat Cut off Vout = VDD

B Vtn < Vin < VDD/2 Non- Sat Sat

C Vin = VDD/2 Sat Sat

D Vdd /2 < Vin < Vdd - Vtp Sat Non Sat

E Vin Vdd - Vtn Cutoff Non Sat Vout = VSS