Unit 3

UNIT 3
SYLLABUS : PART 1
CMOS LOGIC CIRCUITS-
• NMOS inverter (resistive and active load),
• Pull up to Pull-down ratio(βp/βn) for a NMOS
Inverter and CMOS Inverter,
• determination of inverter parameter (VIL, VIH
VOL VOH) and Noise Margin.
• Speed and power dissipation analysis of CMOS
inverter.
SYLLABUS : PART 2
• Combinational Logic, NAND Gate, NOR gate,
XOR gate, Compound Gates, 2 input CMOS
Multiplexer,
• Memory latches and registers,
• Transmission Gate (TG),
• estimation of Gate delays, Power dissipation
and Transistor sizing.
SYLLABUS : PART 3
• Basic physical design of simple Gates and Layout
issues.
• Layout issues for CMOS inverter,
• Layout for NAND, NOR and Complex Logic gates,
• Layout of TG,
• Layout optimization using Eular path.
• DRC rules for layout and issues of interconnects,
Latch up problem
Inverter Operation
Resistive Load Inverter
Resistive Load Inverter
• A simple inverter circuit can be constructed
using a transistor with source connected to
ground and a load resistor of connected from
the drain to the positive supply rail VDD·
• The output is taken from the drain and the
input applied between gate and ground .
• But, during the fabrication resistors are not
conveniently produced on the silicon substrate
and even small values of resistors occupy
excessively large areas .
• Hence some other form of load resistance is
used.
• A more convenient way to solve this problem
is to use a depletion mode transistor as the
load,
NMOS Inverter
NMOS Inverter
The salient features of the n-MOS inverter are :
• For the depletion mode transistor, the gate is
connected to the source so it is always on .
• In this configuration the depletion mode device is
called the pull-up (P.U) and the enhancement
mode device the pull-down (P.D) transistor.
• With no current drawn from the output, the
currents Ids for both transistors must be equal.
NMOS Inverter transfer characteristic
• The transfer characteristic is drawn by taking Vds on
x-axis and Ids on Y-axis for both enhancement and
depletion mode transistors.
• So,to obtain the inverter transfer characteristic for
Vgs = 0 depletion mode characteristic curve is
superimposed on the family of curves for the
enhancement mode device and from the graph it can
be seen that , maximum voltage across the
enhancement mode device corresponds to minimum
voltage across the depletion mode transistor.
• From the graph it is clear that as Vin(=Vgs p.d.
transistor) exceeds the Pulldown threshold
voltage current begins to flow.
• The output voltage Vout thus decreases and
the subsequent increases in Vin will cause the
Pull down transistor to come out of saturation
and become resistive.
CMOS INVETER
CMOS INVETER
• A CMOS inverter contains a PMOS and a
NMOS transistor connected at the drain and
gate terminals,
• a supply voltage VDD at the PMOS source
terminal, and a ground connected at the
NMOS source terminal,
• were VIN is connected to the gate terminals
and VOUT is connected to the drain terminals.
( given in diagram).
CMOS INVETER
In the inverter circuit :
• if the input is high the lower n-MOS device
closes to discharge the capacitive load .
• if the input is low, the top p-MOS device is
turned on to charge the capacitive load.
• At no time both the devices are on ,which
prevents the DC current flowing from positive
power supply to ground.
CMOS INVETER
• Qualitatively this circuit acts like the switching
circuit, since the p-channel transistor has
exactly the opposite characteristics of the n-
channel transistor.
• In the transition region both transistors are
saturated and the circuit operates with a large
voltage gain.
• The C-MOS transfer characteristic is shown in
the below graph.
CMOS INVETER
CMOS INVETER
CMOS INVETER
in region 1 for which Vi = logic 0, we have the p-
transistor fully turned on while the n-
transistor is fully turned off.
Thus no current flows through the inverter and
the output is directly connected to VDD
through the p-transistor.
• Hence the output voltage is logic 1 .
CMOS INVETER
• In region 2 the input voltage has increased to
a level which just exceeds the threshold
voltage of the n-transistor.
• The n-transistor conducts and has a large
voltage between source and drain; so it is in
saturation.
• The p-transistor is also conducting but with
only a small voltage across it, it operates in the
unsaturated resistive region
• A small current now flows through the
inverter from VDD to VSS.
• If we wish to analyze the behavior in this
region, we equate the p-device resistive region
current with the n-device saturation current
and thus obtain the voltage and current
relationships.
CMOS INVETER
• Region 4 is similar to region 2 but with the
roles of the p- and n-transistors reversed.
• However, the current magnitudes in regions 2
and 4 are small and most of the energy
consumed in switching from one state to the
other is due to the larger current which flows
in region 3.
CMOS INVETER
• Region 3 is the region in which the inverter
exhibits gain and in which both transistors are
in saturation.
• The currents in each device must be the
same ,since the transistors are in series.
• So,we can write that
CMOS INVETER
CMOS INVETER
• Since both transistors are in saturation, they
act as current sources so that the equivalent
circuit in this region is two current sources in
series between VDD and Vss with the output
voltage coming from their common point.
• The region is inherently unstable in
consequence and the changeover from one
logic level to the other is rapid.
CMOS INVETER
Inverter‘s Operations
Inverter DC Characteristics
• The characteristic
shows that when input
is zero output will high
and vice versa.
• Five regions namely

region A, B, C, D & E.
CMOS Inverter VTC: Device Operation
Region A
• The output in this region is high because the P

device is OFF and n device is ON.
• In region A, NMOS is cutoff region and PMOS
is on, therefore output is logic high.
Region B
Region B
Region C
• Both N and P transistors are in saturation
region.
Region C
Region D
Region E
Region E
Noise Margin
PART :2
• Combinational Logic,
• NAND Gate,
• NOR gate,
• XOR gate,
• Compound Gates,
• 2 input CMOS Multiplexer,
• Memory latches and registers,
• Transmission Gate (TG),
• Estimation of Gate delays, Power dissipation and
Transistor sizing.
PART :3
• Basic physical design of simple Gates and Layout
issues.
• Layout issues for CMOS inverter,
• Layout for NAND, NOR and Complex Logic
gates,
• Layout of TG,
• Layout optimization using Eular path.
• DRC rules for layout and issues of
interconnects, Latch up problem

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UNIT 3

• Five regions namely

• The output in this region is high because the P

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