19EC6PCMSD Mixed Signal Design

Question Bank
April – July 2022

Unit I
1. Discuss the impact of channel length modulation and body effect on MOSFET. [Aug’19] 05

2. Find the value of aspect ratio for an NMOS device having intrinsic gain of 73.27 and drain current
0.5 mA, λn = 0.1, µn Cox = 1.3422 × 10−4 A/V2 . [Jun’17] 04

3. Obtain the small-signal voltage gain of a common source stage with resistive load with channel
length modulation taken into account. Also draw the small-signal equivalent model. [May’17] 10

4. Illustrate the working of common source amplifier with resistive load. [Aug’18] 05

5. For the circuit shown in the Figure 1, if (W/L) = 50/0.5, RD = 2 kΩ, λ = 0 and
µn Cox = 1.34225 × 10−4 A/V2 , Vth = 0.7 V, VDD = 3 V.
(a) What is the small signal gain if M1 is in saturation and ID = 1 mA?
(b) What input voltage places M1 at the edge of triode region? What is the small-signal gain under
this condition? [Jul’19] 08

6. For a Common Source stage with a diode connected NMOS load, calculate the small signal gain
if (W/L)1 = 50/0.5, (W/L)2 = 10/0.5, ID1 = ID2 = 0.5 mA, η = 0.3. What is the gain if M2 is
implemented as diode connected PMOS device, if µn = 4µp ? [Jun’17, Jul’19] 06

7. Derive an expression for voltage gain of common source amplifier with diode connected load.
Justify how output varies linearly with the help of input-output characteristics. [Jun’18] 08

8. Find the small signal voltage gain of the circuit shown in Figure 2 assuming all transistors are in
saturation and neglecting channel length modulation, given:
NMOS (M1 ): ID1 = 100 µA, W1 = 100 µm, L1 = 1 µm, µn Cox = 130 µA/V2 .
PMOS (M2 ): W2 = 200 µm, L2 = 1 µm, µp Cox = 65 µA/V2 . 05

VDD VDD VDD

M2 60 µA VB M2
RD
vout
vout vout
vin M1 vin M1 vin M1

Figure 1: Question 5 Figure 2: Question 8 Figure 3: Question 10

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 9. Illustrate that input output characteristics is relatively linear for a common source stage with diode-
connected load. [May’19] 10

10. Analyze the circuit shown in Figure 3 to evaluate small signal gain, assuming VDD = 3 V,
(W/L)1 = 50/0.5, (W/L)2 = 50/2, ID1 = ID2 = 0.5 mA when both devices are in satura-
tion if λn = 0.1 and λp = 0.2, if µn Cox = 1.3422 × 10−4 A/V2 , µp Cox = 3.835 × 10−5 A/V2 .
[Jun’17, Jul’19] 05, 06

11. Compare different amplifier configurations in terms of their voltage gain and Rout . If the circuits is
used as a buffer, which configuration is preferred and why? Use necessary diagrams and equations.
[Jul’17] 10

12. Illustrate the working of common source amplifier with source degeneration considering the effect
of channel length modulation and body effect along with small-signal equivalent model.
[Jun’18] 10

13. Analyze the nonlinearity and the voltage headroom limitation of a source follower. [Aug’18] 10

14. A source follower using NMOS current source shown in Figure 4, which operates as a level shifter
is designed to increase the output level by 1 V than the input level. Calculate the sizes of both the
transistors if ID1 = ID2 = 0.5 mA; VGS2 − VGS1 = 0.5 V, µn Cox = 100 µA/V2 , VT H = 0.7 V,
λ = γ = 0. [Jul’17] 10

15. Analyze the given circuit in Figure 5 to obtain Vout if (W/L)1 = 20/0.5, ID = 200 µA,
Vth = 0.6 V, µn Cox = 50 µA/V2 and Vin = 1.2 V. [Aug’18] 05

16. Calculate the small-signal voltage gain of the circuit shown in Figure 6.
Assume gm1 = gm2 = 1 mA/V, η = 0.2, RD = 10 kΩ and ro1 = ro2 = 20 kΩ. [May’17] 10

VDD

RD
VDD VDD
vout
VB M2 vin M1 VB M2
vout
vout
vin M1 vin M1

Figure 4: Question 14 Figure 5: Question 15 Figure 6: Question 16

17. Demonstrate that the Common-Source Common-Gate cascode amplifier has:

(i) superior gain compared to a common-source amplifier for same voltage swing
(ii) smaller difference in drain currents due to a difference in drain voltages than without the
stacking transistor (shielding property) 08

Unit II
18. Perform the qualitative analysis of a differential pair circuit with the aid of input output character-
istics plots. Illustrate that small-signal gain is maximum for equal inputs. [May’19] 10

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 19. Perform the quantitative analysis of a differential pair circuit and calculate the differential output
current. Indicate the variations of drain currents and the overall trans-conductance of differential
pair versus input voltage. [Jun’17, Aug’18, Jul’19] 10

20. For the differential amplifier circuit with resistive loads, derive an expression for ID1 − ID2 in
terms of VG1 − VG2 . Calculate the short circuit transconductance for VG1 − VG2 = 0. [May’17] 10

21. Discuss the common mode response and common mode gain of a differential amplifier with sim-
plified circuit assuming circuit is symmetric but current source has finite output impedance.
[Jun’18] 06

22. For the differential amplifier with resistor RSS , current through the resistor is 1 mA,
(W/L)1,2 = 25/0.5, µn Cox = 50 µA/V2 , VT H = 0.6 V, λ = γ = 0 and VDD = 3 V. (Figure 7)
(a) If the voltage across RSS is 0.5 V, what is the applied input common mode voltage?
(b) Calculate RD for a differential gain of 5. [Jul’17] 05

23. A differential amplifier shown in Figure 7 uses resistor than current source to define tail current of
1 mA. Assume (W/L)1,2 = 25/0.5, µn Cox = 50 µA/V2 , VT H = 0.6 V, λ = γ = 0 and VDD = 3 V.
(a) What is the required input CM for which RSS sustains 0.5 V?
(b) Calculate RD for a differential gain of 5.
(c) What happens at the output if the input CM level is 50 mV higher than the value calculated in
(a)? [Jun’18] 10

24. With appropriate analyses, demonstrate when a change (one condition in each case) in the input
common-mode level of a differential pair leads to a
(a) change in the output common-mode voltage
(b) change in the output differential voltage

25. Justify the need for current mirrors in integrated circuit design. Consider the circuit in the Figure 8
with RL = 10 kΩ, VDD = 1.8 V and
NMOS (M1 ): ID1 = 100 µA, (W/L)1 = 50 µm/1 µm, µn Cox = 120 µA/V2 .
PMOS (M2 ): (W/L)2 = 100 µm/1 µm, µp Cox = 60 µA/V2 .
PMOS (M3 ): (W/L)3 = 100 µm/1 µm, µp Cox = 60 µA/V2 .
Neglecting channel length modulation, determine
(i) the output DC (or average) voltage
(ii) the small-signal voltage gain

VDD
VDD

RD RD IREF
VDD
vout1 vout2
M2 M3 N
vin1 M1 M2 vin2 M0 +
P vout X
vin VGS0 + VX
RSS M1 RL M1
-

Figure 7: Questions 21, 22 and 23 Figure 8: Question 25 Figure 9: Question 26

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 (iii) the limits on the input and output voltages; given threshold voltage, VT = 0.5 V and the
minimum drain-to-source voltage to keep the transistor in saturation as 0.2 V. 10

26. Modify the mirror circuit shown in Figure 9 to generate cascode bias potential and construct a
Cascode current mirror. Analyze the cascode mirror circuit to illustrate that one of the threshold
voltage is wasted for voltage headroom. [Jun’17, May’19, Jul’19] 10

27. What is the need for a cascode current mirror in an analog circuit? Show how biasing can be
obtained. [Jul’17] 05

28. For the circuit shown in the Figure 10, if IREF requires 0.5 V to operate as current source, calculate
the maximum value of IREF . [Jun’17, Jun’18, May’19] 05, 06, 05

29. In the circuit of Figure 11, assume ISS = 1 mA and W/L = 50/0.5 for all of the transistors.
(a) Determine the voltage gain, assuming µn Cox = 350 µA/V 2 , µp Cox = 100 µA/V2 .
(b) Calculate Vb such that ID5 = ID6 = 0.8 (ISS /2) and µp Cox = 38.3 µA/V2 and VT HP = 0.8 V.
(c) If ISS requires a minimum voltage of 0.4 V, what is the maximum differential output swing?
[May’17] 10

VDD
VDD
VB M5 M3 M4 M6 VB
IREF
0.8 (ISS /2) Vout 0.8 (ISS /2)
Iout
N M1 M2
M0 M3
Vin
X Y
M1 M2 ISS

Figure 10: Question 28 Figure 11: Question 28

Unit III
30. Perform the large signal analysis of a differential pair with current mirror load. Also work out the
limits on input and output voltage swings. 10

31. With the help of neat circuit diagram and appropriate analyses, obtain the small-signal gain of a
differential pair with current mirror load in differential and common-mode. 10

32. In the circuit shown in Figure 12, given IBIAS = 100 µA, (W/L)1−4 = 100/1, VT = 0.7 V,
µn Cox = 92 µA/V2 and λn = λp = 0.05/V, find the small-signal differential voltage gain. 05

33. Consider the differential amplifier circuit of Figure 12, IBias = 200 µA and all transistors have
W/L =(100 µm/1.6 µm). Given that µn Cox = 92 µA/V2 , Vth = 0.8 V, and
rds = 8000 × L(µm)/ID (mA). Find the gain from the differential input to the output. [Jul’17] 10

34. Explain and bring out the importance of the following performance parameters of op-amp:

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 VDD

M3 M4
vout

M1 M2
vin

IBIAS

Figure 12: Questions 32 and 33

(a) Gain (c) Noise and offset (e) Small signal bandwidth
(b) Output swing (d) Linearity [Jun’18] 10

35. Describe op-amp design parameters and also mention their importance.
[Jun’17, Aug,18, May’19] 10

36. The circuit shown in Figure 13 is designed for a nominal gain of 10, i.e., 1 + R1 /R2 = 10.
Determine the minimum value of A1 for a gain error of 1%.

37. In the circuit of Figure 14, assume the Op-Amp is a single pole voltage amplifier. If Vin is a small
step, calculate the time required for the output voltage to reach within 1% of its final value. What
unity-gain bandwidth must the Op-Amp provide if 1 + R1 /R2 ≈ 10 and the settling time is to be
less than 5 ns? For simplicity, assume that the low-frequency gain is much greater than unity.

Figure 13: Question 36 Figure 14: Question 37

38. Calculate the input common-mode voltage range and the closed loop output impedance of the
unity gain buffer shown below in Figure 15, given: threshold voltage of each device 0.7 V and
overdrive voltage 0.3 V. Comment on the result. [Jun’17, Aug’18] 10

39. Consider the amplifier of Figure 16 with (W/L)1−4 = 50/0.5, ISS = 1 mA, VDD = 3 V,
L = 0.5 µm and input common-mode level of 1.3 V. Determine the small signal gain and dif-
ferential output swing if all transistors remain in saturation. Assume γ = 0, µn Cox = 75 µA/V2 ,
µp Cox = 30 µA/V2 , λn = 0.1 V−1 , λp = 0.2 V−1 and VT Hn = |VT Hp | = 0.7 V. [May’17] 05

40. For the circuit shown in Figure 17, explain in which region each transistor operates as Vin varies
from below Vb − VT H4 to above Vb − VGS4 + VT H2 . [Jun’18] 05

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 Figure 15: Question 38 Figure 16: Question 39

Figure 17: Question 40 Figure 18: Question 41

41. Design a folded cascode op-amp with an NMOS input pair shown in Figure 18 to satisfy the follow-
ing specifications: VDD = 3 V, differential output swing = 3 V, power dissipation = 10 mW, volt-
age gain = 2000. Assume µn Cox = 60 µA/v2 , µp Cox = 30 µA/ v2 , λn = 0.1 V−1 , λp = 0.1 V−1
(for an effective channel length of 0.5 µm), γ = 0, Vthn = |Vthp | = 0.7 V. [Aug’18] 10

42. Design a folded cascade op-amp with a PMOS input pair to satisfy the following specifications:
VDD = 3 V, Maximum differential swing= 2.4 V, total power dissipation= 6 mW, minimum volt-
age gain= 200. Assume µn Cox = 60 µA/V2 , µp Cox = 30 µA/V2 , λn = 0.1 V−1 , λp = 0.2 V−1 ,
γ = 0, VT Hn = |VT Hp | = 0.7 V, VISS = 0.3 V and VOV for input pair is 0.53V. [May’17] 10

43. Identify the type of amplifier in Figure 19, employed in boosting the gain. Also calculate the
output impedance at the drain of transistor M3 . (Replace ideal current sources with transistors for
the calculation). Assume gmn = 1 mA/V, gmp = 2 mA/V and ron = 5 kΩ, rop = 10 kΩ.
[May’17] 05

44. Justify how two stage op-amp can overcome the gain and output swing limitation encountered by
cascode op-amp. [Jun’17, May’19] 10

45. Highlight the drawbacks of a single-stage op-amp and show the implementation which can over-
come the same. [Aug’18] 10

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 Figure 19: Question 43

46. Explain the construction and working of two stage op-amp circuit. [Jul’17, May’19] 10

47. Explain in brief about simple implementation of two stage op-amp and two stage op-amp employ-
ing cascoding. [Jun’18] 10

48. Design a 2 stage op-amp of Figure 20 for the following requirements: maximum differential
swing = 4 V, total power dissipation = 6 mW, ISS = 0.5 mA, VOD5 = 0.6 V, VDD = 3 V,
L = 0.5 µm, VOD7 = 0.4 V. Assume γ = 0, µn Cox = 75 µA/V2 , µp Cox = 30 µA/V2 ,
λn = 0.1 V−1 , λp = 0.2 V−1 and VT Hn = |VT Hp | = 0.7 V. [May’17] 10

Figure 20: Question 48

49. It is required to boost the output impedance of a differential cascade stage. Suggest a suitable
circuit and illustrate how output impedance can be boosted substantially with appropriate descrip-
tion. [Jun’17, Jun’18, May’19] 10

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 Unit IV
50. Demonstrate that a switched-capacitor can lead to the realization of a large resistance on-chip.
Also highlight the limitations of such a realization. 07

51. Discuss the limitations of using a single NMOS and PMOS transistor as a sampling switch and
how a transmission gate improves the performance. 06

52. Briefly discuss any two phenomena that affect the precision of sampled analog voltages. 06

53. With the help of a neat circuit diagram, explain the operation of a fully differential amplifier built
using switched capacitors. 08

54. Demonstrate the realization of a non-inverting amplifier using switched capacitors. 06

55. With the help of neat circuit diagrams, demonstrate the operation of a multiply-by-two circuit in
sampling mode and amplification mode. 07

56. Design an integator using switched capacitor circuits. 06

57. What is the need for common-mode feedback in fully differential amplifiers? Demonstrate how
switched capacitors can be employed for it. 08

58. In the circuit shown in Figure 21, Cin = 0.5 pF and CH = 2 pF. What is the minimum op amp
gain that guarantees a maximum gain error of 0.1%? 05

Figure 21: Question 58

Unit V
59. Describe any two specifications of DAC. [Jul’17] 06

60. A DAC has a full-scale voltage of 4.97 V using a 5 V reference and its minimum output voltage is
limited by the value of one LSB. Determine the resolution and dynamic range of the converter.
[May’17, Jul’17] 04

61. A digitally programmable signal generator used a 14-bit DAC with a 10 V reference voltage to
generate a DC output voltage. What is the smallest incremental change at the output that can
occur? Determine DAC’s full scale value and accuracy. [Jun’17] 06

62. Determine the maximum DNL (in LSBs) for a 3-bit DAC, which has the following characteristics.
Does the DAC have 3-bit accuracy? If not, what is the resolution of the DAC having this charac-
teristic? [Jun’18] 06

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 Digital Input Voltage Output (V)
000 0
001 0.625
010 1.5625
011 2.0
100 2.5
101 3.125
110 3.4375
111 4.275

Figure 22: Question 63 Figure 23: Question 64

63. Determine the INL and DNL for a DAC that has a transfer curve shown in Figure 22. [May’17] 08
64. Identify different errors in the transfer curve given in Figure 23. Calculate DNL for each digital
code and maximum resolution of the converter. [Aug’18] 05
65. Define the following terms: [May’17] 04
(a) Offset (c) Latency
(b) Gain error (d) Signal-to-Noise Ratio (SNR)

66. Discuss mixed signal layout issues. [Jun’17, May’19] 10

67. Discuss mixed signal layout issues at system, device and interconnect levels. [Jun’18] 10
68. Find maximum INL and DNL for a 3-bit R-2R DAC if R = 1.1 kΩ and 2R = 2 kΩ. Assume
VREF = 5 V. [Jun’17] 10
69. Plot the transfer curve of a 3-bit R-2R DAC if R = 1.1 kΩ and 2R = 2 kΩ by making a table
of the actual output voltage for each input combinations. Label the node voltage for each input
combination, given VREF = 5 V. If the switches are ideal, what is the maximum INL and DNL of
the converter? [Jul’17] 10
70. In a 3-bit R-2R DAC, if R = 1.1 kΩ and 2R = RF = 2 kΩ, determine the maximum INL and
DNL for the converter. (Assume ideal case to be R = 1 kΩ.) Assume all the switches to be ideal
and VREF = 5 V. [Aug’18] 15

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71. Design a 3-bit generic current-steering DAC. Assume that each current source I is 5 µA. Find the
total output current for each input code. [Jun’18] 04

72. Explain the construction and working of charge-scaling DACs. [May’19] 10

73. Assume that an 8-bit pipeline ADC was fabricated and that all the amplifiers had a gain of 2.1 V/V
instead of 2 V/V. If VIN = 3 V and VREF = 5 V, what would be the resulting digital output if
the remaining components were considered to be ideal? What are the DNL for this converter for
digital outputs ranging from 0 to 4 V? [Jun’18] 08

74. Explain the working of a single slope integrating ADC with the help of block diagram and discuss
the accuracy issues related to the same. [Jun’18] 08

75. An 8-bit single-slope ADC with a 5 V reference is used to convert a slow-moving analog signal.
What is the maximum conversion time assuming that the clock frequency is 1 MHz? What is the
maximum frequency of the analog signal? What is the maximum value of the analog signal which
can be converted? [Jun’17, Aug’18] 10, 06

76. Explain the principle of successive approximation. Assume that Vin = 2.49 V, VREF = 5 V and
4-bit for the successive approximation ADC and that the comparator, because of its offset, makes
the wrong decision for the MSB conversion. What will be the final digital output? [Aug’18] 10

77. With the help of a neat block diagram, briefly describe the concept of noise shaping in oversam-
pling ADCs. 10

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