Department of Electronics and Communication Engineering

Introduction to VerilogHDL
Hardware description languages such as Verilog differ from software programming
languages because they include ways of describing the propagation of time and signal
dependencies (sensitivity). There are two assignment operators, a blocking assignment (=),
and a non-blocking (<=) assignment. The non-blocking assignment allows designers to
describe a state-machine update without needing to declare and use temporary storage
variables. Since these concepts are part of Verilog's language semantics, designers could
quickly write descriptions of large circuits in a relatively compact and concise form. At the
time of Verilog's introduction (1984), Verilog represented a tremendous productivity
improvement for circuit designers who were already using graphical schematic capture
software and specially written software programs to document and simulate electronic
circuits.

The designers of Verilog wanted a language with syntax similar to the C programming
language, which was already widely used in engineering software development. Like C,
Verilog is case-sensitive and has a basic preprocessor (though less sophisticated than that
of ANSI C/C++). Its control flow keywords (if/else, for, while, case, etc.) are equivalent,
and its operator precedence is compatible. Syntactic differences include variable declaration
(Verilog requires bit-widths on net/reg types demarcation of procedural blocks (begin/end
instead of curly braces {}), and many other minor differences.

A Verilog design consists of a hierarchy of modules. Modules encapsulate design

hierarchy, and communicate with other modules through a set of declared input, output,
and bidirectional ports. Internally, a module can contain any combination of the following:
net/variable declarations (wire, reg, integer, etc.), concurrent and sequential statement
blocks, and instances of other modules (sub-hierarchies). Sequential statements are placed
inside a begin/end block and executed in sequential order within the block. However, the
blocks themselves are executed concurrently, making Verilog a dataflow language.

Verilog's concept of 'wire' consists of both signal values (4-state: "1, 0, floating,
undefined") and strengths (strong, weak, etc.). This system allows abstract modeling of
shared signal lines, where multiple sources drive a common net. When a wire has multiple
drivers, the wire's (readable) value is resolved by a function of the source drivers and their
strengths.

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A subset of statements in the Verilog language are synthesizable. Verilog modules that
conform to a synthesizable coding style, known as RTL (register-transfer level), can be
physically realized by synthesis software. Synthesis software algorithmically transforms the
(abstract) Verilog source into a netlist, a logically equivalent description consisting only of
elementary logic primitives (AND, OR, NOT, flip-flops, etc.) that are available in a specific
FPGA or VLSI technology. Further manipulations to the netlist ultimately lead to a circuit
fabrication blueprint (such as a photo mask set for an ASIC or a bitstream file for an FPGA).

History

Verilog was the first modern hardware description language to be invented. It was
created by Phil Moorby and Prabhu Goel during the winter of 1983/1984. The wording for
this process was "Automated Integrated Design Systems" (later renamed to Gateway
Design Automation in 1985) as a hardware modeling language. Gateway Design Automation
was purchased by Cadence Design Systems in 1990. Cadence now has full proprietary rights
to Gateway's Verilog and the Verilog-XL, the HDL-simulator that would become the de-facto
standard (of Verilog logic simulators) for the next decade. Originally, Verilog was intended
to describe and allow simulation; only afterwards was support for synthesis added.

Verilog-95

With the increasing success of VHDL at the time, Cadence decided to make the
language available for open standardization. Cadence transferred Verilog into the public
domain under the Open Verilog International (OVI) (now known as Accellera) organization.
Verilog was later submitted to IEEE and became IEEE Standard 1364-1995, commonly
referred to as Verilog-95.

In the same time frame Cadence initiated the creation of Verilog-A to put standards
support behind its analog simulator Spectre. Verilog-A was never intended to be a
standalone language and is a subset of Verilog-AMS which encompassed Verilog-95.

Verilog 2001

Extensions to Verilog-95 were submitted back to IEEE to cover the deficiencies that
users had found in the original Verilog standard. These extensions became IEEE Standard
1364-2001 known as Verilog-2001.

Verilog-2001 is a significant upgrade from Verilog-95. First, it adds explicit support for
(2's complement) signed nets and variables. Previously, code authors had to perform signed

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operations using awkward bit-level manipulations (for example, the carry-out bit of a simple
8-bit addition required an explicit description of the Boolean algebra to determine its correct
value). The same function under Verilog-2001 can be more succinctly described by one of
the built-in operators: +, -, /, *, >>>. A generate/endgenerate construct (similar to VHDL's
generate/endgenerate) allows Verilog-2001 to control instance and statement instantiation
through normal decision operators (case/if/else). Using generate/endgenerate, Verilog-2001
can instantiate an array of instances, with control over the connectivity of the individual
instances. File I/O has been improved by several new system tasks. And finally, a few
syntax additions were introduced to improve code readability (e.g. always @*, named
parameter override, C-style function/task/module header declaration).

Verilog-2001 is the dominant flavor of Verilog supported by the majority of commercial

EDA software packages.

Verilog 2005

Not to be confused with SystemVerilog, Verilog 2005 (IEEE Standard 1364-2005)

consists of minor corrections, spec clarifications, and a few new language features (such as
the uwire keyword).

A separate part of the Verilog standard, Verilog-AMS, attempts to integrate analog and
mixed signal modeling with traditional Verilog.

SystemVerilog

SystemVerilog is a superset of Verilog-2005, with many new features and capabilities to

aid design verification and design modeling. As of 2009, the System Verilog and Verilog
language standards were merged into System Verilog 2009 (IEEE Standard 1800-2009).

The advent of hardware verification languages such as OpenVera, and Verisity's e

language encouraged the development of Superlog by Co-Design Automation Inc. Co-
Design Automation Inc was later purchased by Synopsys. The foundations of Superlog and
Vera were donated to Accellera, which later became the IEEE standard P1800-2005: System
Verilog.

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Steps Involved In Simulation Using Xilinx

 Starting the ISE Software:

To start ISE, double-click the desktop icon,

 Create a New Project

Create a new ISE project which will target the FPGA device on the Spartan-3 Startup Kit
demo board.

 To create a new project:

1. Select File > New Project... The New Project Wizard appears.

2. Type tutorial in the Project Name field.

3. Enter or browse to a location (directory path) for the new project. A tutorial

Sub directory is created automatically.

4. Verify that HDL is selected from the Top-Level Source Type list.

5. Click Next to move to the device properties page.

6. Fill in the properties in the table as shown below:

 Product Category: All

 Family: Spartan3E
 Device: XC3S100E
 Package: CP132
 Speed Grade: -4
 Top-Level Module Type: HDL
 Synthesis Tool: XST (VHDL/Verilog)
 Simulator: ISE Simulator (VHDL/Verilog)
 Verify that Enable Enhanced Design Summary is selected.

Leave the default values in the remaining fields. When the table is complete, the project
properties will look like the following:

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7. Click Next to proceed to the Create New Source window in the New Project Wizard.
At the end of the next section, new project will be complete.

 Create an HDL Source

In this section, create the top-level HDL file for your design. Determine the language to
use for the tutorial. Then, continue either to the “Creating a VHDL Source” section below, or
skip to the “Creating a Verilog Source” section.

 Creating a VerilogHDL Source

Create a VerilogHDL source file for the project as follows:

1. Click the New Source button in the New Project Wizard.

2. Select Verilog Module as the source type.

3. Type in the file name counter.

4. Verify that the Add to project checkbox is selected.

5. Click Next.

6. Declare the ports for the counter design by filling in the port information as shown
below:

7. Click Next, then Finish in the New Source Information dialog box complete the new
source file template

8. Click Next, then Next, then Finish.

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7. Click Next, then Finish in the New Source Information dialog box to complete the
new source file template.

8. Click Next, then Next, then Finish.

The source file containing the entity/architecture pair displays in the Workspace, and
the counter displays in the Sources tab, as shown below:

 Checking the Syntax

When the source files are complete, check the syntax of the design to find errors and
typos.

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1. Verify that Synthesis/Implementation is selected from the drop-down list in the

Sources window.

2. Select the counter design source in the Sources window to display the related
processes in the Processes window.

3. Click the “+” next to the Synthesize-XST process to expand the process group.

4. Double-click the Check Syntax process.

5. Close the HDL file.

 Design Simulation
 Verifying Functionality using Behavioral Simulation
 Create a test bench waveform containing input stimulus you can use to verify the
functionality of the counter module. The test bench waveform is a graphical view of a
test bench.
 Create the test bench waveform as follows:

1. Select the counter HDL file in the Sources window.

2. Create a new test bench source by selecting Project → New Source.

3. In the New Source Wizard, select verilog text fixture as the source type, and type

counter_tbw in the File Name field.

4. Click Next.

5. The Associated Source page shows that you are associating the test bench waveform

with the source file counter. Click Next.

6. The Summary page shows that the source will be added to the project, and it displays

the source directory, type and name. Click Finish.

7. You need to set the clock frequency, setup time and output delay times in the Initialize

Timing dialog box before the test bench waveform editing window opens.

8. In the Sources window, select the Behavioral Simulation view to see that the test bench
waveform file is automatically added to your project.

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12. Close the test bench waveform.

 This shows the project window. You can find the file names in Source in project window.
You can also see the processes like Synthesize, Implement design, Generate
programming file. Select appropriate process, click right mouse button and select “run”
from pop down menu.

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Expt-1

HDL Code to Realize all the Logic Gates

AIM:-To realize all the logic gates using Verilog HDL.
To simulate and synthesize the code.
TOOL:-Xilinx ISE 13.2i Version
FAMILY SPARTAN 3E
Device 3S100E
Package CP132
Speed -4
Synthesis XST(VERILOG/VHDL)
Simulator ISE Simulator
1. AND GATE:
Logic gate symbol: Truth Table:

A B Y1
0 0 0
0 1 0
1 0 0
1 1 1

2. OR GATE:
Logic gate symbol: Truth Table:

A B Y2
0 0 0
0 1 1
1 0 1
1 1 1

3. NOT GATE:
Logic gate symbol: Truth Table:

A Y3
0 1
1 0

4. NAND GATE:

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Logic gate symbol: Truth Table:

A B Y4
0 0 1
0 1 1
1 0 1
1 1 0

5. NOR GATE:
Logic gate symbol: Truth Table:

A B Y5
0 0 1
0 1 0
1 0 0
1 1 0

6. EX-OR GATE:
Logic gate symbol: Truth Table:

A B Y6
0 0 0
0 1 1
1 0 1
1 1 0

7. EX-NOR GATE:
Logic gate symbol: Truth Table:

A B Y7
0 0 1
0 1 0
1 0 0
1 1 1

Source Code:
module logicgates(Y1,Y2,Y3,Y4,Y5,Y6,Y7,A,B);
input A,B;

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output Y1,Y2,Y3,Y4,Y5,Y6,Y7;
assign Y1=A & B;
assign Y2=A | B;
assign Y3= ~A;
assign Y4=~(A & B);
assign Y5=~(A | B);
assign Y6=A ^ B;
assign Y7=~(A ^ B);
endmodule
Testbench:-
module logicgates_tb_v;
reg A,B;
wire Y1,Y2,Y3,Y4,Y5,Y6,Y7;
logicgates uut (.Y1(Y1),.Y2(Y2),.Y3(Y3),.Y4(Y4),.Y5(Y5),.Y6(Y6),.Y7(Y7),.A(A),.B(B));
initial begin
A = 0; B = 0;
#100; A = 0; B = 1;
#100; A = 1; B = 0;
#100; A = 1; B = 1;
#100;
end
endmodule
Simulated Waveform:

RTL Schematic:

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Synthesis Report:
=====================================================
* Final Report *
=====================================================
Final Results
RTL Top Level Output File Name : logicgates.ngr
Top Level Output File Name : logicgates
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs :9
Cell Usage :
# BELS :7
# INV :1
# LUT2 :6
# IO Buffers :9
# IBUF :2
# OBUF :7
================================================
Timing Report:

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Device utilization report:

Technology Schematic:

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Result: The Logic Gates were designed using Verilog HDL & implemented in FPGA Spartan 3
kit.

Expt-2

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Design of 2 to 4 Decoder
AIM:-To Design & Implement 3X8 DECODER program using Verilog HDL.

TOOL:-Xilinx ISE 9.2i Version

FAMILY SPARTAN 3E
Device 3S100E
Package CP132
Speed -4
Synthesis XST(VERILOG/VHDL)
Simulator ISE Simulator

Architecture:-

Truth Table:
INPUTS OUTPUTS
X0 X1 En Y3 Y2 Y1 Y0
0 0 0 0 0 0 0
0 0 1 0 0 0 1
0 1 1 0 0 1 0
1 0 1 0 1 0 0
1 1 1 1 0 0 0

Source Code:-

module decoder24(o,a,en);
input [1:0]a;
input en;
output [3:0] o;
reg [3:0] o;
always @ (a,en)
begin
if(en==1'b1)

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case(a)
2'b00 : o=4'b0001;
2'b01 : o=4'b0010;
2'b10 : o=4'b0100;
2'b11 : o=4'b1000;
endcase
else
o=4'b0000;
end
endmodule
Testbench:-

module decoder24tb();
reg [2:0] a;
reg en;
wire [7:0] o;
decoder38 d1 (o,a,en);
initial begin
a=2'b00;
en=1'b1;
end
always #20 a[1]=~a[1];
always #10 a[0]=~a[0];
always #40 en=~en;
initial #160 $stop;
endmodule

Simulated Waveform:-

RTL Schemantic:-

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Synthesis Report:-

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Timing Report:-

Device Utilization Summary:-

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Technology Schematic:-

Result:-

The 3X8 Decoder was designed using Verilog HDL & implemented in FPGA Spartan 3 kit.

Expt-3.1

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Design of 8 to 3 encoder without priority

Aim:- To Design & Implement 8X3 ENCODER program using Verilog HDL.
Tool:-Xilinx ISE 9.2i Version

FAMILY SPARTAN 3E
Device 3S100E
Package CP132
Speed -4
Synthesis XST(VERILOG/VHDL)
Simulator ISE Simulator

Architecture:

Truth Table:

I0 I1 I2 I3 I4 I5 I6 I7 EN Y2 Y1 Y0
1 0 0 0 0 0 0 0 1 0 0 0
0 1 0 0 0 0 0 0 1 0 0 1
0 0 1 0 0 0 0 0 1 0 1 0
0 0 0 1 0 0 0 0 1 0 1 1
0 0 0 0 1 0 0 0 1 1 0 0
0 0 0 0 0 1 0 0 1 1 0 1
0 0 0 0 0 0 1 0 1 1 1 0
0 0 0 0 0 0 0 1 1 1 1 1

Source Code:-

module encoder83(o,a,en);
input [7:0] a;
input en;

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output [2:0] o;
reg [2:0] o;
always @ (a,en)
begin
if(en==1'b1)
case(a)
8'b00000001 : o=3'b000;
8'b00000010 : o=3'b001;
8'b00000100 : o=3'b010;
8'b00001000 : o=3'b011;
8'b00010000 : o=3'b100;
8'b00100000 : o=3'b101;
8'b01000000 : o=3'b110;
8'b10000000 : o=3'b111;
endcase
else
o=3'bzzz;
end
endmodule

Testbench:-

module encoder83tb;
reg [7:0] a;
reg en;
wire [2:0] o;
encoder83 e1 (o,a,en);
initial begin
a=8'b00000000;
en=1'b1;
#10 a=8'b00000001;
#10 a=8'b00000010;
#10 a=8'b00000100;
#10 a=8'b00001000;
#10 a=8'b00010000;
#10 a=8'b00100000;
#10 a=8'b01000000;
#10 a=8'b10000000;
end
always #90 en=~en;
initial #120 $stop;
endmodule

Simulated Waveform:-

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RTL Schemantic:-

Synthesis Report:-

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Timing Report:-

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Device Utilization Summary:-

Synthesis Diagram:-

Result:-

The 8X3 Encoder was designed using Verilog HDL & implemented in FPGA Spartan 3 kit.

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Expt-3.2

Design of 8 to 3 Priority encoder

Aim:- To Design & Implement 8X3 Priority ENCODER program using Verilog HDL.
Tool:-Xilinx ISE 9.2i Version

FAMILY SPARTAN 3E
Device 3S100E
Package CP132
Speed -4
Synthesis XST(VERILOG/VHDL)
Simulator ISE Simulator

Architecture:

Truth Table:

D0 D1 D2 D3 x y v

0 0 0 0 x x 0

1 0 0 0 0 0 1

x 1 0 0 0 1 1

x X 1 0 1 0 1

x X x 1 1 1 1

Source Code:-

Module priorityenc (o,v,a,en);

input [7:0] a;
input en;
output v;
output [2:0] o;
reg [2:0] o;
assign v=|a;
always @ (a,en)

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begin
if(en==1'b1)
begin
if(a[7]) o=3'b111;
else if(a[6]) o=3'b110;
else if(a[5]) o=3'b101;
else if(a[4]) o=3'b100;
else if(a[3]) o=3'b011;
else if(a[2]) o=3'b010;
else if(a[1]) o=3'b001;
else if(a[0]) o=3'b000;
else
o=3'bxxx;
end
else if(en==1'b0)
o=3'bzzz;
end
endmodule

Testbench:-
module priorityenctb();
reg [7:0] a;
reg en;
wire v;
wire [2:0] o;
priorityenc p1 (o,v,a,en);
initial begin
a=8'b00000000;
en=1'b0;
end
always #1280 a[7]=~a[7];
always #640 a[6]=~a[6];
always #320 a[5]=~a[5];
always #160 a[4]=~a[4];
always #80 a[3]=~a[3];
always #40 a[2]=~a[2];
always #20 a[1]=~a[1];
always #10 a[0]=~a[0];
always #2 en=1'b1;
always #2560 $stop;
endmodule

Simulated Waveform:-

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RTL Schemantic:-

Synthesis Report:-

Timing Report:-

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Device Utilization Summary:-

Technology Schematic:-

Result:-

The Priority encoder was designed using Verilog HDL & implanted in FPGA Spartan 3 kit.

Expt-4.1

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Design of 8 X 1 Multiplexer
Aim:- To Design & Implement 8X1 Multiplexer using Verilog HDL.
Tool:-Xilinx ISE 9.2i Version

FAMILY SPARTAN 3E
Device 3S100E
Package CP132
Speed -4
Synthesis XST(VERILOG/VHDL)
Simulator ISE Simulator

Architecture:

Truth Table:

A B C EN F

0 0 0 1 E0
0 0 1 1 E1
0 1 0 1 E2
0 1 1 1 E3
1 0 0 1 E4
1 0 1 1 E5
1 1 0 1 E6
1 1 1 1 E7
X X X 0 X
Source Code:-

module mux(y,s,in);
output y;

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input [7:0] in;

input [2:0] s;
reg y;
always @(s)
begin
if(s==3'd0) y=in[0];
else if(s==3'd1) y=in[1];
else if(s==3'd2) y=in[2];
else if(s==3'd3) y=in[3];
else if(s==3'd4) y=in[4];
else if(s==3'd5) y=in[5];
else if(s==3'd6) y=in[6];
else y=in[7];
end
endmodule

Testbench:

module tb_mux();
reg [7:0]in;
reg [2:0]s;
wire y;
mux m1(y,s,in);
initial
begin
in=8'b10110110;
s[0]=1'b0;
s[1]=1'b0;
s[2]=1'b0;
end
always #40 s[2]=~s[2];
always #20 s[1]=~s[1];
always #10 s[0]=~s[0];
initial
begin
#200 $finish;
end
endmodule

Simulated Waveform:-

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RTL Schemantic:-

Synthesis Report:-

Timing Report:-

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Device Utilization Summary:-

Synthesis Diagram:-

Result:-

The 8X1 mux using 2X1 mux was designed using Verilog HDL & implemented in FPGA
Spartan 3 kit.

Expt-4.2

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Design of 1 X 8 Demultiplexer
Aim:- To Design & Implement 1X8 Demultiplexer using Verilog HDL.
Tool:-Xilinx ISE 9.2i Version

FAMILY SPARTAN 3E
Device 3S100E
Package CP132
Speed -4
Synthesis XST(VERILOG/VHDL)
Simulator ISE Simulator

Architecture:

Truth Table:

S2 S1 S0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 1 0 0 0
1 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0

Source Code:

module demux(y0,y1,y2,y3,y4,y5,y6,y7,s,in);

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output y0,y1,y2,y3,y4,y5,y6,y7;
input [2:0]s;
input in;
reg y0,y1,y2,y3,y4,y5,y6,y7;
always @(s|in)
begin
case(s)
3'b000 : y0=in;
3'b001 : y1=in;
3'b010 : y2=in;
3'b011 : y3=in;
3'b100 : y4=in;
3'b101 : y5=in;
3'b110 : y6=in;
3'b111 : y7=in;
endcase
end
endmodule

Testbench:
module tb_demux();
reg [2:0]s;
reg in;
wire y0,y1,y2,y3,y4,y5,y6,y7;
demux d1(y0,y1,y2,y3,y4,y5,y6,y7,s,in);
initial
begin
in=1;
s=3'b000;
end
always #10 in=~in;
always #80 s[2]=~s[2];
always #40 s[1]=~s[1];
always #20 s[0]=~s[0];
initial
begin
#200 $finish;
end
endmodule

Simulation Waveform:

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RTL Schematic Diagram:

Synthesis Report:
a) Timing Report:
Timing constraint: Default OFFSET OUT AFTER for Clock 'y7_cmp_eq0000'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 7.078ns (Levels of Logic = 1)
Source: y7 (LATCH)
Destination: y7 (PAD)
Source Clock: y7_cmp_eq0000 falling

Data Path: y7 to y7
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
LD:G->Q 1 0.633 0.801 y7 (y7_OBUF)
OBUF:I->O 5.644 y7_OBUF (y7)
----------------------------------------
Total 7.078ns (6.277ns logic, 0.801ns route)
(88.7% logic, 11.3% route)
=========================================================
CPU : 7.76 / 8.07 s | Elapsed : 7.00 / 8.00 s
b) Device utilization summary:

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Selected Device : 3s50pq208-4

Number of Slices: 4 out of 768 0%
Number of Slice Flip Flops: 8 out of 1536 0%
Number of 4 input LUTs: 8 out of 1536 0%
Number of IOs: 12
Number of bonded IOBs: 12 out of 124 9%
IOB Flip Flops: 8

c) Schematic Diagram After Synthesis:

Result: The design is implemented on Spartan 3 FPGA board with Synthesis and
Simulation.

Expt-5

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Design of 4 bit Binary to Gray code converter

Aim:- To Design & Implement 4 bit binary to gray code converter using Verilog HDL.
Tool:-Xilinx ISE 9.2i Version

FAMILY SPARTAN 3E
Device 3S100E
Package CP132
Speed -4
Synthesis XST(VERILOG/VHDL)
Simulator ISE Simulator

Architecture:

Truth table:

Source Code:-

module Binary_to_Gray ( din ,dout );

output [3:0] dout ;

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input [3:0] din ;

assign dout[3] = din[3];
assign dout[2] = din[3]^din[2];
assign dout[1] = din[2]^din[1];
assign dout[0] = din[1]^din[0];
endmodule

Testbench:-

module btog_tb_v;
reg [3:0] din;
wire [3:0] dout;
Binary_to_Gray uut ( .din(din), .dout(dout));
initial begin
din = 0; #100;
end
always #80 din[3]=~din[3];
always #40 din[2]=~din[2];
always #20 din[1]=~din[1];
always #10 din[0]=~din[0];
endmodule
Simulated Waveform:-

RTL Schematic:-

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Synthesis Report:-

=======================================================*
Final Report *
=======================================================
Final Results
RTL Top Level Output File Name : Binary_to_Gray.ngr
Top Level Output File Name : Binary_to_Gray
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs :8
Cell Usage :
# BELS :3
# LUT2 :3
# IO Buffers :8
# IBUF :4
# OBUF :4
=======================================================
Timing Report:-

=======================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 7 / 4
-------------------------------------------------------------------------
Delay: 6.236ns (Levels of Logic = 3)
Source: din<2> (PAD)
Destination: dout<2> (PAD)
Data Path: din<2> to dout<2>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 1.218 0.622 din_2_IBUF (din_2_IBUF)
LUT2:I0->O 1 0.704 0.420 Mxor_dout<2>_Result1 (dout_2_OBUF)

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OBUF:I->O 3.272 dout_2_OBUF (dout<2>)

----------------------------------------
Total 6.236ns (5.194ns logic, 1.042ns route)
(83.3% logic, 16.7% route)

Device Utilization Summary:-

Device utilization summary:

---------------------------
Selected Device : 3s100ecp132-4
Number of Slices: 2 out of 960 0%
Number of 4 input LUTs: 3 out of 1920 0%
Number of IOs: 8
Number of bonded IOBs: 8 out of 83 9%

Synthesis Diagram:-

Result:-The 4-bit comparator was designed using Verilog HDL & implemented in FPGA
Spartan 3 kit.

Expt-6

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Design of 4 bit Comparator

Aim:- To Design & Implement 4 bit comparator using Verilog HDL.
Tool:-Xilinx ISE 9.2i Version

FAMILY SPARTAN 3E
Device 3S100E
Package CP132
Speed -4
Synthesis XST(VERILOG/VHDL)
Simulator ISE Simulator

Architecture:

Truth table:

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A3 A2 A1 A0 B3 B2 B1 B0 A>B(grt) A<B(lsr) A=B(eql)

0 0 0 0 0 0 1 0 0 1 0
0 0 1 0 0 0 0 0 1 0 0
0 0 0 1 0 0 1 0 0 1 0
1 0 0 0 0 1 0 0 1 0 0
1 0 0 1 1 0 0 0 1 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 1 1 0 0 0 0 1
1 1 1 0 0 0 0 1 1 0 0
1 1 1 1 1 1 1 1 0 0 1

Source Code:-

module comp4bit(eq,gr,ls,a,b);
input [3:0] a,b;
output eq,gr,ls;
assign eq = (a==b) ? 1 : 0;
assign gr = (a>b) ? 1 : 0;
assign ls = (a<b) ? 1 : 0;
endmodule

Testbench:-

module comp4bittb();
reg [3:0] a,b;
wire eq,gr,ls;
comp4bit c1 (eq,gr,ls,a,b);
initial begin
a=4'b0000;b=4'b0000;
end
always #80 a[3]=~a[3];
always #40 a[2]=~a[2];
always #20 a[1]=~a[1];
always #10 a[0]=~a[0];
always #80 b[0]=~b[0];
always #40 b[1]=~b[1];
always #20 b[2]=~b[2];
always #10 b[3]=~b[3];
initial #320 $stop;
endmodule

Simulated Waveform:-

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RTL Schematic:-

Synthesis Report:-

Timing Report:-

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Device Utilization Summary:-

Synthesis Diagram:-

Result:-The 4-bit comparator was designed using Verilog HDL & implemented in FPGA
Spartan 3 kit.

Expt-7

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Design of Full Adder using 3 modeling styles

Aim:- To Design & Implement Full adder using Verilog HDL.
Tool:-Xilinx ISE 9.2i Version

FAMILY SPARTAN 3E
Device 3S100E
Package CP132
Speed -4
Synthesis XST(VERILOG/VHDL)
Simulator ISE Simulator

Architecture:

Truth Table:

A B C_in C_out SUM

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

Source Code:-

Structural:-

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module fulladder(s,co,a,b,cin);
input a,b,cin;
output s,co;
wire t1,t2,t3;
xor x1 (t1,a,b);
xor x2 (s,t1,cin);
and x3 (t2,a,b);
and x4 (t3,t1,cin);
or x5 (co,t2,t3);
endmodule

Behavioural:
module fulladder(s,co,a,b,cin);
input a,b,cin;
output s,co;
always@(a,b,cin)
begin
assign s=(a^b^cin);
assign co=(a&b)|(b&cin)|(a&cin);
end
endmodule

Dataflow:
module fulladder(s,co,a,b,cin);
input a,b,cin;
output s,co;
assign s=(a^b^cin);
assign co=(a&b)|(b&cin)|(a&cin);
endmodule

Test Bench:-

module fulladdertb();
reg a,b,cin;
wire s,co;
fulladder f1 (s,co,a,b,cin);

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initial begin
{a,b,cin}=3'b000;
End
always #40 a=~a;
always #20 b=~b;
always #10 cin=~cin;
initial #80 $stop;
endmodule
Simulated Waveform:-

RTL Schemantic:-

Synthesis Report:-

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Timing Report:-

Device Utilization Summary:-

Synthesis Diagram:-

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Result:- The Full Adder was designed using Verilog HDL & implemented in FPGA Spartan 3
kit.

Expt-8.1

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Design of SR Flip-Flop
Aim:- To Design & Implement SR Flip Flop using Verilog HDL.
Tool:-Xilinx ISE 9.2i Version

FAMILY SPARTAN 3E
Device 3S100E
Package CP132
Speed -4
Synthesis XST(VERILOG/VHDL)
Simulator ISE Simulator

Architecture:

Truth Table:

Source Code:
module sr_ff( sr  , clk    , reset , q ,qb );
input [1:0] sr;

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input clk, reset ;

output q,qb;
reg q,qb;
always @ ( posedge clk or posedge reset)
if (reset)
begin
q = 1'b0;
qb = ~q;
end
else
begin
case (sr)
2'd0 : q = q;
2'd1 : q = 1'b0;
2'd2 : q = 1'b1;
2'd3 : q = 1'bX;
endcase
qb = ~q;
end
endmodule

Test Bench Code:

module sr_tb;

// Inputs
reg [1:0] sr;
reg clk;
reg reset;

// Outputs
wire q;
wire qb;

// Instantiate the Unit Under Test (UUT)

sr_ff uut (
.sr(sr),
.clk(clk),
.reset(reset),
.q(q),
.qb(qb)
);

initial begin

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sr[0] = 0;sr[1] = 0;
clk = 1'b1;
reset = 1'b1;
#10 reset=1'b0;
end
always #5 clk=~clk;
always #20 sr[0]=~sr[0];
always #10 sr[1]=~sr[1];
initial #160 $stop;

endmodule
Result: The SR-Flipflop was designed using Verilog HDL & implemented in FPGA Spartan 3
kit

Expt-8.2

Design of JK Flip-Flop
Aim:- To Design & Implement JK-Flip Flop using Verilog HDL.

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Tool:-Xilinx ISE 9.2i Version

FAMILY SPARTAN 3E
Device 3S100E
Package CP132
Speed -4
Synthesis XST(VERILOG/VHDL)
Simulator ISE Simulator

Architecture:

Truth Table:

Q j k Q(t+1)

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 0

Source Code:-

module jkff(q,j,k,clk,clr);
input j,k,clk,clr;
output q;
reg q;
always @ (posedge clk)
begin

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if(clr==1'b1)
q<=1'b0;
else if (j==1'b0 & k==1'b0)
q<=q;
else if (j==1'b0 & k==1'b1)
q<=1'b0;
else if (j==1'b1 & k==1'b0)
q<=1'b1;
else if (j==1'b1 & k==1'b1)
q<=~q;
end
endmodule

Testbench:-

module jkfftb_v;
reg j,k,clk,clr;
wire q;
jkff uut (.q(q),.j(j),.k(k),.clk(clk),.clr(clr));
initial begin
j = 0;k = 0;
clk = 1'b1;
clr = 1'b1;
#10 clr=1'b0;
end
always #5 clk=~clk;
always #20 j=~j;
always #10 k=~k;
initial #160 $stop;
endmodule

Simulated Waveforms:-

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RTL Schemantic:-

Synthesis Report:-

Timing Report:-

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Device Utilization Summary:-

Synthesis Diagram:-

Result:-

The JK-Flipflop was designed using Verilog HDL & implemented in FPGA Spartan 3 kit.

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Expt-8.3

Design of D Flip-Flop
Aim:- To Design & Implement D Flip-Flop using Verilog HDL.
Tool:-Xilinx ISE 9.2i Version

FAMILY SPARTAN 3E
Device 3S100E
Package CP132
Speed -4
Synthesis XST(VERILOG/VHDL)
Simulator ISE Simulator

Architecture:

Truth Table:

CLK D RST Q QBAR

1 0 1 0

0 0 0 1

1 0 1 0

0 0 0 1

Source Code:-

module dff(q,qbar,clk,rst,d);
input d,clk,rst;
output q,qbar;
reg q,qbar;
always @ (posedge clk ,negedge rst)
begin

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if(rst==1'b0)
begin
q=1'b0;
qbar=1'b1;
end
else
begin
q=d;
qbar=~q;
end
end
endmodule

Test Bench:-

module dfftb_v;
reg clk,rst,d;
wire q,qbar;
dff uut (.q(q),.qbar(qbar),.clk(clk),.rst(rst), .d(d));
initial begin
clk = 0;
rst = 0;
d = 0;
#10 rst=1'b1;
end
always #10 clk=~clk;
always #20 d=~d;
endmodule

Simulated Waveform:-

RTL Schemantic:-

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Synthesis Report:-

Timing Report:-

Device Utilization Summary:-

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Synthesis Diagram:-

Result:-

The D-flipflop was designed using Verilog HDL & implemented in FPGA Spartan 3 kit.

Expt-8.4

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Design of T Flip-Flop
Aim:- To Design & Implement T Flip-Flop using Verilog HDL.
Tool:-Xilinx ISE 9.2i Version

FAMILY SPARTAN 3E
Device 3S100E
Package CP132
Speed -4
Synthesis XST(VERILOG/VHDL)
Simulator ISE Simulator

Architecture:

Truth Table:

Q t Q(t+1)

0 0 0

0 1 1

1 0 1

1 1 0

SOURCE CODE:-

module tff(q,qbar,clk,rst,t);

input clk;

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input rst;

input t;

output q,qbar;

reg q,qbar;

wire qq=t^q;

always @ (posedge clk,negedge rst)

begin

if(rst==1'b0)

begin

q=1'b0;

qbar=1'b1;

end

else

begin

q=qq;

qbar=~q;

end

end

endmodule

Test Bench:-

module tfftb_v;

reg clk,rst,t;

wire q,qbar;

tff uut (.q(q), .qbar(qbar), .clk(clk), .rst(rst), .t(t));

initial begin

rst = 1'b0;

clk = 1'b0;

t = 1'b0;

end

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always #10 clk=~clk;

always #20 t=~t;

always #200 rst=~rst;

endmodule

Simulated Waveform:-

RTL Schemantic:-

Synthesis Report:-

Timing Report:-

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Device Utilization Summary:-

Synthesis Diagram:-

Result:-

The T-flipflop was designed using Verilog HDL & implemented in FPGA Spartan 3 kit.

Expt-9.1

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Design of 4 bit Binary Counter

Aim:- To Design & Implement 4 Bit Binary Counter using Verilog HDL.
Tool:-Xilinx ISE 9.2i Version

FAMILY SPARTAN 3E
Device 3S100E
Package CP132
Speed -4
Synthesis XST(VERILOG/VHDL)
Simulator ISE Simulator

Architecture:-

Truth Table:-

Clk Clr Q3 Q2 Q1 Q0
0 1 0 0 0 0
1 0 0 0 0 1
1 0 0 0 1 0
1 0 0 0 1 1
1 0 0 1 0 0
1 0 0 1 0 1
1 0 0 1 1 0
1 0 0 1 1 1
1 0 1 0 0 0
1 0 1 0 0 1
1 0 0 0 0 0

Source Code:-

module counter4bit(count,clk,clr);
input clk,clr;
output [3:0] count;
reg [3:0] count;
initial count = 4'b0000;
always @ (posedge clk)
begin
if(clr==1'b1)

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count<=4'b0000;
else
count <= count +1'b1;
end
endmodule

Testbench:-

module counter4bit(count,clk,clr);
input clk,clr;
output [3:0] count;
reg [3:0] count;
initial count = 4'b0000;
always @ (posedge clk)
begin
if(clr==1'b1)
count<=4'b0000;
else
count <= count +1'b1;
end
endmodule

Simulated Waveforms:-

RTL SCHEMANTIC:-

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Synthesis Report:-

Timing Report:-

Device Utilization Summary:-

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Synthesis Diagram:-

Result:-

The 4-bit counter was designed using Verilog HDL & implemented in FPGA Spartan 3 kit.

Expt-9.2

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Design of 4 bit BCD Counter

Aim:- To Design & Implement 4 bit BCD Counter using Verilog HDL.
Tool:-Xilinx ISE 9.2i Version

FAMILY SPARTAN 3E
Device 3S100E
Package CP132
Speed -4
Synthesis XST(VERILOG/VHDL)
Simulator ISE Simulator

Architecture:

Truth Table:

Clk Clr Q3 Q2 Q1 Q0
0 1 0 0 0 0
1 0 0 0 0 1
1 0 0 0 1 0
1 0 0 0 1 1
1 0 0 1 0 0
1 0 0 1 0 1
1 0 0 1 1 0
1 0 0 1 1 1
1 0 1 0 0 0
1 0 1 0 0 1
1 0 0 1 0 0
1 0 1 0 1 0
1 0 1 0 1 1
1 0 1 1 0 0
1 0 1 1 0 1
1 0 1 1 1 0
1 0 1 1 1 1

Source Code:

module bcd9(count,rst,clk);

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input rst,clk;
output [3:0]count;
reg [3:0]count;
always @(posedge clk , negedge rst)
begin
if(~rst)
count=4'b0000;
else if(count<4'b1001)
count=count+4'b0001;end
endmodule

Testbench:

module tb_bcd9();
reg rst,clk;
wire [3:0]count;
bcd9 c1(count,rst,clk);
initial
begin
rst=1'b0;
clk=1'b0;end
always #10 clk=~clk;
always #300 rst=1'b1;
initial
begin
#1000 $finish;
end
endmodule

Simulation waveform:

Schematic Diagram:

Synthesis Report:
a) Timing Report:

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Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |4 |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:

----------------------------------------
-----------------------------------+------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
rst_inv(rst_inv1_INV_0:O) | NONE(count_3) |4 |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4
Minimum period: 4.036ns (Maximum Frequency: 247.770MHz)
Minimum input arrival time before clock: No path found
Maximum output required time after clock: 7.367ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
========================================================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 4.036ns (frequency: 247.770MHz)
Total number of paths / destination ports: 26 / 8
-------------------------------------------------------------------------
Delay: 4.036ns (Levels of Logic = 1)
Source: count_3 (FF)
Destination: count_0 (FF)
Source Clock: clk rising
Destination Clock: clk rising
Data Path: count_3 to count_0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
------------------------------------------ ------------
FDCE:C->Q 3 0.720 1.246 count_3 (count_3)
LUT4:I0->O 4 0.551 0.917 count_cmp_lt00001 (count_cmp_lt0000)
FDCE:CE 0.602 count_0
----------------------------------------
Total 4.036ns (1.873ns logic, 2.163ns route)
(46.4% logic, 53.6% route)

========================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 4 / 4
-------------------------------------------------------------------------
Offset: 7.367ns (Levels of Logic = 1)
Source: count_0 (FF)

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Destination: count<0> (PAD)

Source Clock: clk rising
Data Path: count_0 to count<0>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE:C->Q 6 0.720 1.003 count_0 (count_0)
OBUF:I->O 5.644 count_0_OBUF (count<0>)
----------------------------------------
Total 7.367ns (6.364ns logic, 1.003ns route)
(86.4% logic, 13.6% route)

=========================================================
CPU : 7.98 / 8.29 s | Elapsed : 8.00 / 9.00 s

b) Device utilization Summary:

Selected Device : 3s50pq208-4
Number of Slices: 3 out of 768 0%
Number of Slice Flip Flops: 4 out of 1536 0%
Number of 4 input LUTs: 6 out of 1536 0%
Number of IOs: 6
Number of bonded IOBs: 6 out of 124 4%
Number of GCLKs: 1 out of 8 12%

b) Schematic Diagram:

Result: The design is implemented on Spartan 3 FPGA board with Synthesis and
Simulation.

Expt-10

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Design of FSM(Moore Machine)

Aim:- To Design & Implement FSM (Moore Machine) using Verilog HDL.
Tool:-Xilinx ISE 9.2i Version

FAMILY SPARTAN 3E
Device 3S100E
Package CP132
Speed -4
Synthesis XST(VERILOG/VHDL)
Simulator ISE Simulator

Architecture:

Truth Table:

PRESENT STATE INPUT NEXT STATE OUTPUT

A B x Ta(t+1) Tb(t+1) Y=AB
0 0 0 0 0 0
0 0 1 1 0 0
0 1 0 0 0 0
0 1 1 1 1 0
1 0 0 0 1 0
1 0 1 1 1 0
1 1 0 0 1 1
1 1 1 1 0 1

State Diagram:

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Source Code:

module mooremachine2(y, x, clk, rst);

output y;
input x;
input clk;
input rst;
reg [1:0]state;
parameter s0=2'b00,s1=2'b01,s2=2'b10,s3=2'b11;
always@(posedge clk or negedge rst)
if(~rst)
state=s0;
else
case(state)
s0:if(x)
state=s1;
else
state=s0;
s1:if(x)
state=s2;
else
state=s1;
s2:if(x)
state=s3;
else
state=s2;
s3:if(x)
state=s0;
else
state=s3;
endcase
assign y=state[0]&state[1];
endmodule

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Testbench:

module tb_mooremachine2();
reg clk,rst,x;
wire y;
mooremachine2 m44(y,clk,rst,x);
initial
begin
clk=1'b0;
rst=1'b0;
x=1'b0;
end
always #10 clk=~clk;
always #20 x=~x;
always #200 rst=~rst;
initial
begin
#1000 $finish;
end
endmodule
Simulation waveform:

RTL SCHEMANTIC:-

Synthesis Report:-

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Timing Report:-

Device Utilization Summary:-

Synthesis Diagram:-

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Result:-

The Moore machine was designed using Verilog HDL & implemented in FPGA Spartan 3 kit.

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