DIGITAL SYSTEM DESIGN USING VERILOG HDL INTRODUCTION

Module 4 Part A

INTRODUCTION TO VERILOG

4.1 Why HDL?

Hardware Description Language (HDL) is a specialized programming language used for

designing, modeling, and simulating digital circuits and hardware systems. HDLs serve several
important purposes in the field of digital hardware design and are essential for several reasons:

Design Detailed (RTL) Functional

Ideas Design Simulation
(Specifications)

Device Timing Synthesis &

Programming Simulation Implementation

FPGA
CPLD
tpd=22
.1ns

Fig 1. Flow of Digital Design

Digital Circuit Design: HDLs are specifically designed for expressing the behavior and
structure of digital circuits. They provide a means to describe complex digital systems, such as
microprocessors, memory units, and digital signal processors, in a comprehensible and
systematic manner.

Simulation: HDLs enable the simulation of digital circuits before physical implementation.
Engineers and designers can test the functionality and performance of a design in a virtual
environment, allowing for early detection and correction of errors and issues.

Verification and Testing: HDLs facilitate the verification and testing of digital hardware
systems. By modeling the system in a language like VHDL (VHSIC Hardware Description
Language) or Verilog, designers can rigorously test the system's behavior, ensuring it meets the
specified requirements.

Design Abstraction: HDLs offer different levels of abstraction, allowing designers to work at
various levels of detail. This means that they can focus on the overall system architecture,
specific modules, or individual logic gates, depending on the needs of the project.

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Parallelism and Parallel Processing: Digital hardware often relies on parallelism to perform
tasks efficiently. HDLs provide a natural way to express parallelism in digital circuits, making
it easier to design and optimize systems that execute multiple tasks simultaneously.

Reusability: HDLs promote reusability in hardware design. Designers can create and reuse
modules or components in different projects, improving efficiency and reducing development
time.

FPGA and ASIC Design: HDLs are commonly used for field-programmable gate array
(FPGA) and application-specific integrated circuit (ASIC) design. These devices allow
hardware to be reconfigured or custom-designed, and HDLs are crucial for defining this
hardware's functionality.

Hardware Synthesis: HDLs can be synthesized into actual hardware implementations. Tools
like Xilinx Vivado and Intel Quartus take HDL code and convert it into the configuration files
needed to program FPGAs or ASICs.

Collaboration: HDLs provide a common language for hardware designers, which enhances
collaboration in large design teams. Engineers can work on different parts of a project while
sharing a common specification language.

Standardization: There are industry-standard HDLs, such as VHDL and Verilog, which have
well-defined syntax and semantics. This standardization ensures that designs created using these
languages can be used across different platforms and tools.

Education and Research: HDLs are widely used in educational settings to teach digital design
and in research to explore new digital hardware concepts and innovations.

Real-time Systems: HDLs are used in the design of real-time systems, such as control systems
and digital signal processing, where timing and reliability are critical.

4.2 Brief history of Hardware Description Language (HDL)

Assembly Language (1940s-1950s): The earliest form of hardware description can be traced
back to assembly languages, which were used for programming early computers like the ENIAC
and UNIVAC. Assembly languages provided a low-level means to describe the operation of
these machines but were not specifically designed for hardware description.

IPL (Information Processing Language) (1950s): IPL, developed at the Massachusetts

Institute of Technology (MIT) in the 1950s, is considered one of the earliest examples of a
high-level programming language for computer hardware. It allowed for the specification of
algorithms and was used to design early digital computers.

Machine Description Languages (1950s-1960s): In the late 1950s and early 1960s, machine
description languages were introduced to describe the architecture and organization of digital
computers. These early efforts laid the foundation for what would later become HDLs.

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Verilog (1984): The first HDL that gained significant popularity was Verilog. It was developed
by Gateway Design Automation, a company founded by Phil Moorby, and released in 1984.
Verilog was initially designed for simulation but later extended to support synthesis. It has since
become one of the most widely used HDLs for digital design.
 1984 - Developed by Gateway Design Automation
 1990 – Cadence
 1995 - IEEE –1364 -1995

VHDL (VHSIC Hardware Description Language) (1987): VHDL was developed as a result
of the U.S. Department of Defense's Very High-Speed Integrated Circuit (VHSIC) program. It
was created to standardize the design process and ensure interoperability of designs. VHDL was
first standardized in 1987 and is known for its strong type system and simulation capabilities.

Synthesis Tools (1990s): In the 1990s, the development of synthesis tools allowed HDL code
to be translated into gate-level descriptions for field-programmable gate arrays (FPGAs) and
application-specific integrated circuits (ASICs). This marked a significant shift in the use of
HDLs, as they became more closely tied to physical hardware implementation.

Other HDLs (2000s-Present): Over the years, various other HDLs and hardware modeling
languages have been developed to cater to specific needs. SystemVerilog, for instance, added
object-oriented programming features and enhanced testbench capabilities. MyHDL and Chisel
are open-source alternatives that enable hardware description in Python and Scala, respectively.

Industry Adoption (2000s-Present): HDLs have continued to evolve and adapt to new
challenges in hardware design. They are now widely adopted in the semiconductor industry,
aerospace, and various embedded systems applications.

Integration of High-Level Synthesis (HLS) (2010s-Present): The integration of High-Level

Synthesis (HLS) tools has allowed for the automatic conversion of high-level code (C/C++) into
hardware descriptions, further bridging the gap between software and hardware design.

4.3 Structure of Verilog Module

module module_name(signal_names);
signal_type signal_names; Signal_type
signal_names;
assign statements;
assign statements;
endmodule

Eg.:
module half_adder (I1, I2, O1, O2);
input I1;
input I2;
output O1;
output O2;
//Blank lines are allowed

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assign O1 = I1 ^ I2; //statement 1
assign O2 = I1 & I2; //statement 2
endmodule

Verilog Ports:

◼ Input: The port is only an input port.I. In any assignment statement, the port
should appear only on the right hand side of the statement
◼ Output: The port is an output port. The port can appear on either side of the
assignment statement.
◼ Inout: The port can be used as both an input & output. The inout represents a
bidirectional bus.

a. Lexical Conventions

Verilog contains a stream of tokens. Tokens can be comments, delimiters, numbers, strings,
identifiers, and keywords. Verilog HDL is a case-sensitive language. All keywords are in
lowercase.

b. Whitespace

Blank spaces (\b) , tabs (\t) and newlines (\n) comprise the whitespace. Whitespace is ignored
by Verilog except when it separates tokens. Whitespace is not ignored in strings.

c. Comments

Comments can be inserted in the code for readability and documentation. There are two ways to
write comments. A one-line comment starts with "//". Verilog skips from that point to the end of
line. A multiple-line comment starts with "/*" and ends with "*/". Multiple-line comments cannot
be nested. However, one-line comments can be embedded in multiple-line comments.

a = b && c; // This is a one-line comment

/* This is a multiple line
comment */
/* This is /* an illegal */ comment */
/* This is //a legal comment */

d. Operators

Operators are of three types: unary, binary, and ternary. Unary operators precede the operand.
Binary operators appear between two operands. Ternary operators have two separate operators
that separate three operands.

a = ~ b; // ~ is a unary operator. b is the operand

a = b && c; // && is a binary operator. b and c are operands
a = b ? c : d; // ?: is a ternary operator. b, c and d are operands

e. Number Specification

There are two types of number specification in Verilog: sized and unsized.
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f. Sized numbers

Sized numbers are represented as <size> '<base format> <number>. <size> is written only in
decimal and specifies the number of bits in the number. Legal base formats are decimal ('d or 'D),
hexadecimal ('h or 'H), binary ('b or 'B) and octal ('o or 'O). The number is specified as consecutive
digits from 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f. Only a subset of these digits is legal for a
particular base. Uppercase letters are legal for number specification.

4'b1111 // This is a 4-bit binary number

12'habc // This is a 12-bit hexadecimal number
16'd255 // This is a 16-bit decimal number.

g. Unsized numbers

Numbers that are specified without a <base format> specification are decimal numbers by default.
Numbers that are written without a <size> specification have a default number of bits that is
simulator- and machine-specific (must be at least 32).
23456 // This is a 32-bit decimal number by default
'hc3 // This is a 32-bit hexadecimal number
'o21 // This is a 32-bit octal number

h. X or Z values
Verilog has two symbols for unknown and high impedance values. These values are very
important for modeling real circuits. An unknown value is denoted by an x. A high impedance
value is denoted by z.

12'h13x // This is a 12-bit hex number; 4 least significant bits

unknown
6'hx // This is a 6-bit hex number
32'bz // This is a 32-bit high impedance number

An x or z sets four bits for a number in the hexadecimal base, three bits for a number in the octal
base, and one bit for a number in the binary base. If the most significant bit of a number is 0, x,
or z, the number is automatically extended to fill the most significant bits, respectively, with 0,
x, or z. This makes it easy to assign x or z to whole vector. If the most significant digit is 1, then
it is also zero extended.

i. Negative numbers
Negative numbers can be specified by putting a minus sign before the size for a constant number.
Size constants are always positive. It is illegal to have a minus sign between <base format> and
<number>. An optional signed specifier can be added for signed arithmetic.

-6'd3 // 8-bit negative number stored as 2's complement of 3

-6'sd3 // Used for performing signed integer math
4'd-2 // Illegal specification

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j. Underscore characters and question marks
An underscore character "_" is allowed anywhere in a number except the first character.
Underscore characters are allowed only to improve readability of numbers and are ignored by
Verilog.

A question mark "?" is the Verilog HDL alternative for z in the context of numbers. The ? is used
to enhance readability in the casex and casez statements,where the high impedance value is a
don't care condition.

12'b1111_0000_1010 // Use of underline characters for readability

4'b10?? // Equivalent of a 4'b10zz

k. Strings

A string is a sequence of characters that are enclosed by double quotes. The restriction on a string
is that it must be contained on a single line, that is, without a carriage return. It cannot be on
multiple lines. Strings are treated as a sequence of one-byte ASCII values.

"Hello Verilog World" // is a string

"a / b" // is a string

l. Identifiers and Keywords

Keywords are special identifiers reserved to define the language constructs. Keywords are in
lowercase. Identifiers are made up of alphanumeric characters, the underscore ( _ ), or the dollar
sign ( $ ). Identifiers are case sensitive. Identifiers start with an alphabetic character or an
underscore. They cannot start with a digit or a $ sign (The $ sign as the first character is reserved
for system tasks, which are explained later in the book).

reg value; // reg is a keyword; value is an identifier

input clk; // input is a keyword, clk is an identifier

m. Escaped Identifiers

Escaped identifiers begin with the backslash ( \ ) character and end with whitespace (space, tab,
or newline). All characters between backslash and whitespace are processed literally. Any
printable ASCII character can be included in escaped identifiers. Neither the backslash nor the
terminating whitespace is considered to be a part of the identifier.

\a+b-c
\**my_name**

4.4 VERILOG OPERATORS

Operators in Verilog are the same as operators in programming languages. They take two
values and compare or operate on them to yield a new result. Nearly all the operators in Verilog
are exactly the same as the ones in the C programming language.

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Arithmetic, logical, relational and shift operators are used to build expressions. Expressions
perform operation on one or more operands, the operands being vectored or scalared nets,
registers, bit-selects, part selects, function calls or concatenations thereof.

• Unary Expression

<operator> <operand>

• Binary and Other Expressions

<operand> <ope rator> <operand>

Parentheses can be used to change the precedence of

operators. For example, ((a+b) * c)

Operator Precedence:

All operators associate left to right, except for the ternary operator “?:” which associates from
right to left.

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Relational Operators

Arithmetic Operators

Logical Operators

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Equality and Identity Operators

Unary, Bitwise and Reduction Operators

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Shift Operators and other Operators

4.5 Verilog Data Types

Data Types
This section discusses the data types used in Verilog.

Value Set
Verilog supports four values and eight strengths to model the functionality of real
hardware. The four value levels are listed in Table

Verilog support several data types including : nets,register,vectors,integer,real,parameters and

arrays

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I. Nets

Nets represent connections between hardware elements. Just as in real circuits, nets have values
continuously driven on them by the outputs of devices that they are connected to
In Figure

net a is connected to the output of and gate g1. Net a will continuously assume the value
computed at the output of gate g1, which is b & c.

Example of Nets

Nets are declared primarily with the keyword wire. Nets are one-bit values by default unless they
are declared explicitly as vectors. The terms wire and net are often used interchangeably. The
default value of a net is z (except the trireg net, which defaults to x ). Nets get the output value of
their drivers. If a net has no driver, it gets the value z.wire a; // Declare net a for the above circuit
wire b,c; // Declare two wires b,c for the above circuit wire d = 1'b0; // Net d is fixed to logic
value 0 at declaration. Note that net is not a keyword but represents a class of data types such as
wire, wand, wor, tri, triand, trior, trireg, etc. The wire declaration is used most frequently.

II. Registers

Registers represent data storage elements. Registers retain value until another value is placed onto
them. Do not confuse the term registers in Verilog with hardware registers built from edge-
triggered flipflops in real circuits. In Verilog, the term register merely 47 means a variable that can
hold a value. Unlike a net, a register does not need a driver. Verilog registers do not need a clock
as hardware registers do. Values of registers can be changed anytime in a simulation by assigning
a new value to the register.Register data types are commonly declared by the keyword reg. The
default value for a reg data type is x. An example of how registers are used is shown Example.

Example of Register
reg reset; // declare a variable reset that can hold its value
initial // this construct will be discussed later
begin
reset = 1'b1; //initialize reset to 1 to reset the digital circuit.
#100 reset = 1'b0; // after 100 time units reset is deasserted.
end
Registers can also be declared as signed variables. Such registers can be used for signed arithmetic.
Example shows the declaration of a signed register.

Signed Register Declaration

reg signed [63:0] m; // 64 bit signed value
integer i; // 32 bit signed value

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III. Vectors

Nets or reg data types can be declared as vectors (multiple bit widths). If bit width is not
specified, the default is scalar (1-bit).
wire a; // scalar net variable, default
wire [7:0] bus; // 8-bit bus
wire [31:0] busA,busB,busC; // 3 buses of 32-bit width.
reg clock; // scalar register, default
reg [0:40] virtual_addr; // Vector register, virtual address 41 bits
wide
Vectors can be declared at [high# : low#] or [low# : high#], but the left number in the squared
brackets is always the most significant bit of the vector. In the example shown above, bit 0 is the
most significant bit of vector virtual_addr.

IV. Arrays

Arrays are allowed in Verilog for reg, integer, time, real, realtime and vector register data
types. Multi-dimensional arrays can also be declared with any number of dimensions. Arrays of
nets can also be used to connect ports of generated instances. Each element of the array can be
used in the same fashion as a scalar or vector net. Arrays are accessed by
<array_name>[<subscript>]. For multi-dimensional arrays, indexes need to be provided
for each dimension.
integer count[0:7]; // An array of 8 count variables
reg bool[31:0]; // Array of 32 one-bit boolean register variables
time chk_point[1:100]; // Array of 100 time checkpoint variables
reg [4:0] port_id[0:7]; // Array of 8 port_ids; each port_id is 5 bits wide
It is important not to confuse arrays with net or register vectors. A vector is a single
element that is n-bits wide. On the other hand, arrays are multiple elements that are 1-bit
or n-bits wide.
V. Integer
The integers are general-purpose 32-bit register data types. They are declared by the
‘integer’ keyword.
integer count;

VI. Real
The real data types can be constants or real register data types. They are declared
using the ‘real’ keyword.
The real value is rounded off if they are assigned to integer data type,

real data = 3.14;

VII. Parameters

Verilog allows constants to be defined in a module by the keyword parameter. Parameters

cannot be used as variables. Parameter values for each module instance can be overridden
individually at compile time. This allows the module instances to be customized. This

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aspect is discussed later. Parameter types and sizes can also be defined.
parameter port_id = 5; // Defines a constant port_id
parameter cache_line_width = 256; // Constant defines width of cache
line
parameter signed [15:0] WIDTH; // Fixed sign and range for parameter
// WIDTH

Styles (Types) of Descriptions

Verilog language has the capability of designing a module in several coding styles. Depending on
the needs of a design, internals of each module can be defined at four level of abstractions.
Irrespective of the internal abstraction level, the module would behave exactly in the similar way
to the external environment. Following are the four different levels of abstraction which can be
described by four different coding styles of Verilog language:

1. Behavioral or Algorithmic level

2. Dataflow level
3. Gate level or Structural level
4. Switch level

1. Behavioral or Algorithmic level

• This is the highest level of abstraction provided by Verilog HDL.

• A module can be implemented in terms of the desired design algorithm without concern
for the hardware implementation details.
• It specifies the circuit in terms of its expected behavior.
• It is the closest to a natural language description of the circuit functionality, but also the
most difficult to synthesize.

module mux_4to1(
input [3:0] i,
input [1:0] s,
output reg o
);

always @(s or i)
begin
case (s)
2'b00 : o = i[0];
2'b01 : o = i[1];
2'b10 : o = i[2];
2'b11 : o = i[3];
default : o = 1'bx;
endcase
end
endmodule

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2. Dataflow level

• At this level, the module is designed by specifying the data flow.

• Looking towards this design, one can realize how data flows between hardware registers
and how the data is processed in the design.
• This style is similar to logical equations. The specification is comprised of expressions
made up of input signals and assigned to outputs.
• In most cases, such an approach can be quite easily translated into a structure and then
implemented.

module mux_4to1_df(
input [3:0] i,
input [1:0] s,
output o
);

assign o = (~s[1] & ~s[0] & i[0]) | (~s[1] & s[0] & i[1]) | (s[1] &
~s[0] & i[2]) | (s[1] & s[0] & i[3]);
endmodule

3. Gate level or Structural level

• The module is implemented in terms of logic gates and interconnections between these
gates.
• It resembles a schematic drawing with components connected with signals.
• A change in the value of any input signal of a component activates the component. If two
or more components are activated concurrently, they will perform their actions
concurrently as well.
• A structural system representation is closer to the physical implementation than behavioral
one but it is more involved because of large number of details. Since logic gate is most
popular component, Verilog has a predefined set of logic gates known as primitives. Any
digital circuit can be built from these primitives.

module mux_4to1_gate(
input [3:0] i,
input [1:0] s,
output o
);

wire NS0, NS1;

wire Y0, Y1, Y2, Y3;
not N1(NS0, s[0]);
not N2(NS1, s[1]);
and A1(Y0, i[0], NS1, NS0);
and A2(Y1, i[1], NS1, s[0]);
and A3(Y2, i[2], s[1], NS0);
and A4(Y3, i[3], s[1], s[0]);
or O1(o, Y0, Y1, Y2, Y3);
endmodule

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4. Switch level

• This is the lowest level of abstraction provided by Verilog.

• A module can be implemented in terms of transistors, switches, storage nodes, and the
interconnections between them.
• In Verilog HDL transistors are known as Switches that can either conduct or open.

Design at this level requires knowledge of switch-level implementation details.

module inver (y,a);

input a;
ouput y,
supply1 vdd;
supply0 gnd;
pmos p1(y,vdd,a);
nmos n1(y,gnd,a);
endmodule

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