Verilog is a hardware description language used for digital circuit design. It supports different modeling styles like gate-level, dataflow, and behavioral. Key concepts include modules defined with ports, hierarchical design using instances, and modeling concurrency. Verilog allows top-down or bottom-up design approaches and simulation of a design and testbench.
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Verilog is a hardware description language used for digital circuit design. It supports different modeling styles like gate-level, dataflow, and behavioral. Key concepts include modules defined with ports, hierarchical design using instances, and modeling concurrency. Verilog allows top-down or bottom-up design approaches and simulation of a design and testbench.
Verilog is a hardware description language used for digital circuit design. It supports different modeling styles like gate-level, dataflow, and behavioral. Key concepts include modules defined with ports, hierarchical design using instances, and modeling concurrency. Verilog allows top-down or bottom-up design approaches and simulation of a design and testbench.
Copyright:
Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPTX, PDF, TXT or read online from Scribd
Verilog is a hardware description language used for digital circuit design. It supports different modeling styles like gate-level, dataflow, and behavioral. Key concepts include modules defined with ports, hierarchical design using instances, and modeling concurrency. Verilog allows top-down or bottom-up design approaches and simulation of a design and testbench.
Copyright:
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UNIT-V VERILOG
HARDWARE DESCRIPTION LANGUAGE TOPICS • Overview of digital design with Verilog HDL • Hierarchical modeling concepts • Modules and port definitions • Gate level modeling • Data flow modeling • Behavioral modeling • Tasks & functions • Test bench Overview of digital design with Verilog HDL Evolution of Computer Aided Digital Design Digital ckt Designed with vacuum tube & transistors ● ●
IC Logic gates are placed on a single chip
● ●
SSI Gate count was very small(<10)
● ●
MSI Hundreds of gates on a single chip(10-100)
● ●
LSI Thousands of gates on a single chip
● ●
VLSI More than 1,00,000 transistors
● ● Emergence of HDLs • For a long time, programming languages such as FORTRAN, Pascal & C were being used to describe computer programs that were sequential in nature. • Similarly, in the digital design field, designers felt the need for std. language to describe digital ckts. (HDLs) • Allowed the designers to model the concurrency of processes found in hardware elements. Hardware Design Languages
Currently, almost all integrated circuits are designed with
using HDL
Two widely used hardware description languages
— VHDL — Verilog HDL
HDL languages can describe circuits from two perspectives
— function — structure Hardware Design Languages • Hardware Description Language (HDL) is a language used to describe a digital system. • Digital system can be described at several levels: • Switch level: wires, resistors and transistors • Gate level: logical gates and flip flops • Register Transfer Level (RTL): registers and the transfers of information between registers. Verilog HDL vs. VHDL VHDL • “V” is short for Very High Speed Integrated Circuits. • Designed for and sponsored by US Department of Defense. • Designed by committee (1981-1985). • Syntax based on ADA programming language. • Was made an IEEE Standard in 1987.
Verilog HDL • Was introduced in 1985 by Gateway Design System Corporation, now a part of Cadence Design Systems, Inc.'s Systems Division. • Was made an IEEE Standard in 1995 • Syntax based on C programming language. VLSI DESIGN FLOW
Process VLSI DESIGN FLOW
Describe abstractly the
functionality, interface & overall architecture of the digital ckt to be designed.
Process VLSI DESIGN FLOW
Used to analyze design
in terms of functions, performance compliance to standards & other high level issues
Process VLSI DESIGN FLOW
Describe dataflow that
will implement the desired digital ckts, then design process is done with EDA tool.
Process VLSI DESIGN FLOW
RTL description gate
level net list
Process VLSI DESIGN FLOW
Description of the ckt in
terms of gates & connection b/w them.
Process Hierarchical modeling concepts Design Methodologies • Two basic types of design methodologies – Top-down design – Bottom-up design
Top-down design Bottom-up design
Example: 4-bit Ripple Carry Adder Level of abstraction
Behavioral or algorithmic level
Dataflow level
Gate level or structural
Switch level Behavioral or algorithmic level • This is the highest level of abstraction provided by verilog HDL. • Module can be implemented in terms of the desired design algorithm without concern for h/w implementation details. • Very similar to C programming. Dataflow level • Module is designed by specifying the dataflow. • The designer is aware of how data flows b/w hardware reg’s & how data is processed in design. Gate level or structural • Module is implemented in terms of logic gates and interconnections b/w those gates. • Similar to describing a design in terms of a gate level logic diagram. Modules and port definitions Definition of Module • Modules are the basic building blocks in Verilog. • Interface: port and parameter declaration • Body: Internal part of module • Add-ons (optional) A simple Verilog Example
Verilog Code Circuit
a // A simple example comment line c b module and2 (a, b ,c); module name port list
input a, b; port declarations output c;
assign c = a & b; body
endmodule end module
Port declaration Verilog Code Circuit
module MAT (enable, data, all_zero, result, status);
To make code easy to read, use self-explanatory port names
For the purpose of conciseness, use short port names In vector port declaration, MSB can be smaller index. e.g. output [0:3] result (result[0] is the MSB) The Module Interface • Port List
• Port Declaration Instances • The process of creating objects from a module template is called instantiation. • The objects are called instances. Components of simulation • Design block • Stimulus block One language, Many Coding Style One language, Many Coding Style (contd.) One language, Many Coding Style (contd.) Behavioral style: Verilog Code Dataflow style: Verilog Code Structural style: Verilog Code Basic concepts Keywords Module name Module ports module Add_half ( sum, c_out, a, b ); input a, b; Declaration of port outputsum, c_out; modes wire c_out_bar; Declaration of internal signal
xor (sum, a, b); Instantiation of primitive
gates nand (c_out_bar, a, b); a not (c_out, c_out_bar); b sum endmodule c_out_bar Verilog keywords c_out 1.Lexical conventions • Basic lexical conventions used by verilog HDL are similar to C. • Contains a stream of tokens. • Tokens: whitespace,comments,delimiters,strings, identifiers & keywords • Verilog HDL- case sensitive language • All keywords are in lowercase. Whitespace • Blank spaces \b • Tabs \t • New line \n
• Whitespace is not ignored in strings.
Comments One line comment (// ………….) Block Comment (/*…………….*/) Operators • 3 types: unary, binary, & ternary Number specification • Numbers are specified using the following form <size><base format><number> • Size: a decimal number specifies the size of the number in bits. • Base format: is the character ’ followed by one of the following characters – b for binary,d for decimal,o(octal),h(hex). • Number: set of digits to represent the number. • Sized numbers:
• Unsized numbers:
• X or Z values:
• Underscore & question mark:
Numbers • Example : x = 347 // decimal number x = 4’b101 // 4- bit binary number 0101 x = 6’o12 // 6-bit octal number x = 16’h87f7 // 16-bit hex number h87f7 x = 2’b101010 x = 2’d83 • String in double quotes “ this is an introduction” Integer constants Un-sized integer example
— 12 // decimal number 12 — `h12 // hex number 12 (18 decimal number) —`o12 // octal number 12 (10 decimal number) —`b1001 // binary number 1001 (9 decimal number)
Sized integer example
— 8`d12 // decimal number 12 taking 8 bits
— 8`h12 // hex number 12 taking 8 bits —8`b10010011 // —8`b1 // binary number 00000001 Note Verilog uses left padding Integer constants Negative numbers — Negative numbers are represented in 2’s complement form — - 8`d12 // stored as 11110100
Use of ?, X, Z, _ characters — 8`h1? // 0001ZZZZ — 2`b1? // 1Z — 4`b10XX // 10XX — 4`b100Z // 100Z — 8`b1010_0011 // 10100011 Strings • Sequence of characters that are enclosed by double qoutes. Identifiers • Identifiers are names given to objects so that they can be referenced in the design. • --made up of a space-free sequence of uppercase and lowercase letters from alphabet, digits (0,1,….9), underscore (_), and the $ symbol. • Verilog is a case sensitive language. – c_out_bar and C_OUT_BAR are two different identifiers. • The name of a variable may not begin with a digit or $, and may be up to 1,024 characters long. – e.g. clock_, state_3 2.Data Types • Value set: verilog supports 4 values & 8 strengths to model the functionality of real h/w. • Four signal values: Strength levels Available signal values
Four signal values
—1 True —0 False —X Unknown —Z High impedance Logic operations on four-value signals
Truth table AND 1 0 X Z a b c 1 1 0 X X 0 0 0 0 0 X X 0 X X Z X 0 X X Signal Classification Each signal in Verilog belongs to either a net or a register
A net represents a physical wire. Its signal value is
determined by its driver. If it is not driven by any driver, its value is high impedance (Z).
A register is like a variable in programming languages.
It keeps its value until a new value is assigned to it.
Unlike registers, nets do not have storage capacity.
Class of Signals • Nets: physical connection between hardware elements
• Registers: Store value even if disconnected Net declaration Nets: Represents connections b/w h/w elements. A net declaration starts with keyword wire …… addr wire r_w; // scalar signal
Processor
Memory wire [7:0] data; // vector signal data
wire [9:0] addr; // vector signal
r_w ……
— Selecting a single bit or a portion of vector signals
data[2]single bit data [5:3] 3 bits
Other keywords that can be used to declare nets are:
Nets are internal signals that cannot be accessed by outside environment
Ports are external signals to interface with outside environment
— input ports can be read but cannot be written
— output ports can be written but cannot be read — inout ports can be read and written pc module pc (clk, rst, status, i_o); input clk, rst; clk output [3:0] status; addr[9:0] inout [7:0] i_o; rst
Processor
Memory wire r_w; data[7:0] wire [7:0] data; status[3:0] wire [9:0] addr; r_w …… i_o[7:0] endmodule Register declaration A register declaration starts with keyword reg …… reg done; // scalar signal reg [7:0] count; // vector signal …… Registers can be used to describe the behavior of sequential circuits
Registers can also be used to implemented registered output ports
module pc (clk, rst, status, i_o);
input clk, rst; output [3:0] status; reg [3:0] status; inout [7:0] i_o; …… Defining memory A memory component can be defined using reg variables
Example:
…… reg [7:0] myMem [3:0]; // It defines a memory with 4 locations and each // location contains an 8-bit data
Bit 7 6 5 4 3 2 1 0 myMem[0] myMem[1] myMem[2] myMem[3] Using parameters The use of parameters make code easy to read and modify
Example:
…… parameter bussize = 8; reg [bussize-1 : 0] databus1; reg [bussize-1 : 0] databus2; …… • Strings: strings can be stored in reg. 3.System Tasks & Compiler Directives System Tasks • Verilog provides std. system tasks to do certain routine operations. • Syntax: $<keyword> • Operations: displaying on the screen, monitoring values of nets, stopping, & finishing. Display information • Usage: $display(p1,p2,p3,……,pn) – p1, ,p2,p3,……,pn can be quoted strings or variables or expressions.
