Introduction

Unit - 1
 Evolution of Computer Aided Digital Design

• Digital circuit design has evolved rapidly over the last 25 years.
• The earliest digital circuits were designed with vacuum tubes and transistors.
• Integrated circuits were then invented where logic gates were placed on a single chip.
• SSI (Small scale integration)
• MSI (Medium Scale Integration)
• LSI (Large Scale Integration)

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 EDA(Electronic Design Automation)
• Design processes started getting very complicated, and designers felt the need to automate
these processes.
• Chip designers began to use circuit and logic simulation techniques to verify the functionality
of building blocks.
• VLSI (Very Large Scale Integration) designers could design single chips with more than
millions of transistors.
• Computer-aided techniques became critical for verification and design of VLSI digital circuits
• Logic simulators came into existence to verify the functionality of these circuits before they
were fabricated on chip
• Designers could iron out functional bugs in the architecture before the chip was designed
further
• Goals
– most reliable design process, with minimum cost and time
– avoid design errors!

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 HDL (Hardware Description Language)
• HDL allowed the designers to model the concurrency of processes found in hardware elements.

• Hardware description languages such as Verilog HDL and VHDL became popular.

• Verilog HDL originated in 1983 at Gateway Design Automation.

• The advent of logic synthesis in the late 1980s changed the design methodology radically.

• Digital circuits could be described at a register transfer level (RTL) by use of an HDL.

• The details of gates and their interconnections to implement the circuit were automatically
extracted by logic synthesis tools from the RTL description.

• HDLs were used for simulation of system boards, interconnect buses, FPGAs (Field
Programmable Gate Arrays), and PAL (Programmable Array Logic).

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 VLSI design flow
• Architectural design – input, output, Unshaded – design description
components, cost estimate
Shaded – design process

• RTL – Register Transfer level

• Translate
• Technology Mapping
• Optimize • List of gates and nets (interconnections)
• Testability

• Transistor level

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6
Two Modeling Hardware Description Languages

VHDL and Verilog

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 Verilog HDL
⦿ Verifying Logic
⦿ Phil Moorby from Gateway Design Automation in 1984 to 1987 (absorbed by Cadence)
⦿ Verilog-XL Simulator from GDA in 1986
⦿ Synopsys synthesis tool in 1988
⦿ In 1990 became open language, OVI (Open Verilog International)
⦿ IEEE standard 1995
⦿ Similar to C
⦿ Fairly efficient and easy to write
⦿ Case sensitive

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 What is Verilog HDL?
• Verilog Hardware Description Language(HDL)?
– A high-level computer language to model, represent and simulate digital design
• Hardware concurrency
• Parallel Activity Flow
• Semantics for Signal Value and Time

– Design examples using Verilog HDL

• Intel Pentium, AMD - K5, K6, Athlon, ARM7, etc
• Thousands of ASIC designs using Verilog HDL
 Design Methodologies
•

In a top-down design methodology, we define the top-level block

and identify the sub-blocks necessary to build the top-level block.
We further subdivide the sub-blocks until we come to leaf cells,
which are the cells that cannot further be divided.
 Design Methodologies
•

In a bottom-up design methodology, we first identify the building

blocks that are available to us. We build bigger cells, using these
building blocks. These cells are then used for higher-level blocks until
we build the top-level block in the design.
 Modules
• A module is the basic building block in Verilog.
• A module can be an element or a collection of lower-level design blocks.
• A module provides the necessary functionality to the higher-level block through its
port interface (inputs and outputs), but hides the internal implementation.
• In Verilog, it is illegal to nest modules.
• One module definition cannot contain another module definition within the
module and endmodule statements.
 Modules
• In Verilog, a module is declared by the keyword module.
• A corresponding keyword endmodule must appear at the end of the module
definition.
• Each module must have a module-name, which is the identifier for the module,
and a module-terminal-list, which describes the input and output terminals of the
module.
 Modules
• Internals of each module can be defined at four levels of abstraction, depending
on the needs of the design.
• The module behaves identically with the external environment irrespective of the
level of abstraction at which the module is described.
 Modules
• Verilog allows the designer to mix and match all four levels of abstractions in a
design.
• In the digital design community, the term register transfer level (RTL) is frequently
used for a Verilog description that uses a combination of behavioral and dataflow
constructs and is acceptable to logic synthesis tools.
Components of a module
 Components of a module
• The module name, port list, port declarations, and optional parameters must come
first in a module definition.
• Port list and port declarations are present only if the module has any ports to
interact with the external environment.
• The five components within a module are - variable declarations, dataflow
statements, instantiation of lower modules, behavioral blocks, and tasks or
functions.
• These components can be in any order and at any place in the module definition.
• The endmodule statement must always come last in a module definition.
 Keywords
• Note : All keywords are defined in lower case

Examples :
• module, endmodule
• input, output, inout
• reg, integer, real, time
• not, and, nand, or, nor, xor
• parameter
• begin, end
• fork, join
• specify, endspecify

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 Ports
input, output, inout
These keywords declare input, output and bidirectional ports of a module or task.
Input and inout ports are of type wire.
An output port can be configured to be of type wire, reg, wand, wor or tri.
The default is wire.

Syntax
input [msb:lsb] input_port_list;
output [msb:lsb] output_port_list;
inout [msb:lsb] inout_port_list;

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 Instances
• The process of creating objects from a module template is called instantiation, and
the objects are called instances.
• Each instance must be given a unique name.
• A module definition can incorporate copies of other modules by instantiating
them.
 Module instantiation
• Port mapping by order
Example:
half_adder ha1 (a , b, s1, c1)
half_adder ha2 (s1 , cin, sum, c2)
or or1 (cout, c1, c2)

• Port mapping by name (may skip any ports; advantageous when large number of
ports are there)
Example:
half_adder ha1 (.a(a) , .b(b), .sum(s1), .carry(c1))
half_adder ha2 (.a(s1) , .b(cin), .sum(sum), .carry(c2))
or or1 (cout, c1, c2)
 //Port-mapping by order
module SYNCHRO (ASYNC,SYNC,CLOCK);
input ASYNC;
input CLOCK;
module DFF (Q, D, CLK); output SYNC;
input D, CLK; wire C1_ASYNC;
output reg Q; DFF DFF1 (C1_ASYNC, ASYNC, CLOCK);
always @ (posedge CLK) DFF DFF2 (SYNC, C1_ASYNC, CLOCK);
Q <= D; endmodule
----------------------------------------------------
endmodule
//Port-mapping by name
module SYNCHRO (ASYNC, SYNC, CLOCK);
input ASYNC;
input CLOCK;
output SYNC;
wire C1_ASYNC;

DFF D1 (.D (ASYNC), .CLK (CLOCK), .Q (C1_ASYNC));

DFF D2 (.D (C1_ASYNC), .Q (SYNC), .CLK (CLOCK));
endmodule
 Components of Simulation
• The functionality of the design block can be tested by applying stimulus and
checking results.
• We call such a block the stimulus block.
• It is good practice to keep the stimulus and design blocks separate.
• The stimulus block can be written in Verilog.
• The stimulus block is also commonly called a test bench.
 Components of Simulation
• In the first style, the stimulus block instantiates the design block and directly drives
the signals in the design block.
 Ports
• List of ports
• Port declaration
• Port connection rules
 Port connection rules
• One can visualize a port as consisting of two units, one unit that is internal to the
module another that is external to the module. The internal and external units are
connected. There are rules governing port connections when modules are
instantiated within other modules.
 Port connection rules
• Input : Internally, input ports must always be of the type net. Externally, the inputs can be
connected to a variable which is a reg or a net.
• Output : Internally, outputs ports can be of the type reg or net. Externally, outputs must always
be connected to a net. They cannot be connected to a reg.
• Inout : Internally, inout ports must always be of the type net. Externally, inout ports must always
be connected to a net.
• In VHDL, D should be strictly in either in or inout mode, but Verilog is not that strict in
compilation. The output mode can also be used as an input in a statement inside the same
module, but inout has to be used if the variable has to be used as input and output by other
modules.
• Width matching : It is legal to connect internal and external items of different sizes when making
inter-module port connections. However, a warning is typically issued that the widths do not
match.
• Unconnected ports
Example of illegal port connection
 Connecting Ports to External Signals
• Connecting ports by order

• Connecting ports by name

– Advantageous when there are large number of ports involved
– Unconnected ports need not be listed
 Elements of Verilog-logic values
▪ 0: zero, logic low, false, ground

▪ 1: one, logic high, power

• X: unknown

• Z: high impedance, unconnected, tri-state

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 Data Types
• Nets and Registers
• Vectors
• Integer, Real, and Time Register Data Types
• Arrays
• Memories
• Parameters
• Strings

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 Nets
• Used to represent connections between HW elements
– Values continuously driven on nets
• Keyword: wire
– Default: One-bit values (unless declared as vectors)
– Default value: z
• For trireg, default is x
– Note that net is not a keyword but represents a class of data types such as wire,
wand, wor, tri, triand, trior, trireg, etc. The wire declaration is used most
frequently.
– Examples
• wire a;
• wire b, c;
• wire d=1’b0;
• Port declaration – “nets” by default
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 Registers
• Registers represent data storage elements
– Retain value until next assignment
– NOTE: this is not a hardware register or flipflop
– Keyword: reg
– Default value: x
– Example:
reg reset;
initial
begin
reset = 1’b1;
#100 reset=1’b0;
end

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 Vectors
• Net and register data types can be declared as vectors (multiple bit widths)
• Syntax:
– wire/reg [msb_index : lsb_index] data_id;
• Example
wire a;
wire [7:0] bus;
wire [31:0] busA, busB, busC;
reg clock;
reg [0:40] virtual_addr;

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 Vectors (cont’d)
• Consider
wire [7:0] bus;
wire [31:0] busA, busB, busC;
reg [0:40] virtual_addr; // bit-0 is the MSB
• Access to bits or parts of a vector is possible:
busA[7]
bus[2:0] // three least-significant bits of bus
// bus[0:2] is illegal.
virtual_addr[0:1] /* two most-significant bits
* of virtual_addr
*/

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Integer, Real, and Time - Register Data Types (cont’d)

• Integer
– Keyword: integer
– Very similar to a vector of reg
• integer variables are signed numbers
• reg vectors are unsigned numbers
– Bit width: implementation-dependent (at least 32-bits)
• Designer can also specify a width:
integer [7:0] tmp;
– Examples:
integer counter;
initial
counter = -1;

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Integer, Real, and Time - Register Data Types (cont’d)
• Real
– Keyword: real
– Values:
• Default value: 0
• Decimal notation: 12.24
• Scientific notation: 3e6 (=3x106)
– Cannot have range declaration; bit-width 64

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Integer, Real, and Time - Register Data Types (cont’d)

• Time
– Used to store values of simulation time
– Keyword: time
– Bit width: implementation-dependent (at least 64)
– $time system function gives current simulation time
– Example:
time save_sim_time;
initial
save_sim_time = $time;
• Simulation time is measured in terms of simulation seconds.

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 Arrays
• Only one-dimensional arrays supported
• Allowed for reg, integer, time
– Not allowed for real data type
• Syntax:
<data_type> <var_name> [start_idx : end_idx];
• Examples:
integer count [0:7];
reg bool[31:0];
time chk_point [1:100];
reg [4:0] port_id [0:7];
integer matrix[4:0][4:0]; // illegal
count[5]
chk_point[100]
port_id[3]
• Note the difference between vectors and arrays

Verilog thinks in bits, so reg [7:0] a[0:3] will give you a 4x8 bit array (=4x1 byte array).
You get the first byte out of this with a[0]. The third bit of the 2nd byte is a[1][2].
 Memories
• RAM, ROM, and register-files used many times in digital systems
• Memory = array of registers in Verilog
• Word = an element of the array
– Can be one or more bits
• Examples:
reg membit[0:1023];
reg [7:0] membyte[0:1023];
membyte[511]
• Note the difference (as in arrays): It is important to differentiate between n 1-bit
registers and one n-bit register.
reg membit[0:127];
reg [0:127] register;

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 Parameters
• Similar to const in C
– But can be overridden for each module at compile-time
• Syntax:
parameter <const_id>=<value>;
• Gives flexibility
– Allows to customize the module
• Example:
parameter port_id=5;
parameter cache_line_width=256;
parameter bus_width=8;
wire [bus_width-1:0] bus;

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 Strings
• Strings are stored in reg variables.
• 8-bits required per character
• Example:
reg [8*18:1] string_value;
initial
string_value = “Hello World!”;
• Escaped characters
– \n : newline
– \t : tab
– %% : %
– \\ : \
– \” : “

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 Numbers
Format : <size>’<base><value>
Example : 8’d16
8’h10
8’b00010000
8’o20

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• Modules
• Ports
• System tasks & compiler directives
Lexical Conventions – White space
White space
Comments
Case sensitivity
Identifiers
Numbers format
Numbers format
Numbers format
Escaped characters
Escaped characters
 System Tasks and Compiler Directives
System Tasks

• Verilog provides standard system tasks to do certain routine operations.

• All system tasks appear in the form $<keyword>.

• Important system tasks

– Operations such as displaying on the screen, monitoring values of nets, stopping, and
finishing are done by system tasks.
 Displaying information ($display)
• $display is the main system task for displaying values of variables or strings or
expressions.

• Usage: $display ( p1 , p2, p3 ,....., pn);

• p1, p2, p3,..., pn can be quoted strings or variables or expressions.

• The format of $display is very similar to printf in C.

• A $display inserts a newline at the end of the string by default.

Displaying information ($display)
Displaying information ($display)
 Monitoring information $monitor
• Verilog provides a mechanism to monitor a signal when its value changes. This
facility is provided by the $monitor task.

• Usage: $monitor(p1,p2,p3,....,pn);

• The parameters p1, p2, ...,pn can be variables, signal names, or quoted strings.

• $monitor continuously monitors the values of the variables or signals specified in

the parameter list and displays all parameters in the list whenever the value of any
one variable or signal changes.

• Unlike $display, $monitor needs to be invoked only once.

 Monitoring information $monitor
• Only one monitoring list can be active at a time.
• If there is more than one $monitor statement in your simulation, the last
$monitor statement will be the active statement.
• The earlier $monitor statements will be overridden.
• Two tasks are used to switch monitoring on and off.
Usage: $monitoron; $monitoroff;
•
Monitoring information $monitor
 Stopping and finishing in a simulation
• The task $stop suspends a simulation.
Usage: $stop;

• The $stop task is used whenever the designer wants to suspend the simulation and
examine the values of signals in the design.

• The $finish task terminates the simulation.

Usage: $finish;
Stopping and finishing in a simulation
 Compiler directives
• Verilog HDL allows the reference time unit for modules to be specified with the
`timescale compiler directive.

• Usage: `timescale <reference-time-unit> / <time-precision>

• The <reference-time-unit> specifies the unit of measurement for times and delays.
The <time-precision> specifies the precision to which the delays are rounded off
during simulation.

• Only 1, 10, and 100 are valid integers for specifying time unit and time precision

• https://www.javatpoint.com/verilog-timescale
 Examples
•
Comparator using full adders