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Introduction To Verilog Programming

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Hamza
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16 views

Introduction To Verilog Programming

Uploaded by

Hamza
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Introductio

n to Verilog Basics of Verilog for Digital Logic Design


Programmi
ng By
ASMA TOUQIR
What is Verilog?

Introductio • A Hardware Description Language (HDL)

n to Verilog • Used for modeling electronic systems


• Levels of abstraction: Behavioral, RTL, Gate level
Benefits:

•Design, simulation, and synthesis of hardware


•Describes data transfers between registers
•Supports top-down and bottom-up design methodologies
Why Use
Verilog? Applications:

•FPGA and ASIC design


•Digital circuits modeling and verification
Module Syntax:
Basic
•module <module_name> (input/output ports);
Structure of •Declarations, Behavioral or Structural description,
Verilog endmodule

Code Example:

•module AND_gate(input A, input B, output Y);


•assign Y = A & B;
•endmodule
Net Types:

• wire, tri: Used to connect components


Data Types Variable Types:
in Verilog
• reg: Holds values across procedural blocks
• integer: 32-bit signed integer
• real: Real number for testbenches
Operators • Arithmetic: +, -, *, /, %
• Relational: >, <, >=, <=
in Verilog • Logical: &&, ||, !
• Bitwise: &, |, ^, ~
/*
This is an example for Multi-lined comment.
Comments Hello there
*/

//this is an example for single line comment.


//Hello there.
• There are mainly 4 used number systems in
Verilog. They are
• Binary - b or B
• Octal - o or O
• Decimal - d or D
• Hexadecimal - h or H
Numbers • So, numbers are represented in Verilog using
the following format.
<size>'<base><number>. If we didn't
mention the size in Verilog it takes default of
size 32 bits. If both the base and size are not
mentioned it takes default of 32 bits and
decimal number system notation.
• For example: 4'b1100 is same is 4'd12 in
decimal notation.
• 'b0111 is same as
00000000000000000000000000000111
• There are mainly three levels of
abstraction(Different perspectives or views at
which a design can be viewed or analyzed) for
writing in Verilog:
• Gate Level Modeling
• Data-flow Modeling
• Behavioral Modeling
Before diving into the abstraction levels, let's
Abstraction learn what is RTL.

• Register Transfer Level(RTL)


• Register transfer level is a low-level abstraction
used in digital design to describe the behavior
and functionality of a digital circuit or system.
RTL is a general approach that describes
digital circuits in terms of data flow
at register level.
• If a circuit is represented completely using basic gates it is called
gate level modeling. For example, refer the below circuit of half
adder where we can represent it simply using the AND and XOR
gates. This level of abstraction involves describing the circuit
using primitive logic gates such as AND, OR, XOR, etc. This level
provides a detailed representation of the circuit's structure and
logic. Given Below is the RTL Code for Half Adder.

Gate Level Modeling


• In this level of abstraction, we make use of
the functions that define the working of the
circuit instead of its gate structure. This
abstraction level mainly focuses on the flow
of data through the circuit logic gates or
functional expressions.

Data-Flow Modeling
• This is the highest level of abstraction in Verilog. At
this level the designers describe the functionality
of the circuit without specifying the functionality
and structure of digital circuit. This modeling will
be helpful because it focuses on what the circuit
should do rather than how it should be
implemented.

Behavioral Modeling
Sequential Always Block for Sequential Logic:
Circuits in • always @(posedge clock)
Verilog • begin // Sequential logic end

Example: D Flip-Flop
Assign Statement:
Combinatio
nal Circuits • assign Y = A & B;

in Verilog Always Block for Combinational Logic:

• always @(*) // Combinational logic


Behavioral Modeling:
Verilog
Modeling • Describes what the circuit does, not how it's constructed

Styles Structural Modeling:

• Describes actual gate-level construction


Purpose:
Testbenche
• To verify Verilog code functionality by applying inputs and
s in Verilog observing outputs

• Example of a Simple Testbench


Simulation:
Simulation
and • Verifying functionality with testbenches

Synthesis Synthesis:

• Converting Verilog code into hardware (FPGA/ASIC)


Key Takeaways:

• Understand modules, data types, and operators


• Testbenches verify design functionality

Conclusion • Simulation and synthesis convert designs to real hardware


• Verilog is powerful for digital design

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