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Module 7 Verilog Tutorial

The document outlines the course ECI620 on ASIC and FPGA design using Verilog, taught by Dr. Muhammad Awais at COMSATS Institute. It covers various aspects of digital design including the ASIC design flow, Verilog coding styles, module instantiation, data types, and procedural constructs. Key topics include design hierarchy, abstraction levels, and the differences between blocking and non-blocking assignments in Verilog.

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7 views

Module 7 Verilog Tutorial

The document outlines the course ECI620 on ASIC and FPGA design using Verilog, taught by Dr. Muhammad Awais at COMSATS Institute. It covers various aspects of digital design including the ASIC design flow, Verilog coding styles, module instantiation, data types, and procedural constructs. Key topics include design hierarchy, abstraction levels, and the differences between blocking and non-blocking assignments in Verilog.

Uploaded by

Destroyer
Copyright
© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
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Course : ECI620

ASIC AND FPGA DESIGN


Digital Design using Verilog

Instructor: Muhammad Awais (PhD)

Department of Electrical Engineering.


COMSATS Institute of Information Technology, Wah Cantt.
ASIC Design Flow

High level design Low level design

Functional Verification
/ Simulation
RTL Coding

Logic Synthesis

LOGIC CELL

Place and route


Traditional Approaches

Schematic Design
Gate Level Design
Verilog v.s. VHDL
Verilog
Module : The most basic design entry in Verilog is module.
• A module can be a stand alone element or a collection of lower design blocks (modules)

Ports : physical signals that interface the module with


higher level module (or external world)
Design Hierarchy

Top Down Approach Bottom Up Approach


Abstraction Levels
Coding Styles, Design Levels : The way modules are designed in Verilog

Abstraction
Levels

Structural Data Flow Behavioral Mixed


Switch Level
Level Level Level RTL
Module Instantiation Methods
Module Ports
A module interacts with other modules, or outside
world using dedicated signals called ports
Input ports
• In Verilog, any module supports three types of ports
- Input
- Output
-Inout (bidirectional)

Port Connection Rules

Size matching:
The size (no. of bits) of internal
and external ports much match each other
Stimulus (Test bench)
• To check the behavioral functionality of a module, we must write stimulus module
and instantiate the concerned module as UUT (unit under test) in it.
Verilog Lexical Conventions
Verilog Data Types
Three things to know
• What is the data?
• What is the strength?
• What is the data type?
Verilog Data Types
Three things to know
• What is the data?
• What is the strength?
• What is the data type?

• Nets • Registers • Others


• wire • reg • Integer
• tri • real
• trireg • time
•tri0 and tri1 • stime
• supply0 , supply1 • realtime
• wor, wand, trior, triand
Nets
• Nets : nets are declared as wire, means a physical (wire) connection between two pieces
of hardware
• A net does not store value (except for trireg net)
• It must be driven by a driver (e.g. a source or some logic gate)

• If no source is connected, the value on wire is ‘Z’


Advanced Nets
Advanced Nets
Verilog Reg data type
Vectors (multiple data bits)
Arrays
Abstraction Levels (Structural)
Abstraction Levels (Dataflow)
Operators
Operators
Operators
Operators
Operators Precedence Rules
Examples (Data Flow Abstraction)
Abstraction Levels (Behavioral)

Contains procedural structural statements

• always
• initial
Always and Initial blocks
always block initial block
Blocking and Non blocking procedural assignments

blocking assignment Non Blocking assignment

blocking

non blocking
Application of Non blocking procedural assignments
Timing Controls

Delay based timing control


Timing Controls
Event based timing control
An event is the change in the value on a register or net. Events can be used to trigger
Execution of a statement or block of statements
More procedural constructs

Conditional Statements

Case Statements
More procedural constructs
Case Statements

Casex
Verilog Behavioral code examples

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