2-Nov-22 7 Verilog basic language elements Module Module is the fundamental hardware building block in Verilog. Keywords Keywords have a predefined purpose that is understood by Verilog compilers across the board. Eg: wire, module,nand,output
2-Nov-22 8 Key words
2-Nov-22 9 Identifiers An identifier is a unique name, which identifies an object. They are case- sensitive made up of alphanumeric characters, underscore, or a dollar sign. We can start identifiers using alphanumeric or underscore. It’s not possible to name identifiers beginning with a dollar sign since it is reserved for naming system tasks. Also starting with numbers is not advisable.
2-Nov-22 10 Number Specifications There are two types of number specification in Verilog. Sized numbers The size specifies the number of bits in the number. It is written in decimal only. The base format is used for representing which base we use to represent our number. Legal base formats are binary(‘B or ‘b), decimal(‘d or ‘D), octal(‘O or ‘o) or hexadecimal(‘h or ‘H).
2-Nov-22 11 Number Specifications
Sized numbers in Verilog
2-Nov-22 12 Number Specifications
Unsized number Numbers without <size> have a default size of 32 bits. The default size differs depending on the machine and simulator. When no base is specified, it is decimal by default.
2-Nov-22 13 X or Z values For representing ‘unknown’ and ‘high impedance,’ Verilog uses x and z. These are important for modeling real circuits. An x or z sets four bits in the hexadecimal base, three bits in the octal base, and one bit in the binary base.
2-Nov-22 14 Comments • For describing or documenting a model, we use comments. This part of the code will be skipped during execution.
• Comments could be written in two ways. To skip one full line during execution, specify the comment using //. Verilog jumps from that point to the end of the line. • To write multiline comments, start with /* and end it with */.
2-Nov-22 15 Verilog –Levels of Abstraction Levels of abstraction means, the amount of complexity by which a system is viewed or programmed. The higher the level, the less detail. The lower the level, the more detail. There are four levels of abstraction in Verilog. They are • Behavioral level (Design of Algorithm) • Dataflow level (Design of Equation) • Gate level ( Interconnection with logic gates) • Switch level (Implementation in terms of switches).
2-Nov-22 16 Data types Data types in Verilog inform the compiler whether to act as a transmission line (like a wire) or store data (like a flip flop). This depends on what group of data type is declared. There are two groups: NET and REGISTER. Net The entire purpose of an HDL like Verilog is to describe circuits. A Net represents connections between hardware elements. Nets don’t store values. They have the values of the drivers.
• The net out connected to the output is driven by the driving output value A&B. A net data type must be used when a signal is: • Driven by the output of some devices. • Declared as an input or in-out port. • On the left-hand side of a continuous assignment statement. 2-Nov-22 17 Types of Nets wire The keyword wire is the most commonly used net in modeling circuits. When used in the code, it exhibits the same property as an electrical wire used for making connections. module and_gate; input wire A,B; output wire C; assign C = A & B; endmodule
2-Nov-22 18 Types of Nets tri This is another type of net that has identical syntax and function as wire. A wire net can be used for nets that are driven by a single gate or continuous assignment. Whereas, the tri net can be used where multiple drivers drive a net.
A tri state buffer is a gate which functions exactly opposite to the NOT gate: it transfers the signal to the output from the input exactly as it is. These are used to implement delays in circuits.
bufif0(out, in, ctrl);
bufif1(out, 2-Nov-22 in, ctrl); 19 Supply supply0 and supply1 In every circuit, there are two crucial elements – power supply and ground. The supply1 is used to model power supply and the supply0 is for modeling ground. These nets have constant logic values and strength level supply, which is the strongest of all strength levels.
supply1 Vcc; // all nets connected to Vcc are connected to power
supply supply0 GND; // all nets connected to GND are connected to ground
2-Nov-22 20 Variable Datatypes The variable datatypes are responsible for the storage of values in the design. It is used for the variables, whose values are assigned inside the always block. Also, the input port can not be defined as a variable group. reg and integer are examples of the variable data types. For designing purposes, we commonly use reg. In Verilog, the term register means a variable that can hold value. It can retain value until another value is placed. Unlike a net, a register does not need a driver. It doesn’t need a clock as hardware registers do. reg reset // declare a variable reset that can hold it's value initial begin reset = 1'b1; //initialize the reset variable to 1 to reset the digital circuit #10 reset = 1'b0; //After 10 time units, reset is deasserted. end
2-Nov-22 21 Integer, Real and Time Register Data Types Integer An integer is a general-purpose register data type used for manipulating quantities. The integer register is a 32-bit wide data type. The reg store values as unsigned quantities, whereas integer stores signed values. To declare an integer in Verilog, we use the keyword integer integer counter; //general purpose variable used as a counter. initial counter = -1 // A negative one is stored in the counter.
2-Nov-22 22 Integer, Real and Time Register Data Types real The real register is a 64-bit wide data type. In order to store decimal notation(eg 3.14) or scientific notation(eg: 3e6 which is 3 X 106 ), we use the keyword real. Real numbers cannot have a range declaration, and their default value is 0. real delta; // define a real variable called delta initial begin delta = 4e10; //assigned scientific notation delta = 2.13 //assigned a decimal value of 2.13 end If a real value is assigned to an integer, it gets rounded off to the nearest integer. integer i; initial begin i = delta // i gets the value 2 (rounded value of 2.13); end
2-Nov-22 23 Integer, Real and Time Register Data Types Time registers Since timing is an essential factor in designing digital circuits, we need something to keep track of it. Hence, the keyword time helps us to record the simulation time. The default size of time-register is implementation-specific but should be at least 64 bit. To get the current simulation time, the $time system function is invoked. time save_sim_time; //Define a time variable save_sim_time initial begin save_sim_time = $time; // Save the current simulation time. end The realtime register is also a time register which will record current simulation time. Defining the variable irealtime save_sim_time; //nitial begin save_sim_time = $realtime // The system task $realtime will invode real value of the current simulation time end
2-Nov-22 24 Integer, Real and Time Register Data Types Scalar and Vector datatypes 1-bit is declared as a scalar datatype. It has only one bit. When we declare a wire or reg as a scalar, wire n; reg d1;
Vector data types are multi-bit. We either use [<MSB bit number> : <LSB bit number>] or [<LSB bit number> : <MSB bit position>] to represent them. wire [0:3] a; reg [3:0] d0;
2-Nov-22 25 Scalar and Vector data types
2-Nov-22 26 Module declaration The module forms the building block of a Verilog design. A module definition always starts with the keyword module and ends with endmodule. There are five components within a module.
2-Nov-22 27 Module declaration
2-Nov-22 28 Simulator
2-Nov-22 29 Verilog –Levels of Abstraction
Levels of abstraction means, the amount of complexity by which a system is viewed or
programmed. The higher the level, the less detail. The lower the level, the more detail. There are four levels of abstraction in Verilog. They are • Behavioral level (Design of Algorithm) • Dataflow level (Design of Equation) • Gate level / Structural level ( Interconnection with logic gates) • Switch level (Implementation in terms of switches).
2-Nov-22 30 Gate level
Circuits can be defined by use of logic gates.
These gates are predefined in verilog library. Eg. and a1(outputs,inputs) nand a2(outputs,inputs)
• More concerned about the behavior and performance of the algorithm. • It is just like writing the algorithm of a high level language. • Verilog procedural statements are used to model a design at a higher level of abstraction than the other levels. They provide powerful ways of doing complex designs. However small changes n coding methods can cause large changes in the hardware generated.
2-Nov-22 34 Verilog Basic Gates – Data flow Model AND Function
2-Nov-22 48 Full adder Full adder is a three bit adder, which adds two input bits and an input carry bit.
s = a’b’cin + a’b c’in+ab’ c’in+abcin
= (b’c’in+ bcin) a+ (b’cin+bc’in) a’ = (bXORcin)’ a + (bXORcin)a’ { This is of the form P’Q+PQ’ where P = bXORcin and Q = a } = aXORbXORcin
c out= a’bcin+ ab’cin+ abc’in + abcin
= ab+bcin+acin 2-Nov-22 49 Full adder
module full-adder(a,b,cin,s,cout); input a,b, cin; output s,cout; xor sum1(s,a,b,cin); and x1(w1,a,b); and x2(w2,b,cin); and x3(w3,a,cin); or x4(cout,w1,w2,w3); endmodule
2-Nov-22 50 Multiplexer
4:1 Mux
Y= S0’S1’D0+S0’S1D1+S0S1’D2+S0S1D3
2-Nov-22 51 4:1 Multiplexer
module fourto1mux(d0,d1,d2,d3,s0,s1,y); input d0,d1,d2,d3,s0,s1; output y; wire w1,w2,w3,w4; and x1(w1,(~s0),(~s1),d0); and x2(w2,(~S0),S1,d1); and x3(w3,S0,(~s1),d2); and x4(w4,S0,S1,d3); Y= S0’S1’D0+S0’S1D1+S0S1’D2+S0S1D3 or x5(y,w1,w2,w3,w4); endmodule
HW: Write the Verilog Code for 8:1 Mux
2-Nov-22 52 1:4 Demux
2-Nov-22 53 1:4 De Multiplexer
module oneto4demux(I,s1,s0,Y0,Y1,Y2,Y3); input d0,d1,d2,d3,s0,s1; output YO,Y1,Y2,Y3; wire w1,w2; not(w0,s0) not(w1,s1) and x1(Y0,w1,w0,I); and x2(Y1,w1,s0,I); and x3(Y2,w0,s1,I); and x4(Y1,s1,s0,I); endmodule
