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Verilog: Hardware Description Language

Verilog is a hardware description language used to model digital circuits. Some key points: - Verilog models circuits using modules that contain ports, nets, and statements. Modules can be instantiated within other modules to build hierarchies. - It supports different net types like wire, wor, wand for modeling circuit connections. Registers use reg type to model storage elements like counters. - Examples show simple logic gates, multi-level circuits, and hierarchical designs modeled in Verilog. Syntax for module definition, port connections, and constant values is also covered.

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sambhunit
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81 views

Verilog: Hardware Description Language

Verilog is a hardware description language used to model digital circuits. Some key points: - Verilog models circuits using modules that contain ports, nets, and statements. Modules can be instantiated within other modules to build hierarchies. - It supports different net types like wire, wor, wand for modeling circuit connections. Registers use reg type to model storage elements like counters. - Examples show simple logic gates, multi-level circuits, and hierarchical designs modeled in Verilog. Syntax for module definition, port connections, and constant values is also covered.

Uploaded by

sambhunit
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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VERILOG

Hardware Description Language

About Verilog
Along with VHDL, Verilog is among the most widely used HDLs. Main differences:
VHDL was designed to support system-level design and specification. Verilog was designed primarily for digital hardware designers developing FPGAs and ASICs.

The differences become clear if someone analyzes the language features.


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VHDL
Provides some high-level constructs not available in Verilog (user defined types, configurations, etc.).

Verilog
Provides comprehensive support for low-level digital design Not available in native VHDL Range of type definitions and supporting functions (called packages) needs to be included.
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Concept of Verilog Module


In Verilog, the basic unit of hardware is called a module.
Modules cannot contain definitions of other modules. A module can, however, be instantiated within another module. Allows the creation of a hierarchy in a Verilog description.

Basic Syntax of Module Definition


module module_name (list_of_ports); input/output declarations

local net declarations


Parallel statements endmodule
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Example 1 :: simple AND gate


module simpleand (f, x, y); input x, y; output f; assign f = x & y; endmodule

Example 2 :: two-level circuit


module two_level (a, b, c, d, f); input a, b, c, d; output f; wire t1, t2; assign t1 = a & b; assign t2 = ~ (c | d); assign f = t1 ^ t2; endmodule

Example 3 :: a hierarchical design


module add3 (s, cy3, cy_in, x, y); input [2:0] x, y; input cy_in; output [2:0] s; output cy3; wire [1:0] cy_out; add B0 (cy_out[0], s[0], x[0], y[0], cy_in); add B1 (cy_out[1],s[1],x[1],y[1],cy_out[0]); add B2 (cy3, s[2], x[2], y[2], cy_out[1]); endmodule
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Specifying Connectivity
There are two alternate ways of specifying connectivity:
Positional association The connections are listed in the same order add A1 (c_out, sum, a, b, c_in); Explicit association May be listed in any order add A1 (.in1(a), .in2(b), .cin(c_in), .sum(sum), .cout(c_out));
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Variable Data Types


A variable belongs to one of two data types:
Net Must be continuously driven Used to model connections between continuous assignments & instantiations Register Retains the last value assigned to it Often used to represent storage elements
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Net data type


Different net types supported for synthesis: wire, wor, wand, tri, supply0, supply1 wire and tri are equivalent; when there are multiple drivers driving them, the outputs of the drivers are shorted together. wor / wand inserts an OR / AND gate at the connection. supply0 / supply1 model power supply connections.

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module using_wire (A, B, C, D, f); input A, B, C, D; output f; wire f; // net f declared as wire assign f = A & B; assign f = C | D; endmodule

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module using_wired_and (A, B, C, D, f); input A, B, C, D; output f; wand f; // net f declared as wand assign f = A & B; assign f = C | D; endmodule

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module using_supply_wire (A, B, C, f); input A, B, C; output f; supply0 gnd; supply1 vdd; nand G1 (t1, vdd, A, B); xor G2 (t2, C, gnd); and G3 (f, t1, t2); endmodule
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Register data type


Different register types supported for synthesis: reg, integer The reg declaration explicitly specifies the size. reg x, y; // single-bit register variables reg [15:0] bus; // 16-bit bus, bus[15] MSB For integer, it takes the default size, usually 32-bits. Synthesizer tries to determine the size.
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Other differences:
In arithmetic expressions, An integer is treated as a 2s complement signed integer. A reg is treated as an unsigned quantity. General rule of thumb reg used to model actual hardware registers such as counters, accumulator, etc. integer used for situations like loop counting.
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module simple_counter (clk, rst, count); input clk, rst; output count; reg [31:0] count;
always @(posedge clk) begin if (rst) count = 32b0; else count = count + 1; end endmodule
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When integer is used, the synthesis system often carries out a data flow analysis of the model to determine its actual size.
Example: wire [1:10] A, B; integer C; C = A + B;

The size of C can be determined to be equal to 11 (10 bits plus a carry).


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Specifying Constant Values


A value may be specified in either the sized or the un-sized form. Syntax for sized form: <size><base><number> Examples: 8b01110011 // 8-bit binary number 12hA2D // 1010 0010 1101 in binary 12hCx5 // 1100 xxxx 0101 in binary 25 // signed number, 32 bits 1b0 // logic 0 1b1 // logic 1
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