Verilog Basics

Hardware Description Language -

Introduction
• HDL is a language that describes the hardware of digital
systems in a textual form.
• It resembles a programming language, but is specifically
oriented to describing hardware structures and behaviors.
• The main difference with the traditional programming
languages is HDL’s representation of extensive parallel
operations whereas traditional ones represents mostly serial
operations.
• The most common use of a HDL is to provide an alternative to
schematics.
 HDL – Introduction (2)

• When a language is used for the above purpose (i.e. to

provide an alternative to schematics), it is referred to as a
structural description in which the language describes an
interconnection of components.
• Such a structural description can be used as input to logic
simulation just as a schematic is used.
• Models for each of the primitive components are
required.
• If an HDL is used, then these models can also be written in
the HDL providing a more uniform, portable
representation for simulation input.
 HDL – Introduction (3)
• HDL can be used to represent logic diagrams,
Boolean expressions, and other more complex digital
circuits.
• Thus, in top down design, a very high-level
description of a entire system can be precisely
specified using an HDL.
• This high-level description can then be refined and
partitioned into lower-level descriptions as a part of
the design process.
 HDL – Introduction (4)
• As a documentation language, HDL is used to represent and
document digital systems in a form that can be read by both
humans and computers and is suitable as an exchange
language between designers.
• The language content can be stored and retrieved easily and
processed by computer software in an efficient manner.
• There are two applications of HDL processing: Simulation and
Synthesis
 Logic Simulation
• A simulator interprets the HDL description and produces a
readable output, such as a timing diagram, that predicts
how the hardware will behave before its is actually
fabricated.
• Simulation allows the detection of functional errors in a
design without having to physically create the circuit.
 Logic Simulation (2)
• The stimulus that tests the functionality of the design is called
a test bench.
• To simulate a digital system
– Design is first described in HDL
– Verified by simulating the design and checking it with a test bench
which is also written in HDL.
 Logic Simulation
• Logic simulation is a fast,
accurate method of
analyzing a circuit to see its
waveforms
 Types of HDL
• There are two standard HDL’s that are supported by IEEE.
– VHDL (Very-High-Speed Integrated Circuits Hardware
Description Language) - Sometimes referred to as VHSIC
HDL, this was developed from an initiative by US. Dept. of
Defense.
– Verilog HDL – developed by Cadence Data systems and
later transferred to a consortium called Open Verilog
International (OVI).
 Verilog
• Verilog HDL has a syntax that describes precisely the legal
constructs that can be used in the language.
• It uses about 100 keywords pre-defined, lowercase, identifiers
that define the language constructs.
• Example of keywords: module, endmodule, input, output wire,
and, or, not , etc.,
• Any text between two slashes (//) and the end of line is
interpreted as a comment.
• Blank spaces are ignored and names are case sensitive.
 Verilog - Module
• A module is the building block in Verilog.
• It is declared by the keyword module and is always
terminated by the keyword endmodule.
• Each statement is terminated with a semicolon, but there
is no semi-colon after endmodule.
 Verilog – Module (2)
HDL Example
module smpl_circuit(A,B,C,x,y);
input A,B,C;
output x,y;
wire e;
and g1(e,A,B);
not g2(y,C);
or g3(x,e,y);
endmodule
 Verilog – Gate Delays
• Verilog simulation depends on how time is defined because
the simulator needs to know what a #1 means in terms of
time. The `timescale compiler directive specifies the time
unit and precision for the modules that follow it.
• Sometimes it is necessary to specify the amount of delay
from the input to the output of gates.
• In Verilog, the delay is specified in terms of time units and
the symbol #.
• The association of a time unit with physical time is made
using timescale compiler directive.
• Compiler directive starts with the “backquote (`)” symbol.
`timescale 1ns/100ps
• The first number specifies the unit of measurement for time
delays.
• The second number specifies the precision for which the
delays are rounded off, in this case to 0.1ns.
 Syntax
• `timescale <time_unit>/<time_precision>
// Example
– `timescale 1ns/1ns
– `timescale 10ns/1ns
– `timescale 1ns/1ps

See timescale.pdf
 Verilog – Module (4)
//Description of circuit with delay
module circuit_with_delay (A,B,C,x,y);
input A,B,C;
output x,y;
wire e;
and #(30) g1(e,A,B);
or #(20) g3(x,e,y);
not #(10) g2(y,C);
endmodule
 Operators
• There are three types of operators: unary,
binary, and ternary or conditional.
– Unary operators shall appear to the left of their
operand
– Binary operators shall appear between their
operands
– Conditional operators have two separate
operators that separate three operands
 Arithmetic Operators
• These perform arithmetic operations. The + and -
can be used as either unary (-z) or binary (x-y)
operators.
• Operators Example
parameter n = 4;
+ (addition) reg[3:0] a, c, f, g, count;
f = a + c;
- (subtraction) g = c - n;
count = (count +1)%16; //Can count 0 thru 15.
* (multiplication)
/ (division)
% (modulus)
 Relational Operators
• Relational operators compare two operands and return a
single bit 1or 0. These operators synthesize into comparators.
• Wire and reg variables are positive Thus (-3’b001) = = 3’b111
and (-3d001)>3d110. However for integers -1< 6.

Operators
Example
< (lessthan)
if (x = = y) e = 1;
<= (less than or equal to)
else e = 0;
> (greaterthan)
// Compare in 2’s compliment; a>b
>= (greater than or equal to)
reg [3:0] a,b;
== (equal to)
if (a[3]= = b[3]) a[2:0] > b[2:0];
!= (not equal to)
else b[3];
 Bit-wise Operators
• Bit-wise operators do a bit-by-bit comparison
between two operands
Operators Example
~ (bitwiseNOT) module and2 (a, b, c);
& (bitwiseAND) input [1:0] a, b;
| (bitwiseOR) output [1:0] c;
^ (bitwiseXOR) assign c = a & b;
~^ or ^~(bitwise XNOR) endmodule
 Logical Operators
• Logical operators return a single bit 1 or 0. They are the same
as bit-wise operators only for single bit operands.
• They can work on expressions, integers or groups of bits, and
treat all values that are nonzero as “1”.
• Logical operators are typically used in conditional (if ... else)
statements since they work with expressions.
Example
Operators
wire[7:0] x, y, z; // x, y and z are multibit variables.
! (logicalNOT)
reg a;
&& (logical AND)
...
|| (logical OR)
if ((x == y) && (z)) a = 1; // a = 1 if x equals y, and z is nonzero.
else a = !x; // a =0 if x is anything but zero.
 Reduction Operators
• Reduction operators operate on all the bits of an operand
vector and return a single-bit value. These are the unary (one
argument) form of the bit-wise operators above.

Operators Example
& (reductionAND) module chk_zero (a, z);
| (reductionOR) input [2:0] a;
~& (reduction NAND) output z;
~| (reduction NOR) assign z = ~| a; // Reduction NOR
^ (reductionXOR) endmodule
~^ or ^~(reduction XNOR)
 Number Format
• We are most familiar with numbers being
represented as decimals.
• However, numbers can also be represented in binary,
octal and hexadecimal.
• By default, Verilog simulators treat numbers as
decimals. In order to represent them in a different
radix, certain rules have to be followed.
16 // Number 16 in decimal
0x10 // Number 16 in hexadecimal
10000 // Number 16 in binary
20 // Number 16 in octal
 Sized
• Sized numbers are represented as shown below, where size is
written only in decimal to specify the number of bits in the
number.

[size]'[base_format][number]

• base_format can be either decimal ('d or 'D), hexadecimal ('h

or 'H) and octal ('o or 'O) and specifies what base the number
part represents.

• number is specified as consecutive digits from 0, 1, 2 ... 9 for

decimal base format and 0, 1, 2 .. 9, A, B, C, D, E, F for
hexadecimal.
16'hcafe; // lowercase letters Valid
16'hCAFE; // uppercase letters Valid
32'h1D40_CAFE; // underscore can be used as separator
between 4 letters Valid
 unsized
• Numbers without a base_format specification
are decimal numbers by default.
• Numbers without a size specification have a
default number of bits depending on the type
of simulator and machine.
integer a = 5423; // base format is not specified, a get the decimal value of 5423
integer a = 'h1AD7; // size is not specified, because a is int (32 bit) value stored in a
= 32’h0000_1AD7
 Negative
• Negative numbers are specified by placing a minus - sign
before the size of a number.
• It is illegal to have a minus sign between base_format and
number.

-6'd3; // legal

8'd-4; // Illegal
 Identifiers
• Identifiers are names of variables so that they can be
referenced later on.
• They are made up of alphanumeric characters [a-z][A-Z][0-9] ,
underscores _ or dollar sign $ and are case sensitive.
• They cannot start with a digit or a dollar sign.
 Keywords
• Keywords are special identifiers reserved to
define the language constructs and are in
lower case. A list of important keywords is
given below.
 Data Types
• Value Set: Verilog consists of only four basic
values. Almost all Verilog data types store all
these values:
– 0 (logic zero, or false condition)
– 1 (logic one, or true condition)
– x (unknown logic value) x and z have limited use
for synthesis.
– z (high impedance state)
 integer
• Integers are general-purpose variables.
• they are used mainly loops-indicies, parameters, and
constants.
• They are of implicitly of type reg. However they store data as
signed numbers
• whereas explicitly declared reg types store them as unsigned.

Example
integer a; // single 32-bit integer
assign b=63; // 63 defaults to a 7-bit variable.
 Reg
• Declare type reg for all data objects on the left hand side of
expressions in inital and always procedures, or functions.
• A reg is the data type that must be used for latches, flip-flops
and memory.
• However it often synthesizes into leads rather than storage.
• In multi-bit registers, data is stored as unsigned numbers and
no sign extension is done for what the user might have
thought were two’s complement numbers.
Example
reg a; // single 1-bit register variable
reg [7:0] tom; // an 8-bit vector; a bank of 8 registers.
reg [5:0] b, c; // two 6-bit variables
 Wire
• A wire represents a physical wire in a circuit and
is used to connect gates or modules.
• The value of a wire can be read, but not assigned
to, in a function or block.
• A wire does not store its value but must be
driven by a continuous assignment statement or
by connecting it to the output of a gate or
module
• Ex wire out;
 Time
• Time is a 64-bit quantity that can be used in
conjunction with the $time system task to
hold simulation time.
• Time is not supported for synthesis and hence
is used only for simulation purposes.
Example
time c;
c = $time; // c = current simulation time
 Scalar and Vector
• A reg declaration without a range specification
is considered 1-bit wide and is a scalar.
• If a range is specified, then the reg becomes a
multibit entity known as a vector.
• The range gives the ability to address
individual bits in a vector.
• The most significant bit of the vector should
be specified as the left hand value in the range
while the least significant bit of the vector
should be specified on the right.
wire o_nor; // single bit scalar net
wire [7:0] o_flop; // 8-bit vector net
reg parity; // single bit scalar variable
reg [31:0] addr; // 32 bit vector variable
 Bit-selects
• Any bit in a vectored variable can be individually
selected and assigned a new value as shown below.
This is called as a bit select.
• If the bit-select is out of bounds or the bit-select is x
or z, then the value returned will be x.
Blocking
blocking
Non blocking
Non blocking
 Verilog – Module (14)

• A module can be described in any one (or a

combination) of the following modeling techniques.
– Gate-level modeling using instantiation of primitive gates
and user defined modules.
• This describes the circuit by specifying the gates and how they
are connected with each other.
– Dataflow modeling using continuous assignment
statements with the keyword assign.
• This is mostly used for describing combinational circuits.
– Behavioral modeling using procedural assignment
statements with keyword always.
• This is used to describe digital systems at a higher level of
abstraction.
 Gate-Level Modeling
• Here a circuit is specified by its logic gates and their
interconnections.
• It provides a textual description of a schematic diagram.
• Verilog recognizes 12 basic gates as predefined primitives.
– 4 primitive gates of 3-state type.
– Other 8 are: and, nand, or, nor, xor, xnor, not, buf
• When the gates are simulated, the system assigns a four-
valued logic set to each gate – 0,1,unknown (x) and high
impedance (z)
 Gate-level modeling (2)
• When a primitive gate is incorporated into a
module, we say it is instantiated in the module.
• In general, component instantiations are
statements that reference lower-level
components in the design, essentially creating
unique copies (or instances) of those components
in the higher-level module.
• Thus, a module that uses a gate in its description
is said to instantiate the gate.
 Gate-level Modeling (3)

• Modeling with vector data (multiple bit widths):

– A vector is specified within square brackets and two
numbers separated with a colon.
e.g. output[0:3] D; - This declares an output vector
D with 4 bits, 0 through 3.
wire[7:0] SUM; – This declares a wire vector
SUM with 8 bits numbered 7 through 0.
The first number listed is the most significant bit of the
vector.
 Gate-level Modeling

• Two or more modules can be combined to build a

hierarchical description of a design.
• There are two basic types of design methodologies.
– Top down: In top-down design, the top level block is defined and
then sub-blocks necessary to build the top level block are
identified.
– Bottom up: Here the building blocks are first identified and then
combine to build the top level block.
• In a top-down design, a 4-bit binary adder is defined as
top-level block with 4 full adder blocks. Then we describe
two half-adders that are required to create the full adder.
• In a bottom-up design, the half-adder is defined, then the
full adder is constructed and the 4-bit adder is built from
the full adders.
 Gate-level Modeling

• A bottom-up hierarchical description of a 4-bit

adder is described in Verilog as
– Half adder: defined by instantiating primitive gates.
– Then define the full adder by instantiating two half-
adders.
– Finally the third module describes 4-bit adder by
instantiating 4 full adders.
• Note: In Verilog, one module definition cannot be
placed within another module description.