Intro To HDL Midterm
Intro To HDL Midterm
Intro To HDL Midterm
Introduction to HDL
Hardware Description Language - Introduction
•When a language is used for the above purpose (i.e. to provide an alternative
to schematics), it is referred to as a structural description in which the language
describes an interconnection of components.
•Such a structural description can be used as input to logic simulation just as a
schematic is used.
•Models for each of the primitive components are required.
•If an HDL is used, then these models can also be written in the HDL providing
a more uniform, portable representation for simulation input.
HDL – Introduction (3)
•HDL can be used to represent logic diagrams, Boolean expressions, and other
more complex digital circuits.
•Thus, in top down design, a very high-level description of a entire system can
be precisely specified using an HDL.
•This high-level description can then be refined and partitioned into lower-
level descriptions as a part of the design process.
HDL – Introduction (4)
•The stimulus that tests the functionality of the design is called a test bench.
•To simulate a digital system
• Design is first described in HDL
• Verified by simulating the design and checking it with a test bench which is also written
in HDL.
Logic Simulation
•Verilog HDL has a syntax that describes precisely the legal constructs that can
be used in the language.
•It uses about 100 keywords pre-defined, lowercase, identifiers that define the
language constructs.
•Example of keywords: module, endmodule, input, output wire, and, or, not ,
etc.,
•Any text between two slashes (//) and the end of line is interpreted as a
comment.
•Blank spaces are ignored and names are case sensitive.
Verilog - Module
HDL Example
module smpl_circuit(A,B,C,x,y);
input A,B,C;
output x,y;
wire e;
and g1(e,A,B);
not g2(y,C);
or g3(x,e,y);
endmodule
Verilog – Gate Delays
•In order to simulate a circuit with HDL, it is necessary to apply inputs to the
circuit for the simulator to generate an output response.
•An HDL description that provides the stimulus to a design is called a test
bench.
•The initial statement specifies inputs between the keyword begin and end.
•Initially ABC=000 (A,B and C are each set to 1’b0 (one binary digit with a
value 0).
•$finish is a system task.
Verilog – Module (6)
Bitwise operators
• Bitwise NOT : ~
• Bitwise AND: &
• Bitwise OR: |
• Bitwise XOR: ^
• Bitwise XNOR: ~^ or ^~
Verilog – Module (8)
Boolean Expressions:
•These are specified in Verilog HDL with a continuous assignment
statement consisting of the keyword assign followed by a Boolean
Expression.
•The earlier circuit can be specified using the statement:
assign x = (A&B)|~C)
E.g. x = A + BC + B’D
y = B’C + BC’D’
Verilog – Module (9)
UDP features ….
•UDP’s do not use the keyword module. Instead they are declared
with the keyword primitive.
• There can be only one output and it must be listed first in the
port list and declared with an output keyword.
•There can be any number of inputs. The order in which they are
listed in the input declaration must conform to the order in which
they are given values in the table that follows.
Verilog – Module (12)
//User defined primitive(UDP)
primitive crctp (x,A,B,C);
output x;
input A,B,C;
//Truth table for x(A,B,C) = Minterms (0,2,4,6,7)
table
// A B C : x (Note that this is only a comment)
0 0 0 : 1;
0 0 1 : 0; // Instantiate primitive
0 1 0 : 1;
module declare_crctp;
0 1 1 : 0;
1 0 0 : 1; reg x,y,z;
1 0 1 : 0;
1 1 0 : 1; wire w;
1 1 1 : 1; crctp (w,x,y,z);
endtable
endprimitive endmodule
Week 3-4
Gate Level Modeling
Gate-Level Modeling
•Three-state gates have a control input that can place the gate into a high-
impedance state. (symbolized by z in HDL).
•The bufif1 gate behaves like a normal buffer if control=1. The output goes to
a high-impedance state z when control=0.
•bufif0 gate behaves in a similar way except that the high-impedance state
occurs when control=1
•Two not gates operate in a similar manner except that the o/p is the
complement of the input when the gate is not in a high impedance state.
•The gates are instantiated with the statement
• gate name (output, input, control);
Three-State Gates
• Concatenations are used to combine data, the above example does bit wise
or of in0 and {in1 [2:0], in2} which essentially means that
• o0 = in0 [0]*in2; o1 = in0 [1]*in1 [0];
• o2 = in0 [2]*in1 [1]; o3 = in0 [3]*in1 [2];
Implicit Continuous Assignment
• Here we have declared the out wire and assigned the in0^in1 to it, we can
achieve the same with
• There are three types of delays associated with dataflow modeling. They
are: Normal/regular assignment delay, implicit continuous assignment delay
and net declaration delay.
Normal/regular assignment delay
• This delay is applicable when the signal in LHS is already defined and this
delay represents the delay in changing the value of the already declared
net. Assign #10 out = in0 | in1;
• If there is any change in the operands in the RHS, then RHS expression will
be evaluated after 10 units of time and evaluated expression will be
assigned to LHS. Let’s say that at time t, if there is change in one of the
operands in the above example, then the expression is calculated at t+10
units of time. It means that if in0 or in1 changes value again before 10 time
units than the values of in1 and in2 at the time of re- computation (t+10)
are considered.
Implicit continuous assignment delay
• Wire out;
• Assign #10 out = in0 ^ in1;
Net declaration delay
• In this case the delay is associated with net instead of the assignment. If any
changes applied to net is delayed according to this delay.
• Wire #10 out; Assign out = in; Is same as Wire out;
• Assign #10 out = in;
Operators
• An initial block starts at simulation time 0 and executes exactly once during
simulation
• It is used to initialize signals or to monitor waveforms
• The syntax is as follows:
initial [timing_control] procedural statement
• The procedural statement could be any of the following:
❑ Selection statement
❑ Case statement
❑ Loop statement
Initial Block
• Delay timing control specifies the time duration when the statement is
encountered and when the statement is executed
• It is specified by “#” and has the following form:
#delay_value
• Delay timing control can be divided into two types depending on the
position of the delay specifier in the statement
❑ Regular delay control
❑ Intra-assignment delay control
Regular Delay Control
1. Obtain either the state diagram or the state table from the statement of
the problem.
2. If only a state diagram is available from step 1, obtain state table.
3. Assign binary codes to the states.
4. Derive the flip-flop input equations from the next-state entries in the
encoded state table.
5. Derive output equations from the output entries in the state table.
6. Simplify the flip-flop input and output equations.
7. Draw the logic diagram with D flip-flops and combinational gates, as
specified by the flip-flop I/O equations.
Behavioral Modeling in SSD
• There are two kinds of behavioral statements in Verilog HDL: initial and
always.
• The initial behavior executes once beginning at time=0.
• The always behavior executes repeatedly and re-executes until the
simulation terminates.
• A behavior is declared within a module by using the keywords initial or
always, followed by a statement or a block of statements enclosed by the
keywords begin and end.
Behavioral Modeling in SSD
initial begin
clock = 1’b0;
repeat (30);
#10 clock = ~clock;
end
initial begin
clock = 1’b0;
#300 $finish;
end
always #10 clock = ~clock
Behavioral Modeling in SSD
initial begin
clock = 1’b0;
repeat (30);
#10 clock = ~clock;
end
initial begin
clock = 1’b0;
#300 $finish;
end
always #10 clock = ~clock
Behavioral Modeling in SSD
• The always statement can be controlled by delays that wait for a certain
time or by certain conditions to become true or by events to occur.
• This type of statement is of the form: always @ (event control expression)
•The statements within the block, after the event control expression, execute
sequentially and the execution suspends after the last statement has executed.
•Then the always statement waits again for an event to occur.
Two kind of events:
• Level sensitive (E.g. in combinational circuits and in latches)
always @(A or B or Reset) will cause the execution of the procedural statements in the
always block if changes occur in A or B or Reset.
• Edge-triggered (In synchronous sequential circuits, changes in flip-flops must occur only
in response to a transition of a clock pulse.
always @(posedge clock or negedge reset)will cause the execution of the procedural
statements only if the clock goes through a positive transition or if the reset goes through
a negative transition.
Behavioral Modeling in SSD
module D_latch(Q,D,control);
output Q;
input D,control;
reg Q;
always @(control or D)
if(control) Q = D; //Same as: if(control=1)
endmodule
Flip-Flops and Latches
D Flip-Flop with
Asynchronous
Reset
T & J-K Flip-Flops
T & J-K Flip-Flops
//T flip-flop from D flip-flop and gates //JK flip-flop from D flip-flop and gates
module TFF (Q,T,CLK,RST); module JKFF (Q,J,K,CLK,RST);
output Q; output Q;
input T,CLK,RST; input J,K,CLK,RST;
wire DT; wire JK;
assign DT = Q ^ T ; assign JK = (J & ~Q) | (~K & Q);
//Instantiate the D flip-flop //Instantiate D flipflop
DFF TF1 (Q,DT,CLK,RST); DFF JK1 (Q,JK,CLK,RST);
endmodule endmodule