Lecture: Verilog HDL

Dr. Manish Patel

 Outline
• Case Study: Test-bench from X student
• HDL
• VHDL vs. Verilog
• Different Modelling Styles
• Example: Counter, Mux
`timescale 1ns / 1ps
module top;

//declare testbench variables

reg A_input, B_input, C_input;
wire Sum, C_output;

//instantiate the design module and connect to the testbench variables

full_adder instantiation(.A(A_input), .B(B_input), .Cin(C_input), .S(Sum),
.Cout(C_output));

initial
begin
//set stimulus to test the code
A_input=0;
B_input=0;
C_input=0;
#100 $finish;
end

//provide the toggling input (just like truth table input)

//this acts as the clock input
always #4 A_input=~A_input;
always #2 B_input=~B_input;
always #1 C_input=~C_input;
`timescale 1ns / 1ps
module code_convert_tb;
//declare testbench variables
reg [6:0]I;
wire [2:0]O;
//instantiate the design module and connect to the testbench variables
code_convert instantiation(I,O);
initial
begin
//set stimulus to test the code
//I=0;
#10 I=7'b0000001;
#20 I=7'b0000010;
#30 I=7'b0000100;
#40 I=7'b0010000;
#50 I=7'b0100000;
#60 $finish;
end
endmodule
 Port Connection Rule
Two parts of a port:
– internal to module (when defining the module)
– external to module (when instantiating the module)

External to module External to module

Internal to
module
 HDL
• Traditional PL: Sequential process
• HDL: Characteristics of digital hardware
– Connections of parts
– Concurrent operations
– Concept of propagation delay and timing
 Popularity of Verilog HDL
• Verilog HDL
– General-purpose
– Easy to learn, easy to use
– Similar in syntax to C
– Allows different levels of abstraction and mixing them
– Supported by most popular logic synthesis tools
– Post-logic-synthesis simulation libraries by all
fabrication vendors
 Alternative of Verilog® HDL
• VHDL
– VHSIC (Very High Speed Integrated Circuit)
Hardware Description Language
– Developed under contract from DARPA
– IEEE standard
– Public domain
– Other EDA vendors adapted VHDL
 VHDL vs. Verilog

Behavioral

Dataflow
VHDL
Structural Verilog
& Gate

Switch
 VHDL vs. Verilog
• Ada based • C and Ada
constructs constructs
• High level: system • Low Level: Gate &
descriptor structural descriptor
• Mostly in America, • Mostly in Europe
Japan….
 Definition of Module
• Interface: port and parameter declaration
• Body: Internal part of module
• Add-ons (optional)
 Some points to remember
• The name of Module

• Comments in Verilog
– One line comment (// ………….)
– Block Comment (/*…………….*/)

• Description of Module (optional but

suggested)
 List of Ports
• Example: 4-bit full-adder

module fulladd4(sum, c_out, a, b, c_in);

output [3:0] sum;
output c_out;

input [3:0] a, b;
input c_in;
...
endmodule
Module Interface – ALU ?
Behavioural Modelling
Behavioural Modelling of Mux
 Lexical Conventions: Numbers
 General syntax: <size>’<base><number>
 <size> :
number of bits (in decimal)
 <base> :
– d or D for decimal (radix 10)
– b or B for binary (radix 2)
– o or O for octal (radix 8)
– h or H for hexadecimal (radix 16)
 <number> :
is the number in radix <base>
 Examples:
– 4’b1111
– 12’habc
– 16’d255
Lexical Conventions: Numbers

• Underscore character
– Use ‘_’ to improve readability, not at
starting
• 12’b1111_0000_1010
Structural Modelling
Structural Modelling
Structural Modelling of Mux
Primitive Gates
Dataflow Modelling
Dataflow Modelling for Mux
 Lexical Conventions
• Very similar to C
– Verilog is case-sensitive
– All keywords are in lowercase
– A Verilog program is a string of tokens which can
be:
• Whitespace
• Comments
• Numbers
• Strings
• Identifiers
• Keywords
 Outline
• Lexical Conventions in Verilog HDL
• Whitespace, comments, number specification,
string, operators, identifiers
• Logic Values
• Data Types in Verilog HDL
• Value set and strengths
• Nets and Registers
• Vectors
• Integer, Real, and Time Register Data Types
• Arrays, Memories, Parameters and Strings
 Lexical Conventions
• Very similar to C
– Verilog is case-sensitive
– All keywords are in lowercase
– A Verilog program is a string of tokens which can
be:
• Whitespace
• Comments
• Numbers
• Strings
• Keywords
• Identifiers
 Lexical Conventions (cont’d)
• Number Specification
– Sized numbers
– Unsized numbers
– Unknown and high-impedance values
– Negative numbers
 Lexical Conventions (cont’d)
 Sized numbers
o General syntax: <size>’<base><number>
 <size> :
number of bits (in decimal)
 <base> :
– d or D for decimal (radix 10)
– b or B for binary (radix 2)
– o or O for octal (radix 8)
– h or H for hexadecimal (radix 16)
 <number> :
is the number in radix <base>
 Examples:
– 4’b1111
– 12’habc
– 16’d255
 Lexical Conventions (cont’d)
Unsized numbers
o Default base is decimal
o Default size is at least 32
o Examples:
 23232
 ’habc
 ’o234
o Examples:
 23232 //32-bit decimal no
 ’habc //32-bit hex no
 ’o234 //32-bit octal no
Lexical Conventions (cont’d)
X or Z values
– Unknown value: lowercase x
• 4 bits in hex, 3 bits in octal, 1 bit in binary
– High-impedance value: lowercase z
• 4 bits in hex, 3 bits in octal, 1 bit in binary

– Examples:
• 12’h13x //this is 12-bit hex
• 6’ox //this is 6-bit octal no -> xxxxxx
• 32’bz //this is 32-bit high impedance no
 Value Set

Value level HW Condition

0 Logic zero, false
1 Logic one, true
x Unknown
z High imp., floating
Value Set
 Lexical Conventions (cont’d)
• Negative numbers
– Put the sign before the <size>
– Two’s complement is used to store the
value
– Examples:
• -6’d3 //6-bit negative no 2’s
complement form
• 4’d-2 // illegal
• -6’sd3 //used for performing signed
integer math
 Lexical Conventions (cont’d)
• Operators
– Unary
a = ~b;
– Binary
a = b && c;
– Ternary
a = b ? c : d; // the only ternary operator
Operators
 Lexical Conventions (cont’d)
• Identifiers and keywords
– identifiers
• Names given to objects for references in the
design
• Alphanumeric characters, ‘_’, and ‘$’
• Are case sensitive
• Should start with an alphabetic character or ‘_’
• Only system tasks can start with ‘$’
– Examples:
reg value;
input clk;
input clock, in1
 Keywords
• Identifiers and keywords
– keywords
• Special identifiers reserved to define the
language construct
• Lowercase only
Keywords
 Data Types
• Value set and Strength levels
• Nets and Registers
• Vectors
• Integer, Real, and Time Register Data
Types
• Arrays
• Memories
• Parameters
• Strings
 Value Set
• Hardware modeling requirements
– Value Level – Verilog supports - 4
– Value Strength – Verilog supports – 8
• Used to resolve conflict between drivers of
different strength
• Used to accurately model
– Signal contention
– MOS devices
– Dynamic MOS
– Other low-level details/devices
 Value Set

Value level HW Condition

0 Logic zero, false
1 Logic one, true
x Unknown
z High imp., floating
High Impedance Logic
 Strength Levels
Strength Type Degree Data Type
level
supply Driving Strongest
strong Driving
pull Driving
large Storage only trireg
weak Driving
medium Storage only trireg
small Storage only trireg
highz High Weakest
Impedance
 Net Data Type
• Used to represent connections between HW elements
– Values continuously driven on nets
• Continuous assignment (assign)
• Module or gate instantiation (output ports)
• Keyword: wire
– Default: One-bit values
• unless declared as vectors
– Default value: z
– Examples
• wire a;
• wire b, c;
• wire d=1’b0; //net d fixed to logic value 0
 Register Data Types
• Registers represent data storage elements
– Retain value until next assignment
– Similar to “variables” in other high level language
– NOTE: this is not a hardware register or flipflop
– Keyword: reg
– Default value: x
– Example:
reg reset;
initial
begin
reset = 1’b1;
#100 reset=1’b0;
End
Register Data Types (continue)
• Registers can also be declared as signed
variable
• Such registers can be used for signed
arithmetic
• Example:
– reg signed [63:0] m //64-bit signed value
 Vectors
• Vector ≡ Multiple-bit width data
• Applicable to both net and register data types

• Syntax:
– wire/reg [msb_index : lsb_index] data_id;
• Example
wire a;
wire [7:0] bus;
wire [31:0] busA, busB, busC;
reg clock;
reg [0:40] virtual_addr;
Vectors( cont’d) Variable Vector
Part Select
• Consider
wire [7:0] bus;
wire [31:0] busA, busB, busC;
reg [0:40] virtual_addr;

• Bit-select and part-select allowed:

busA[7]
bus[2:0] // three least-significant bits of bus
bus[0:2] // illegal
virtual_addr[0:1] /* two most-significant bits * of virtual_addr */
 Vectors( cont’d) Variable Vector Part Select

o reg [255:0] data1; //Little endian notation

o reg [0:255] data2; //Big endian notation
o reg [7:0] byte;

data1 255 to 248 …. 31 to 24 …. 7 to 0

//Using a variable part select, one can choose parts

o byte = data1[31-:8]; //starting bit = 31, width =8 => data1[31:24]
o byte = data1[24+:8]; //starting bit = 24, width =8 => data1[31:24]
o byte = data2[31-:8]; //starting bit = 31, width =8 => data2[24:31]
o byte = data2[24+:8]; //starting bit = 24, width =8 => data2[24:31]

data2 0 to 7 …. 24 to 31 …. 248 to 255

 Vectors( cont’d) Variable Vector Part Select

//The starting bit can also be a variable. The width has

//to be constant. Therefore, one can use the variable
//part select in a loop to select all bytes of the vector.

for (j=0; j<=31; j=j+1)

byte = data1[(j*8)+:8];

//Sequence is [7:0], [15:8]... [255:248]

//Can initialize a part of the vector data1 [(byteNum*8)+:8] = 8'b0;

//If byteNum = 1, clear 8 bits [15:8]
 Examples: Nets and Registers
 Wires and registers can be bits, vectors, and
arrays

wire a; // Simple wire

tri [15:0] dbus;// 16-bit tristate bus
tri #(5,4,8) b; // Wire with delay
reg [-1:4] vec; // Six-bit register

integer imem[0:1023]; // Array of 1024 integers

reg [31:0] dcache[0:63]; // A 32-bit memory
 Register Data Types (cont’d)
• Integer
– Keyword: integer
– Very similar to a vector of reg
• For manipulating quantities
• integer variables are signed numbers
• reg vectors are unsigned numbers, unless specified
– reg signed [63:0] m; // 64 bit signed value
– Bit width: implementation-dependent (at least 32-bits)
• Designer can also specify a width:
integer [7:0] tmp;
– Examples:
integer counter;
Initial
counter = -1;
 Register Data Types (cont’d)
• Real
– Keyword: real
– Real no constant and real register
– Values:
• Decimal notation: 12.24
• Scientific notation: 3e6 (=3x106)
• Default value: 0
 Register Data Types (cont’d)
• Real
– Cannot have range declaration
– When assigned to integer => the real no is rounded
off to the nearest integer
– Example:
real delta;
initial
begin
delta = 4e10;
delta = 2.13;
End

integer i;
initial
i = delta; // i gets the value 2 (rounded value of 2.13)
 Register Data Types (cont’d)
• Time
o Verilog simulation is done with respect to simulation time
o Used to store values of simulation time
o time register data type
o Keyword: time
o Bit width: implementation-dependent (at least 64)
o $time system function gives current simulation time
o Example:
time save_sim_time;
initial
save_sim_time = $time;
 Arrays
• Data types: wire, reg, integer, time, real,
realtime and vector register etc..
• Single dimensional array
• Multi-dimensional array is also possible
• Syntax:
<data_type> <array_var_name> [start_idx : end_idx]
[start_idx : end_idx] ...
[start_idx : end_idx];
• Access:
<array_name> [<subscrip/index>]
For multidimensional indexes for each dimension
 Arrays
• Examples:
integer count [0:7]; //array of 8 count variable
reg bool [31:0]; // array of 32 one-bit boolean
time chk_point [1:100];
integer matrix[4:0][0:16]; //two dimentional
reg [4:0] port_id [0:7];
reg [63:0] array_4d [15:0][7:0][7:0][255:0];
wire w_array1[7:0][5:0]; //array of single bit wires
wire [7:0] w_array2 [5:0]; //array of 8-bit vector wire

• Difference between vectors and arrays??

 Arrays
• Examples (cont’d)
integer count[0:7];
time chk_point[1:100];
reg [4:0] port_id[0:7];
integer matrix[4:0][0:16];
reg [63:0] array_4d[15:0][7:0][7:0][255:0];

count[5] = 0;
chk_point[100] = 0;
port_id[3] = 0;
matrix[1][0] = 33559;
array_4d[0][0][0][0][15:0] = 0;

port_id = 0; // Illegal
matrix [1] = 0; // Illegal
 Memories
• RAM, ROM and register-files used many
times in digital systems
• Modeled as a one-dimensional array of
registers
• Memory = array of registers (register
data type) in Verilog
• Word = an element of the array
– Can be one or more bits
 Memories
• Examples:
reg mem1bit [0:1023];
reg [7:0] membyte[0:1023];
membyte[511] //fetches 1 byte word
addr:511
• Note the difference (as in arrays):
• n 1-bit register Vs one n-bit register
reg mem1bit[0:127];
reg [0:127] register;
 Parameter
• Similar to const in C
– But can be overridden for each module at compile-time
• Constants to be defined by parameter
• Can not be used as variable
• Syntax:
parameter <const_id> = <value>;
• Gives flexibility
– Allows to customize the module
• Example:
parameter port_id = 5;
parameter cache_line_width = 256;
parameter bus_width = 8;
parameter signed [15:0] WIDTH;
wire [bus_width-1:0] bus;