Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
Scribd
Upload
9 views

Introduction To FPGA and Verilog

Ee

Uploaded by

bibhuprasadbarik03072006
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
9 views

Introduction To FPGA and Verilog

Ee

Uploaded by

bibhuprasadbarik03072006
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 21

INTRODUCTION TO

FPGA & VERILOG


PROGRAMMING
VLSI Design Flow
Hardware Description Language
(HDL)…..?

Hardware Description Language (HDL) is


a programming language that is used to
describe the structure, behavior and
timing of electronic circuits, and most
commonly, digital logic circuits.

There are several HDLs available but the


most popular HDLs are
• Verilog HDL (verification of logic)
• VHDL (VHSIC)
Hardware Description Language
Strength of Verilog
• Simple to learn and simple syntax
• Widely used in the industry and has a sizable user base
• Quick and easy to simulate and test digital circuits
• Integrate with other design tools
• Quicker development
• Less code to be written
Weakness of Verilog
• Limited abstraction support
• Weakly typed
• Verilog does not offer as strong formal verification
• Poor concurrent programming support
• Lacks object-oriented programming support
• Small amount of support for dynamic simulation
VHDL vs Verilog

VHDL Verilog
Strongly typed Weakly typed
Easier to understand Less code to write
More natural in use More of a hardware modeling language
Wordy Succinct

Non-C-like syntax Similarities to the C language


Variables must be described by data A lower level of programming
type constructs
It supports a multidimensional array. It does not support a multidimensional
array.
More difficult to learn Simpler to learn
What is an FPGA?
PRACTICAL FPGA BOARD (BASYS-3)
Introduction to
Verilog Programming
Module Representation in Verilog.
A module is a block of Verilog code that implements certain
functionality. Modules can be embedded within other modules, and a
higher level module can communicate with its lower-level modules
using their input and output ports.
Module Representation …..cont.
A module consists of variable declaration, dataflow statements,
behavioral blocks, instantiation of lower hierarchical modules, tasks,
and functions. All of these are optional depending on the requirement
statements or blocks that can be used, but module, endmodule, and
module name are mandatory.
Verilog Timescale

Verilog simulation depends on how time is defined because the


simulator needs to know what a #1 means in terms of time.
The `timescale compiler directive specifies the time unit and precision
for the modules that follow it.

Syntax
1. `timescale <time_unit>/<time_precision>
Character Unit

for example s seconds


1. `timescale 1ns/1ps ms milliseconds
2. `timescale 10us/100ns
3. `timescale 10ns/1ns us microseconds

ns nanoseconds

ps picoseconds

fs Femtoseconds
Modelling styles in Verilog HDL.
A module can be designed in several ways using Verilog
HDL. There are
four types of abstraction levels, as per the designer
specifications;

▪ Switch level
▪ Gate level (Structural)
▪ Data flow
▪ Behavioral

Out of these four, behavioral has the highest level of


abstraction, and the switch level has the lowest level of
abstraction
Structural Modelling (Gate-level Modelling)

Design can be implemented using logic gates, and Verilog HDL


has a predefined set of logic gates.

Ex:-
module xyz(A,B,Y);
input A,B;
output Y;
nor N1(Y,A,B);
endmodule

• Modeling style is similar to the schematic drawing


• Module implementation is possible in terms of logic gates
and interconnections between these gates.
• Concurrency is possible in the gate-level modeling style.
Data flow Modelling

Based on logic equations and keyword assign. It is used in


writing the code for Boolean expressions.
Ex:-
module xyz(A, B,Y);
input A,B;
output Y;
assign Y=~(A|B);
endmodule

• Module is designed by specifying the data flow.


• Can realize how data flows between hardware registers
and how the data is processed in the design.
• This style is similar to logical equations.
• Operations are written as the symbols (AND as &, OR as|,
NOT as ~).
Behavioural Modelling

Related to the algorithm or behavior of the circuit & known as


algorithmic modeling.

During the simulation of the behavioral model, all the flows


defined by the ‘always’ and ‘initial’ statements start together at
simulation time ‘zero’.

The initial statements are executed once, and the always


statements are executed repetitively.
Behavioural Modelling

Related to the algorithm or behavior of the circuit & known as


algorithmic modelling.

Ex:-
module xyz(P, Q,R);
input P,Q;
output R;
reg R;
always @(P or Q)
begin
Y=~(P|Q);
end
endmodule
Behavioural Modelling …..cont.

Behavioral modeling is the highest level of abstraction provided


by Verilog HDL.

A module can be implemented in terms of the desired design


algorithm without concern for the hardware implementation
details.

It specifies the circuit in terms of its expected behavior.


It is the closest to a natural language description of the circuit
functionality, but also the most difficult to synthesize.
Switch level Modelling

lowest level of abstraction provided by Verilog. It consists of PMOS


and NMOS switches.
Syntax pmos/nmos p1(p_out, d_in, ctrl);
Ex:-
module my_nor(Y,A,B);
output Y;
input A,B;
wire C;
supply1 pwr;
supply0 gnd ;
pmos P1(C, pwr, A);
pmos P2(Y,C,B);
nmos N1(Y, gnd, A);
nmos (Y, gnd, B);
endmodule
Half Adder Using Verilog: Structural Method

module half_adder_structural (
input a, // Input 'a'
input b, // Input 'b'
output s, // Output 's' (Sum)
output c // Output 'c' (Carry)
);
xor gate_xor (s, a, b); // XOR gate for sum
and gate_and (c, a, b); // AND gate for carry
endmodule
Half Adder Using Verilog: Dataflow Method
module half_adder_dataflow (
input a, // Input 'a'
input b, // Input 'b'
output s, // Output 's' (Sum)
output c // Output 'c' (Carry)
);

assign s = a ^ b; // Dataflow expression for sum


assign c = a & b; // Dataflow expression for carry
endmodule
Thank You

You might also like