Cortex M0 M3

ARM Cortex-M0 Features
ISA Support Thumb
/ Thumb-2 subset
Pipeline 3-stage
Performance Efficiency 2.33 CoreMarks/MHz*

Performance Efficiency 0.84 / 0.99 / 1.21 DMIPS/MHz**
Interrupts Non-maskable Interrupt (NMI) + 1 to 32 physical interrupts
Sleep Modes
Integrated WFI and WFE Instructions and Sleep On Exit capability
Sleep & Deep Sleep Signals
Optional Retention Mode with ARM Power Management Kit
Bit Manipulation Bit banding region can be implemented with Cortex-M System Design Kit
Enhanced Instructions Hardware single-cycle (32x32) multiply option
Debug Optional JTAG or Serial-Wire Debug Ports. Up to 4 Breakpoints and 2 Watchpoints

ARM Cortex-M0+ Features
ISA Support Thumb / Thumb-2 subset
Pipeline 2 stage
Performance Efficiency 2.42 CoreMarks/MHz*
Memory Protection Optional 8 region MPU with sub regions and background region
Sleep Modes
Integrated WFI and WFE Instructions and Sleep On Exit capability
Sleep & Deep Sleep Signals
Bit Manipulation Bit banding region can be implemented with Cortex-M System Design Kit
Enhanced Instructions Hardware single-cycle (32x32) multiply option
Debug Optional JTAG or Serial-Wire Debug Ports Up to 4 Breakpoints and 2 Watchpoints
Trace Optional Micro Trace Buffer

The Cortex-M1 processor is a streamlined three-stage 32-bit RISC processor that implements the
popular, high densityThumb-2
instruction set. This enables both the processor and software

footprint to meet the area budget of the smallest FPGA devices, while retaining compatibility with
Thumb code for any ARM processor from the ARM7TDMI
processor upwards. Despite being the

smallest processor in the Cortex processor family, the Cortex-M1 processor can deliver 0.8
DMIPS/MHz.
Feature Set
Streamlined three stage 32 bit RISC processor
High frequency, low area design
Configurable instruction and data tightly coupled memories (0K - 1024K)
Integrated interrupt controller
1 to 32 interrupts supported
4 priority levels per interrupt
Highly configurable debug logic
Removable debug, breakpoint and watchpoint
Big or Little endian configurability
Fast or small multiplier configuration options supported
AMBA
AHB-Lite 32-bit bus interface

ARM Cortex-M3 Features
ISA Support Thumb
/ Thumb-2
Pipeline 3-stage
Performance Efficiency 3.32 CoreMark/MHz*
Memory Protection Optional 8 region MPU with sub regions and background region
Interrupt Priority Levels 8 to 256 priority levels
Wake-up Interrupt
Controller
Up to 240 Wake-up Interrupts
Sleep Modes
Integrated WFI and WFE Instructions and Sleep On Exit capability.
Sleep & Deep Sleep Signals.
Bit Manipulation Integrated Instructions & Bit Banding
Enhanced Instructions
Hardware Divide (2-12 Cycles), Single-Cycle (32x32) Multiply, Saturated Math
Support.
Debug Optional JTAG & Serial-Wire Debug Ports. Up to 8 Breakpoints and 4 Watchpoints.
Trace
Optional Instruction Trace (ETM), Data Trace (DWT), and Instrumentation Trace
(ITM)
pipeline adalah seperangkat elemen pengolahan data dihubungkan secara seri, di mana output dari
satu elemen adalah input yang berikutnya.
SysTick Timer : Sebuah timer sistem 24 - bit yang memperluas fungsionalitas dari kedua prosesor dan
Nested vektor Interrupt Controller ( NVIC ) . Ketika hadir, itu juga memberikan prioritas dikonfigurasi
tambahan SysTick interupsi . Meskipun timer SysTick adalah opsional , sangat jarang untuk melihat
mikrokontroler Cortex - M tanpa itu .
Bit Banding : Memetakan sebuah kata lengkap memori ke sebuah bit tunggal di wilayah bit -band .
Misalnya, menulis sebuah kata alias akan mengatur atau menghapus bit yang sesuai di wilayah bitband .
Hal ini memungkinkan setiap bit individu dalam wilayah bit - bandeng secara langsung diakses dari
alamat kata -blok , dan bit individu harus toggle dari C / C + + tanpa melakukan urutan read -
memodifikasi - write instruksi .
Satuan Perlindungan memori ( MPU ) : Menyediakan dukungan untuk melindungi daerah memori
melalui menegakkan hak istimewa dan akses aturan . Hal ini mendukung hingga delapan daerah yang
berbeda , yang masing-masing dapat dibagi menjadi delapan lebih sama ukuran sub - wilayah .

Some of the most important options for the Cortex-M cores are:
SysTick Timer: A 24-bit system timer that extends the functionality of both the processor and the
Nested Vectored Interrupt Controller (NVIC). When present, it also provides an additional
configurable priority SysTick interrupt.
[6][7][8]
Though the SysTick timer is optional, it's rare to see
a Cortex-M microcontroller without it.
Bit Banding: Maps a complete word of memory onto a single bit in the bit-band region. For
example, writing to an alias word will set or clear the corresponding bit in the bitband region.
This allows every individual bit in the bit-banding region to be directly accessible from a word-
aligned address, and individual bits to be toggled from C/C++ without performing a read-modify-
write sequence of instructions.
[6][7][8]

Memory Protection Unit (MPU): Provides support for protecting regions of memory through
enforcing privilege and access rules. It supports up to eight different regions, each of which can
be split into a further eight equal-size sub-regions.
[6][7][8]

Cortex M0 M3

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ARM Cortex-M0 Features

ISA Support Thumb

instruction set. This enables both the processor and software

processor upwards. Despite being the

AHB-Lite 32-bit bus interface

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