The STM32L476xx devices

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The STM32L476xx devices
 The STM32L476xx devices are the ultra-low-power
microcontrollers based on the high-performance Arm® Cortex®-
M4 32-bit RISC core operating at a frequency of up to 80 MHz.

 The Cortex-M4 core features a Floating point unit (FPU) single

precision which supports all Arm® single-precision data-
processing instructions and data types.

 Italso implements a full set of DSP instructions and a memory

protection unit (MPU) which enhances application security.
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ARM Cortex-M4 Organization (STM32L4)

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The STM32L476xx devices
 The STM32L476xx devices embed
 high-speedmemories (Flash memory up to 1 Mbyte, up
to 128 Kbyte of SRAM)
aflexible external memory controller (FSMC) for static
memories
a Quad SPI flash memories interface
 an extensive range of enhanced I/Os and peripherals
connected to two APB buses, two AHB buses and a 32-
bit multi-AHB bus matrix.
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The STM32L476xx devices
 The devices offer
 up to three fast 12-bit ADCs (5 Msps),
 two comparators,
 two operational amplifiers,
 two DAC channels,
 an internal voltage reference buffer,
a low-power RTC,

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The STM32L476xx devices
 The devices offer
 Two general-purpose 32-bit timer,
 two 16-bit PWM timers dedicated to motor control,
 Seven general-purpose 16-bit timers, and two 16-bit
low-power timers.
 Four digital filters for external sigma delta modulators
(DFSDM).
 up to 24 capacitive sensing channels
 an integrated LCD driver 8x40 or 4x44
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The STM32L476xx devices
 They also feature standard communication interfaces
 Three I2Cs
 Three SPIs
 Three USARTs, two UARTs and one Low-Power UART.
 Two SAIs (Serial Audio Interfaces)
 One SDMMC
 One CAN
 One USB OTG full-speed
 One SWPMI (Single Wire Protocol Master Interface)
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STM32L476xx family device features and peripheral counts

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The STM32L476xx devices

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The STM32L476xx devices

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The STM32L476xx devices

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The STM32L476xx devices

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 The STM32L476 Arm Cortex-M4 core with FPU
a low-cost platform
a reduced pin count
 low-power consumption
 delivering outstanding computational performance
 an advanced response to interrupts
 32-bit RISC processor features exceptional code efficiency
 delivering
the high-performance expected from an Arm core in
the memory size usually associated with 8- and 16-bit devices.
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 The STM32L476 Arm Cortex-M4 core with FPU
 The processor supports a set of DSP instructions which
allow efficient signal processing and complex algorithm
execution.
 Its
single precision FPU speeds up software development
by using metalanguage development tools, while avoiding
saturation.

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The STM32L476 ART Accelerator
 The Adaptive real-time memory accelerator (ART
Accelerator) is a memory accelerator which is optimized
for STM32 processors.
 Itbalances the inherent performance advantage of the
Cortex-M4 over Flash memory technologies, which
normally requires the processor to wait for the Flash
memory at higher frequencies.

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 The STM32L476 ART Accelerator
 Theaccelerator implements an instruction prefetch queue and
branch cache, which increases program execution speed
from the 64-bit Flash memory.
 The performance achieved thanks to the ART accelerator is
equivalent to 0 wait state program execution from Flash
memory at a CPU frequency up to 80 MHz.

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 The STM32L476 Memory protection unit
 The memory protection unit (MPU) is used to manage the CPU
accesses to memory to prevent one task to accidentally corrupt
the memory or resources used by any other active task.
 This memory area is organized into up to 8 protected areas
that can in turn be divided up into 8 subareas.
 It is usually managed by an RTOS (real-time operating
system).
 The MPU is optional and can be bypassed for applications that
do not need it.
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The STM32L476 Memory Map

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The STM32L476 Memory Map
Memory Address Size
Main Flash Memory Bank 1 0x0800 000-0x0807 FFFF 512 KB
Main Flash Memory Bank 2 0x0808 000-0x080F FFFF 512 KB
SRAM2 0x1000 000-0x1000 7FFF 32 KB
System Memory Bank 1 (Flash) 0x1FFF 0000-0x1FFF 6FFF 28 KB
OTP (one-time programmable) 0x1FFF 7000-0x1FFF 73FF 1 KB
Option bytes (Flash) Bank 1 0x1FFF 7800 - 0x1FFF 780F 16 B
System Memory Bank 2 (Flash) 0x1FFF 8000 - 0x1FFF EFFF 28 KB
Option bytes (Flash) Bank 2 0x1FFF F800 - 0x1FFF F80F 16 B
SRAM1 0x2000 000-0x2001 7FFF 96 KB

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The STM32L476 Memory organization

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The STM32L476 Memory organization

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The STM32L476 Memory organization

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 The STM32L476 Embedded Flash memory
 The Flash memory is composed of two distinct physical areas:
 The main Flash memory block. It contains the application
program and user data if necessary.
 The information block. It is composed of three parts:
 Option bytes for hardware and memory protection user
configuration.
 System memory that contains the ST proprietary code.
 OTP (one-time programmable) area
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The STM32L476 Embedded Main Flash memory
 STM32L476xxdevices feature up to 1 Mbyte of embedded
Main Flash memory available for storing programs and
data.

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The STM32L476 Embedded Main Flash memory
 TheMain Flash memory is divided into two banks allowing
read-while-write operations.
 Thisfeature allows to perform a read operation from one
bank while an erase or program operation is performed to
the other bank.
 The dual bank boot is also supported.
 Each bank contains 256 pages of 2 Kbyte.

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 The STM32L476 Embedded Main Flash memory
 Flexible protections can be configured thanks to option bytes:
 Readout protection (RDP) to protect the whole memory. Three levels
are available.
 Level 0: no readout protection
 Level 1: memory readout protection
 Level 2: chip readout protection
 Write protection (WRP): the protected area is protected against erasing
and programming.
 Proprietary code readout protection (PCROP): a part of the flash
memory can be protected against read and write from third parties.
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The STM32L476 Embedded SRAM
 STM32L476xxdevices feature up to 128 Kbyte of
embedded SRAM.

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The STM32L476 Embedded SRAM
 This SRAM is split into two blocks:
 96 Kbyte mapped at address 0x2000 0000 (SRAM1)
 32 Kbyte located at address 0x1000 0000 with
hardware parity check (SRAM2).
 The SRAM2 can be write-protected with 1 Kbyte
granularity.
 Thememory can be accessed in read/write at CPU clock
speed with 0 wait states.
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 The STM32L476 Boot Modes
 Atstartup, BOOT0 pin and BOOT1 option bit are used to
select one of three boot options:
 Boot from Main Flash Memory
 Boot from system memory
 Boot from embedded SRAM1
 The boot loader is located in system memory. It is used to
reprogram the main Flash memory by using USART, I2C,
SPI, CAN or USB OTG FS in Device mode through DFU
(device firmware upgrade).
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The STM32L476 General-purpose inputs/outputs

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The STM32L476 General-purpose inputs/outputs
 Eachof the General-purpose inputs/output (GPIO) pins can
be configured by software:
 as output (push-pull or open-drain)
 as input (with or without pull-up or pull-down)
 as peripheral alternate function
 Most of the GPIO pins are shared with digital or analog
alternate functions.
 FastI/O toggling can be achieved thanks to their mapping on
the AHB2 bus.
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 The STM32L476 Direct memory access
controller
 The
device embeds 2 Direct memory access controllers
(DMAs).

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 The STM32L476 Direct memory access
controller
 The device embeds 2 Direct memory access controllers (DMAs).
 DMA is used in order to provide high-speed data transfer between
peripherals and memory as well as memory to memory.
 Data can be quickly moved by DMA without any CPU actions.
This keeps CPU resources free for other operations.
 Each DMA controller has 7 channels (14 channels in total), each
dedicated to managing memory access requests from one or
more peripherals.
 Each has an arbiter for handling the priority between DMA
requests.
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 The STM32L476 Direct memory access
controller
 14 independently configurable channels (requests)
 Each channel is connected to dedicated hardware DMA requests.
 software trigger is also supported on each channel. This configuration is done by
software.
 Priorities between requests from channels of one DMA are software programmable at
4 levels:
 very high
 high
 medium
 low
 hardware priorities in case of equality
 request 1 has priority over request 2, etc
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 The STM32L476 Direct memory access
controller
 Independent source and destination transfer size (byte, half
word, word), emulating packing and unpacking.
 Source/destination addresses must be aligned on the data
size.
 Support for circular buffer management
3 event flags (DMA Half Transfer, DMA Transfer complete
and DMA Transfer Error) logically ORed together in a single
interrupt request for each channel.

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 The STM32L476 Direct memory access
controller
 Transfer types:
 Memory-to-memory

 Peripheral-to-memory

 Memory-to-peripheral,

 Peripheral-to-peripheral

 Accessto Flash, SRAM, APB and AHB peripherals as source

and destination
 Programmable number of data to be transferred: up to 65536.
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The STM32L476 Nested vectored interrupt controller
(NVIC)
 TheNVIC hardware block provides flexible interrupt
management features with minimal interrupt latency

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The STM32L476 Nested vectored interrupt controller (NVIC)
 handle up to 81 maskable interrupt channels
 handle the 16 interrupt lines of the Cortex®-M4
 manage 16 priority levels
 Interrupt entry vector table address passed directly to the core
 Allows early processing of interrupts
 Processing of late arriving higher priority interrupts
 Support for tail chaining
 Processor state automatically saved on interrupt entry, and
restored on interrupt exit, with no instruction overhead.
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The STM32L476 Extended interrupt/event controller (EXTI)
 40 edge detector lines used to generate interrupt/event
requests and wake-up the system from Stop mode.
 Each external line can be independently configured to
select the trigger event (rising edge, falling edge, both)
and can be masked independently.
A pending register maintains the status of the interrupt
requests.

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The STM32L476 Extended interrupt/event controller (EXTI)
 The internal lines are connected to peripherals with
wakeup from Stop mode capability.
 The EXTI can detect an external line with a pulse width
shorter than the internal clock period.
 Up to 114 GPIOs can be connected to the 16 external
interrupt lines.

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The STM32L476 multilayer AHB bus matrix
 The main system consists of 32-bit multilayer AHB bus matrix that interconnects:
 5 masters
 Cortex-M4 with FPU core I-bus
 Cortex-M4 with FPU core D-bus
 Cortex-M4 with FPU core S-bus
 DMA1
 DMA2
 7 slaves
 Internal Flash memory on the ICode bus
 Internal Flash memory on DCode bus
 Internal SRAM1
 Internal SRAM2
 AHB1 peripherals including AHB to APB bridges and APB peripherals (connected to
APB1 and APB2)
 AHB2 peripherals
41  Flexible Memory Controller (FMC) and QUADSPI interface
The STM32L476 multilayer AHB bus matrix
 The Bus Matrix manages
the access arbitration
between masters.
 The arbitration uses a
Round Robin algorithm.

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The STM32L476 multilayer AHB bus matrix
 The bus matrix provides
access from a master to a
slave, enabling concurrent
access and efficient operation
even when several high-
speed peripherals work
simultaneously.

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 The STM32L476 multilayer AHB bus matrix
 S0: I-bus
 This bus connects the instruction bus of the
Cortex-M4 core to the BusMatrix.
 This bus is used by the core to fetch
instructions.
 The targets of this bus are:
 internal Flash memory
 SRAM1
 SRAM2
 external memories through QUADSPI or the
FMC.

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 The STM32L476 multilayer AHB bus matrix
 S1: D-bus
 This bus connects the data bus of the Cortex-
M4 core to the BusMatrix.
 This bus is used by the core for literal load and
debug access.
 The targets of this bus are:
 internal Flash memory
 SRAM1
 SRAM2
 external memories through QUADSPI or the
FMC.

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 The STM32L476 multilayer AHB bus matrix
 S2: S-bus
 This bus connects the system bus of the
Cortex-M4 core to the BusMatrix.
 This bus is used by the core to access data
located in a peripheral or SRAM area.
 The targets of this bus are:
 SRAM1
 AHB1 peripherals including the APB1 and
APB2 peripherals
 AHB2 peripherals
 external memories through QUADSPI or the
FMC.
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 The STM32L476 multilayer AHB bus matrix
 S3, S4: DMA-bus
 This bus connects the AHB master interface of the
DMA to the Bus Matrix.
 This bus is used by the core to access data located in
a peripheral or SRAM area.
 The targets of this bus are:
 internal Flash memory
 SRAM1
 SRAM2
 AHB1 peripherals including the APB1 and APB2
peripherals
 AHB2 peripherals
 external memories through QUADSPI or the FMC.
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 The STM32L476 AHB/APB bridges
 The two AHB/APB bridges provide full synchronous connections between the
AHB and the two APB buses, allowing flexible selection of the peripheral
frequency.
 After each device reset, all peripheral clocks are disabled (except for the
SRAM1/2 and Flash memory interface).
 Before using a peripheral you have to enable its clock in the following resisters:
 RCC_AHB1ENR
 RCC_AHB2ENR
 RCC_AHB3ENR
 RCC_APB1ENR1
 RCC_APB1ENR2
 RCC_APB2ENR
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 The STM32L476 peripheral clock enable
registers

Flash
ART
Memory

Advanced High-
performance
Bus (AHB1)

TSC CRC

Direction Memory
Access Controllers
DMA1
DMA2

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 The STM32L476 peripheral clock enable
registers

USB OTG

AHB2

GPIO Port A ADC1 RNG

GPIO Port B ADC2
GPIO Port C ADC3
GPIO Port D
GPIO Port E
GPIO Port F
GPIO Port G
GPIO Port H

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 The STM32L476 peripheral clock enable
registers

Quad SPI memory interface

AHB3 Flexible static memory controller

(FSMC)

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 The STM32L476 peripheral clock enable
registers

TIM2 USART4
TIM3 USART5
TIM4 I2C1/SMBUS
TIM5 I2C2/SMBUS
TIM6 I2C3/SMBUS
TIM7 CAN1
LCD PWR
AHB Bus Matrix RTC DAC1
WWDG OpAmp
SPI2 LPTIM1
Flash SPI3 LPUART1
ART USART2 SWPMI1
Memory
USART3 LPTIM2
Advanced High-
performance APB1
Bus (AHB1) AHB to APB Bridge 1
AHB to APB Bridge 2
ABP2

TSC CRC

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 The STM32L476 peripheral clock enable
registers

TIM2 USART4
TIM3 USART5
TIM4 I2C1/SMBUS
TIM5 I2C2/SMBUS
TIM6 I2C3/SMBUS
TIM7 CAN1
LCD PWR
AHB Bus Matrix RTC DAC1
WWDG OpAmp
SPI2 LPTIM1
Flash SPI3 LPUART1
ART USART2 SWPMI1
Memory
USART3 LPTIM2
Advanced High-
performance APB1
Bus (AHB1) AHB to APB Bridge 1
AHB to APB Bridge 2
ABP2

TSC CRC

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 The STM32L476 peripheral clock enable
registers

Advanced High-

AHB Bus Matrix

performance APB1
Bus (AHB1) AHB to APB Bridge 1
AHB to APB Bridge 2
ABP2

TSC CRC
VREF USART1
COMP1 TIM15
COMP2 TIM16
Firewall TIM17
SDIO/MMC1 SAI1
TIM1/PWM SAI2
SPI1 DFSDM
TIM8/PWM EXTI/WKUP

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 The STM32L476 Memory organization
 Program memory, data memory, registers and I/O ports
are organized within the same linear 4-Gbyte address
space.
 The bytes are coded in memory in Little Endian format.
The lowest numbered byte in a word is considered the
word’s least significant byte and the highest numbered
byte the most significant.
 Theaddressable memory space is divided into eight main
blocks, of 512 Mbytes each.
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Memory Map of Cortex-M4
 32-bit Memory Address

 232 bytes of memory space (4 GB)

 Harvard
architecture: physically separated instruction
memory and data memory.

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Memory Map of Cortex-M4

0xFFFFFFFF
NVIC, System Timer, SCB,
0.5 GB System
vendor-specific memory
0xE0000000

1 GB External RAM Off-chip memory for data

0xA0000000

1 GB External Device 4 GB
Such as SD card

0x60000000
0.5 GB Peripheral AHB & APB, such as timers, GPIO
0x40000000
0.5 GB SRAM On-chip RAM, for heap, stack, & code
0x20000000
0.5 GB Code On-chip Flash, for code & data
0x00000000

One Byte (8 bits)

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Memory Map of Cortex-M4
 The first region is code region. It is 0xFFFFFFFF

primarily used to store program code. It 0.5 GB

0xE0000000
System

can also store data. External RAM

1 GB

0xA0000000

 The code region is on-chip memory, External Device

1 GB

typically on-chip flash. The size of on-chip 0x60000000

flash is limited to half a gigabyte. 0.5 GB

0x40000000
Peripheral

0.5 GB SRAM
0x20000000
0.5 GB Code
 The actual size of the on-chip flash varies 0x00000000

based on different venders and different One Byte (8 bits)

chips.
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Memory Map of Cortex-M4
 The second region is Static Random 0xFFFFFFFF
0.5 GB System

Access Memory (SRAM). 0xE0000000

1 GB External RAM

0xA0000000

 It is primarily used to store data, External Device

1 GB

such as heaps and stacks. We can 0x60000000

Peripheral
also put code here. It supports half a
0.5 GB
0x40000000
0.5 GB SRAM
gigabyte. 0.5 GB
0x20000000
Code
0x00000000

One Byte (8 bits)

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Memory Map of Cortex-M4
 The third region is peripheral. 0xFFFFFFFF
0.5 GB System
0xE0000000

1 GB External RAM
 These peripherals include AHB 0xA0000000

peripherals, such as GPIO, and 1 GB External Device

ADC, and APB peripherals, such as 0x60000000

Peripheral
timers, and USART.
0.5 GB
0x40000000
0.5 GB SRAM
0x20000000
0.5 GB Code
0x00000000

One Byte (8 bits)

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 Memory Map of Cortex-M4
 The next region is for external device, such 0xFFFFFFFF
0.5 GB System
as SD card. 0xE0000000

1 GB External RAM

 The next is external RAM, which is 0xA0000000

executable region for data. It is off-chip 1 GB External Device

memory, primarily used to store large data 0.5 GB

0x60000000
Peripheral
blocks. It has a total of 1 gigabyte. 0.5 GB
0x40000000
SRAM
0x20000000
0.5 GB Code
0x00000000
 The last one is system region, which includes One Byte (8 bits)

the NVIC, system timer, system control block,

and vendor-specific memory.
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Instruction Memory

0xFFFFFFFF 0x1FFFFFFF
0.5 GB System
Reserved
0xE0000000

0x080FFFFF
1 GB External RAM
RW Data Section
Internal
0xA0000000 RO Data Section
Flash
Text Section
Memory
1 GB External Device Interrupt
1 MB
Vector Table
Initial MSP 0x08000000
0x60000000
0.5 GB Peripheral
Mapped Reserved
0x40000000 (aliasing)
0.5 GB SRAM
0x20000000 Interrupt
0.5 GB Code Vector Table
0x00000000 Initial MSP 0x00000000

One Byte (8 bits)

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 Instruction Memory
 While the code space can have as large as half a
gigabyte, much of this space is reserved or not 0x1FFFFFFF

used. For example, STM32L4 chip has, only 1 MB, Reserved

on-chip flash memory. 0x080FFFFF

RW Data Section
Internal
RO Data Section
 The memory address of the on-chip flash memory, Text Section
Flash
Memory
Interrupt
starts at 0x08000000, and ends at 0x80FFFFF. Vector Table
1 MB

Initial MSP 0x08000000

Reserved
 Typically, the on-chip flash memory stores, the
initial value of the stack pointer, the interrupt vector Interrupt
Vector Table
table, the text section, the read-only data section, Initial MSP 0x00000000

and the read-write data section.

Instruction Memory
 The text section consists of binary
machine instructions. 0x1FFFFFFF

Reserved

0x080FFFFF

 The read-only data section that defines RW Data Section

Internal
RO Data Section
the value of variables that cannot change Text Section
Interrupt
Flash
Memory

at runtime. Vector Table

Initial MSP 0x08000000
1 MB

Reserved

 The read-write data section that sets the Interrupt

Vector Table
initial values of statically allocated and Initial MSP 0x00000000

modifiable variables.
Instruction Memory
 In addition, a small memory region
starting at 0x8000000, is mapping to, 0x1FFFFFFF

the lowest memory region starting at Reserved

the address of 0. 0x080FFFFF

RW Data Section
Internal
RO Data Section
Flash
 In other words, two addresses can Text Section
Memory
Interrupt
1 MB
point to the same data item in this Vector Table
Initial MSP 0x08000000

mapped memory region. Mapped Reserved

(aliasing)

Interrupt Vector
 This mapping region includes the Table
Initial MSP 0x00000000
initial value for the main stack pointer,
and the interrupt vector table.
Data Memory

0xFFFFFFFF 0x3FFFFFFF
0.5 GB System
0xE0000000

1 GB External RAM

0xA0000000

1 GB External Device 0x20017FFF

Stack
0x60000000
0.5 GB Peripheral Internal
0x40000000 SRAM
0.5 GB SRAM Heap Memory
0x20000000 96 KB
Zero-initialized data
0.5 GB Code Initialized data
0x00000000 0x20000000

One Byte (8 bits)

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Internal SRAM
 The internal SRAM region, is
assigned a space of half a gigabyte.

 However, the capacity of on-chip

SRAM, is often very small.

 For
example, on-chip SRAM on
STM32L4 has only 96 kilo-bytes.

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 Internal SRAM
 The SRAM is divided into several segments.

 The initialized data segment. It contains global and static

variables, which the program gives some initial values.

 The zero-initialized data segment. It contains all global, or

static variables, which are uninitialized, or initialized to
zero, in the program.

 The heap segment. It holds all data objects, which an

application creates dynamically at runtime.

 The stack segment. Stack is used for various purposes.

For example, the stack can store local variables of
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subroutines, save the runtime environment, and pass
 Internal SRAM
 The stack is placed on the top of the internal SRAM
memory, and it grows downwards.

 The heap is placed at the bottom of the free memory

region, and it grows upwards. The stack and the
heap, are located at the opposite end of, the free
memory region. They grow in the opposite direction.

 In this way, the stack and the heap can take full
advantage of the available memory space. When the
stack meets the heap, free memory space is
exhausted.

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 The STM32L476 Memory organization

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 The STM32L476 Memory organization

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 The STM32L476 Memory organization

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 The STM32L476 Memory organization

73
Interfacing Peripherals
 Port-mapped I/O
 Use special CPU instructions: Special_instruction Reg, Port
 Memory-mapped I/O
 Most CPUs these days do I/O via memory mapped I/O
 A simpler and more convenient way to interface I/O devices
 Each device registers is assigned to a memory address in the address space of the
microprocessor
 Use native load/store instructions to input or output data: LDR/STR Reg, [Reg, #imm]
 When you write to this “special memory location”, the data you write,
is sent to, the corresponding I/O device
0x4800002
4
0x4800002
0
Core Pin output
STR 0x4800001
C GPIO
0x4800001 Output
8
GPIOSpace
0x4800001Memory Data Output Register
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4
ARM0x4800001
Cortex-M microprocessors use memory-mapped I/O.
 Memory Map of Cortex-M4: Peripheral region
0xFFFFFFFF
0.5 GB System  The peripheral region covers the memory
0xE0000000
addresses of all on-chip peripherals, such as
GPIO, timers, USART, SPI, and ADC.
1 GB External Device

 Specific mapping addresses are dependent on

0xA0000000
vendors and chips.
1 GB External RAM

0x60000000
0.5 GB Peripheral
0x40000000
0.5 GB SRAM
0x20000000
0.5 GB Code
0x00000000

75 One Byte (8 bits)

Memory Map of STM32L4: GPIO
0xFFFFFFFF  We will use GPIO on STM32L4 as an example to
0.5 GB System illustrate the concept of memory-mapped I/O.
0xE0000000
 For instance, on STM32L4, the registers of GPIO
1 GB External Device Port A, are mapped to a small memory region
starting at, 0x48000000.
0x60000000
0xA0000000

…
1 GB External RAM
0x48001000
GPIO D (1 KB)
0x60000000 0x48000C00
0.5 GB Peripheral GPIO C (1 KB)
0x40000000 0x48000800
GPIO B (1 KB)
0.5 GB SRAM 0x48000400
0x20000000 GPIO A (1 KB)
0.5 GB Code 0x48000000
0x40000000
…
0x00000000

76 One Byte (8 bits)

 GPIO A Memory Map

0x48000400
Each port has 12 registers, and each register has 4 bytes.

 While a total of 1 KB space is reserved for Port A, only 48

bytes are used.

ASCR
 Within this 48-byte memory region, the GPIO mode register 0x4800002C
MODER, is mapped to the lowest memory address, and the BRR
0x48000028
GPIO analog switch control register, ASCR, is mapped to
0x48000024
AFR[1]
the highest memory address.
AFR[0]
0x48000020
0x48000400 LCKR
0x4800001C
GPIO A (1 KB) BSRR
0x48000000 0x48000018 48 bytes
0x48000014
ODR
IDR
0x48000010
PUPDR
0x4800000C
OSPEEDR
0x48000008
0x48000004
OTYPER
MODER
0x48000000

77
Each register has 4 bytes.
 GPIO A Memory Map
0x48000400
 Suppose we want to set the output of
pin 14 of Port A to high.
 To achieve this, we need to set bit 14
of the output data register (ODR) of ASCR
0x4800002C
GPIO A, to 1. BRR
0x48000028
0x48000024
AFR[1]
AFR[0]
0x48000020
0x48000400 LCKR
0x4800001C
GPIO A (1 KB) BSRR
0x48000000 0x48000018 48 bytes
0x48000014
ODR
IDR
0x48000010
PUPDR
Set pin A.14 to high 0x4800000C Set bit 14
OSPEEDR
0x48000008 of ODR
0x48000004
OTYPER to high
MODER
0x48000000

78
Output Data Register (ODR)
0x48000017
ODR 1 word (i.e. 32 bits)
0x48000014

0x48000017
0x48000016
4 bytes
0x48000015
0x48000014

Little Endian

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1

lUL is an
*((uint32_t *) 0x48000014) |= 1UL<<14; unsigned long
integer with a
value of 1
79 Dereferencing a pointer Bitwise OR
 The STM32L476 Address of peripheral
registers
#define PERIPH_BASE ((uint32_t)0x40000000U)

#define APB1PERIPH_BASE PERIPH_BASE

#define APB2PERIPH_BASE (PERIPH_BASE +
0x00010000U)
#define AHB1PERIPH_BASE (PERIPH_BASE +
0x00020000U)
#define AHB2PERIPH_BASE (PERIPH_BASE +
0x08000000U)

80
 The STM32L476 peripheral registers: GPIOB

81
 The STM32L476 peripheral registers: GPIOB
 In memory-mapped I/O, all registers of a GPIO port, are mapped to a
contiguous block of physical memory. This memory block can be
ASCR represented by using a struct.
0x4800042C
BRR typedef struct {
0x48000428 volatile uint32_t MODER; // Mode register
0x48000424
AFR[1] volatile uint32_t OTYPER; // Output type register
volatile uint32_t OSPEEDR; // Output speed register
AFR[0]
0x48000420 volatile uint32_t PUPDR; // Pull-up/pull-down
LCKR register
0x4800041C volatile uint32_t IDR; // Input data register
BSRR volatile uint32_t ODR; // Output data register
0x48000418 volatile uint32_t BSRR; // Bit set/reset register
0x48000414
ODR volatile uint32_t LCKR; // Configuration lock
IDR register
0x48000410 volatile uint32_t AFR[2]; // Alternate function
PUPDR registers
0x4800040C volatile uint32_t BRR; // Bit Reset register
OSPEEDR volatile uint32_t ASCR; // Analog switch control
0x48000408
0x48000404
OTYPER register
} GPIO_TypeDef;
MODER
0x48000400 // Casting memory address to a pointer
#define
pointer.pGPIOB
Let's ((GPIO_TypeDef *) 0x48000400)
 We use a macro definition here to give a name to the struct pGPIOB->ODR |= 1UL<<14;
name the macro GPIOA. To set bit 14, we can use the membership
operator to access the data output register ODR. We can either use the
arrow operator, or the dot operator, to access the output data register ODR. or(*pGPIOB).ODR |= 1UL<<14;
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 The STM32L476 peripheral registers: GPIOB
typedef struct {
volatile uint32_t MODER; // Mode register
volatile uint32_t OTYPER; // Output type register
volatile uint32_t OSPEEDR; // Output speed register
volatile uint32_t PUPDR; // Pull-up/pull-down register
volatile uint32_t IDR; // Input data register
volatile uint32_t ODR; // Output data register
volatile uint32_t BSRR; // Bit set/reset register
volatile uint32_t LCKR; // Configuration lock register
volatile uint32_t AFR[2]; // Alternate function registers
volatile uint32_t BRR; // Bit Reset register
volatile uint32_t ASCR; // Analog switch control register
} GPIO_TypeDef;

// Casting memory address to a pointer

#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400U)
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)

GPIOB->ODR |= 1UL<<14;

83