Tms 320 C 5517

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TMS320C5517
SPRS727C – AUGUST 2012 – REVISED APRIL 2014
TMS320C5517 Fixed-Point Digital Signal Processor

1 Device Overview
1.1
1
Features
• CORE: – Direct Memory Access (DMA) Controller
– High-Performance, Low-Power, TMS320C55x • Four DMA with Four Channels Each
Fixed-Point Digital Signal Processor – Three 32-Bit General-Purpose (GP) Timers
• 13.33- to 5-ns Instruction Cycle Time • One Selectable as a Watchdog or GP
• 75- to 200-MHz Clock Rate • Clocking Options, Including External
• One or Two Instructions Executed per Cycle General-Purpose I/O (GPIO) Clock Input
• Dual Multiply-and-Accumulate Units (Up to – Two MultiMedia Card and Secure Digital
450 Million Multiply-Accumulates per Second (eMMC, MMC, and SD) Interfaces
[MMACS]) – Serial Port Interface (SPI) with Four Chip
• Two Arithmetic and Logic Units (ALUs) Selects
• Three Internal Data or Operand Read Buses – Master and Slave Inter-Integrated Circuit (I2C
and Two Write Buses Bus)
• Software-Compatible with C55x Devices – Three Inter-IC Sound (I2S Bus) Modules for
• Industrial Temperature Devices Available Data Transport
– 320KB of Zero-Wait State On-Chip RAM: – 10-Bit 4-Input Successive Approximation (SAR)
ADC
• 64KB of Dual-Access RAM (DARAM),
8 Blocks of 4K x 16-Bit – IEEE-1149.1 (JTAG)
Boundary-Scan-Compatible
• 256KB of Single-Access RAM (SARAM),
32 Blocks of 4K x 16-Bit – Up to 26 GPIO Pins (Multiplexed with Other
Functions)
– 128KB of Zero Wait-State On-Chip ROM
(4 Blocks of 16K x 16-Bit) • POWER:
– Tightly Coupled FFT Hardware Accelerator – Four Core Isolated Power Supply Domains:
Analog, RTC, CPU and Peripherals, and USB
• PERIPHERAL:
– Four I/O Isolated Power Supply Domains: RTC
– One Universal Host-Port Interface (UHPI) with
I/O, EMIF I/O, USB PHY, and DVDDIO
16-Bit Muxed Address or Data Bus
– 1.05-V Core, 1.8-, 2.75-, or 3.3-V I/Os
– Master and Slave Multichannel Serial Ports
Interface (McSPI) with Three Chip Selects – 1.3-V Core, 1.8-, 2.75-, or 3.3-V I/Os
– Master and Slave Multichannel Buffered Serial – 1.4-V Core, 1.8-, 2.75-, or 3.3-V I/Os
Ports Interface (McBSP) • CLOCK:
– 16- and 8-Bit External Memory Interface (EMIF) – Real-Time Clock (RTC) with Crystal Input,
with Glueless Interface to: Separate Clock Domain, and Power Supply
• 8- or 16-Bit NAND Flash, 1- or 4-Bit ECC – Software-Programmable Phase-Locked Loop
• 8- and 16-Bit NOR Flash (PLL) Clock Generator
• Asynchronous Static RAM (SRAM) • BOOTLOADER:
• SDRAM or mSDRAM (1.8, 2.75, and 3.3 V) – On-Chip ROM Bootloader
– 3.84375M x 16-Bit Maximum Addressable • Each Peripheral Supports Unencrypted
External Memory Space (SDRAM or mSDRAM) Booting
– Universal Asynchronous Receiver/Transmitter • PACKAGE:
(UART) – 196-Terminal Pb-Free Plastic BGA (Ball Grid
– Device USB Port with Integrated 2.0 High- Array) (ZCH Suffix), 0.65-mm Pitch
Speed PHY that Supports:
• USB 2.0 Full- and High-Speed Devices
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMS320C5517
SPRS727C – AUGUST 2012 – REVISED APRIL 2014 www.ti.com
1.2 Applications
• Digital Two-Way Radios • Audio Devices (such as Echo-Cancellation
• Low-Power Analytics Applications (such as Headphones and Speakerphones or Wireless
Speech Recognition, Vision Sensing, and Headsets and Microphones)
Fingerprint Biometrics) • Portable Medical Devices
• Voice Applications (such as Voice Recorders,
Hands-Free Kits, and Voice-Enhancement
Subsystems)
1.3 Description
This device is a member of TI's C5000™ fixed-point Digital Signal Processor (DSP) product family and is
designed for low active and standby power consumption.
The device is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP
architecture achieves high performance and low power through increased parallelism and total focus on
power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-
bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses
dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data
reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each
with 4 channels, providing data movement for 16 independent channel contexts without CPU intervention.
Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the
CPU activity.
The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit
multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic and logic unit (ALU) is
supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the
ability to optimize parallel activity and power consumption. These resources are managed in the Address
Unit (AU) and Data Unit (DU) of the C55x CPU.
The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction
Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the
Program Unit (PU). The PU decodes the instructions, directs tasks to the AU and DU resources, and
manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution
of conditional instructions.
The GPIO functions along with the 10-bit SAR ADC to provide sufficient pins for status, interrupts, and bit
I/O for keyboards, and media interfaces.
Serial media is supported through two multimedia card and secure digital (MMC and SD) peripherals,
three Inter-IC Sound (I2S Bus) modules, one serial port interface (SPI) with up to four chip selects, one
master and slave multichannel serial port interface (McSPI) with up to three chip selects, one multichannel
serial port (McBSP), one I2C multimaster and slave interface, and a universal asynchronous
receiver/transmitter (UART) interface
The device peripheral set includes an external memory interface (EMIF) that provides glueless access to
asynchronous memories, such as EPROM, NOR, NAND, and SRAM, as well as to high-speed, high-
density memories such as synchronous DRAM (SDRAM) and mobile SDRAM (mSDRAM).
Additional peripherals include a configurable 16-bit universal host-port interface (UHPI), a high-speed
universal serial bus (USB2.0) device mode only, a real-time clock (RTC), three general-purpose timers
with one configurable as a watchdog timer, and an analog phase-locked loop (APLL) clock generator.
2 Device Overview Copyright © 2012–2014, Texas Instruments Incorporated

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The device also includes a tightly coupled FFT hardware accelerate that supports 8- to 1024-point (by
power of 2) real- and complex-valued FFTs and three integrated LDOs to power different sections of the
device, except CVDDRTC which requires an external power source: ANA_LDO to provide 1.3 V to the SAR
and power-management circuits (VDDA_ANA), DSP_LDO to provide 1.3 or 1.05 V to the DSP core (CVDD),
selectable on-the-fly by software as long as operating frequency ranges are observed, and USB_LDO to
provide 1.3 V to the USB core digital (USB_VDD1P3) and PHY circuits (USB_VDDA1P3).
The device is supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™
Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard, and a
large third-party network. Code Composer Studio IDE features code generation tools including a C
Compiler and Linker, RTDX™, XDS100, XDS510™, XDS560™ emulation device drivers, and evaluation
modules. The device is also supported by the C55x DSP library which features more than 50 foundational
software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip support libraries.
Device Information
PART NUMBER PACKAGE BODY SIZE
TMS320C5517AZCH20 NFBGA (196) 10.0 mm x 10.0 mm
TMS320C5517AZCHA20 NFBGA (196) 10.0 mm x 10.0 mm
Copyright © 2012–2014, Texas Instruments Incorporated Device Overview 3

TMS320C5517
1.4 Functional Block Diagram

Figure 1-1 shows the functional block diagram of the device.
DSP System
JTAG Interface C55x DSP CPU
Input PLL/Clock FFT Hardware

Clocks Generator Accelerator
Power 64KB DARAM

Management
256KB SARAM
Pin
Multiplexing 128KB ROM
Switched Central Resource (SCR)
Peripherals
Interconnect Serial Interfaces App-Spec
DMA I2S 10-Bit

(x4) I2C SPI McBSP McSPI UART SAR
(x3) ADC
Connectivity Program/Data Storage System
USB 2.0
NAND, NOR, MMC/SD GP Timer GP Timer
PHY (HS) UHPI (x2) RTC (x2) LDOs
SRAM, mSDRAM or WD
[DEVICE]
Figure 1-1. Functional Block Diagram
4 Device Overview Copyright © 2012–2014, Texas Instruments Incorporated

TMS320C5517
Table of Contents
1 Device Overview ......................................... 1 5.5 Thermal Characteristics ............................. 61
1.1 Features .............................................. 1 5.6 Power-On Hours .................................... 61
1.2 Applications ........................................... 2 5.7 Timing and Switching Characteristics ............... 62
1.3 Description ............................................ 2 6 Detailed Description.................................. 154
1.4 Functional Block Diagram ............................ 4 6.1 CPU ................................................ 154
2 Revision History ......................................... 6 6.2 Memory ............................................ 154
3 Device Comparison ..................................... 7 6.3 Identification........................................ 182
4 Terminal Configuration and Functions .............. 9 6.4 Boot Modes ........................................ 183
4.1 Pin Diagram .......................................... 9 7 Device and Documentation Support .............. 190
4.2 Signal Descriptions .................................. 10 7.1 Device Support..................................... 190
4.3 Pin Multiplexing...................................... 52 7.2 Documentation Support ............................ 192
4.4 Connections for Unused Signals .................... 56 7.3 Community Resources............................. 192
5 Specifications ........................................... 57 7.4 Trademarks ........................................ 192
5.1 Absolute Maximum Ratings ......................... 57 7.5 Electrostatic Discharge Caution ................... 192
5.2 Recommended Operating Conditions ............... 58 7.6 Glossary............................................ 192
5.3 Electrical Characteristics ............................ 59 8 Mechanical Packaging and Orderable
5.4 Handling Ratings .................................... 61 Information ............................................. 193
Copyright © 2012–2014, Texas Instruments Incorporated Table of Contents 5

TMS320C5517
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
This data manual revision history highlights the technical changes made from the previous revision to the
device-specific data manual.
SEE ADDITIONS, MODIFICATIONS, and DELETIONS
Global Removed 225-MHz device information.
6 Revision History Copyright © 2012–2014, Texas Instruments Incorporated

TMS320C5517
3 Device Comparison
Table 3-1 provides characteristics of the C5517 processor.
The table shows significant features of the devices, including the capacity of on-chip RAM, the
peripherals, the CPU frequency, and the package type with pin count. For more detailed information on
the actual device part number and maximum device operating frequency, see Section 7.1.2, Device
Nomenclature.
Table 3-1. Characteristics of the Processor

HARDWARE FEATURES C5517
Asynchronous (8- and 16-bit bus width) SRAM,
External Memory Interface (EMIF) Flash (NOR, NAND),
SDRAM and Mobile SDRAM (16-bit bus width) (1)
Peripherals
Not all peripheral pins Four DMA controllers each with four channels,
are available at the DMA
for a total of 16 channels
same time (for more
detail, see Section 5).
2 32-Bit General-Purpose (GP) Timers

1 Additional Timer Configurable as a 32-Bit GP Timer or a
Watchdog
Timers Each timer is capable of selecting its clock source among the
choices of:
• External from a GPIO pin
• System PLL
• 12.00 MHz USB oscillator
UART 1 (with RTS and CTS flow control)
SPI 1 with 4 chip selects (Master only)
McSPI 1 (Master and Slave synchronous serial bus) with 3 chip selects
UHPI 1 (A configurable 16-bit multiplexed host port interface)
2
I C 1 (Master and Slave)
I2S 3 (Two Channel, Full Duplex Communication)
High- and Full-Speed Device (device mode only, host mode not
USB 2.0
supported)
2 MMC and SD, 256 byte read and write buffer, max 50-MHz clock
MMC and SD
for SD cards, and signaling for DMA transfers
McBSP 1 (with transmit and receive)
ADC (Successive Approximation [SAR]) 1 (10-bit, 4-input, 16-µs conversion time)
Real-Time Clock (RTC) 1 (Crystal Input, Separate Clock Domain and Power Supply)
FFT Hardware Accelerator 1 (Supports 8 to 1024-point 16-bit real and complex FFT)
Up to 26 pins (with 1 Additional General-Purpose Output (XF) and 4
General-Purpose Input/Output Port (GPIO)
General-Purpose Outputs for Use With SAR)
• 64KB On-Chip Dual-Access RAM (DARAM)
On-Chip Memory Size and Organization • 256KB On-Chip Single-Access RAM (SARAM)
• 128KB On-Chip Single-Access ROM (SAROM)
JTAGID Register
JTAG BSDL_ID see Figure 6-2
(Value is: 0x0B95 602F)
CPU Frequency MHz 1.05-V Core 75 MHz
1.3-V Core 175 MHz
1.4-V Core 200 MHz
Cycle Time ns 1.05-V Core 13.3 ns
1.3-V Core 5.71 ns
(1) For more information on SDRAM devices support, see Section 5.7.6, External Memory Interface (EMIF).
Copyright © 2012–2014, Texas Instruments Incorporated Device Comparison 7
TMS320C5517
Table 3-1. Characteristics of the Processor (continued)

HARDWARE FEATURES C5517
1.4-V Core 5 ns
1.05 V (75 MHz)
Core (V) 1.3 V (175 MHz)
Voltage
1.4 V (200 MHz)
I/O (V) 1.8 V, 2.75 V, 3.3 V
1.3 V or 1.05 V, 250 mA max current for the digital core (to be used
only to supply CVDD).
LDOs DSP_LDO
Cannot be used to drive CVDD at the 1.4 V (>200 MHz) operating
range.
1.3 V, 4 mA max current for SAR and power management circuits
ANA_LDO
(to be used only to supply VDDA_ANA)
1.3 V, 25 mA max current for USB core digital and PHY circuits (to
USB_LDO
be used only to supply USB_VDD1P3 and USB_VDDA1P3)
Commercial Temperature (default) TMS320C5517AZCH20
Temperature
Industrial Temperature TMS320C5517AZCHA20
PLL Phase Lock Loop 1 (Software Programmable PLL)
BGA Package 10 x 10 mm 196-Terminal BGA (ZCH), 0.65-mm Pitch
Product Preview (PP),
Product Status (2) Advance Information (AI), PD
or Production Data (PD)
(2) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
8 Device Comparison Copyright © 2012–2014, Texas Instruments Incorporated

TMS320C5517
4 Terminal Configuration and Functions

4.1 Pin Diagram
Figure 4-1 shows the bottom view of the package pin assignments.
I2S2_FS/ I2S2_DX/ UART_CTS/ UART_TXD/

EM_DQM1/ SPI_CS0/ SPI_CS2/ SPI_RX/ GP[12]/ GP[15]/ GP[17]/ UHPI_HD[9]/ UHPI_HD[11]/ UHPI_HD[13]/ UHPI_HD[15]/
P DVDDEMIF DVDDIO UHPI_HCNTL0 UHPI_HR_NW UHPI_HD[0] DVDDIO
UHPI_HBE1 UHPI_HD[2] UHPI_HD[5] UHPI_HD[7] GP[19]/ GP[27]/ GP[29]/ GP[31]/
SPI_CS0 SPI_TX I2S3_FS I2S3_DX
I2S2_CLK/ I2S2_RX/ UART_RTS/ UART_RXD/

GP[21]/ EM_SDCKE/ SPI_CLK/ SPI_CS1/ SPI_CS3/ SPI_TX/ GP[13]/ GP[14]/ GP[16]/ UHPI_HD[8]/ UHPI_HD[10]/ UHPI_HD[12]/ UHPI_HD[14]/
N EM_A[15] UHPI_HHWIL UHPI_HINT UHPI_HCNTL1 UHPI_HRDY UHPI_HD[1] UHPI_HD[3] UHPI_HD[4] UHPI_HD[6] GP[18]/ GP[20]/ GP[28]/ GP[30]/ DVDDIO
SPI_CLK SPI_RX I2S3_CLK I2S3_RX
MMC0_D1/ MMC0_CMD/ MMC1_D1/ MMC1_CLK/ MMC1_D0/

EM_A[14] EM_D[5] EM_SDCLK EM_CS3 EMU1 TCK TDO XF TRST I2S0_RX/ I2S0_FS/ McSPI_SOMI/ McSPI_CLK/ McSPI_SIMO/
M
GP[3]/ GP[1]/ GP[9] GP[6] GP[8]
McBSP_DR McBSP_FSX
MMC0_D0/ MMC0_CLK/ MMC0_D3/

I2S0_DX/ I2S0_CLK/ GP[5]/ MMC0_D2/ MMC1_D3/ MMC1_CMD/
L EM_A[13] EM_A[10] EM_D[12] EM_D[4] CVDD EMU0 TDI TMS GP[2]/ GP[0]/ McBSP_ GP[4]/ McSPI_CS2/ McSPI_CS0/
McBSP_DX McBSP_CLKX CLKR_CLKS McBSP_FSR GP[11] GP[7]
EM_A[12]/ EM_A[11]/ MMC1_D2/

K EM_D[14] EM_D[13] EM_D[6] EM_WAIT3 DVDDIO VSS VSS CVDD VSS DVDDIO VSS
(CLE) (ALE) McSPI_CS1/
GP[10]
GP[26]/
J EM_A[8] EM_A[9] EM_A[20] EM_D[15] DVDDEMIF CVDD VSS VSS VSS RSV1 RSV2 USB_VBUS USB_VDD1P3 USB_DM
USB_ USB_ USB_ USB_

H EM_WE EM_A[7] EM_D[7] EM_WAIT5 DVDDEMIF VSS DVDDEMIF CVDD USB_VSS1P3 USB_DP
VSSA1P3 VDDA1P3 VSSA3P3 VDDA3P3
GP[24]/ GP[25]/
G EM_WAIT4 EM_D[0] DVDDEMIF VSS VSS USB_VDDPLL USB_R1 USB_VSSREF USB_VSSPLL USB_VDDOSC USB_MXI USB_MXO
EM_A[18] EM_A[19]
GP[23]/
F EM_A[6] EM_A[17] EM_D[2] EM_D[9] DVDDEMIF CVDD DVDDIO DVDDRTC VSS VSS USB_VSSOSC USB_LDOO LDOI LDOI
GP[22]/
E EM_A[2] EM_A[16] EM_D[8] EM_OE EM_D[1] DVDDEMIF INT1 WAKEUP VSS DSP_LDOO VSS VSS VSS VSS
EM_WAIT2 RTC_ VSSA_PLL GPAIN0 DSP_ RSV16 RSV3

D EM_A[5] EM_A[3] EM_D[10] EM_D[3] RESET VSS VSS
CLKOUT LDO_EN
C EM_A[4] EM_A[1] EM_CS4 EM_D[11] EM_CS2 INT0 CLK_SEL CVDDRTC VSSRTC VDDA_PLL GPAIN3 RSV0 RSV5 RSV4
B EM_BA[1] EM_A[0] EM_CS0/ EM_SDCAS/ EM_DQM0/ EM_R/W SCL SDA RTC_XI VSSA_ANA GPAIN2 LDOI BG_CAP VSSA_ANA
UHPI_HDS1 UHPI_HCS UHPI_HBE0
A EM_BA[0] DVDDEMIF EM_CS5 EM_CS1/ DVDDEMIF EM_SDRAS/ CLKOUT CLKIN RTC_XO VDDA_ANA GPAIN1 ANA_LDOO VSS VSS
UHPI_HDS2 UHPI_HAS
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Pins with multiple names default to the first, bolded name when reset (for example, GP[21]/EM_A[15] defaults to
GP[21] when reset).
Figure 4-1. Pin Diagram
Copyright © 2012–2014, Texas Instruments Incorporated Terminal Configuration and Functions 9

TMS320C5517
4.2 Signal Descriptions

The signal descriptions tables (Table 4-1 through Table 4-19) identify the external signal names, the
associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin
has any internal pullup or pulldown resistors or bus-holders, and a functional pin description. For more
information on pin multiplexing, see Section 4.3, Pin Multiplexing.
For proper device operation, external pullup and pulldown resistors may be required on some pins.
Section 5.7.20.1.1, Pullup and Pulldown Resistors discusses situations where external pullup and
pulldown resistors are required.
10 Terminal Configuration and Functions Copyright © 2012–2014, Texas Instruments Incorporated

TMS320C5517
4.2.1 Oscillator and PLL

Table 4-1. Oscillator and PLL Signal Descriptions
SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME NO.
DSP clock output signal. For debug purposes, the CLKOUT pin can be used to tap
different clocks within the system clock generator. The CLKOUT_SRC bits in the
CLKOUT Configuration Register (CLKOUTCR) can be used to specify the
CLKOUT pin source. Additionally, the slew rate of the CLKOUT pin can be
controlled by the Output Slew Rate Control Register (OSRCR) [0x1C16].
The output driver of the CLKOUT pin is enabled and disabled through the
IPD CLKOFF bit in the CPU ST3_55 register. When disabled, the CLKOUT pin's
CLKOUT A7 O/Z DVDDIO output driver is placed in high-impedance (Hi-Z) and the IPD is automatically
BH enabled. When enabled, the output driver of the pin is enabled and the IPD is
automatically disabled.
At reset the CLKOUT pin is enabled until the beginning of the boot sequence, at
which point the on-chip Bootloader sets CLKOFF = 1 and the CLKOUT pin is
disabled (Hi-Z). For more information on the ST3_55 register, see the C55x 3.0
CPU Reference Guide [literature number: SWPU073].
The IPD resistor on this pin is enabled when CLKOUT is in Hi-Z state.
Input clock. This signal is used to input an external clock when the 12-MHz on-
chip USB oscillator is not used as the system clock (CLK_SEL = 1).
To appropriately set the various serial port frequencies during bootloading, the
bootloader ROM code assumes CLKIN is running at the frequency indicated by
the setting (see Section 6.4, Boot Modes, for the supported frequencies and
details about the bootmode).
IPD
CLKIN A8 I DVDDIO The CLK_SEL pin selects the source for the system clock generator, with the
BH options being the USB oscillator (CLK_SEL=0) or CLKIN (CLK_SEL=1) pins.
When the CLK_SEL pin is low, this pin should be tied to ground (VSS). When
CLK_SEL is high, this pin should be driven by an external clock source.
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2
(1C18h) register.
The IPD disabled at reset.
Clock input select. This pin selects between the on-chip USB oscillator or CLKIN.
0 = The on-chip USB oscillator is enabled at reset and drives the system clock
generator. The CLKIN is ignored. Also, the USB LDOO is enabled at reset
(USB_LDO_EN=1). The on-chip USB oscillator and USB_LDO cannot be disabled
– if CLK_SEL=0.
CLK_SEL C7 I DVDDIO
BH 1 = CLKIN drives the system clock generator. The on-chip USB oscillator and USB
LDO are disabled at reset (USB_LDO_EN=1), but they can be enabled by
software.
This pin is not allowed to change during device operation; it must be tied high or
low at the board.
1.3-V Analog PLL power supply for the system clock generator.
see Section 5.2,
VDDA_PLL C10 PWR
ROC This supply pin must not be connected to ANA_LDOO pin. The supply pin must be
externally powered.
see Section 5.2,
VSSA_PLL D9 GND Analog PLL ground for the system clock generator.
ROC
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
(2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When they are configured as input or tri-stated, and not driven to a known state, they may cause an excessive IO-supply current.
Prevent this current by externally terminating it or enabling IPD and IPU, if applicable.
(3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.20.1.1, Pullup and Pulldown Resistors.
(4) Specifies the operating I/O supply voltage for each signal

TMS320C5517
4.2.2 Real-Time Clock (RTC)

Table 4-2. RTC Signal Descriptions
SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME NO.
Real-time clock oscillator output. This pin operates at the RTC core voltage,
CVDDRTC, and supports a 32.768-kHz crystal.
If the RTC oscillator is not used, it can be disabled by connecting RTC_XI to
– CVDDRTC and RTC_XO to ground (VSS).
RTC_XO A9 O/Z CVDDRTC A voltage must still be applied to CVDDRTC by an external power source (see
DVDDRTC Section 5.2, Recommended Operating Conditions). None of the on-chip LDOs can
power CVDDRTC.
Note: When RTC oscillator is disabled, the RTC registers (I/O address range
1900h – 197Fh) are not accessible.
Real-time clock oscillator input.
If the RTC oscillator is not used, it can be disabled by connecting RTC_XI to
CVDDRTC and RTC_XO to ground (VSS).
–
RTC_XI B9 I CVDDRTC A voltage must still be applied to CVDDRTC by an external power source (see
DVDDRTC Section 5.2, Recommended Operating Conditions). None of the on-chip LDOs can
power CVDDRTC.
Note: When RTC oscillator is disabled, the RTC registers (I/O address range
1900h – 197Fh) are not accessible.
Real-time clock output pin. This pin operates at DVDDRTC voltage.

– The RTC_CLKOUT pin is enabled and disabled through the RTCCLKOUTEN bit in
RTC_CLKOUT D8 O/Z
DVDDRTC the RTC Power Management Register (RTCPMGT).
At reset, the RTC_CLKOUT pin is disabled (high-impedance [Hi-Z]).
The active-high pin is used to WAKEUP the core from idle condition. This pin
–
WAKEUP E8 I/O/Z defaults to an input at CVDDRTC powerup, but can also be configured as an active-
DVDDRTC
low open-drain output signal to wakeup an external device from an RTC alarm.

TMS320C5517
4.2.3 RESET, Interrupts, and JTAG

Table 4-3. RESET, Interrupts, and JTAG Signal Descriptions
SIGNAL
TYPE (1) (2)
OTHER (3) (4)
DESCRIPTION
NAME NO.
RESET
External Flag Output. XF is used for signaling other processors in
multiprocessor configurations or XF can be used as a fast general-
purpose output pin.
XF is set high by the BSET XF instruction and XF is set low by the
BCLR XF instruction or by writing to bit 13 of the ST1_55 register. For
IPU more information on the ST1_55 register, see the C55x 3.0 CPU
XF M8 O/Z DVDDIO Reference Guide [literature number: SWPU073].
BH
For the XF pin's states after reset, see Figure 5-9, BootMode Latching.
XF pin can manually configured as Hi-Z state only in boundary-scan
mode. When this pin is in Hi-Z state, the IPU is enabled.
The IPU on this pin is disabled at reset.
Device reset. RESET causes the DSP to terminate execution and loads
the program counter with the contents of the reset vector. When
RESET is brought to a high level, the reset vector in ROM at FFFF00h
forces the program execution to branch to the location of the on-chip
IPU ROM bootloader.
RESET D6 I DVDDIO
BH RESET affects the various registers and status bits.
The IPU resistor on this pin can be enabled or disabled via the
PUDINHIBR2 (1C18h).
The IPU is disabled at reset.
JTAG
For more detailed information on emulation header design guidelines, see the XDS560 Emulator Technical Reference [literature number:
SPRU589].
IEEE standard 1149.1 test mode select. This serial control input is
clocked into the TAP controller on the rising edge of TCK.
If the emulation header is located greater than 6 inches from the
device, TMS must be buffered. In this case, the input buffer for TMS
needs a pullup resistor connected to DVDDIO to hold the signal at a
IPU known value when the emulator is not connected. A resistor value of
TMS L8 I DVDDIO 4.7 kΩ or greater is suggested. For board design guidelines related to
BH the emulation header, see the XDS560 Emulator Technical Reference
[literature number: SPRU589].
PUDINHIBR2 (1C18h) register.
The IPU is enabled at reset.
TMS320C5517
Table 4-3. RESET, Interrupts, and JTAG Signal Descriptions (continued)

SIGNAL
TYPE (1) (2)
OTHER (3) (4)
DESCRIPTION
NAME NO.
IEEE standard 1149.1 test data output. The contents of the selected
register (instruction or data) are shifted out of TDO on the falling edge
of TCK. TDO is in the high-impedance (Hi-Z) state except when the
scanning of data is in progress.
For board design guidelines related to the emulation header, see the
XDS560 Emulator Technical Reference [literature number: SPRU589].
device, TDO must be buffered.
IPU Despite the fact that the IEEE 1149.1 (JTAG) standard defines the TDO
TDO M7 I/O/Z DVDDIO pin as a 3-state output (O/Z), this device has a bidirectional IO-cell. The
BH bidirectional cell's input buffer is used for non-JTAG production test
purposes. To achieve the lowest power, this input buffer must not be
allowed to float.
The IEEE standard defines the pin as tri-stated in the Test-Logic-Reset
state and our device obeys that requirement. Therefore, to achieve the
lowest power the IPU should remain enabled.
IEEE standard 1149.1 test data input. TDI is clocked into the selected
register (instruction or data) on a rising edge of TCK.
device, TDI must be buffered. In this case, the input buffer for TDI
IPU needs a pullup resistor connected to DVDDIO to hold this signal at a
TDI L7 I DVDDIO known value when the emulator is not connected. A resistor value of
BH 4.7 kΩ or greater is suggested.
IEEE standard 1149.1 test clock. TCK is normally a free-running clock
signal with a 50% duty cycle. The changes on input signals TMS and
TDI are clocked into the TAP controller, instruction register, or selected
test data register on the rising edge of TCK. Changes at the TAP output
signal (TDO) occur on the falling edge of TCK.
IPU If the emulation header is located greater than 6 inches from the
TCK M6 I DVDDIO device, TCK must be buffered.
BH
IEEE standard 1149.1 reset signal for test and emulation logic. TRST,
when high, allows the IEEE standard 1149.1 scan and emulation logic
to take control of the operations of the device. If TRST is not connected
or is driven low, the device operates in its functional mode, and the
IEEE standard 1149.1 signals are ignored. The device will not operate
properly if this reset pin is never asserted low.
IPD For board design guidelines related to the emulation header, see the
TRST M9 I DVDDIO XDS560 Emulator Technical Reference [literature number: SPRU589].
BH
It is recommended that an external pulldown resistor be used in
addition to the IPD -- especially if there is a long trace to an emulation
header.
The IPD resistor on this pin can be enabled or disabled via the
The IPD is enabled at reset.

TMS320C5517
Table 4-3. RESET, Interrupts, and JTAG Signal Descriptions (continued)

SIGNAL
TYPE (1) (2)
OTHER (3) (4)
DESCRIPTION
NAME NO.
Emulator 1 pin. EMU1 is used as an interrupt to or from the emulator
system and is defined as input/output by way of the emulation logic.
IPU An external pullup to DVDDIO is required to provide a signal rise time of

EMU1 M5 I/O/Z DVDDIO less than 10 µsec. A 4.7-kΩ resistor is suggested for most applications.
BH For board design guidelines related to the emulation header, see the
Emulator 0 pin. When TRST is driven low and then high, the state of
the EMU0 pin is latched and used to connect the JTAG pins (TCK,
TMS, TDI, TDO) to either the IEEE1149.1 Boundary-Scan TAP (when
the latched value of EMU0 = 0) or to the DSP Emulation TAP (when the
latched value of EMU0 = 1). Once TRST is high, EMU0 is used as an
interrupt to or from the emulator system and is defined as input/output
by way of the emulation logic.
IPU
EMU0 L6 I/O/Z DVDDIO An external pullup to DVDDIO is required to provide a signal rise time of
BH less than 10 µsec. A 4.7-kΩ resistor is suggested for most applications.
EXTERNAL INTERRUPTS
IPU External interrupt inputs (INT1 and INT0). These pins are maskable via
INT1 E7 I DVDDIO their specific Interrupt Mask Register (IMR1, IMR0) and the interrupt
BH mode bit. The pins can be polled and reset by their specific Interrupt
Flag Register (IFR1, IFR0).
IPU The IPU resistor on these pins can be enabled or disabled via the
INT0 C6 I DVDDIO PUDINHIBR2 (1C18h) register.
BH
The IPU is disabled at reset.

TMS320C5517
4.2.4 External Memory Interface (EMIF)
Table 4-4. EMIF Signal Descriptions

SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME (5) NO.
EMIF FUNCTIONAL PINS: ASYNC (NOR, SRAM, and NAND)
Note: When accessing 8-bit Asynchronous memory:
• Connect EM_A[20:0] to memory address pins [22:2]
• Connect EM_BA[1:0] to memory address pins [1:0]
For 16-bit Asynchronous memory:
• Connect EM_A[20:1] to memory address pins [20:1]
• Connect EM_BA[1] to memory address pin [0]
This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF
external address pin 20.
IPD Mux control via the A20_MODE bit in the EBSR (see Figure 5-10).
GP[26]/
J3 I/O/Z DVDDEMIF
EM_A[20] The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2
BH
(1C18h) register.
The IPD is disabled at reset.
GP[25]/
G4 I/O/Z DVDDEMIF
BH
(1C18h) register.
GP[24]/
G2 I/O/Z DVDDEMIF
BH
(1C18h) register.
GP[23]/
F2 I/O/Z DVDDEMIF
BH
(1C18h) register.
GP[22]/
E2 I/O/Z DVDDEMIF
BH
(1C18h) register.
(5) Pins with multiple names default to the first, bolded name when reset (for example, GP[21]/EM_A[15] defaults to GP[21] when reset).
TMS320C5517
Table 4-4. EMIF Signal Descriptions (continued)

SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME (5) NO.
GP[21]/
N1 I/O/Z DVDDEMIF
BH
(1C18h) register.
This pin is the EMIF external address pin 14.

IPD
EM_A[14] M1 I/O/Z DVDDEMIF The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5
BH (1C4Dh) register.

IPD
EM_A[13] L1 I/O/Z DVDDEMIF The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5
This pin is the EMIF external address pin 12. When interfacing with NAND Flash,
IPD this pin also acts as Command Latch Enable (CLE).
EM_A[12]/
K1 I/O/Z DVDDEMIF The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5
(CLE)
This pin is the EMIF external address pin 11. When interfacing with NAND Flash,
IPD this pin also acts as Address Latch Enable (ALE).
EM_A[11]/
K2 I/O/Z DVDDEMIF The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5
(ALE)

IPD
EM_A[10] L2 I/O/Z DVDDEMIF The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5

IPD
EM_A[9] J2 I/O/Z DVDDEMIF The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5

IPD
EM_A[8] J1 I/O/Z DVDDEMIF The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5

IPD
EM_A[7] H2 I/O/Z DVDDEMIF The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5

TMS320C5517

SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME (5) NO.

IPD
EM_A[6] F1 I/O/Z DVDDEMIF The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5

IPD
EM_A[5] D1 I/O/Z DVDDEMIF The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5

IPD
EM_A[4] C1 I/O/Z DVDDEMIF The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5

IPD
EM_A[3] D2 I/O/Z DVDDEMIF The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5

IPD
EM_A[2] E1 I/O/Z DVDDEMIF The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5

IPD
EM_A[1] C2 I/O/Z DVDDEMIF The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5

IPD
EM_A[0] B2 I/O/Z DVDDEMIF The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5

TMS320C5517

SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME (5) NO.
EM_D[15] J4
EM_D[14] K3
EM_D[13] K4
EM_D[12] L3
EM_D[11] C4
EM_D[10] D3
EM_D[9] F4 EMIF 16-bit bidirectional bus.
EM_D[8] E3 IPD
I/O/Z DVDDEMIF The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR4
EM_D[7] H3 BH (1C4Ch) register.
EM_D[6] K5 The IPD is disabled at reset.
EM_D[5] M2
EM_D[4] L4
EM_D[3] D4
EM_D[2] F3
EM_D[1] E5
EM_D[0] G3
EMIF chip select 5 output for use with asynchronous memories (that is, NOR flash,
IPD NAND flash, or SRAM).
EM_CS5 A3 O/Z DVDDEMIF The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6
BH (1C4Fh) register.
EMIF chip select 4 output for use with asynchronous memories (that is, NOR flash,
IPD NAND flash, or SRAM).
EM_CS4 C3 O/Z DVDDEMIF The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6
EMIF NAND chip select 3 output for use with asynchronous memories (that is, NOR
IPD flash, NAND flash, or SRAM).
EM_CS3 M4 O/Z DVDDEMIF The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6
EMIF NAND chip select 2 output for use with asynchronous memories (that is, NOR
IPD flash, NAND flash, or SRAM).
EM_CS2 C5 O/Z DVDDEMIF The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6
EMIF asynchronous memory write enable output

IPD
EM_WE H1 O/Z DVDDEMIF The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6
EMIF asynchronous memory read enable output

IPD
EM_OE E4 O/Z DVDDEMIF The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6

TMS320C5517

SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME (5) NO.
EMIF asynchronous read and write output

IPD
EM_R/W B6 O/Z DVDDEMIF The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6
IPD
EM_DQM1/ These pins are multiplexed between EMIF and UHPI. For EMIF, asynchronous data
P1 I/O/Z DVDDEMIF
UHPI_HBE1 write strobes and byte enables or EMIF SDRAM and mSDRAM data mask bits.
BH
Mux control via the PPMODE bits in the EBSR.
IPD The IPD resistor on these pins can be enabled or disabled via the PUDINHIBR6
EM_DQM0/
B5 I/O/Z DVDDEMIF (1C4Fh) register.
UHPI_HBE0
BH
IPD EMIF asynchronous bank address
EM_BA[1] B1 O/Z DVDDEMIF
BH 16-bit wide memory: EM_BA[1] forms the device address[0] and BA[0] forms device
address [23].
8-bit wide memory: EM_BA[1] forms the device address[1] and BA[0] forms device
address [0].
IPD
EM_BA[0] A1 O/Z DVDDEMIF EMIF SDRAM and mSDRAM bank address.
BH The IPD resistor on these pins can be enabled or disabled via the PUDINHIBR6
(1C4Fh) register.
EMIF wait state extension input 5 for EM_CS5

IPD
EM_WAIT5 H4 I DVDDEMIF The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6

IPD
EM_WAIT4 G1 I DVDDEMIF The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6

IPD
EM_WAIT3 K6 I DVDDEMIF The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6

IPD
EM_WAIT2 D5 I DVDDEMIF The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6
EMIF FUNCTIONAL PINS: SDRAM and mSDRAM ONLY
This pin is multiplexed between EMIF and UHPI. For EMIF, SDRAM and mSDRAM
chip select 1 output
IPD
EM_CS1/ Mux control via the PPMODE bits in the EBSR.
A4 I/O/Z DVDDEMIF
UHPI_HDS2
BH The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7
(1C50h) register.

TMS320C5517

SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME (5) NO.
IPD chip select 0 output
EM_CS0/
B3 I/O/Z DVDDEMIF Mux control via the PPMODE bits in the EBSR.
UHPI_HDS1
BH
(1C50h) register.
EMIF SDRAM and mSDRAM clock

IPD
EM_SDCLK M3 O/Z DVDDEMIF The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7
BH (1C50h) register.
clock enable
IPD
EM_SDCKE/ Mux control via the PPMODE bits in the EBSR.
N2 I/O/Z DVDDEMIF
UHPI_HHWIL
(1C50h) register.
row address strobe
IPD
EM_SDRAS/ Mux control via the PPMODE bits in the EBSR.
A6 I/O/Z DVDDEMIF
UHPI_HAS
(1C50h) register.
column strobe
IPD
EM_SDCAS/ Mux control via the PPMODE bits in the EBSR.
B4 I/O/Z DVDDEMIF
UHPI_HCS
(1C50h) register.

TMS320C5517
4.2.5 Inter-Integrated Circuit (I2C)
Table 4-5. Inter-Integrated Circuit (I2C) Signal Descriptions

SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME NO.
I2C
–
This pin is the I2C clock output. Per the I2C standard, an external pullup is required
SCL B7 I/O/Z DVDDIO
on this pin.
BH
–
This pin is the I2C bidirectional data signal. Per the I2C standard, an external pullup
SDA B8 I/O/Z DVDDIO
is required on this pin.
BH

TMS320C5517
4.2.6 Inter-IC Sound (I2S)
Table 4-6. Inter-IC Sound (I2S0, I2S2, and I2S3) Signal Descriptions
SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME (5) NO.
Interface 0 (I2S0)
This pin is multiplexed between MMC0, I2S0, McBSP and GPIO.
For I2S, it is I2S0 transmit data output I2S0_DX.
MMC0_D0/
IPD
I2S0_DX/ Mux control via the SP0MODE bits in the EBSR.
L9 I/O/Z DVDDIO
GP[2]/
McBSP_DX
(1C17h) register.
For I2S, it is I2S0 clock input/output I2S0_CLK.
MMC0_CLK/
IPD
I2S0_CLK/ Mux control via the SP0MODE bits in the EBSR.
L10 I/O/Z DVDDIO
GP[0]/
McBSP_CLKX
(1C17h) register.
For I2S, it is I2S0 receive data input I2S0_RX.
MMC0_D1/
IPD
I2S0_RX/ Mux control via the SP0MODE bits in the EBSR.
M10 I/O/Z DVDDIO
GP[3]/
McBSP_DR
(1C17h) register.
For I2S, it is I2S0 frame synchronization input/output I2S0_FS.
MMC0_CMD/
IPD
I2S0_FS/ Mux control via the SP0MODE bits in the EBSR.
M11 I/O/Z DVDDIO
GP[1]/
McBSP_FSX
(1C17h) register.
Interface 1 (I2S2)
This pin is multiplexed between I2S2, UHPI, GPIO, and SPI.
I2S2_DX/
IPD
UHPI_HD[11]/ Mux control via the PPMODE bits in the EBSR.
P12 I/O/Z DVDDIO
GP[27]/
SPI_TX
(1C19h) register.
TMS320C5517
Table 4-6. Inter-IC Sound (I2S0, I2S2, and I2S3) Signal Descriptions (continued)
SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME (5) NO.
I2S2_CLK/
IPD
N10 I/O/Z DVDDIO
GP[18]/
SPI_CLK
(1C19h) register.
This pin is multiplexed between UHPI, I2S2, GPIO, and SPI.
I2S2_RX/
IPD
N11 I/O/Z DVDDIO
GP[20]/
SPI_RX
(1C19h) register.
I2S2_FS/
IPD
P11 I/O/Z DVDDIO
GP[19]/
SPI_CS0
(1C19h) register.
Interface 2 (I2S3)
This pin is multiplexed between UART, UHPI, GPIO, and I2S3.
UART_TXD/
IPD
P14 I/O/Z DVDDIO
GP[31]/
I2S3_DX
(1C19h) register.
UART_RTS/
IPD
N12 I/O/Z DVDDIO
GP[28]/
I2S3_CLK
(1C19h) register.
UART_RXD/
IPD
N13 I/O/Z DVDDIO
GP[30]/
I2S3_RX
(1C19h) register.
UART_CTS/
IPD
P13 I/O/Z DVDDIO
GP[29]/
I2S3_FS
(1C19h) register.

TMS320C5517
4.2.7 Multichannel Buffered Serial Port (McBSP)
Table 4-7. McBSP Signal Descriptions

SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME (5) NO.
McBSP
MMC0_CLK/ For McBSP, this is the McBSP transmit clock, McBSP_CLKX.

IPD
L10 I/O/Z DVDDIO
GP[0]/
BH
McBSP_CLKX The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
MMC0_CMD/ For McBSP, this is the McBSP transmit frame sync, McBSP_FSX.
IPD
M11 I/O/Z DVDDIO
GP[1]/
BH
McBSP_FSX The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
MMC0_D0/ For McBSP, this is the McBSP transmit data , McBSP_DX.

IPD
L9 I/O/Z DVDDIO
GP[2]/
BH
McBSP_DX The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
MMC0_D1/ For McBSP, this is the McBSP receive data, McBSP_RX.

IPD
M10 I/O/Z DVDDIO
GP[3]/
BH
McBSP_DR The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
This pin is multiplexed between MMC0, McBSP and GPIO.

For McBSP, this is the McBSP receive frame sync, McBSP_FSR.
MMC0_D2/ IPD
GP[4]/ L12 I/O/Z DVDDIO Mux control via the SP0MODE bits in the EBSR.
McBSP_FSR BH
(1C17h) register.
TMS320C5517
Table 4-7. McBSP Signal Descriptions (continued)

SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME (5) NO.
This pin is multiplexed between MMC0, McBSP and GPIO.

For McBSP, this is the McBSP receive clock, McBSP_CLKR or the McBSP sample
MMC0_D3/ rate generator clock input, McBSP_CLKS. The bit 15 of EBSR register determines
IPD this port to be McBSP_CLKR or McBSP_CLKS.
GP[5]/
L11 I/O/Z DVDDIO
McBSP_CLKR_ Mux control via the SP0MODE bits in the EBSR.
BH
CLKS
(1C17h) register.

TMS320C5517
4.2.8 Multichannel Serial Port Interface (McSPI)
Table 4-8. McSPI Signal Descriptions

SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME (5) NO.
McSPI
This pin is multiplexed between MMC1, McSPI and GPIO.

For McSPI, this is the McSPI data clock, McSPI_CLK.
MMC1_CLK/ IPD
McSPI_CLK/ M13 I/O/Z DVDDIO Mux control via the SP1MODE bits in the EBSR.
GP[6] BH
(1C17h) register.

For McSPI, this is the McSPI chip select 0 signal, McSPI_CS0.
MMC1_CMD/ IPD
McSPI_CS0/ L14 I/O/Z DVDDIO Mux control via the SP1MODE bits in the EBSR.
GP[7] BH
(1C17h) register.

For McSPI, this is the McSPI data, McSPI_SIMO (Slave Input Master Output).
MMC1_D0/ IPD
McSPI_SIMO/ M14 I/O/Z DVDDIO Mux control via the SP1MODE bits in the EBSR.
GP[8] BH
(1C17h) register.

For McSPI, this is the McSPI data, McSPI_SOMI (Slave Output Master Input).
MMC1_D1/ IPD
McSPI_SOMI/ M12 I/O/Z DVDDIO Mux control via the SP1MODE bits in the EBSR.
GP[9] BH
(1C17h) register.

MMC1_D2/ IPD
McSPI_CS1/ K14 I/O/Z DVDDIO Mux control via the SP1MODE bits in the EBSR.
GP[10] BH
(1C17h) register.
TMS320C5517
Table 4-8. McSPI Signal Descriptions (continued)

SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME (5) NO.

MMC1_D3/ IPD
McSPI_CS2/ L13 I/O/Z DVDDIO Mux control via the SP1MODE bits in the EBSR.
GP[11] BH
(1C17h) register.

TMS320C5517
4.2.9 Serial Peripheral Interface (SPI)
Table 4-9. SPI Signal Descriptions

SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME (5) NO.
Serial Port Interface (SPI)
This pin is multiplexed between UHPI and SPI.
IPD
SPI_CS0/ For SPI, this pin is SPI chip select SPI_CS0.
P4 I/O/Z DVDDIO
UHPI_HCNTL0
(1C50h) register.
I2S2_FS/
IPD
UHPI_HD[9]/ For SPI, this pin is SPI chip select SPI_CS0.
P11 I/O/Z DVDDIO
GP[19]/
SPI_CS0
(1C19h) register.
This pin is multiplexed between SPI and UHPI.
IPD
N4 I/O/Z DVDDIO
UHPI_HCNTL1
(1C50h) register.

IPD For SPI, this pin is SPI chip select SPI_CS2.
SPI_CS2/
P5 I/O/Z DVDDIO
UHPI_HR_NW The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7
BH
(1C50h) register.

IPD
N5 I/O/Z DVDDIO
UHPI_HRDY
BH
(1C50h) register.

IPD
SPI_CLK / For SPI, this pin is clock output SPI_CLK.
N3 O/Z DVDDIO
UHPI_HINT
BH
(1C50h) register.
TMS320C5517
Table 4-9. SPI Signal Descriptions (continued)

SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME (5) NO.
I2S2_CLK/
IPD
UHPI_HD[8]/ For SPI, this pin is clock output SPI_CLK.
N10 I/O/Z DVDDIO
GP[18]/
SPI_CLK
(1C19h) register.

IPD
SPI_TX / For SPI, this pin is SPI transmit data output.
N6 I/O/Z DVDDIO
UHPI_HD[1]
BH
(1C19h) register.
I2S2_DX/
IPD
UHPI_HD[11]/ For SPI, this pin is SPI transmit data output.
P12 I/O/Z DVDDIO
GP[27]/
SPI_TX
(1C19h) register.

IPD
SPI_RX/ For SPI this pin is SPI receive data input.
P6 I/O/Z DVDDIO
UHPI_HD[0]
BH
(1C19h) register.
I2S2_RX/
IPD
UHPI_HD[10]/ For SPI this pin is SPI receive data input.
N11 I/O/Z DVDDIO
GP[20]/
SPI_RX
(1C19h) register.

TMS320C5517
4.2.10 Universal Asynchronous Receiver and Transmitter (UART)
Table 4-10. UART Signal Descriptions

SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME (5) NO.
UART
When used by UART, it is the receive data input UART_RXD.
UART_RXD/
IPD
N13 I/O/Z DVDDIO
GP[30]/
I2S3_RX
(1C19h) register.
In UART mode, it is the transmit data output UART_TXD.
UART_TXD/
IPD
P14 I/O/Z DVDDIO
GP[31]/
I2S3_DX
(1C19h) register.
In UART mode, it is the clear to send input UART_CTS.
UART_CTS/
IPD
P13 I/O/Z DVDDIO
GP[29]/
I2S3_FS
(1C19h) register.
In UART mode, it is the ready to send output UART_RTS.
UART_RTS/
IPD
N12 I/O/Z DVDDIO
GP[28]/
I2S3_CLK
(1C19h) register.

TMS320C5517
4.2.11 Universal Serial Bus (USB) 2.0
Table 4-11. USB2.0 Signal Descriptions

SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME NO.
USB 2.0
12-MHz crystal oscillator input used for the USB subsystem and optionally for the
system clock generator.
If CLK_SEL=0, the USB oscillator is enabled at reset and is used as the clock
source for the system clock generator. In this configuration (CLK_SEL=0), the USB
oscillator cannot be disabled.
If CLK_SEL=1, the USB oscillator is disabled at reset and the CLKIN pin is used as
USB_MXI G13 I USB_VDDOSC the source for the system clock generator. In this configuration (CLK_SEL=1), the
USB oscillator can be enabled or disabled via software.
When using an external 12-MHz oscillator, the external oscillator clock signal should
be connected to the USB_MXI pin and the amplitude of the oscillator clock signal
must meet the VIH requirement (see Section 5.2, Recommended Operating
Conditions). The USB_MXO is left unconnected and the USB_VSSOSC signal is
connected to board ground (VSS).
12-MHz crystal oscillator output used for the USB subsystem and optionally for the
system clock generator.
If CLK_SEL=0, the USB oscillator is enabled at reset and is used as the clock
source for the system clock generator. In this configuration (CLK_SEL=0), the USB
oscillator cannot be disabled.
If CLK_SEL=1, the USB oscillator is disabled at reset and the CLKIN pin is used as
USB_MXO G14 O USB_VDDOSC the source for the system clock generator. In this configuration (CLK_SEL=1), the
USB oscillator can be enabled or disabled via software.
When using an external 12-MHz oscillator, the external oscillator clock signal should
be connected to the USB_MXI pin and the amplitude of the oscillator clock signal
must meet the VIH requirement (see Section 5.2, Recommended Operating
see 3.3-V power supply for USB oscillator.

USB_VDDOSC G12 S Section 5.2, When the USB peripheral is not used, USB_VDDOSC should be connected to ground
ROC (VSS).
Ground for USB oscillator. When using a 12-MHz crystal, this pin is a local ground
for the crystal and must not be connected to the board ground (See Figure 5-11).
see When using an external 12-MHz oscillator, the external oscillator clock signal should
USB_VSSOSC F11 S Section 5.2, be connected to the USB_MXI pin and the amplitude of the oscillator clock signal
ROC must meet the VIH requirement (see Section 5.2, Recommended Operating
USB power detect. 5-V input that signifies that VBUS is connected.
see This signal must be powered on in the order listed in Section 5.7.2.2, Power-Supply
USB_VBUS J12 A Section 5.2, Sequencing.
ROC
When the USB peripheral is not used, the USB_VBUS signal should be connected
to ground (VSS).
USB_DP H14 A I/O USB_VDDA3P3 USB bidirectional Data Differential signal pair [positive and negative].
USB_DM J14 A I/O USB_VDDA3P3 When the USB peripheral is not used, the USB_DP and USB_DM signals should
both be tied to ground (VSS).
TMS320C5517
Table 4-11. USB2.0 Signal Descriptions (continued)

SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME NO.
External resistor connect. Reference current output. This pin must be connected via
a 10-kΩ ±1% resistor to USB_VSSREF and be placed as close to the device as
USB_R1 G9 A I/O USB_VDDA3P3 possible.
When the USB peripheral is not used, the USB_R1 signal should be connected via
a 10-kΩ resistor to USB_VSSREF.
Ground for reference current. This must be connected via a 10-kΩ ±1% resistor to
see USB_R1.
USB_VSSREF G10 GND Section 5.2,
ROC When the USB peripheral is not used, the USB_VSSREF signal should be connected
directly to ground (Vss).
Analog 3.3 V power supply for USB PHY.
USB_VDDA3P3 H12 S Section 5.2, Sequencing.
ROC
When the USB peripheral is not used, the USB_VDDA3P3 signal should be
connected to ground (VSS).
see
USB_VSSA3P3 H11 GND Section 5.2, Analog ground for USB PHY.
ROC
Analog 1.3 V power supply for USB PHY. [For high-speed sensitive analog circuits]
ROC
see
USB_VSSA1P3 H9 GND Section 5.2, Analog ground for USB PHY [For high speed sensitive analog circuits].
ROC
1.3-V digital core power supply for USB PHY.
USB_VDD1P3 J13 S Section 5.2, Sequencing.
ROC
When the USB peripheral is not used, the USB_VDD1P3 signal should be connected
to ground (VSS).
see
USB_VSS1P3 H13 GND Section 5.2, Digital core ground for USB PHY.
ROC
3.3 V USB Analog PLL power supply.
see Care should be taken to prevent noise on this supply. Consider using a ferrite bead
USB_VDDPLL G8 S Section 5.2, if the power supply for this pin is shared with digital logic. See the Filtering
ROC Techniques Application Report [literature number: SCAA048] for more information.
When the USB peripheral is not used, the USB_VDDPLL signal should be connected
to ground (VSS).
see
USB_VSSPLL G11 GND Section 5.2, USB Analog PLL ground.
ROC

TMS320C5517
4.2.12 Universal Host-Port Interface (UHPI)
Table 4-12. UHPI Signal Descriptions

SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME (5) NO.
For UHPI, this pin is UHPI host interrupt, UHPI_HINT.
IPD
SPI_CLK/ Mux control via the PPMODE bits in the EBSR.
N3 O/Z DVDDIO
UHPI_HINT
BH The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7 (1C50h)
register.
For UHPI, this pin is UHPI access control, UHPI_HCNTL0.
IPD
SPI_CS0/ Mux control via the PPMODE bits in the EBSR.
P4 I/O/Z DVDDIO
UHPI_HCNTL0
register.
For UHPI, this pin is UHPI access control, UHPI_HCNTL1.
IPD
N4 I/O/Z DVDDIO
UHPI_HCNTL1
register.
For UHPI this pin is UHPI read and write, UHPI_HR_NW.
IPD
P5 I/O/Z DVDDIO
UHPI_HR_NW
register.
For UHPI, this pin is the UHPI ready, UHPI_HRDY.
IPD
N5 I/O/Z DVDDIO
UHPI_HRDY
register.
This pin is multiplexed between UHPI, UART, SPI, I2S, and GPIO.
For UHPI, this pin is the UHPI data bus, UHPI_HD[15:0].
UART_TXD/
IPD
P14 I/O/Z DVDDIO
GP[31]/
I2S3_DX
register.
TMS320C5517
Table 4-12. UHPI Signal Descriptions (continued)

SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME (5) NO.
UART_RXD/
IPD
N13 I/O/Z DVDDIO
GP[30]/
I2S3_RX
register.
UART_CTS/
IPD
P13 I/O/Z DVDDIO
GP[29]/
I2S3_FS
register.
UART_RTS/
IPD
N12 I/O/Z DVDDIO
GP[28]/
I2S3_CLK
register.
I2S2_DX/
IPD
P12 I/O/Z DVDDIO
GP[27]/
SPI_TX
register.
I2S2_RX/
IPD
N11 I/O/Z DVDDIO
GP[20]/
SPI_RX
register.
I2S2_FS/
IPD
P11 I/O/Z DVDDIO
GP[19]/
SPI_CS0
register.
I2S2_CLK/
IPD
N10 I/O/Z DVDDIO
GP[18]/
SPI_CLK
register.

TMS320C5517

SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME (5) NO.
This pin is multiplexed between UHPI and GPIO.
IPD
GP[17]/ Mux control via the PPMODE bits in the EBSR.
P10 I/O/Z DVDDIO
UHPI_HD[7]
register.
IPD
N9 I/O/Z DVDDIO
UHPI_HD[6]
register.
IPD
P9 I/O/Z DVDDIO
UHPI_HD[5]
register.
IPD
N8 I/O/Z DVDDIO
UHPI_HD[4]
register.
IPD
N7 I/O/Z DVDDIO
UHPI_HD[3]
register.
IPD
P7 I/O/Z DVDDIO
UHPI_HD[2]
register.
IPD
SPI_TX/ Mux control via the PPMODE bits in the EBSR.
N6 I/O/Z DVDDIO
UHPI_HD[1]
register.

TMS320C5517

SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME (5) NO.
IPD
SPI_RX/ Mux control via the PPMODE bits in the EBSR.
P6 I/O/Z DVDDIO
UHPI_HD[0]
register.
IPD
EM_DQM1/ These two pins are multiplexed between UHPI and SDRAM.
P1 I/O/Z DVDDIO
UHPI_HBE1
BH For UHPI, these two pins are UHPI Byte Enables, UHPI_HBE[1:0].
IPD
EM_DQM0/ The IPD resistor on these pins can be enabled or disabled via the PUDINHIBR6
B5 I/O/Z DVDDIO
UHPI_HBE0 (1C4Fh) register.
BH
IPD
EM_CS1/ These two pins are multiplexed between UHPI and SDRAM.
A4 I/O/Z DVDDIO
UHPI_HDS2
BH For UHPI, these two pins are UHPI data strobe pins, UHPI_HDS[2:1].
IPD
EM_CS0/ The IPD resistor on these pins can be enabled or disabled via the PUDINHIBR7
B3 I/O/Z DVDDIO
UHPI_HDS1 (1C50h) register.
BH
This pin is multiplexed between UHPI and SDRAM.

For UHPI, this pin is Half-word Identification control input pin, UHPI_HHWIL.
IPD
EM_SDCKE/ Mux control via the PPMODE bits in the EBSR.
N2 I/O/Z DVDDIO
UHPI_HHWIL
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7 (1C50h)
register.

For UHPI, this pin is address strobe pin, UHPI_HAS.
IPD
EM_SDRAS/ Mux control via the PPMODE bits in the EBSR.
A6 I/O/Z DVDDIO
UHPI_HAS
BH
register.

For UHPI, this pin is chip select pin, UHPI_HCS.
IPD
EM_SDCAS/ Mux control via the PPMODE bits in the EBSR.
B4 I/O/Z DVDDIO
UHPI_HCS
BH
register.

TMS320C5517
4.2.13 MultiMedia Card (MMC)
Table 4-13. MMC1 and SD Signal Descriptions

SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME (5) NO.
MMC and SD
This pin is multiplexed between MMC1, McSPI, and GPIO.
For MMC and SD, this is the MMC1 data clock output MMC1_CLK.
MMC1_CLK/ IPD
Mux control via the SP1MODE bits in the EBSR.
McSPI_CLK/ M13 O DVDDIO
GP[6] BH The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
For MMC and SD, this is the MMC1 command I/O output MMC1_CMD.
MMC1_CMD/ IPD
McSPI_CS0/ L14 O DVDDIO
(1C17h) register.
MMC1_D3/ IPD
McSPI_CS2/ L13 I/O/Z DVDDIO
GP[11] BH These pins are multiplexed between MMC1, McSPI, and GPIO.
MMC1_D2/ IPD In MMC and SD mode, all these pins are the MMC1 nibble wide bidirectional data
McSPI_CS1/ K14 I/O/Z DVDDIO bus.
GP[10] BH
MMC1_D1/ IPD Mux control via the SP1MODE bits in the EBSR.
McSPI_SOMI/ M12 I/O/Z DVDDIO The IPD resistor on these pins can be enabled or disabled via the PUDINHIBR1
GP[9] BH (1C17h) register.
MMC1_D0/ IPD
McSPI_SIMO/ M14 I/O/Z DVDDIO
GP[8] BH

TMS320C5517
Table 4-14. MMC0 and SD Signal Descriptions

SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME (5) NO.
MMC and SD
This pin is multiplexed between MMC0, I2S0, McBSP, and GPIO.
For MMC and SD, this is the MMC0 data clock output MMC0_CLK.
MMC0_CLK/
IPD
L10 O DVDDIO
GP[0]/
McBSP_CLKX
(1C17h) register.
For MMC and SD, this is the MMC0 command I/O output MMC0_CMD.
MMC0_CMD/
IPD
M11 O DVDDIO
GP[1]/
McBSP_FSX
(1C17h) register.
MMC0_D3/
IPD
GP[5]/
L11 I/O/Z DVDDIO
McBSP_CLKR_
BH
CLKS
MMC0_D2/ IPD These pins are multiplexed between MMC0, I2S0, McBSP and GPIO
GP[4]/ L12 I/O/Z DVDDIO In MMC and SD mode, these pins are the MMC0 nibble wide bidirectional data bus.
McBSP_FSR BH
MMC0_D1/ Mux control via the SP0MODE bits in the EBSR.
IPD
I2S0_RX/ The IPD resistor on these pins can be enabled or disabled via the PUDINHIBR1
M10 I/O/Z DVDDIO
GP[3]/ (1C17h) register.
BH
McBSP_DR
MMC0_D0/
IPD
I2S0_DX/
L9 I/O/Z DVDDIO
GP[2]/
BH
McBSP_DX

TMS320C5517
4.2.14 Successive Approximation (SAR) Analog-to-Digital Converter (ADC)
Table 4-15. 10-Bit SAR ADC Signal Descriptions

SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME NO.
SAR ADC
GPAIN0: General -Purpose Output and Analog Input pin 0. This pin is demuxed
internally into ADC Channels 0, 1, and 2. GPAIN0 can also be used as a general-
purpose open-drain output. This pin is unique among the GPAIN pins in that it is the
GPAIN0 D10 I/O VDDA_ANA only pin that is 3.6 V-tolerant to support measuring a battery voltage. GPAIN0 can
accommodate input voltages from 0 V to 3.6 V; although, the ADC is unable to
accept signals greater than VDDA_ANA without clamping. ADC Channel 1 is capable
of switching in an internal resistor divider that has a divide ratio of approximately 1/8.
GPAIN1: General -Purpose Output and Analog Input pin 1. This pin is connected to
ADC Channel 3. GPAIN1 can be used as a general-purpose output if certain
requirements are met (see the following note). GPAIN1 can accommodate input
voltages from 0 V to VDDA_ANA.
GPAIN1 A11 I/O VDDA_ANA Note: If the ANA_LDO is used to supply power to VDDA_ANA, this pin must not be
used as a general-purpose output (driving high) since the max current capability
(see the ISD parameter in Section 5.3.2, Electrical Characteristics) of the ANA_LDO
can be exceeded. Doing so may result in the on-chip power-on reset (POR)
resetting the chip.
GPAIN2 B11 I/O VDDA_ANA
Note: If the ANA_LDO is used to supply power to VDDA_ANA, this pin must not be
can be exceeded. Doing so may result in the on-chip POR resetting the chip.
GPAIN3 C11 I/O VDDA_ANA
Note: If the ANA_LDO is used to supply power to VDDA_ANA, this pin must not be
can be exceeded. Doing so may result in the on-chip POR resetting the chip.

TMS320C5517
4.2.15 General-Purpose Input and Output (GPIO)
Table 4-16. GPIO Signal Descriptions

SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME (5) NO.
General-Purpose Input/Output
External Flag Output. XF is used for signaling other processors in multiprocessor
configurations or XF can be used as a fast general-purpose output pin.
XF is set high by the BSET XF instruction and XF is set low by the BCLR XF
instruction or by writing to bit 13 of the ST1_55 register. For more information on the
IPU ST1_55 register, see the C55x 3.0 CPU Reference Guide [literature number:
XF M8 O/Z DVDDIO SWPU073].
BH
For the XF pin's states after reset, see Figure 5-9, BootMode Latching.
XF pin can manually configured as Hi-Z state only in boundary-scan mode. When
this pin is in Hi-Z state, the IPU is enabled.
The IPU on this pin is disabled at reset.
For GPIO, it is general-purpose input/output pin 0 (GP[0]).
MMC0_CLK/
IPD
L10 I/O/Z DVDDIO
GP[0]/
McBSP_CLKX
(1C17h) register.
MMC0_CMD/
IPD
M11 I/O/Z DVDDIO
GP[1]/
McBSP_FSX
(1C17h) register.
MMC0_D0/
IPD
L9 I/O/Z DVDDIO
GP[2]/
McBSP_DX
(1C17h) register.
MMC0_D1/
IPD
M10 I/O/Z DVDDIO
GP[3]/
McBSP_DR
(1C17h) register.
TMS320C5517
Table 4-16. GPIO Signal Descriptions (continued)

SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME (5) NO.
This pin is multiplexed between MMC0, McBSP, and GPIO.
MMC0_D2/ IPD
GP[4]/ L12 I/O/Z DVDDIO
McBSP_FSR BH The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
This pin is multiplexed between MMC0, McBSP, and GPIO.
MMC0_D3/
IPD
GP[5]/ Mux control via the SP0MODE bits in the EBSR.
L11 I/O/Z DVDDIO
McBSP_CLKR_
CLKS
(1C17h) register.
MMC1_CLK/ IPD
McSPI_CLK/ M13 I/O/Z DVDDIO
(1C17h) register.
MMC1_CMD/ IPD
(1C17h) register.
MMC1_D0/ IPD
McSPI_SIMO/ M14 I/O/Z DVDDIO
(1C17h) register.
MMC1_D1/ IPD
McSPI_SOMI/ M12 I/O/Z DVDDIO
(1C17h) register.
MMC1_D2/ IPD
McSPI_CS1/ K14 I/O/Z DVDDIO
(1C17h) register.

TMS320C5517

SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME (5) NO.
MMC1_D3/ IPD
(1C17h) register.
This pin is multiplexed between GPIO and UHPI.
IPD
P7 I/O/Z DVDDIO
UHPI_HD[2]
(1C19h) register.
IPD
N7 I/O/Z DVDDIO
UHPI_HD[3]
(1C19h) register.
IPD
N8 I/O/Z DVDDIO
UHPI_HD[4]
(1C19h) register.
IPD
P9 I/O/Z DVDDIO
UHPI_HD[5]
(1C19h) register.
IPD
N9 I/O/Z DVDDIO
UHPI_HD[6]
(1C19h) register.
IPD
P10 I/O/Z DVDDIO
UHPI_HD[7]
(1C19h) register.

TMS320C5517

SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME (5) NO.
I2S2_CLK/
IPD
N10 I/O/Z DVDDIO
GP[18]/
SPI_CLK
(1C19h) register.
This pin is multiplexed between I2S2, UHPI, GPIO and SPI.
I2S2_FS/
IPD
P11 I/O/Z DVDDIO
GP[19]/
SPI_CS0
(1C19h) register.
This pin is multiplexed between I2S2, UHPI, GPIO and SPI.
I2S2_RX/
IPD
N11 I/O/Z DVDDIO
GP[20]/
SPI_RX
(1C19h) register.
This pin is multiplexed between EMIF and GPIO.
IPD
GP[21]/ Mux control via the A15_MODE bit in the EBSR.
N1 I/O/Z DVDDEMIF
EM_A[15]
(1C18h) register.
IPD
E2 I/O/Z DVDDEMIF
EM_A[16]
(1C18h) register.
IPD
F2 I/O/Z DVDDEMIF
EM_A[17]
(1C18h) register.
IPD
G2 I/O/Z DVDDEMIF
EM_A[18]
(1C18h) register.

TMS320C5517

SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME (5) NO.
IPD
G4 I/O/Z DVDDEMIF
EM_A[19]
(1C18h) register.
IPD
J3 I/O/Z DVDDEMIF
EM_A[20]
(1C18h) register.
I2S2_DX/
IPD
P12 I/O/Z DVDDIO
GP[27]/
SPI_TX
(1C19h) register.
UART_RTS/
IPD
N12 I/O/Z DVDDIO
GP[28]/
I2S3_CLK
(1C19h) register.
UART_CTS/
IPD
P13 I/O/Z DVDDIO
GP[29]/
I2S3_FS
(1C19h) register.
UART_RXD/
IPD
N13 I/O/Z DVDDIO
GP[30]/
I2S3_RX
(1C19h) register.
UART_TXD/
IPD
P14 I/O/Z DVDDIO
GP[31]/
I2S3_DX
(1C19h) register.

TMS320C5517
4.2.16 Regulators and Power Management
Table 4-17. Regulators and Power Management Signal Descriptions

SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME NO.
Regulators
DSP_LDO output. When enabled, this output provides a regulated 1.3 V or 1.05 V
output and up to 250 mA of current (see the ISD parameter in Section 5.3.2,
Electrical Characteristics).
DSP_LDOO E10 S The DSP_LDO is intended to supply current to the digital core circuits only (CVDD)
but not to CVDDRTC or external devices. For proper device operation, the external
decoupling capacitor of this pin should be 5µF ~ 10µF. For more detailed
information, see Section 5.7.2.5, Power-Supply Decoupling.
When disabled, this pin is in the high-impedance (Hi-Z) state.
LDO inputs. For proper device operation, LDOI must always be powered. The LDOI
F14,
pins must be connected to the same power supply source with a voltage range of
LDOI F13, S
1.8 V to 3.6 V. These pins supply power to the internal LDOs, the bandgap
B12
reference generator circuits, and serve as the I/O supply for some input pins.
DSP_LDO enable input. This signal is not intended to be dynamically switched.
0 = DSP_LDO is enabled. The internal POR monitors the DSP_LDOO pin voltage
and generates the internal POWERGOOD signal.
–
DSP_LDO_EN D12 I 1 = DSP_LDO is disabled. The internal POR voltage monitoring is also disabled.
LDOI
The internal POWERGOOD signal is forced high and the external reset signal on
the RESET pin (D6) is the only source of the device reset. Note, the device's
internal reset signal is generated as the logical AND of the RESET pin and the
internal POWERGOOD signal.
USB_LDO output. This output provides a regulated 1.3 V output and up to 25 mA of

current (see the ISD parameter in Section 5.3.2, Electrical Characteristics).
For proper device operation, this pin must be connected to a 1 µF ~ 2 µF decoupling
capacitor to VSS. For more detailed information, see Section 5.7.2.5, Power-Supply
Decoupling. This LDO is intended to supply power to the USB_VDD1P3,
USB_VDDA1P3 pins but not to CVDDRTC or external devices.
USB_LDOO F12 S
Note: The reset state of the register that enables and disables the USB_LDO is
dependent on the setting of CLK_SEL pin at reset.
If CLK_SEL is high, the USB_LDO is disabled at reset but can be enabled by
software.
If CLK_SEL is low, the USB LDO is enabled (USB_LDO_EN=1) at reset and cannot
be disabled by software. (See Section 5.7.2.1.1.2.1 LDO Control for details.)
ANA_LDO output. This output provides a regulated 1.3 V output and up to 4 mA of
current (see the ISD parameter in Section 5.3.2, Electrical Characteristics).
ANA_LDOO A12 S For proper device operation, this pin must be connected to an ~ 1.0 µF decoupling
capacitor to VSS. For more detailed information, see Section 5.7.2.5, Power-Supply
Decoupling. This LDO is intended to supply power to the VDDA_ANA pin but not to
VDDA_PLL, CVDDRTC or external devices.
TMS320C5517
Table 4-17. Regulators and Power Management Signal Descriptions (continued)

SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME NO.
Bandgap reference filter signal. For proper device operation, this pin needs to be
bypassed with a 0.1 µF capacitor to analog ground (VSSA_ANA).
BG_CAP provides a settling time of 200 ms that must elapse before executing
BG_CAP B13 A, O bootloader code. The settling time time is used by Timer0.
This external capacitor provides filtering for stable reference voltages and currents
generated by the bandgap circuit. The bandgap produces the references for use by
the SAR and POR circuits.

TMS320C5517
4.2.17 Supply Voltage
Table 4-18. Supply Voltage Signal Descriptions

SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME NO.
SUPPLY VOLTAGES
F6
H8 1.05-V Digital Core supply voltage (75 MHz)
J6 PWR 1.3-V Digital Core supply voltage (175 MHz)
CVDD K10 1.4-V Digital Core supply voltage (200 MHz)
L5
F7
K7
DVDDIO K12 PWR 1.8-V, 2.75-V, or 3.3-V I/O power supply for non-EMIF and non-RTC I/Os
N14 DVDDIO must always be powered for proper operation.
P3
P8
A2
A5
E6
F5 1.8-V, 2.75-V, or 3.3-V EMIF I/O power supply
DVDDEMIF must always be powered for proper operation. GP[26:21] are used for
DVDDEMIF G5 PWR
boot mode configuration.
H5
H7
J5
P2
1.05-V RTC digital core and RTC oscillator power supply.
CVDDRTC C8 PWR Note: The CVDDRTC pin must always be powered by an external power source even
though RTC is not used. None of the on-chip LDOs can power CVDDRTC.
1.8-V, 2.75-V, or 3.3-V I/O power supply for peripheral pins.

DVDDRTC F8 PWR DVDDRTC can be tied to ground (VSS) when RTC_CLKOUT and WAKEUP pins are
not used permanently. In this case, the WAKEUP pin must be configured as output
by software. (See Table 5-1, RTCPMGT Register Bit Descriptions.)
1.3-V Analog PLL power supply for the system clock generator.
VDDA_PLL C10 PWR Section 5.2, if the power supply for this pin is shared with digital logic. See the Filtering
This signal cannot be powered from the ANA_LDOO pin. It must be powered
externally.
3.3 V USB Analog PLL power supply.
USB_VDDPLL G8 S Section 5.2, if the power supply for this pin is shared with digital logic. See the Filtering
When the USB peripheral is not used, the USB_VDDPLL signal should be connected
to ground (VSS).
TMS320C5517
Table 4-18. Supply Voltage Signal Descriptions (continued)

SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME NO.
1.3-V digital core power supply for USB PHY.
USB_VDD1P3 J13 S Section 5.2, Sequencing.
ROC
When the USB peripheral is not used, the USB_VDD1P3 signal should be connected
to ground (VSS).
Analog 1.3 V power supply for USB PHY. [For high-speed sensitive analog circuits]
ROC
Analog 3.3 V power supply for USB PHY.
ROC
see 3.3-V power supply for USB oscillator.

USB_VDDOSC G12 S Section 5.2, When the USB peripheral is not used, USB_VDDOSC should be connected to
ROC ground (VSS).
1.3-V supply for power management and 10-bit SAR ADC
VDDA_ANA A10 PWR
This signal can be powered from the ANA_LDOO pin.

TMS320C5517
4.2.18 Ground
Table 4-19. Ground Signal Descriptions

SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME NO.
A13
A14
D7
D11
E9
E11
E12
E13
E14
VSS F9 GND Ground pins
F10
G6
G7
H6
J7
J8
J9
K8
K9
K11
K13
Ground for RTC oscillator. When using a 32.768-kHz crystal, this pin is a local
ground for the crystal and must not be connected to the board ground (See
VSSRTC C9 GND
Figure 5-13 and Figure 5-16). When not using RTC and the crystal is not populated
on the board, this pin is connected to the board ground.
see
VSSA_PLL D9 GND Section 5.2, Analog PLL ground for the system clock generator.
ROC
see
USB_VSSPLL G11 GND Section 5.2, USB Analog PLL ground.
ROC
see
USB_VSS1P3 H13 GND Section 5.2, Digital core ground for USB PHY.
ROC
see
USB_VSSA1P3 H9 GND Section 5.2, Analog ground for USB PHY [For high speed sensitive analog circuits].
ROC
see
USB_VSSA3P3 H11 GND Section 5.2, Analog ground for USB PHY.
ROC
see
USB_VSSOSC F11 GND Section 5.2, Ground for USB oscillator.
ROC
TMS320C5517
Table 4-19. Ground Signal Descriptions (continued)

SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME NO.
Ground for reference current. This must be connected via a 10-kΩ ±1% resistor to
see USB_R1.
USB_VSSREF G10 GND Section 5.2,
ROC When the USB peripheral is not used, the USB_VSSREF signal should be connected
directly to ground (Vss).
B10 Analog ground pins for power management (POR and Bandgap circuits) and 10-bit
VSSA_ANA GND
B14 SAR ADC

TMS320C5517
4.3 Pin Multiplexing

Extensive pin multiplexing is used to accommodate the largest number of peripheral functions in the
smallest possible package. The external bus selection register (EBSR) controls all the pin multiplexing
functions on the device.
This section discusses how to program the external bus selection register (EBSR) to select the desired
peripheral functions and pin muxing. See the individual subsections for muxing details for a specific
muxed pin. After changing any of the pin mux control registers, it will be necessary to reset the peripherals
that are affected.
4.3.1 UHPI, SPI, UART, I2S2, I2S3, and GP[31:27, 20:12] Pin Multiplexing [EBSR.PPMODE Bits]
The UHPI, SPI, UART, I2S2, I2S3, and GPIO signal muxing is determined by the value of the PPMODE
bit fields in the External Bus Selection Register (EBSR) register. For more details on the actual pin
functions, see Table 4-20.

TMS320C5517
Table 4-20. UHPI, SPI, UART, I2S2, I2S3, and GP[31:27, 20:12] Pin Multiplexing
EBSR PPMODE BITS
MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6
PULLUP and PULLDOWN
PIN NUMBER
CONTROL REGISTER BIT 001
000 (Reset 010 011 100 101 110
Default)
PUDINHIBR7 (0x1C50) Bit 12 N3 UHPI_HINT SPI_CLK Reserved Reserved Reserved Reserved SPI_CLK
PUDINHIBR3 (0x1C19) Bit 0 P6 UHPI_HD[0] SPI_RX Reserved Reserved Reserved Reserved SPI_RX
PUDINHIBR3 (0x1C19) Bit 1 N6 UHPI_HD[1] SPI_TX Reserved Reserved Reserved Reserved SPI_TX
PUDINHIBR3 (0x1C19) Bit 2 P7 UHPI_HD[2] GP[12] Reserved Reserved Reserved Reserved GP[12]
PUDINHIBR3 (0x1C19) Bit 3 N7 UHPI_HD[3] GP[13] Reserved Reserved Reserved Reserved GP[13]
PUDINHIBR3 (0x1C19) Bit 8 N10 UHPI_HD[8] I2S2_CLK GP[18] SPI_CLK I2S2_CLK SPI_CLK I2S2_CLK
PUDINHIBR3 (0x1C19) Bit 9 P11 UHPI_HD[9] I2S2_FS GP[19] SPI_CS0 I2S2_FS SPI_CS0 I2S2_FS
PUDINHIBR3 (0x1C19) Bit 10 N11 UHPI_HD[10] I2S2_RX GP[20] SPI_RX I2S2_RX SPI_RX I2S2_RX
PUDINHIBR3 (0x1C19) Bit 11 P12 UHPI_HD[11] I2S2_DX GP[27] SPI_TX I2S2_DX SPI_TX I2S2_DX
PUDINHIBR3 (0x1C19) Bit 12 N12 UHPI_HD[12] UART_RTS GP[28] I2S3_CLK UART_RTS UART_RTS I2S3_CLK
PUDINHIBR3 (0x1C19) Bit 13 P13 UHPI_HD[13] UART_CTS GP[29] I2S3_FS UART_CTS UART_CTS I2S3_FS
PUDINHIBR3 (0x1C19) Bit 14 N13 UHPI_HD[14] UART_RXD GP[30] I2S3_RX UART_RXD UART_RXD I2S3_RX
PUDINHIBR3 (0x1C19) Bit 15 P14 UHPI_HD[15] UART_TXD GP[31] I2S3_DX UART_TXD UART_TXD I2S3_DX
PUDINHIBR7 (0x1C50) Bit 8 P4 UHPI_HCNTL0 SPI_CS0 Reserved Reserved Reserved Reserved SPI_CS0
PUDINHIBR7 (0x1C50) Bit 9 N4 UHPI_HCNTL1 SPI_CS1 Reserved Reserved Reserved Reserved SPI_CS1
PUDINHIBR7 (0x1C50) Bit 10 P5 UHPI_HR_NW SPI_CS2 Reserved Reserved Reserved Reserved SPI_CS2
PUDINHIBR7 (0x1C50) Bit 11 N5 UHPI_HRDY SPI_CS3 Reserved Reserved Reserved Reserved SPI_CS3
PUDINHIBR6 (0x1C4F) Bit 7 B5 UHPI_HBE0 EM_DQM0 EM_DQM0 EM_DQM0 EM_DQM0 EM_DQM0 EM_D1M0
PUDINHIBR6 (0x1C4F) Bit 8 P1 UHPI_HBE1 EM_DQM1 EM_DQM1 EM_DQM1 EM_DQM1 EM_DQM1 EM_DQM1
PUDINHIBR7 (0x1C50) Bit 3 A6 UHPI_HAS EM_SDRAS EM_SDRAS EM_SDRAS EM_SDRAS EM_SDRAS EM_SDRAS
PUDINHIBR7 (0x1C50) Bit 2 B4 UHPI_HCS EM_SDCAS EM_SDCAS EM_SDCAS EM_SDCAS EM_SDCAS EM_SDCAS
PUDINHIBR7 (0x1C50) Bit 4 B3 UHPI_HDS1 EM_CS0 EM_CS0 EM_CS0 EM_CS0 EM_CS0 EM_CS0
PUDINHIBR7 (0x1C50) Bit 5 A4 UHPI_HDS2 EM_CS1 EM_CS1 EM_CS1 EM_CS1 EM_CS1 EM_CS1
PUDINHIBR7 (0x1C50) Bit 1 N2 UHPI_HHWIL EM_SDCKE EM_SDCKE EM_SDCKE EM_SDCKE EM_SDCKE EM_SDCKE

TMS320C5517
4.3.2 MMC1, McSPI, and GP[11:6] Pin Multiplexing [EBSR.SP1MODE Bits]

The MMC1, McSPI, and GPIO signal muxing is determined by the value of the SP1MODE bit fields in the
External Bus Selection Register (EBSR) register. For more details on the actual pin functions, see
Table 4-21.
Table 4-21. MMC1, McSPI, and GP[11:6] Pin Multiplexing

EBSR SP1MODE BITS
PUDINHIBR1
MODE 0 MODE 1 MODE 2
REGISTER PIN NUMBER
BIT (1) 00
01 10
(Reset Default)
Bit 8 M13 MMC1_CLK McSPI_CLK GP[6]
Bit 9 L14 MMC1_CMD McSPI_CS0 GP[7]
Bit 10 M14 MMC1_D0 McSPI_SIMO GP[8]
Bit 11 M12 MMC1_D1 McSPI_SOMI GP[9]
Bit 12 K14 MMC1_D2 McSPI_CS1 GP[10]
Bit 13 L13 MMC1_D3 McSPI_CS2 GP[11]
(1) The pin names with PUDINHIBR1 (1C17h) register bit field references can have the pulldown register enabled or disabled via this
register. Pin 0 on serial port 1 corresponds to bit 8, pin 1 to bit 9, and so on up to pin 5 which corresponds to bit 13.
4.3.3 MMC0, I2S0, McBSP, and GP[5:0] Pin Multiplexing [EBSR.SP0MODE Bits]
The MMC0, I2S0, McBSP, and GPIO signal muxing is determined by the value of the SP0MODE bit fields
in the External Bus Selection Register (EBSR) register. For more details on the actual pin functions, see
Table 4-22.
Table 4-22. MMC0, I2S0, McBSP, and GP[5:0] Pin Multiplexing

EBSR SP0MODE BITS
PUDINHIBR1
MODE 0 MODE 1 MODE 2 MODE 3
REGISTER PIN NUMBER
BIT (1) 00
01 10 11
(Reset Default)
Bit 0 L10 MMC0_CLK I2S0_CLK GP[0] McBSP_CLKX
Bit 1 M11 MMC0_CMD I2S0_FS GP[1] McBSP_FSX
Bit 2 L9 MMC0_D0 I2S0_DX GP[2] McBSP_DX
Bit 3 M10 MMC0_D1 I2S0_RX GP[3] McBSP_DR
Bit 4 L12 MMC0_D2 GP[4] GP[4] McBSP_FSR
Bit 5 L11 MMC0_D3 GP[5] GP[5] McBSP_CLKR_CLKS (2)
register. Pin 0 on serial port 0 corresponds to bit 0, pin 1 to bit 1, and so on up to pin 5 which corresponds to bit 5.
(2) Bit 15 of the EBSR register determines this port to be McBSP_CLKR or McBSP_CLKS.

TMS320C5517
4.3.4 EMIF EM_A[20:15] and GP[26:21] Pin Multiplexing [EBSR.Axx_MODE bits]

The EMIF Address and GPIO signal muxing is determined by the value of the A20_MODE, A19_MODE,
A18_MODE, A17_MODE, A16_MODE, and A15_MODE bit fields in the External Bus Selection Register
(EBSR) register. For more details on the actual pin functions, see Table 4-23.
Table 4-23. EM_A[20:16] and GP[26:21] Pin Multiplexing

PUDINHIBR2 Axx_MODE BIT
REGISTER PIN NUMBER
BIT (1) 0 1
Bit 0 N1 EM_A[15] GP[21]
Bit 1 E2 EM_A[16] GP[22]
Bit 2 F2 EM_A[17] GP[23]
Bit 3 G2 EM_A[18] GP[24]
Bit 4 G4 EM_A[19] GP[25]
Bit 5 J3 EM_A[20] GP[26]
register.

TMS320C5517
4.4 Connections for Unused Signals

Table 4-24 lists the signals that are reserved or are not connected on this device.
Table 4-24. Reserved and No Connects Signal Descriptions

SIGNAL TYPE (1)
(2) OTHER (3) (4)
DESCRIPTION
NAME NO.
Reserved
–
RSV0 C12 I Reserved. For proper device operation, this pin must be tied directly to VSS.
LDOI
RSV1 J10 PWR Reserved. For proper device operation, this pin must be tied directly to CVDD.
RSV2 J11 PWR Reserved. For proper device operation, this pin must be tied directly to CVDD.
–
RSV3 D14 I Reserved. For proper device operation, this pin must be tied directly to VSS.
LDOI
–
LDOI
–
LDOI
–
RSV16 D13 I Reserved. For proper device operation, this pin must be tied directly to VSS.
LDOI

TMS320C5517
5 Specifications
For the device maximum operating frequency, see Section 7.1.2, Device Nomenclature.
5.1 Absolute Maximum Ratings

Over Operating Case Temperature Range (Unless Otherwise Noted) (1)
Supply voltage ranges: Digital Core (CVDD, CVDDRTC, USB_VDD1P3) (2) –0.5 V to 1.7 V
I/O, 1.8 V, 2.75 V, 3.3 V (DVDDIO, DVDDEMIF, DVDDRTC) 3.3V –0.5 V to 4.2 V
USB supplies USB PHY (USB_VDDOSC, USB_VDDPLL,
USB_VDDA3P3) (2)
LDOI –0.5 V to 4.2 V
Analog, 1.3 V (VDDA_PLL, USB_VDDA1P3, VDDA_ANA) (2) –0.5 V to 1.7 V
Input and Output voltage ranges: VI I/O, All pins with DVDDIO or DVDDEMIF or USB_VDDOSC or –0.5 V to 4.2 V
USB_VDDPLL or USB_VDDA3P3 as supply source
VO I/O, All pins with DVDDIO or DVDDEMIF or USB_VDDOSC or –0.5 V to 4.2 V
USB_VDDPLLor USB_VDDA3P3 as supply source
RTC_XI and RTC_XO –0.5 V to 1.7 V
VI and VO, GPAIN[0] –0.5 V to 4.2 V
VI and VO, GPAIN[3:1] –0.5 V to 1.7 V
VO, BG_CAP –0.5 V to 1.7 V
ANA_LDOO, DSP_LDOO, and USB_LDOO –0.5 V to 1.7 V
USB_VBUS Input 0 V to 5.5 V
Operating case temperature ranges, Tc: Commercial Temperature (default) -10°C to 70°C
Industrial Temperature -40°C to 85°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS.
Copyright © 2012–2014, Texas Instruments Incorporated Specifications 57

TMS320C5517
5.2 Recommended Operating Conditions

MIN NOM MAX UNIT
75 MHz 0.998 1.05 1.15 V
Supply voltage, Digital Core
CVDD
175 MHz 1.24 1.3 1.43 V
Slew rate < 200 µs for full swing
200 MHz 1.33 1.4 1.47 V

CVDDRTC Supply voltage, RTC and RTC OSC 32.768 kHz 0.998 CVDD V
USB_VDD1P3 Supply voltage, Digital USB 1.24 1.3 1.43 V
Core Supplies
USB_VDDA1P3 Supply voltage, 1.3 V Analog USB 1.24 1.3 1.43 V
VDDA_ANA Supply voltage, 1.3 V SAR and Pwr Mgmt 1.24 1.3 1.43 V
VDDA_PLL Supply voltage, System PLL 1.24 1.3 1.43 V
USB_VDDPLL Supply voltage, 3.3 V USB PLL 2.97 3.3 3.63 V
Supply voltage, I/O, 3.3 V 2.97 3.3 3.63 V
DVDDIO
DVDDEMIF Supply voltage, I/O, 2.75 V 2.48 2.75 3.02 V
DVDDRTC
Supply voltage, I/O, 1.8 V 1.65 1.8 1.98 V
I/O Supplies
USB_VDDOSC Supply voltage, I/O, 3.3 V USB OSC 2.97 3.3 3.63 V
USB_VDDA3P3 Supply voltage, I/O, 3.3 V Analog USB PHY 2.97 3.3 3.63 V
LDOI Supply voltage, Analog Pwr Mgmt and LDO Inputs 1.8 3.6 V
VSS Supply ground, Digital I/O
VSSRTC Supply ground, RTC
USB_VSSOSC Supply ground, USB OSC
USB_VSSPLL Supply ground, USB PLL
USB_VSSA3P3 Supply ground, 3.3 V Analog USB PHY
GND 0 0 0 V
USB_VSSA1P3 Supply ground, USB 1.3 V Analog USB PHY
USB_VSSREF Supply ground, USB Reference Current
VSSA_PLL Supply ground, System PLL
USB_VSS1P3 Supply ground, 1.3 V Digital USB PHY
VSSA_ANA Supply ground, SAR and Pwr Mgmt
(1) High-level input voltage, 3.3, 2.75, 1.8 V I/O (except
VIH 0.7 * DVDD DVDD + 0.3 V
GPAIN[3:0] pins) (2)
(1) Low-level input voltage, 3.3, 2.75, 1.8 V I/O (except
VIL -0.3 0.3 * DVDD V
GPAIN[3:0] pins) (2)
Input voltage, GPAIN0 pin (3) -0.3 3.6 V
VIN
Input voltage, GPAIN[3:1] pins -0.3 VDDA_ANA + 0.3 V
Commercial
-10 70 °C
Tc Operating case temperature (default)
Industrial -40 85 °C
1.05 V 0 75 MHz
FSYSCLK DSP Operating Frequency (SYSCLK)
1.3 V 0 175 MHz
1.4 V 0 200 MHz
(1) DVDD refers to the pin I/O supply voltage. To determine the I/O supply voltage for each pin, see Section 4.2, Signal Descriptions.
(2) The I2C pin SDA and SCL do not feature fail-safe I/O buffers. These pin could potentially draw current when the DVDDIO is powered
down. Due to the fact that different voltage devices can be connected to I2C bus and the I2C inputs are LVCMOS, the level of logic 0
(low) and logic 1 (high) are not fixed and depend on DVDDIO.
(3) The GNDON bit in the SARPINCTRL register should be set to "1" before SAR channels 0, 1, or 2 are enabled via the CHSEL bit in the
SARCTRL register, when VIN greater than VDDA_ANA.
58 Specifications Copyright © 2012–2014, Texas Instruments Incorporated

TMS320C5517
5.3 Electrical Characteristics
5.3.1 Power Consumption
NOTE
Power consumption on this device depends on several operating parameters such as operating
voltage, operating frequency, and temperature. Power consumption also varies by end applications
that determine the overall processor, CPU, and peripheral activity. For more specific power
consumption details, see Estimating Power Consumption on the TMS320C5517 Digital Signal
Processor [literature number SPRABV3]. This document includes a spreadsheet for estimating
power based on parameters that closely resemble the end application to generate a realistic
estimate of power consumption on this device based on use-case and operating conditions.
5.3.2 Electrical Characteristics

Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted)
(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Full speed: USB_DN and
2.8 USB_VDDA3P3 V
USB_DP (2)
High speed: USB_DN and
360 440 mV
USB_DP (2)
VOH High-level output voltage, 3.3,
2.75, 1.8 V I/O (except IO = IOH 0.8 * DVDD V
GPAIN[3:0] pins)
High-level output voltage,
IO = IOH 0.8 * VDDA_ANA V
GPAIN[3:1] pins
Full speed: USB_DN and
0.0 0.3 V
USB_DP (2)
High speed: USB_DN and
–10 10 mV
USB_DP (2)
Low-level output voltage, 3.3,
VOL 2.75, 1.8V I/O (except I2C and IO = IOL 0.2 * DVDD V
GPAIN[3:0] pins)
Low-level output voltage, I2C
VDD > 2 V, IOL = 3 mA 0 0.4 V
pins (3)
Low-level output voltage,
IO = IOL 0.2 * VDDA_ANA V
GPAIN[3:0] pins
DVDD = 3.3 V 162 mV
VHYS Input hysteresis (4)
DVDD = 1.8 V 122 mV
USB_LDOO voltage 1.24 1.3 1.43 V
ANA_LDOO voltage 1.24 1.3 1.43 V
VLDO
DSP_LDO_V bit in the LDOCNTL register = 1 1.24 1.3 1.43 V
DSP_LDOO voltage
DSP_LDO_V bit in the LDOCNTL register = 0 0.998 1.05 1.15 V
DSP_LDO shutdown current (5) LDOI = VMIN 250 mA
ISD ANA_LDO shutdown current (5) LDOI = VMIN 4 mA
USB_LDO shutdown current (5) LDOI = VMIN 25 mA
Input only pin, internal pulldown or pullup disabled –5 +5 µA
Input current [DC] (except
(6) (7) (8) –59 to
IILPU WAKEUP, I2C, and GPAIN[3:0] DVDD = 3.3 V with internal pullup enabled µA
–161
pins)
(8)
DVDD = 1.8 V with internal pullup enabled –14 to –44 µA
(1) For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table.
(2) The USB I/Os adhere to the Universal Bus Specification Revision 2.0 (USB2.0 spec).
(3) VDD is the voltage to which the I2C bus pullup resistors are connected.
(4) Applies to all input pins except WAKEUP, I2C pins, GPAIN[3:0], RTC_XI, and USB_MXI.
(5) ISD is the amount of current the LDO is ensured to deliver before shutting down to protect itself.
(6) II applies to input-only pins and bidirectional pins. For input-only pins, II indicates the input leakage current. For bidirectional pins, II
indicates the input leakage current and off-state (Hi-Z) output leakage current.
(7) When CVDD power is "ON", the pin bus-holders are disabled. For more detailed information, see Section 5.7.2.3, Digital I/O Behavior
When Core Power (CVDD) is Down.
(8) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
TMS320C5517
Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted)
(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input only pin, internal pulldown or pullup disabled –5 +5 µA
Input current [DC] (except
IIHPD (6) (7) WAKEUP, I2C, and GPAIN[3:0] DVDD = 3.3 V with internal pulldown enabled (8) 52 to 158 µA
pins)
DVDD = 1.8 V with internal pulldown enabled (8) 11 to 35 µA
IIH/ VI = VSS to DVDD with internal pullups and
Input current [DC], ALL pins –5 +5 µA
IIL (7) pulldowns disabled.
All Pins (except USB, EMIF, CLKOUT, and
–4 mA
GPAIN[3:0] pins)
DVDD = 3.3 V –6 mA
EMIF pins
DVDD = 1.8 V –5 mA
DVDD = 3.3 V –6 mA
CLKOUT pin
IOH (7) High-level output current [DC] DVDD = 1.8 V –4 mA
DVDD = VDDA_ANA =
GPAIN[3:1] pins 1.3 V, –4 mA
External Regulator (9)
(GPAIN0 is open-drain DV = V
DDA_ANA =
and cannot drive high) 1.3DD
V, –100 µA
Internal Regulator (9)
All Pins (except USB, EMIF, CLKOUT, and
+4 mA
GPAIN[3:0] pins)
DVDD = 3.3 V +6 mA
EMIF pins
DVDD = 1.8 V +5 mA
DVDD = 3.3 V +6 mA
IOL (7) Low-level output current [DC] CLKOUT pin
DVDD = 1.8 V +4 mA
DVDD = VDDA_ANA =
+4 mA
1.3 V, external regulator
GPAIN[3:0] DVDD = VDDA_ANA =
1.3 V, internal +4 mA
regulator (9)
(10)
All Pins (except USB and GPAIN[3:0]) –10 +10 µA
IOZ I/O Off-state output current
GPAIN[3:0] pins –10 +10 µA
Supply voltage, I/O, 3.3 V 2.2 mA
Bus Holder pull low current when
IOLBH (11) Supply voltage, I/O, 2.75 V 1.6 mA
CVDD is powered "OFF"
Supply voltage, I/O, 1.8 V 0.72 mA
Supply voltage, I/O, 3.3 V –1.3 mA
Bus Holder pull high current
IOHBH (11) Supply voltage, I/O, 2.75 V –0.97 mA
when CVDD is powered "OFF"
Supply voltage, I/O, 1.8 V –0.46 mA
VDDA_PLL = 1.3 V
Room Temp, Phase detector = 12 MHz, VCO = 0.93

125 MHz
VDDA_PLL = 1.3 V
Analog PLL (VDDA_PLL) supply
I Room Temp, Phase detector = 12 MHz, VCO = 1.23 mA
current
175 MHz
VDDA_PLL = 1.3 V
Room Temp, Phase detector = 12 MHz, VCO = 1.54

200 MHz
SAR Analog (VDDA_ANA) supply VDDA_ANA = 1.3 V, SAR clock = 2 MHz, Temp
1 mA
current (70 °C)
CI Input capacitance 4 pF
Co Output capacitance 4 pF
(9) When the ANA_LDO supplies VDDA_ANA, it is not recommended to use the GPAIN[3:1] signals for general-purpose outputs (driving
high). The ISD parameter of the ANA_LDO is too low to drive any realistic load on the GPAIN[3:1] pins while also supplying the PLL
through VDDA_PLL and the SAR through VDDA_ANA.
(10) IOZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current.
(11) This parameter specifies the maximum strength of the Bus Holder and is needed to calculate the minimum strength of external pullups
and pulldowns.

TMS320C5517
5.4 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range (default) –65 150 ºC
(2)
Electrostatic Discharge Human Body Model (HBM) 0 >1000 V
(ESD) Stress Voltage (1)
Charged Device Model (CDM) (3) 0 >250 V
(1) ESD to measure device sensitivity and immunity to damage caused by electrostatic discharges into the device.
(2) Level listed is the passing level per ANSI/ESDA/JEDEC JS-001-2010. JEDEC document JEP155 states that 500 V HBM allows safe
manufacturing with a standard ESD control process, and manufacturing with less than 500 V HBM is possible if the necessary
precautions are taken. Pins listed as 1000 V may actually have higher performance.
(3) Level listed is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250 V CDM allows safe
manufacturing with a standard ESD control process. Pins listed as 250 V may actually have higher performance.
Section 5.5 shows the thermal resistance characteristics for the PBGA–ZCH mechanical package.
5.5 Thermal Characteristics

over operating free-air temperature range (unless otherwise noted)
NO. °C/W (1) AIR FLOW
(m/s) (2)
1 RTJC Junction-to-case 1S0P 6.74 N/A
2 1S0P 14.5 N/A
RTJB Junction-to-board
2S2P 13.8
3 1S0P 57.0 0.00
RTJA Junction-to-free air
2S2P 33.4
4 0.50
5 1.00
RTJMA Junction-to-moving air
6 2.00
7 3.00
8 0.09 0.00
9 0.50
10 PsiJT Junction-to-package top 1.00
11 2.00
12 3.00
13 13.7 0.00
14 0.50
15 PsiJB Junction-to-board 1.00
16 2.00
17 3.00
(1) These measurements were conducted in a JEDEC defined 2S2P system and will change based on environment as well as application.
For more information, see these EIA/JEDEC standards – EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment
Conditions - Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount
Packages.
(2) m/s = meters per second
5.6 Power-On Hours

Over Operating Case Temperature Range (Unless Otherwise Noted)
Device Operating Life DSP Operating Frequency Commercial -10 to 70°C 100,000
Power-On Hours (POH) (1) (SYSCLK): ≤200 MHz POH (2)
Industrial -40 to 85°C
(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI’s standard terms
and conditions for TI semiconductor products.
(2) POH = 100,000 when the Maximum Core Supply Voltages are limited to 105% of the Nominal Core Supply Voltages (For details on the
Core Supplies, see Section 5.2, Recommended Operating Conditions).

TMS320C5517
5.7 Timing and Switching Characteristics
5.7.1 Parameter Information
Tester Pin Electronics Data Sheet Timing Reference Point
42 Ω 3.5 nH Output
Transmission Line Under
Test
Z0 = 50 Ω
(see Note) Device Pin
4.0 pF 1.85 pF (see Note)
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be
taken into account. A transmission line with a delay of 2 ns can be used to produce the desired transmission line effect. The transmission line is
intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 5-1. 3.3-V Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals. This
load capacitance value does not indicate the maximum load the device is capable of driving.
5.7.1.1 1.8-V, 2.75-V, and 3.3-V Signal Transition Levels

All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL
MAX and VOH MIN for output clocks.
Vref = VIH MIN (or VOH MIN)
Vref = VIL MAX (or VOL MAX)
Figure 5-2. Rise and Fall Transition Time Voltage Reference Levels
5.7.1.2 3.3-V Signal Transition Rates

All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns).
5.7.1.3 Timing Parameters and Board Routing Analysis

The timing parameter values specified in this data manual do not include delays by board routing. As a
good board design practice, such delays must always be taken into account. Timing values may be
adjusted by increasing and decreasing such delays. TI recommends utilizing the available I/O buffer
information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS
models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing
Analysis application report [literature number SPRA839]. If needed, external logic hardware such as
buffers may be used to compensate any timing differences.

TMS320C5517
5.7.2 Power Supplies
5.7.2.1 Power Considerations

The device provides several means of managing power consumption.
To minimize power consumption, the device divides its circuits into nine main isolated supply domains:
• LDOI (LDOs and Bandgap Power Supply)
• Analog POR, SAR, and PLL (VDDA_ANA and VDDA_PLL)
• RTC Core (CVDDRTC) — Note: CVDDRTC must always be powered by an external power source. None
of the on-chip LDOs can be used to power CVDDRTC.
• Digital Core (CVDD)
• USB Core (USB_VDD1P3 and USB_VDDA1P3)
• USB PHY and USB PLL (USB_VDDOSC, USB_VDDA3P3, and USB_VDDPLL)
• EMIF I/O (DVDDEMIF)
• RTC I/O (DVDDRTC)
• Rest of the I/O (DVDDIO)
5.7.2.1.1 LDO Configuration

The device includes three Low-Dropout Regulators (LDOs) which can be used to regulate the power
supplies of the SAR ADC and Power Management (ANA_LDO), Digital Core (DSP_LDO), and USB Core
(USB_LDO).
These LDOs are controlled by a combination of pin configuration and register settings. For more detailed
information see the following sections.
5.7.2.1.1.1 LDO Inputs

The LDOI pins (B12, F13, F14) provide power to the internal Analog LDO, DSP LDO, USB LDO, the
bandgap reference generator, and some I/O input pins, and can range from 1.8 V to 3.6 V. The bandgap
provides accurate voltage and current references to the POR, LDOs, PLL, and SAR; therefore, for proper
device operation, power must always be applied to the LDOI pins even if the LDO outputs are not used.
5.7.2.1.1.2 LDO Outputs

The ANA_LDOO pin (A12) is the output of the internal ANA_LDO and can provide regulated 1.3 V power
of up to 4 mA. The ANA_LDOO pin is intended to be connected, on the board, to the VDDA_ANA pin to
provide a regulated 1.3 V to the 10-bit SAR ADC and Power Management Circuits. VDDA_ANA may be
powered by this LDO output, which is recommended, to take advantage of the device's power
management techniques, or by an external power supply. The ANA_LDO cannot be disabled individually
(see Section 5.7.2.1.1.2.1, LDO Control).
The DSP_LDOO pin (E10) is the output of the internal DSP_LDO and provides software-selectable
regulated 1.3 V or regulated 1.05 V power of up to 250 mA. The DSP_LDOO pin is intended to be
connected, on the board, to the CVDD pins. In this configuration, the DSP_LDO_EN pin should be tied to
the board VSS, thus enabling the DSP_LDO.
Optionally, the CVDD pins may be powered by an external power supply. In this configuration the
DSP_LDO_EN pin should be tied (high) to LDOI, disabling DSP_LDO.
The DSP_LDO_EN also affects how reset is generated to the chip (for more details, see the
DSP_LDO_EN pin description in Table 4-17, Regulators and Power Management Signal Descriptions).
When the DSP_LDO is disabled, its output pin is in a high-impedance state.
The LDOs cannot supply power to CVDDRTC, which requires an external power source because CVDDRTC
must always be on for proper operation.

TMS320C5517
NOTE
DSP_LDO can only provide a regulated 1.05 V or 1.3 V. When the DSP Core (CVDD)
requires 1.4 V, an external supply is required to supply 1.4 V to the DSP Core (CVDD) and
the DSP_LDO_EN pin should be tied to LDOI.
The USB_LDOO pin (F12) is the output of the internal USB_LDO and provides regulated 1.3 V, software-
switchable (on and off) power of up to 25 mA. The USB_LDOO pin is intended to be connected, on the
board, to the USB_VDD1P3 and USB_VDDA1P3 pins to provide power to portions of the USB. Optionally, the
USB_VDD1P3 and USB_VDDA1P3 may be powered by an external power supply and the USB_LDO can be
left disabled. When the USB_LDO is disabled, its output pin is in a high-impedance state.
5.7.2.1.1.2.1 LDO Control

All three LDOs can be simultaneously disabled via software by writing to either the BG_PD bit or the
LDO_PD bit in the RTCPMGT register (see Figure 5-3). When the LDOs are disabled via this mechanism,
the only way to re-enable them is by cycling power to the CVDDRTC pin.
ANA_LDO: The ANA_LDO is only disabled by the BG_PD and the LDO_PD mechanism described above.
Otherwise, it is always enabled.
DSP_LDO: The DSP_LDO can be statically disabled by the DSP_LDO_EN pin as described in
Section 5.7.2.1.1.2, LDO Outputs. The DSP_LDO can also be dynamically enabled and disabled via the
BG_PD and the LDO_PD mechanism described above. The DSP_LDO can change its output voltage
dynamically by software via the DSP_LDO_V bit in the LDOCNTL register (see Figure 5-4). The
DSP_LDO output voltage is set to 1.3 V at reset.
USB_LDO: The reset state of the USB_LDO is dependent on the setting of CLK_SEL pin. If CLK_SEL is
high, the USB_LDO is disabled but can be independently and dynamically enabled or disabled by
software via the USB_LDO_EN bit in the LDOCNTL register (see Figure 5-4). If CLK_SEL is low, the USB
LDO is enabled at reset and can never be disabled. This is to ensure the USB oscillator has power when
it is the source of the system clock.
Table 5-3 shows the ON and OFF control of each LDO and its register control bit configurations.
Figure 5-3. RTC Power Management Register (RTCPMGT) [1930h]

15 14 13 12 11 10 9 8
Reserved
R-0
7 6 5 4 3 2 1 0
Reserved WU_DOUT WU_DIR BG_PD LDO_PD RTCCLKOUTE
N
R/W-1 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-1. RTCPMGT Register Bit Descriptions

Bit Name Description
15:5 Reserved Reserved. Read-only, writes have no effect.
Wakeup output, active low, open-drain.
4 WU_DOUT 0 = WAKEUP pin driven low.
1 = WAKEUP pin is in high-impedance (Hi-Z).
Wakeup pin direction control.
0 = WAKEUP pin configured as a input.
1 = WAKEUP pin configured as a output.
3 WU_DIR Note: When the WAKEUP pin is configured as an input, it is active high. When the WAKEUP pin is
configured as an output, is an open-drain that is active low and should be externally pulled-up via a
10-kΩ resistor to DVDDRTC. WU_DIR must be configured as an input to allow the WAKEUP pin to
wake the device up from idle modes.

TMS320C5517
Table 5-1. RTCPMGT Register Bit Descriptions (continued)

Bandgap, on-chip LDOs, and the analog POR power down bit.
This bit shuts down the on-chip LDOs (ANA_LDO, DSP_LDO, and USB_LDO), the Analog POR,
and Bandgap reference. BG_PD and LDO_PD are only intended to be used when the internal
LDOs supply power to the chip. If the internal LDOs are bypassed and not used then the BG_PD
and LDO_PD power-down mechanisms should not be used.
2 BG_PD
After this bit is asserted, the on-chip LDOs, Analog POR, and the Bandgap reference can be re-
enabled by the WAKEUP pin (high) or the RTC alarm interrupt. The Bandgap circuit will take about
100 msec to charge the external 0.1 uF capacitor via the internal 326-kΩ resistor.
0 = On-chip LDOs, Analog POR, and Bandgap reference are enabled.
1 = On-chip LDOs, Analog POR, and Bandgap reference are disabled (shutdown).
On-chip LDOs and Analog POR power down bit.
This bit shuts down the on-chip LDOs (ANA_LDO, DSP_LDO, and USB_LDO) and the Analog
POR. BG_PD and LDO_PD are only intended to be used when the internal LDOs supply power to
the chip. If the internal LDOs are bypassed and not used then the BG_PD and LDO_PD power-
down mechanisms should not be used.
1 LDO_PD
After this bit is asserted, the on-chip LDOs and Analog POR can be re-enabled by the WAKEUP
pin (high) or the RTC alarm interrupt. This bit keeps the Bandgap reference turned on to allow a
faster wake-up time with the expense power consumption of the Bandgap reference.
0 = On-chip LDOs and Analog POR are enabled.
1 = On-chip LDOs and Analog POR are disabled (shutdown).
Clockout output enable bit.
0 RTCCLKOUTEN 0 = Clock output disabled.
1 = Clock output enabled.
Figure 5-4. LDO Control Register (LDOCNTL) [7004h]

15 14 13 12 11 10 9 8
Reserved
R-0
7 6 5 4 3 2 1 0
Reserved DSP_LDO_V USB_LDO_EN
R-0 R/W-0 R/W-CLK_SEL
Table 5-2. LDOCNTL Register Bit Descriptions

15:2 Reserved Reserved. Read-only, writes have no effect.
DSP_LDO voltage select bit.
1 DSP_LDO_V 0 = DSP_LDOO is regulated to 1.3 V.
1 = DSP_LDOO is regulated to 1.05 V.
USB_LDO enable bit.

The reset state of this bit is dependent on the setting of CLK_SEL pin at reset.
If CLK_SEL is high, the USB_LDO is disabled (USB_LEO_EN = 0).
0 USB_LDO_EN If CLK_SEL is low, the USB LDO is enabled (USB_LDO_EN=1).

0 = USB_LDO output is disabled. USB_LDOO pin is placed in high-impedance (Hi-Z) state.
1 = USB_LDO output is enabled. USB_LDOO is regulated to 1.3 V.
Note: When CLK_SEL = 0, this bit will not be able to be set to 0 and the USB_LDO will stay
enabled.

TMS320C5517
Table 5-3. LDO Controls Matrix

RTCPMGT Register LDOCNTL Register
(0x1930) (0x7004) DSP_LDO_EN CLK_SEL
ANA_LDO DSP_LDO USB_LDO
(Pin D12) (Pin C7)
BG_PD Bit LDO_PD Bit USB_LDO_EN Bit
1 Don't Care Don't Care Don't Care 0 OFF OFF ON
Don't Care 1 Don't Care Don't Care 0 OFF OFF ON
0 0 Don't Care Low 0 ON ON ON
0 0 Don't Care High 0 ON OFF ON
1 Don't Care Don't Care Don't Care 1 OFF OFF OFF
Don't Care 1 Don't Care Don't Care 1 OFF OFF OFF
0 0 0 Low 1 ON ON OFF
0 0 0 High 1 ON OFF OFF
0 0 1 Low 1 ON ON ON
0 0 1 High 1 ON OFF ON

TMS320C5517
5.7.2.2 Power-Supply Sequencing

The device includes four core voltage-level supplies (CVDD, CVDDRTC, USB_VDD1P3, USB_VDDA1P3), and
several I/O supplies including—DVDDIO, DVDDEMIF, DVDDRTC, USB_VDDOSC, and USB_VDDA3P3.
Some TI power-supply devices include features that facilitate power sequencing—for example, Auto-Track
and Slow-Start and Enable features. For more information regarding TI's power management products
and suggested devices to power TI DSPs, visit www.ti.com/processorpower.
The device does not require a specific power-up sequence. However, if the DSP_LDO is disabled
(DSP_LDO_EN = high) and an external regulator supplies power to the CPU Core (CVDD), the external
reset signal (RESET) must be held asserted until all of the supply voltages reach their valid operating
ranges.
Note: the external reset signal on the RESET pin must be held low until all of the power supplies reach
their operating voltage conditions.
The I/O design allows either the core supplies (CVDD, CVDDRTC, USB_VDD1P3, USB_VDDA1P3) or the I/O
supplies (DVDDIO, DVDDEMIF, DVDDRTC, USB_VDDOSC, and USB_VDDA3P3) to be powered up for an indefinite
period of time while the other supply is not powered if the following constraints are met:
1. All maximum ratings and recommended operating conditions are satisfied.
2. All warnings about exposure to maximum rated and recommended conditions, particularly junction
temperature are satisfied. These apply to power transitions as well as normal operation.
3. Bus contention while core supplies are powered must be limited to 100 hours over the projected
lifetime of the device.
4. Bus contention while core supplies are powered down does not violate the absolute maximum ratings.
If the USB subsystem is used, the subsystem must be powered up in the following sequence:
1. USB_VDDA1P3 and USB_VDD1P3
2. USB_VDDA3P3
3. USB_VBUS
If the USB subsystem is not used, the following can be powered off:
• USB Core
– USB_VDD1P3
– USB_VDDA1P3
• USB PHY and I/O Level Supplies
– USB_VDDOSC
– USB_VDDA3P3
– USB_VDDPLL
A supply bus is powered up when the voltage is within the recommended operating range. The supply bus
is powered down when the voltage is below that range, either stable or while in transition.

TMS320C5517
5.7.2.3 Digital I/O Behavior When Core Power (CVDD) is Down

With some exceptions (listed below), all digital I/O pins on the device have special features to allow
powering down of the Digital Core Domain (CVDD) without causing I/O contentions or floating inputs at the
pins (see Figure 5-5). The device asserts the internal signal called HHV high when power has been
removed from the Digital Core Domain (CVDD). Asserting the internal HHV signal causes the following
conditions to occur in any order:
• All output pin strong drivers to go to the high-impedance (Hi-Z) state
• Weak bus holders to be enabled to hold the pin at a valid high or low
• The internal pullups or pulldowns (IPUs and IPDs) on the I/O pins will be disabled
The exception pins that do not have this special feature are:
• Pins driven by the CVDDRTC Power Domain [This power domain is "Always On"; therefore, the pins
driven by CVDDRTC do not need these special features]:
– RTC_XI, RTC_XO, RTC_CLKOUT, and WAKEUP
• USB Pins:
– USB_DP, USB_DM, USB_R1, USB_VBUS, USB_MXI, and USB_MXO
• Pins for the Analog Block:
– GPAIN[3:0], DSP_LDO_EN, and BG_CAP
DVDD
PAD
hhvgz
GZ HHV
OR
HHV
PI hhvpi
OR
HHV
Figure 5-5. Bus Holder I/O Circuit
NOTE
Figure 5-5 shows both a pullup and pulldown but pins only have one, not both.
PI = Pullup and Pulldown Inhibit
GZ = Output Enable (active low)
HHV = Described in Section 5.7.2.3

TMS320C5517
5.7.2.4 Power-Supply Design Considerations

Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize
inductance and resistance in the power delivery path. Additionally, when designing for high-performance
applications utilizing the device, the PC board should include separate power planes for core, I/O,
VDDA_ANA and VDDA_PLL (which can share the same PCB power plane), and ground; all bypassed with
high–quality low–ESL and ESR capacitors.
5.7.2.5 Power-Supply Decoupling

In order to properly decouple the supply planes from system noise, place capacitors (caps) as close as
possible to the device. These caps need to be no more than 1.25 cm maximum distance from the device
power pins to be effective. Physically smaller caps, such as 0402, are better but need to be evaluated
from a yield and manufacturing point-of-view. Parasitic inductance limits the effectiveness of the
decoupling capacitors, therefore physically smaller capacitors should be used while maintaining the largest
available capacitance value.
Larger caps for each supply can be placed further away for bulk decoupling. Large bulk caps (on the order
of 10 µF) should be furthest away, but still as close as possible. Large caps for each supply should be
placed outside of the BGA footprint.
As with the selection of any component, verification of capacitor availability over the product's production
lifetime should be considered.
The recommended decoupling capacitance for the DSP core supplies should be 1 µF in parallel with 0.01-
µF capacitor per supply pin.
5.7.2.6 LDO Input Decoupling

The LDO inputs should follow the same decoupling guidelines as other power-supply pins above.
5.7.2.7 LDO Output Decoupling

The LDO circuits implement a voltage feedback control system which has been designed to optimize gain
and stability tradeoffs. As such, there are design assumptions for the amount of capacitance on the LDO
outputs. For proper device operation, the following external decoupling capacitors should be used when
the on-chip LDOs are enabled:
• ANA_LDOO– 1µF
• DSP_LDOO – 5µF ~ 10µF
• USB_LDOO – 1µF ~ 2µF

TMS320C5517
5.7.3 Reset
The device has two main types of reset: hardware reset and software reset.
Hardware reset is responsible for initializing all key states of the device. The hardware reset occurs
whenever the RESET pin is asserted or when the internal power-on-reset (POR) circuit deasserts an
internal signal called POWERGOOD. The device's internal POR is a voltage comparator that monitors the
DSP_LDOO pin voltage and generates the internal POWERGOOD signal when the DSP_LDO is enabled
externally by the DSP_LDO_EN pin. POWERGOOD is asserted when the DSP_LDOO voltage is above a
minimum threshold voltage provided by the bandgap. When the DSP_LDO is disabled (DSP_LDO_EN is
high), the internal voltage comparator becomes inactive, and the POWERGOOD signal logic level is
immediately set high. The RESET pin and the POWERGOOD signal are internally combined with a logical
AND gate to produce an (active low) hardware reset (see Figure 5-6, Power-On Reset Timing
Requirements and Figure 5-7, Reset Timing Requirements).
There are two types of software reset: the CPU's software reset instruction and the software control of the
peripheral reset signals. For more information on the CPU's software reset instruction, see the C55x CPU
3.0 CPU Reference Guide [literature number: SWPU073]. In all the device documentation, all references
to "reset" refer to hardware reset. Any references to software reset will explicitly state software reset.
The device RTC has one additional type of reset, a power-on-reset (POR) for the registers in the RTC
core. This POR monitors the voltage of CVDDRTC and resets the RTC registers when power is first applied
to the RTC core.
5.7.3.1 Power-On Reset (POR) Circuits

The device includes two power-on reset (POR) circuits, one for the RTC (RTC POR) and another for the
rest of the chip (MAIN POR).
5.7.3.1.1 RTC Power-On Reset (POR)

The RTC POR ensures that the flip-flops in the CVDDRTC power domain have an initial state upon
powerup. In particular, the RTCNOPWR register is reset by this POR and is used to indicate that the RTC
time registers need to be initialized with the current time and date when power is first applied.
5.7.3.1.2 Main Power-On Reset (POR)

The device includes an analog power-on reset (POR) circuit that keeps the DSP in reset until specific
voltages have reached predetermined levels. When the DSP_LDO is enabled externally by the
DSP_LDO_EN pin, the output of the POR circuit, POWERGOOD, is held low until the following conditions
are satisfied:
• LDOI is powered and the bandgap is active for at least approximately 8 ms
• VDD_ANA is powered for at least approximately 4 ms
• DSP_LDOO is above a threshold of approximately 950 mV (see the following Note:)
Note: The POR comparator has hysteresis, so the threshold voltage becomes approximately 850 mV after
POWERGOOD signal is set high.
Once these conditions are met, the internal POWERGOOD signal is set high. The POWERGOOD signal
is internally combined with the RESET pin signal, via an AND-gate, to produce the DSP subsystem's
global reset. This global reset is the hardware reset for the whole chip, except the RTC. When the global
reset is deasserted (high), the boot sequence starts. For more detailed information on the boot sequence,
see Section 6.4.1, Boot Sequence.
When the DSP_LDO is disabled (DSP_LDO_EN pin = 1), the voltage monitoring on the DSP_LDOO pin is
de-activated and the POWERGOOD signal is immediately set high. The RESET pin will be the sole
source of hardware reset.

TMS320C5517
5.7.3.1.3 Reset Pin (RESET)

The device can receive an external reset signal on the RESET pin. As specified above in
Section 5.7.3.1.2, Main Power-On Reset, the RESET pin is combined with the internal POWERGOOD
signal, that is generated by the MAIN POR, via an AND-gate. The output of the AND gate provides the
hardware reset to the chip. The RESET pin may be tied high and the MAIN POR can provide the
hardware reset in case DSP_LDO is enabled (DSP_LDO_EN = 0), but an external hardware reset must
be provided via the RESET pin when the DSP_LDO is disabled (DSP_LDO_EN = 1).
Once the hardware reset is applied, the system clock generator is enabled and the DSP starts the boot
sequence. For more information on the boot sequence, see Section 6.4.1, Boot Sequence.
5.7.3.2 Pin Behavior at Reset

All pins are in Hi-Z state when RESET is applied, and pins are held in Hi-Z state for the first two clock
cycles after RESET is de-asserted (set to high).
During normal operation, pins are controlled by the respective peripheral selected in the External Bus
Selection Register (EBSR) register. During power-on reset and reset, the behavior of the output pins
changes and is categorized as follows:
• Z, High Group: EM_CS2, EM_CS3, EM_CS4, EM_CS5, EM_DQM0/UHPI_HBE0,

EM_DQM1/UHPI_HBE1, EM_OE, EM_SDCAS/UHPI_HCS, EM_SDRAS/UHPI_HAS, EM_WE, XF
• Z, Low Group: SPI_CLK/UHPI_HINT, I2S2_DX/UHPI_HD[11]/GP[27]/SPI_TX, EM_R/W,
MMC0_CLK/I2S0_CLK/GP[0]/McBSP_CLKX, MMC1_CLK/McSPI_CLK/GP[6], EM_SDCLK
• Z Group: EM_D[0:15], GP[21:26]/EM_A[15:20], GP[12:17]/UHPI_HD[2:7], EM_WAIT2, EM_WAIT3,
EM_WAIT4, EM_WAIT5, EMU0, EMU1, SCL, SDA, TDO, USB_MXO, WAKEUP, RTC_CLKOUT
I2S2_CLK/UHPI_HD[8]/GP[18]/SPI_CLK, I2S2_FS/UHPI_HD[9]/GP[19]/SPI_CS0,
I2S2_RX/UHPI_HD[10]/GP[20]/SPI_RX
MMC0_CMD/I2S0_FS/GP[1]/McBSP_FSX, MMC0_D0/I2S0_DX/GP[2]/McBSP_DX,
MMC0_D1/I2S0_RX/GP[3]/McBSP_DR, MMC0_D2/GP[4]/McBSP_FSR,
MMC0_D3/GP[5]/McBSP_CLKR_CLKS
MMC1_CMD/McSPI_CS0/GP[7], MMC1_D0/McSPI_SIMO/GP[8], MMC1_D1/McSPI_SOMI/GP[9],
MMC1_D2/McSPI_CS1/GP[10], MMC1_D3/McSPI_CS2/GP[11]
UART_CTS/UHPI_HD[13]/GP[29]/I2S3_FS, UART_RXD/UHPI_HD[14]/GP[30]/I2S3_RX,
SPI_TX/UHPI_HD[1], SPI_RX/UHPI_HD[0]
• Z, CLKOUT Group: CLKOUT
• Z Group - Analog: GPAIN0, GPAIN1, GPAIN2, GPAIN3
• Z, SYNCH 0→1 Group: EM_SDCKE/UHPI_HHWIL
• Z, SYNCH 1→0 Group: EM_CS0/UHPI_HDS1, EM_CS1/UHPI_HDS2
• Z, SYNCH22 0→1 Group: SPI_CS0/UHPI_HCNTL0, SPI_CS1/UHPI_HCNTL1,

SPI_CS2/UHPI_HR_NW, SPI_CS3/UHPI_HRDY
• Z, SYNCH X→1 Group: EM_BA[0], EM_BA[1], UART_RTS/UHPI_HD[12]/GP[28]/I2S3_CLK,
UART_TXD/UHPI_HD[15]/GP[31]/I2S3_DX
• Z, SYNCH X→0 Group: EM_A[0:10], EM_A[11]/(ALE), EM_A[12]/(CLE), EM_A[13], EM_A[14]

TMS320C5517
5.7.3.3 Reset Electrical Data and Timing
Table 5-4. Timing Requirements for Reset (1) (see Figure 5-6 and Figure 5-7)
CVDD = 1.05 V CVDD = 1.3/1.4 V
NO. UNIT
MIN MAX MIN MAX
1 tw(RSTL) Pulse duration, RESET low 3P 3P ns
(1) P = 1/SYSCLK clock frequency in ns. For example, if SYSCLK = 12 MHz, use P = 83.3 ns. In IDLE3 mode the system clock generator
is bypassed and the SYSCLK frequency is equal to either CLKIN or the RTC clock frequency depending on CLK_SEL.
For a description of IDLE3 mode, see the System chapter in the TMS320C5517 Digital Signal Processor Technical Reference Manual
[literature number SPRUH16].
POWERGOOD
(internal)
RESETN
(POWERGOOD &&
RESETN)
(internal)
1 2
CLKIN or
USB_Osc
System Reset
(internal)
(DSP & Periphs)
Z
Z,Low Group
Z
Z,High Group
Z
Z Group
Z,Synch X->0 Z
Group
Z
Z,Synch X->1
Group
Z
Z,Synch 0->1
Group
Z,Synch 1->0 Z
Group
Z
Z,Synch22 0->1
Group
Z
CLKOUT
22 clocks
65535 clocks if CLK_SEL=1,

131071 clocks if CLK_SEL=0
Figure 5-6. Reset Timing When DSP_LDO_EN = 0

TMS320C5517
POWERGOOD
(internal)
RESETN
(POWERGOOD &&
RESETN)
(internal)
1 2
CLKIN or
USB_Osc
System Reset
(internal)
(DSP & Periphs)
Z
Z,Low Group
Z
Z,High Group
Z
Z Group
Z,Synch X->0 Z
Group
Z
Z,Synch X->1
Group
Z
Z,Synch 0->1
Group
Z,Synch 1->0 Z
Group
Z
Z,Synch22 0->1
Group
Z
CLKOUT
22 clocks

Figure 5-7. Reset Timing When DSP_LDO_EN = 1

TMS320C5517
5.7.3.4 Configurations at Reset
Some device configurations are determined at reset. The following subsections give more details.
5.7.3.4.1 Device and Peripheral Configurations at Device Reset

Table 5-5 summarizes the device boot and configuration pins that are required to be statically tied high,
tied low, or left unconnected during device operation. For proper device operation, a device reset should
be initiated after changing any of these pin functions.
Table 5-5. Default Functions Affected by Device Configuration Pins

CONFIGURATION PINS SIGNAL NO. IPU and IPD FUNCTIONAL DESCRIPTION
DSP_LDO_EN D12 – DSP_LDO enable input.
This signal is not intended to be dynamically
switched.
0 = DSP_LDO is enabled. The internal DSP LDO
is enabled to regulate power on the DSP_LDOO
pin at either 1.3 V or 1.05 V according to the
LDO_DSP_V bit in the LDOCNTL register, see
Figure 5-4). At power-on-reset, the internal POR
monitors the DSP_LDOO pin voltage and
generates the internal POWERGOOD signal
when the DSP_LDO voltage is above a minimum
threshold voltage. The internal device reset is
generated by the AND of POWERGOOD and the
RESET pin.
1 = DSP_LDO is disabled and the DSP_LDOO
pin is in high-impedance (Hi-Z). The internal
voltage monitoring on the DSP_LDOO is
bypassed and the internal POWERGOOD signal
is immediately set high. The RESET pin (D6) will
act as the sole reset source for the device. If an
external power supply is used to provide power to
CVDD, then DSP_LDO_EN should be tied to
LDOI, DSP_LDOO should be left unconnected,
and the RESET pin must be asserted
appropriately for device initialization after
powerup.
Note: to pullup this pin, connect it to the same
supply as LDOI pins.
CLK_SEL C7 –
Clock input select.
0 = The on-chip USB oscillator is enabled and
drives the system clock generator. Also, the USB
LDOO is enabled at reset (USB_LDO_EN=1). In
this configuration, CLKIN must be tied to GND.
1 = CLKIN drives the system clock generator.
The on-chip USB oscillator and USB_LDO are
disabled at reset (USB_LDO_EN=0) but can be
enabled by software
This pin is not allowed to change during device
operation; it must be tied to DVDDIO or GND at
the board.
For proper device operation, external pullup and pulldown resistors may be required on these device
configuration pins. For discussion on situations where external pullup and pulldown resistors are required,
see Section 5.7.20.1.1, Pullup and Pulldown Resistors.
This device also has RESERVED pins that need to be configured correctly for proper device operation
(statically tied high, tied low, or left unconnected at all times). For more details on these pins, see Table 4-
24, Reserved and No Connects Signal Descriptions.

TMS320C5517
5.7.3.4.2 BootMode Implementation and Requirements

The EM_A[20:15]/GP[26:21] pins are used to latch the bootmode, as defined in Table 6-34. These pins
are defined as GPIO function at reset and they are in input state. Therefore these pins can be driven to
the desired bootmode terminations at reset. Approximately 10 system cycles after the rising edge of the
RESET pin, the state on these pins will be latched into registers readable by the DSP at IO-space address
0x1C5A.
As the bootloader code starts executing, it reads the latched value in the bootmode register and uses that
value to determine from which peripheral or method to boot. In any case where the ASYNC modes
(except for NAND) are used as the source data for bootloading (for example, bootload from external NOR
flash to internal memory), the bootloader routine in ROM will change the EM_A[20:15] or GP[26:21] pins
from GPIO mode to EMIF mode by writing to the EBSR (0x1C00). When this occurs, no signal contentions
must be on the EM_A[20:15] or GP[26:21] pins. Passive static terminations by external pullup or pulldown
resistors should also be considered.
Note: Bootloading directly to external peripherals on the EMIF is not supported because the EMIF clock is
turned off before jumping to bootloaded code.
The bootloader must enable the EMIF function on these pins in order to increase the address reach from
15-bits (EM_A[14:0] 32 kW) to the full 21-bits (EM_A[20:0] 2 MW). The bootloader does not have to
enable the EMIF mode on the EM_A[20:15] or GP[26:21] pins for the following external memory types:
NAND: Uses the EM_D[15:0] pins for both address and data and command signaling.
SDRAM: Uses column and row addressing using no more than 11 bits of EM_A pins
The following image contains two BootMode termination scenarios. Other options are also possible.

TMS320C5517
1.8V/2.75V/3.3V
DVDD_EMIF
A[20] EM_A[20]/GP[26]
A[19] EM_A[19]/GP[25]
A[18] EM_A[18]/GP[24]
NOR A[17] EM_A[17]/GP[23] DSP
Flash
A[16] EM_A[16]/GP[22]
A[15] EM_A[15]/GP[21]
A[14:0] EM_[14:0]
XF
VSS
1.8V/2.75V/3.3V
DVDD_EMIF
A[20] EM_A[20]/GP[26]
A[19] EM_A[19]/GP[25]
A[18] EM_A[18]/GP[24]
NOR A[17] EM_A[17]/GP[23] DSP
Flash
A[16] EM_A[16]/GP[22]
A[15] EM_A[15]/GP[21]
A[14:0] EM_[14:0]
XF
VSS
OE
External control logic
Figure 5-8. BootMode Termination Scenarios

TMS320C5517
1 2 3 4 5 6 7 8 9 10
System Clock
RESET
Bootmode latched from

[5:0] GP[26:21]
...
XF Hi-Z
CLKOUT Hi-Z
EM_A[20:15]/ GPIO input mode

Hi-Z EMIF A[20:15] (output mode)
GP[26:21] (externally driven with desired bootmode)
time allowed fro external

device to get off the bus

131071 clocks id CLK_SEL=0
A. DSP changes the pin mode to EMIF Address (outputs) only if needed for the selected bootmode.
Figure 5-9. BootMode Latching
5.7.3.5 Configurations After Reset

The following sections provide details on configuring the device after reset. Multiplexed pin functions are
selected by software after reset. For more details on multiplexed pin function control, see Section 4.3, Pin
Multiplexing.
5.7.3.5.1 External Bus Selection Register (EBSR)

The External Bus Selection Register (EBSR) determines the mapping of the UHPI, I2S2, I2S3, UART,
SPI, McBSP, McSPI, and GPIO signals to 28 signals of the external parallel port pins. The EBSR also
determines the mapping of the I2S, McBSP, McSPI, GPIO, or MMC and SD ports to serial port 0 pins and
serial port 1 pins. The EBSR register is located at IO-space 0x1C00. Once the bit fields of this register are
changed, the routing of the signals takes place on the next CPU clock cycle.
In addition, the EBSR controls the function of the upper bits of the EMIF address bus. Pins EM_A[20:15]
or GP[26:21] can be individually configured as GPIO pins through the Axx_MODE bits. When Axx_MODE
= 1, the EM_A[xx] pin functions as a GPIO pin. When Axx_MODE = 0, the EM_A[xx] pin has EMIF
address output functionality.
Before modifying the values of the external bus selection register, you must clock gate all affected
peripherals through the Peripheral Clock Gating Control Register. After the external bus selection register
has been modified, you must reset the peripherals before using them through the Peripheral Software
Reset Counter Register.
Figure 5-10. External Bus Selection Register (EBSR) [1C00h]

15 14 13 12 11 10 9 8
McBSP_CLKS PPMODE SP1MODE SP0MODE
Selection
R/W-0 R/W-001 R/W-00 R/W-00
7 6 5 4 3 2 1 0
Reserved A20_MODE A19_MODE A18_MODE A17_MODE A16_MODE A15_MODE
R-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

TMS320C5517
Table 5-6. EBSR Register Field Descriptions

Bit Field Description
McBSP_CLKS Selection
McBSP_CLKS 0 = McBSP_CLKR signal is routed to MMC0_D3/GP[5]/McBSPCLKR_CLKS (L11) when
15
Selection SP0MODE=3
1 = McBSP_CLKS signal is routed to MMC0_D3/GP[5]/McBSPCLKR_CLKS (L11) when
SP0MODE=3
Parallel Port Mode Control Bits. These bits control the pin multiplexing of the UHPI, SPI, UART,
I2S2, I2S3, and GP[31:27, 20:12] pins on the parallel port. For more details, see Table 4-20.
000 = Mode 0 (16-bit UHPI bus). All 28 signals of the UHPI bus module are routed to the 28
external signals of the parallel port. Note: SDRAM control signals are multiplexed with UHPI bus
control signals. In this mode, UHPI bus signals are routed to the control ports, so SDRAM cannot
be accessible.
001 = Mode 1 (SPI, GPIO, UART, I2S2, and SDRAM). 7 signals of the SPI module, 6 GPIO
signals, 4 signals of the UART module, 4 signals of the I2S2 module, and 7 SDRAM control signals
are routed to the 28 external signals of the parallel port.
010 = Mode 2 (GPIO and SDRAM). 8 GPIO and 7 SDRAM control signals are routed to the 28
14:12 PPMODE external signals of the parallel port.
011 = Mode 3 (SPI, I2S3, and SDRAM). 4 signals of the SPI module, 4 signals of the I2S3 module,
and 7 SDRAM control signals are routed to the 28 external signals of the parallel port.
100 = Mode 4 (I2S2, UART, and SDRAM). 4 signals of the I2S2 module, 4 signals of the UART
module, and 7 SDRAM control signals are routed to the 28 external signals of the parallel port.
101 = Mode 5 (SPI, UART, and SDRAM). 4 signals of the SPI module, 4 signals of the UART
module, and 7 SDRAM control signals are routed to the 28 external signals of the parallel port.
110 = Mode 6 (SPI, I2S2, I2S3, GPIO, and SDRAM). 7 signals of the SPI module, 4 signals of the
I2S2 module, 4 signals of the I2S3 module, 6 GPIO, and 7 SDRAM control signals are routed to the
28 external signals of the parallel port.
111 = Reserved.
Serial Port 1 Mode Control Bits. The bits control the pin multiplexing of the MMC1, McSPI, and
GPIO pins on serial port 1. For more details, see Table 4-21.
00 = Mode 0 (MMC1 and SD1). All 6 signals of the MMC1 and SD1 module are routed to the 6
external signals of the serial port 1.
11:10 SP1MODE 01 = Mode 1 (McSPI). 6 signals of the McSPI module signals are routed to the 6 external signals of
the serial port 1.
10 = Mode 2 (GP[11:6]). 6 GPIO signals (GP[11:6]) are routed to the 6 external signals of the serial
port 1.
11 = Reserved.
Serial Port 0 Mode Control Bits. The bits control the pin multiplexing of the MMC0, I2S0, McBSP,
and GPIO pins on serial port 0. For more details, see Section 4.3.3.
00 = Mode 0 (MMC0 and SD0). All 6 signals of the MMC0 and SD0 module are routed to the 6
external signals of the serial port 0.
9:8 SP0MODE 01 = Mode 1 (I2S0 and GP[5:4]). 4 signals of the I2S0 module and 2 GP[5:4] signals are routed to
the 6 external signals of the serial port 0.
10 = Mode 2 (GP[5:0]). 6 GPIO signals (GP[5:0]) are routed to the 6 external signals of the serial
port 0.
11 = Mode 3 (McBSP). 6 signals of the McBSP module are routed to the 6 external signal port 0.
7-6 Reserved Reserved. Read-only, writes have no effect.

TMS320C5517
Table 5-6. EBSR Register Field Descriptions (continued)

Bit Field Description
A20 Pin Mode Bit. This bit controls the pin multiplexing of the EMIF address 20 (EM_A[20]) and
general-purpose input/output pin 26 (GP[26]) pin functions.
0 = Pin function is EMIF address pin 20 (EM_A[20]).
5 A20_MODE 1 = Pin function is general-purpose input/output pin 26 (GP[26]).
This is the default mode at reset and the pin is configured as an Input.
Approximately 10 cycles after the rising edge of RESET, the state on this pin is latched into the
BootMode register to specify the boot method.
general-purpose input/output pin 23 (GP[23]) pin functions. For more details, see Table 4-22,
MMC0, I2S0, McBSP, and GP[5:0] Pin Multiplexing.
2 A17_MODE
1 = Pin function is general-purpose input/output pin 23 (GP[23]).
1 A16_MODE
0 A15_MODE

TMS320C5517
5.7.3.5.2 LDO Control Register [7004h]

When the DSP_LDO is enabled by the DSP_LDO_EN pin being tied low, the DSP_LDOO voltage is set
by the DSP_LDO_V bit in this register. The reset state of this bit causes the DSP_LDOO output to be set
to 1.3 V at boot. The DSP_LDOO voltage can be programmed to be either 1.05 V or 1.3 V via the
DSP_LDO_V bit (bit 1) in the LDO Control Register (LDOCNTL).
At reset, the USB_LDO state is dependent on the CLK_SEL pin. At reset, if CLK_SEL is high
(CLK_SEL=1), the USB LDO is disabled but can be enabled via the USBLDOEN bit (bit 0) in the
LDOCNTL register. If CLK_SEL is low (CLK_SEL=0), the USB LDO is enabled and cannot be disabled.
For more detailed information on the LDOs, see Section 5.7.2.1.1, LDO Configuration.
5.7.3.5.3 EMIF and USB System Control Registers (ESCR and USBSCR) [1C33h and 1C32h]
After reset, by default, the CPU performs 16-bit accesses to the EMIF and USB registers and data space.
To perform 8-bit accesses to the EMIF data space, the user must set the BYTEMODE bits to 01b for the
"high byte" or 10b for the "low byte" in the EMIF System Control Register (ESCR). Similarly, the
BYTEMODE bits in the USB System Control Register (USBSCR) must also be configured for byte access.
5.7.3.5.4 Peripheral Clock Gating Control Registers (PCGCR1 and PCGCR2) [1C02h and 1C03h]
After hardware reset, the DSP executes the on-chip bootloader from ROM. Depending on the BootMode
used, the bootloader may leave the PCGCR1 and the PCGCR2 registers in various states. This is also
true of the ICR and the ISR registers.
Programmers should always verify the state of these registers and appropriately set them. Their states
after boot loading are not determined by their reset conditions.

TMS320C5517
5.7.3.5.5 Pullup and Pulldown Inhibit Registers (PUDINHIBR1, 2, 3, 4, 5, 6, and 7) [1C17h, 1C18h, 1C19h,
1C4Ch, 1C4Dh, 1C4Fh, and 1C50h, respectively]
Each internal pullup and pulldown (IPU and IPD) resistor on the device can be individually controlled
through the IPU and IPD registers (PUDINHIBR1 [1C17h] , PUDINHIBR2 [1C18h], PUDINHIBR3 [1C19h],
PUDINHIBR4 [1C4Ch], PUDINHIBR5 [1C4Dh], PUDINHIBR6 [1C4Fh], and PUDINHIBR7 [1C50h]). To
minimize power consumption, internal pullup or pulldown resistors should be disabled in the presence of
an external pullup or pulldown resistor or external driver. Most internal pullups and pulldowns are enabled
at reset to help ensure no pins are left floating. Section 5.7.20.1.1, Pullup and Pulldown Resistors,
describes other situations in which an pullup and pulldown resistors are required.
When CVDD is powered down, pullup and pulldown resistors will be forced disabled and an internal bus-
holder will be enabled. For more detailed information, see Section 5.7.2.3, Digital I/O Behavior When Core
Power (CVDD) is Down.
5.7.3.5.6 Output Slew Rate Control Register (OSRCR) [1C16h]

To provide the lowest power consumption setting, the DSP has configurable slew rate control on the EMIF
and CLKOUT output pins. The output slew rate control register (OSRCR) is used to set a subset of the
device I/O pins, namely CLKOUT and EMIF pins, to either fast or slow slew rate. The slew rate feature is
implemented by staging and delaying turn-on times of the parallel p-channel drive transistors and parallel
n-channel drive transistors of the output buffer. In the slow slew rate configuration, the delay is longer, but
ultimately the same number of parallel transistors are used to drive the output high or low. Thus, the drive
strength is ultimately the same. The slower slew rate control can be used for power savings and has the
greatest effect at lower DVDDIO and DVDDEMIF voltages.

TMS320C5517
5.7.4 Clock Specifications
5.7.4.1 Recommended Clock and Control Signal Transition Behavior

All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
5.7.4.2 Clock Considerations

The system clock, which is used by the CPU and most of the DSP peripherals, is controlled by the system
clock generator. The system clock generator features a software-programmable PLL multiplier and several
dividers. The clock generator accepts an input reference clock from the CLKIN pin or the output clock of
the on-chip USB oscillator. The selection of the input reference clock is based on the state of the
CLK_SEL pin. The CLK_SEL pin is required to be statically tied high or low and cannot change
dynamically after reset.
If CLK_SEL=0 at reset, the on-chip USB oscillator is selected as the source of the system clock generator
and the USB PLL as well. In this configuration, the on-chip USB oscillator cannot be turned off.
If CLK_SEL=1 at reset, the external clock via the CLKIN pin will be used as the source of the system clock
generator and the on-chip USB oscillator is used only for the USB PLL input. In this configuration, the on-
chip USB oscillator can be turned off if the USB peripheral is not being used.
In addition, the DSP requires a reference clock for the real-time clock (RTC). The RTC reference clock is
generated using a dedicated on-chip oscillator with a 32.768-kHz external crystal connected to the
RTC_XI and RTC_XO pins.
The 32.768-kHz crystal can be disabled if the RTC peripheral is not being used. However, when the RTC
oscillator is disabled, the RTC peripheral will not operate and the RTC registers (I/O address range
1900h – 197Fh) will not be accessible. This includes the RTC power management register (RTCPMGT)
which controls the RTCLKOUT and WAKEUP pins. To disable the RTC oscillator, connect the RTC_XI pin
to CVDDRTC and the RTC_XO pin to ground.
For more information on crystal specifications for the RTC oscillator and the USB oscillator, see
Section 5.7.4.3.3, External Clock Input From RTC_XI, CLKIN, and USB_MXI Pins.
5.7.4.2.1 Clock Configurations After Device Reset

After reset, the on-chip Bootloader programs the system clock generator based on the value of
EM_A[20:15] or GP[26:21], which are latched into the BootMode[5:0] bits in the BootMode register
([1C34h]) at reset. (See Section 6.4, Boot Modes, for details.)
5.7.4.2.1.1 Device Clock Frequency

After the boot process is complete, the user is allowed to re-program the system clock generator to bring
the device up to the desired clock frequency and the desired peripheral clock state (clock gating or not).
The user must adhere to various clock requirements when programming the system clock generator. For
more information, see Section 5.7.4.3, Clock PLLs.
Note: The on-chip Bootloader allows for DSP registers to be configured during the boot process.
However, this feature must not be used to change the output frequency of the system clock generator
during the boot process. The bootloader also uses Timer0 to calculate the settling time of BG_CAP until
executing bootloader code. The bootloader register modification feature must not modify the Timer0
registers.
5.7.4.2.1.2 Peripheral Clock State

The clock and reset state of each of peripheral is controlled through a set of system registers. The
peripheral clock gating control registers (PCGCR1 and PCGCR2) are used to enable and disable
peripheral clocks. The peripheral software reset counter register (PSRCR) and the peripheral reset control
register (PRCR) are used to assert and de-assert peripheral reset signals.

TMS320C5517
After hardware reset, the DSP boots via the bootloader code in ROM. During the boot process, the
bootloader chooses a peripheral or method to boot from based on the value of BootMode[5:0] bits in the
BootMode register ([1C34h]) and queries the peripheral to determine if it can boot from that peripheral. At
that time, the individual peripheral clock will be enabled for the query and then disabled again when the
bootloader is finished with the peripheral. By the time the bootloader releases control to the user code, all
peripheral clocks will be off and all domains in the ICR, except the CPU domain, will be idled.
5.7.4.2.1.3 USB Oscillator Control

At reset, if CLK_SEL = 0, the on-chip USB oscillator is enabled and is used as the clock source of the
system clock generator. Since the USB oscillator is the system's clock source, it is not possible to disable
the USB oscillator when CLK_SEL = 0.
When CLK_SEL = 1, the USB Oscillator is disabled at reset but can be enabled or disabled by writing to
the USB system control register (USBSCR). To enable the oscillator, the USBOSCDIS and
USBOSCBIASDIS bits must be cleared to 0. The user must wait until the USB oscillator stabilizes before
proceeding with the USB configuration. The USB oscillator stabilization time is typically 100 µs, with a 10
ms maximum. (Note: The startup time is highly dependent on the ESR and capacitive load on the crystal.)
5.7.4.3 PLLs
The device DSP uses a software-programmable PLL to generate frequencies required by the CPU, DMA,
and peripherals. The reference clock for the PLL is taken from either the CLKIN pin or the USB on-chip
oscillator (as specified through the CLK_SEL pin).
5.7.4.3.1 PLL Device-Specific Information

There is a minimum and maximum operating frequency for CLKIN, PLLIN, and the system clock
(SYSCLK). The system clock generator must be configured not to exceed any of these constraints
documented in this section (certain combinations of external clock inputs, internal dividers, and PLL
multiply ratios are not supported).
Table 5-7. PLL Clock Frequency Ranges

CVDD = 1.05 V CVDD = 1.3 V CVDD = 1.4 V
CLOCK SIGNAL VDDA_PLL = 1.3 V VDDA_PLL = 1.3 V VDDA_PLL = 1.3 V UNIT
NAME
MIN TYP MAX MIN TYP MAX MIN TYP MAX
11.2896, 11.2896, 11.2896,
12.0, 12.0, 12.0,
12.288, 12.288, 12.288,
CLKIN (1) MHz
16.8, 16.8, 16.8,
or or or
19.2 19.2 19.2
PLLIN 1.7 6.79 1.7 6.79 1.7 6.79 MHz
PLLOUT 60 120 60 120 60 120
VCO Output (2)
(before output
125 625 125 625 125 625 MHz
divider OD and
OD2)
SYSCLK 0 75 0 175 0 200 MHz
PLL_LOCKTIME 4 4 4 ms
(1) These CLKIN values are used when the CLK_SEL pin = 1.
(2) To use less PLL power, ensure VCO max is close to the SYSCLK max.

TMS320C5517
The PLL has lock time requirements that must be followed. The PLL lock time is the amount of time
needed for the PLL to complete its phase-locking sequence.
5.7.4.3.2 Clock PLL Considerations With External Clock Sources

If the CLKIN pin is used to provide the reference clock to the PLL, to minimize the clock jitter a single
clean power supply should power both the device and the external clock oscillator circuit. The minimum
CLKIN rise and fall times should also be observed. For the input clock timing requirements, see
Section 5.7.4.4, Input and Output Clocks Electrical Data and Timing.
Rise and fall times, duty cycles (high and low pulse durations), and the load capacitance of the external
clock source must meet the device requirements in this data manual (see Section 5.3.2, Electrical
Characteristics, and Section 5.7.4.4, Input and Output Clocks Electrical Data and Timing.
5.7.4.3.3 External Clock Input From RTC_XI, CLKIN, and USB_MXI Pins
The device DSP includes two options to provide an external clock input to the system clock generator:
• Use the on-chip USB oscillator with an external 12-MHz crystal connected to the USB_MXO and
USB_MXI pins.
• Use an external LVCMOS clock input fed into the CLKIN pin that operates at the same voltage as the
DVDDIO supply (1.8-, 2.75-, or 3.3-V).
The CLK_SEL pin determines which input is used as the clock source for the system clock generator. For
more details, see Section 5.7.3.4.1.
If CLK_SEL = 0 at reset, the on-chip USB oscillator is used as the source of the system clock generator
and the USB PLL as well.
If CLK_SEL= 1 at reset, the external LVCMOS clock input fed into the CLKIN pin will be used as the
source of the system clock generator and the on-chip USB oscillator is used only for the USB PLL source.
In this configuration, the on-chip USB oscillator can be turned off if the USB peripheral is not being used.
Additionally, the DSP requires a reference clock for the on-chip real time clock (RTC). The RTC reference
clock is generated using a dedicated on-chip oscillator with a 32.768-kHz external crystal connected to the
RTC_XI and RTC_XO pins. The crystal for the RTC oscillator is not required if the RTC is not used,
however the RTC must still be powered by an external power source. None of the on-chip LDOs can
power CVDDRTC. The RTC registers starting at I/O address 1900h will not be accessible without an RTC
clock. This includes the RTC Power Management Register which provides control to the on-chip LDOs
and WAKEUP and RTC_CLKOUT pins. Section 5.7.4.3.3.2, Real-Time Clock (RTC) On-Chip Oscillator
With External Crystal, provides more details on using the RTC on-chip oscillator with an external crystal.
5.7.4.3.3.1 USB On-Chip Oscillator With External Crystal

The USB on-chip oscillator requires an external 12-MHz crystal connected across the USB_MXI and
USB_MXO pins, along with two load capacitors, as shown in Figure 5-11. The external crystal load
capacitors must be connected only to the USB oscillator ground pin (USB_VSSOSC). Do not connect to
board ground (VSS). The USB_VDDOSC pin can be connected to the same power supply as USB_VDDA3P3.
If the external clock input via the CLKIN pin is used as the source of the system clock generator
(CLK_SEL =1 at reset) and the USB peripheral is not being used, then the on-chip USB oscillator can be
permanently disabled. To permanently disable the USB oscillator, connect the USB_MXI pin to ground
(VSS) and leave the USB_MXO pin unconnected. The USB oscillator power pins (USB_VDDOSC and
USB_VSSOSC) should also be connected to ground, as shown in Figure 5-12.
When using an external 12-MHz oscillator, the external oscillator clock signal should be connected to the
USB_MXI pin and the amplitude of the oscillator clock signal must meet the VIH requirement (see
Section 5.2, Recommended Operating Conditions). The USB_MXO is left unconnected and the
USB_VSSOSC signal is connected to board ground (VSS).

TMS320C5517
USB_MXI USB_MXO USB_VSSOSC USB_VDDOSC VSS USB_VDDA3P3
Crystal
12 MHz
C1 C2
3.3 V 3.3 V
Figure 5-11. 12-MHz USB Oscillator
USB_MXI USB_MXO USB_VSSOSC USB_VDDOSC VSS USB_VDDA3P3
Figure 5-12. Connections when USB Oscillator is Permanently Disabled
The crystal should be in fundamental-mode operation, and parallel resonant, with a maximum effective
series resistance (ESR) specified in Table 5-8. The load capacitors, C1 and C2 are the total capacitance
of the circuit board and components, excluding the IC and crystal. The load capacitor value is usually
approximately twice the value of the crystal's load capacitance, CL, which is specified in the crystal
manufacturer's datasheet and should be chosen such that the equation below is satisfied. All discrete
components used to implement the oscillator circuit should be placed as close as possible to the
associated oscillator pins (USB_MXI and USB_MXO) and to the USB_VSSOSC pin.
C1 C2
CL =
(C1 + C2 )
Table 5-8. Input Requirements for Crystal on the 12-MHz USB Oscillator
PARAMETER MIN NOM MAX UNIT
Start-up time (from power up until oscillating at stable frequency of 12 MHz) (1) 0.100 10 ms
Oscillation frequency 12 MHz
ESR 100 kΩ
(2)
Frequency stability ±100 ppm
Maximum shunt capacitance 5 pF
Maximum crystal drive 330 µW
(1) The startup time is highly dependent on the ESR and the capacitive load of the crystal.
(2) If the USB is used, a 12-MHz, ±100-ppm crystal is recommended.

TMS320C5517
5.7.4.3.3.2 Real-Time Clock (RTC) On-Chip Oscillator With External Crystal

The on-chip RTC oscillator requires an external 32.768-kHz crystal connected across the RTC_XI and
RTC_XO pins, along with two load capacitors, as shown in Figure 5-13. The external crystal load
capacitors must be connected only to the RTC oscillator ground pin (VSSRTC). Do not connect to board
ground (VSS). Position the VSS lead on the board between RTC_XI and RTC_XO as a shield to reduce
direct capacitance between RTC_XI and RTC_XO leads on the board. The CVDDRTC pin can be connected
to the same power supply as CVDD, or may be connected to a different supply that meets the
recommended operating conditions (see Section 5.2, Recommended Operating Conditions), if desired.
RTC_XI RTC_XO VSSRTC CVDDRTC VSS CVDD
Crystal
32.768 kHz
C1 C2
0.998-CVDD V 1.05/1.3/1.4 V
Figure 5-13. 32.768-kHz RTC Oscillator
The RTC oscillator can be optionally disabled by connecting RTC_XI to CVDDRTC and RTC_XO to ground
(VSS). However, when the RTC oscillator is disabled the RTC registers starting at I/O address 1900h will
not be accessible. This includes the RTC Power Management Register which provides control to the on-
chip LDOs and WAKEUP and RTC_CLKOUT pins. Note: The RTC must still be powered even if the RTC
oscillator is disabled.
RTC_XI CV DDRTC RTC_XO V SS V SSRTC
0.998–CVDD V
Figure 5-14. Connections when RTC Oscillator is Permanently Disabled
The crystal should be in fundamental-mode function, and parallel resonant, with a maximum effective
series resistance (ESR) specified in Table 5-9. The load capacitors, C1 and C2, are the total capacitance
of the circuit board and components, excluding the IC and crystal. The load capacitors values are usually
approximately twice the value of the crystal's load capacitance, CL, which is specified in the crystal
manufacturer's datasheet and should be chosen such that the equation is satisfied. All discrete
components used to implement the oscillator circuit should be placed as close as possible to the
associated oscillator pins (RTC_XI and RTC_XO) and to the VSSRTC pin.
C1 C2
CL =
(C1 + C2 )
TMS320C5517
Table 5-9. Input Requirements for Crystal on the 32.768-kHz RTC Oscillator
PARAMETER MIN NOM MAX UNIT
Start-up time (from power up until oscillating at stable frequency of 32.768-kHz) (1) 0.2 2 sec
Oscillation frequency 32.768 kHz
ESR 100 kΩ
Maximum shunt capacitance 1.6 pF
Maximum crystal drive 1.0 µW
(1) The startup time is highly dependent on the ESR and the capacitive load of the crystal.
5.7.4.3.3.3 CLKIN Pin With LVCMOS-Compatible Clock Input (Optional)

Note: If CLKIN is not used, the pin must be tied low.
A LVCMOS-compatible clock can be fed into the CLKIN pin for use by the DSP system clock generator.
The external connections are shown in Figure 5-15 and Figure 5-16. The bootloader assumes that the
CLKIN pin is connected to the LVCMOS-compatible clock source with a frequency of 11.2896, 12.0,
12.288, 16.8, or 19.2 MHz based on the value of BootMode[5:4] bits at reset. (See Section 6.4, Boot
Mode, for details.) Note: The CLKIN pin operates at the same voltage as the DVDDIO supply (1.8, 2.75, or
3.3 V).
In this configuration the RTC oscillator can be optionally disabled by connecting RTC_XI to CVDDRTC and
RTC_XO to ground (VSS). However, when the RTC oscillator is disabled the RTC registers starting at I/O
address 1900h will not be accessible. This includes the RTC Power Management Register which provides
control to the on-chip LDOs and WAKEUP and RTC_CLKOUT pins. Note: The RTC must still be powered
by an external power source even if the RTC oscillator is disabled. None of the on-chip LDOs can power
CVDDRTC.
CLKIN USB_MXI USB_MXO USB_V SSOSC USB_V DDOSC VSS USB_V DDA3P3
Crystal
12 MHz
C1 C2
3.3 V 3.3 V
Figure 5-15. LVCMOS-Compatible Clock Input With USB Oscillator Enabled

TMS320C5517
CLKIN USB_MXI USB_MXO USB_V SSOSC USB_V DDOSC VSS USB_V DDA3P3
Figure 5-16. LVCMOS-Compatible Clock Input With USB Oscillator Disabled

TMS320C5517
5.7.4.4 Input and Output Clocks Electrical Data and Timing
Table 5-10. Timing Requirements for CLKIN (1) (2)

(see Figure 5-17)
CVDD = 1.05/1.3/1.4 V
NO. UNIT
MIN NOM MAX
11.2896
12.0,
12.288,
1 tc(CLKIN) Cycle time, external clock driven on CLKIN MHz
16.8,
or
19.2
0.466 *
2 tw(CLKINH) Pulse duration, CLKIN high ns
tc(CLKIN)
0.466 *
3 tw(CLKINL) Pulse duration, CLKIN low ns
tc(CLKIN)
4 tt(CLKIN) Transition time, CLKIN 4 ns
(1) The CLKIN frequency and PLL multiply factor should be chosen such that the resulting clock frequency is within the specific range for
CPU operating frequency.
(2) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
1
4
1 2
CLKIN
3
4
Figure 5-17. CLKIN Timing
Table 5-11. Switching Characteristics Over Recommended Operating Conditions for CLKOUT
[I/O = 3.3/2.75 V] (1) (2)
(see Figure 5-18)
CVDD = 1.05/1.3/1.4 V
NO. PARAMETER VDDA_PLL = 1.3 V UNIT
MIN MAX
1 tc(CLKOUT) Cycle time, CLKOUT 10 ns
0.466 *
2 tw(CLKOUTH) Pulse duration, CLKOUT high ns
tc(CLKOUT)
0.466 *
3 tw(CLKOUTL) Pulse duration, CLKOUT low ns
tc(CLKOUT)
4 tt(CLKOUTR) Transition time (rise), CLKOUT 5 ns
5 tt(CLKOUTF) Transition time (fall), CLKOUT 5 ns
(1) The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
(2) P = 1/SYSCLK clock frequency in nanoseconds (ns). For example, when SYSCLK frequency is 100 MHz, use P = 10 ns.

TMS320C5517
Table 5-12. Switching Characteristics Over Recommended Operating Conditions for CLKOUT
[I/O = 1.8 V] (1) (2)
(see Figure 5-18)
CVDD = 1.05/1.3/1.4 V
NO. PARAMETER VDDA_PLL = 1.3 V UNIT
MIN MAX
1 tc(CLKOUT) Cycle time, CLKOUT 20 ns
0.466 *
2 tw(CLKOUTH) Pulse duration, CLKOUT high ns
tc(CLKOUT)
0.466 *
3 tw(CLKOUTL) Pulse duration, CLKOUT low ns
tc(CLKOUT)
4 tt(CLKOUTR) Transition time (rise), CLKOUT 5 ns
5 tt(CLKOUTF) Transition time (fall), CLKOUT 5 ns
(1) The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
(2) P = 1/SYSCLK clock frequency in nanoseconds (ns). For example, when SYSCLK frequency is 100 MHz, use P = 10 ns.
2
1 5
CLKOUT
Figure 5-18. CLKOUT Timing

TMS320C5517
5.7.4.5 Wake-up Events, Interrupts, and XF

The device has a number of interrupts to service the needs of its peripherals. The interrupts can be
selectively enabled or disabled.
5.7.4.5.1 Interrupts Electrical Data and Timing
Table 5-13. Timing Requirements for Interrupts (1) (see Figure 5-19)
CVDD = 1.05 V
CVDD = 1.3 V
NO. CVDD = 1.4 V UNIT
MIN MAX
1 tw(INTH) Pulse duration, interrupt high CPU active 2P ns
2 tw(INTL) Pulse duration, interrupt low CPU active 2P ns
(1) P = 1/SYSCLK clock frequency in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns. For example, when the
CPU core is clocked at 175 MHz, use P = 5.71 ns.
INTx
Figure 5-19. External Interrupt Timings
5.7.4.5.2 Wake-Up From IDLE Electrical Data and Timing
Table 5-14. Timing Requirements for Wake-Up From IDLE (see Figure 5-20)
CVDD = 1.05 V
CVDD = 1.3 V
MIN MAX
1 tw(WKPL) Pulse duration, WAKEUP or INTx low, SYSCLKDIS = 1 30.5 μs
Table 5-15. Switching Characteristics Over Recommended Operating Conditions For Wake-Up From
IDLE (1) (2) (3) (4) (see Figure 5-20)
CVDD = 1.05 V
CVDD = 1.3 V
NO. PARAMETER CVDD = 1.4 V UNIT
MIN TYP MAX
IDLE3 Mode (5) with SYSCLKDIS = 1,
D ns
WAKEUP or INTx event, CLK_SEL = 1
td(WKEVTH-C Delay time, WAKEUP pulse
2 IDLE3 Mode (5) with SYSCLKDIS = 1,
KLGEN) complete to CPU active C ns
WAKEUP or INTx event, CLK_SEL = 0
(5)
IDLE2 Mode ; INTx event 3P ns
(1) D = 1/ External Clock Frequency (CLKIN).
(2) C = 1/RTCCLK= 30.5 µs. RTCCLK is the clock output of the 32.768-kHz RTC oscillator.
(3) P = 1/SYSCLK clock frequency in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns.
(4) Assumes the internal LDOs are used with a 0.1uF bandgap capacitor.
(5) For a description of IDLE2 and IDLE3 mode, see the System chapter in the TMS320C5517 Digital Signal Processor Technical
Reference Manual [literature number SPRUH16].

TMS320C5517
CLKOUT
WAKEUP
INTx
A. INT[1:0] can only be used as a wake-up event for IDLE3 and IDLE2 modes.
For a description of IDLE2 and IDLE3 mode, see the System chapter in the TMS320C5517 Digital Signal Processor
Technical Reference Manual [literature number SPRUH16].
B. RTC interrupt (internal signal) can be used as wake-up event for IDLE3 and IDLE2 modes.
C. Any unmasked interrupt can be used to exit the IDLE2 mode.
D. CLKOUT reflects either the CPU clock, SAR, USB PHY, or PLL clock dependent on the setting of the CLOCKOUT
Clock Source Register. For this diagram, CLKOUT refers to the CPU clock.
Figure 5-20. Wake-Up From IDLE Timings
5.7.4.5.3 XF Electrical Data and Timing
Table 5-16. Switching Characteristics Over Recommended Operating Conditions For XF (1) (2)
(see Figure 5-21)

CVDD = 1.05 V
CVDD = 1.3 V
MIN MAX
1 td(XF) Delay time, CLKOUT high to XF high 0 10.2 ns
(1) P = 1/SYSCLK clock frequency in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns.
(2) C = 1/RTCCLK= 30.5 µs. RTCCLK is the clock output of the 32.768-kHz RTC oscillator.
(A)
CLKOUT
XF
A. CLKOUT reflects either the CPU clock, SAR, USB PHY, or PLL clock dependent on the setting of the CLOCKOUT
Clock Source Register. For this diagram, CLKOUT refers to the CPU clock.
Figure 5-21. XF Timings

TMS320C5517
5.7.5 Direct Memory Access (DMA) Controller

The DMA controller is used to move data among internal memory, external memory, and peripherals
without intervention from the CPU and in the background of CPU operation.
The DSP includes a total of four DMA controllers. Aside from the DSP resources they can access, all four
DMA controllers are identical.
The DMA controller has the following features:
• Operation that is independent of the CPU.
• Four channels, which allow the DMA controller to keep track of the context of four independent block
transfers.
• Event synchronization. DMA transfers in each channel can be made dependent on the occurrence of
selected events.
• An interrupt for each channel. Each channel can send an interrupt to the CPU on completion of the
programmed transfer.
• Ping-Pong mode allows the DMA controller to keep track of double buffering context without CPU
intervention.
• A dedicated clock idle domain. The four device DMA controllers can be put into a low-power state by
independently turning off their input clocks.
5.7.5.1 DMA Channel Synchronization Events

The DMA controllers allow activity in their channels to be synchronized to selected events. The DSP
supports 20 separate synchronization events and each channel can be tied to separate sync events
independent of the other channels. Synchronization events are selected by programming the CHnEVT
field in the DMAn channel event source registers (DMAnCESR1 and DMAnCESR2).

TMS320C5517
5.7.6 External Memory Interface (EMIF)

The device supports several memories and external device interfaces, including: NOR Flash, NAND
Flash, SRAM, Non-Mobile SDRAM, and Mobile SDRAM (mSDRAM).
Note: The device can support non-mobile SDRAM under certain circumstances. The device also always
uses mobile SDRAM initialization, but it is able to support SDRAM memories that ignore the BA0 and BA1
pins for the 'load mode register' command. During the mobile SDRAM initialization, the device issues the
'load mode register' initialization command to two different addresses that differ in only the BA0 and BA1
address bits. These registers are the Extended Mode register and the Mode register. The Extended mode
register exists only in mSDRAM and not in non-mSDRAM. If a non-mobile SDRAM memory ignores bits
BA0 and BA1, the second loaded register value overwrites the first, leaving the desired value in the Mode
register and the non-mobile SDRAM will work with the device.
The EMIF provides an 8-bit or 16-bit data bus, an address bus width up to 21 bits, and 6 chip selects,
along with memory control signals.
The EM_A[20:15] address signals are multiplexed with the GPIO peripheral and controlled by the External
Bus Selection Register (EBSR). For more detail on the pin muxing, see Section 5.7.3.5.1, External Bus
Selection Register (EBSR).
5.7.6.1 EMIF Asynchronous Memory Support

The EMIF supports asynchronous:
• SRAM memories
• NAND Flash memories
• NOR Flash memories
The EMIF data bus can be configured for both 8- or 16-bit width. The device supports up to 21 address
lines and four external wait and interrupt inputs. Up to four asynchronous chip selects are supported by
EMIF (EM_CS[5:2]).
Each chip select has the following individually programmable attributes:
• Data bus width
• Read cycle timings: setup, hold, strobe
• Write cycle timings: setup, hold, strobe
• Bus turn around time
• Select Strobe Option
• NAND flash controller supports 1-bit and 4-bit ECC calculation on blocks of 512 bytes
Each chip select shares the following programmable attribute: Extended Wait Option with Programmable
Timeout.
5.7.6.2 EMIF Non-Mobile and Mobile Synchronous DRAM Memory Supported

The EMIF supports 16-bit non-mobile and mobile single data rate (SDR) SDRAM in addition to the
asynchronous memories listed in Section 5.7.6.1, EMIF Asynchronous Memory Support. The supported
SDRAM and mobile SDRAM configurations are:
• One, two, and four bank SDRAM and mSDRAM devices
• Supports devices with eight, nine, ten, and eleven column addresses
• CAS latency of two or three clock cycles
• 16-bit data-bus width
• 3.3-, 2.75-, and 1.8 -V LVCMOS interface that is separate from the rest of the chip I/Os.
• One (EM_CS0) or two (EM_CS[1:0]) chip selects

TMS320C5517
Additionally, the SDRAM and mSDRAM interface of EMIF supports placing the SDRAM and mSDRAM in
"Self-Refresh" and "Powerdown Modes". Self-Refresh mode allows the SDRAM and mSDRAM to be put
into a low-power state while still retaining memory contents; since the SDRAM and mSDRAM will continue
to refresh itself even without clocks from the DSP. Powerdown mode achieves even lower power, except
the DSP must periodically wake the SDRAM and mSDRAM up and issue refreshes if data retention is
required. To achieve the lowest power consumption, the SDRAM and mSDRAM interface has configurable
slew rate on the EMIF pins.
The device has limitations to the clock frequency on the EM_SDCLK pin based on the CVDD and
DVDDEMIF:
• The clock frequency on the EM_SDCLK pin can be configured either as SYSCLK (DSP operating
frequency) or SYSCLK/2 via bit 0 of the ECDR Register (1C26h).
• When CVDD = 1.3 V or 1.4 V, and DVDDEMIF = 3.3 V or 2.75 V, the max clock frequency on the
EM_SDCLK pin is limited to 100 MHz (EM_SDCLK = 100 MHz). Therefore, if SYSCLK ≤ 100 MHz, the
EM_SDCLK can be configured either as SYSCLK or SYSCLK/2. If SYSCLK > 100 MHz, the
EM_SDCLK must be configured as SYSCLK/2 and ≤ 100 MHz.
• When CVDD =1.05 V, and DVDDEMIF = 3.3 V or 2.75 V, the max clock frequency on the EM_SDCLK pin
is limited to 75 MHz (EM_SDCLK = 75 MHz). Therefore, if SYSCLK ≤ 75 MHz, the EM_SDCLK can be
configured as either SYSCLK or SYSCLK/2. If SYSCLK > 75 MHz, the EM_SDCLK must be configured
as SYSCLK/2 and ≤ 75 MHz.
• When DVDDEMIF = 1.8 V, regardless of the CVDD voltage, the clock frequency on the EM_SDCLK pin
must be configured as SYSCLK/2 and ≤ 50 MHz.

TMS320C5517
5.7.6.3 EMIF Electrical Data and Timing CVDD = 1.05 V, DVDDEMIF = 3.3/2.75/1.8 V
Table 5-17. Timing Requirements for EMIF SDRAM and mSDRAM Interface (1) (see Figure 5-22 and
Figure 5-23)
CVDD = 1.05 V
CVDD = 1.05 V
DVDDEMIF =
NO. DVDDEMIF = 1.8 V UNIT
3.3/2.75 V
MIN MAX MIN MAX
Input setup time, read data valid on EM_D[15:0] before
19 tsu(DV-CLKH) 4.07 5.86 ns
EM_SDCLK rising
Input hold time, read data valid on EM_D[15:0] after EM_SDCLK
20 th(CLKH-DIV) 2.1 2.6 ns
rising
(1) Timing parameters are obtained with 10pF loading on the EMIF pins.
Table 5-18. Switching Characteristics Over Recommended Operating Conditions for EMIF SDRAM and
mSDRAM Interface (1) (2) (see Figure 5-22 and Figure 5-23)
CVDD = 1.05 V CVDD = 1.05 V
NO. PARAMETER DVDDEMIF = 3.3/2.75 V DVDDEMIF = 1.8 V UNIT
MIN TYP MAX MIN TYP MAX
1 tc(CLK) Cycle time, EMIF clock EM_SDCLK 13.33 (3) 20 (4) ns
Pulse duration, EMIF clock EM_SDCLK high
2 tw(CLK) 6.67 10 ns
or low
Delay time, EM_SDCLK rising to
3 td(CLKH-CSV) 1.1 10.67 1.1 13.46 ns
EMA_CS[1:0] valid
5 td(CLKH-DQMV) 1.1 10.67 1.1 13.46 ns
EM_DQM[1:0] valid
Delay time, EM_SDCLK rising to EM_A[20:0]
7 td(CLKH-AV) 1.1 10.67 1.1 13.46 ns
and EM_BA[1:0] valid
Delay time, EM_SDCLK rising to EM_D[15:0]
9 td(CLKH-DV) 1.1 10.67 1.1 13.46 ns
valid
Delay time, EM_SDCLK rising to EM_SDRAS
11 td(CLKH-RASV) 1.1 10.67 1.1 13.46 ns
valid
Delay time, EM_SDCLK rising to EM_SDCAS
13 td(CLKH-CASV) 1.1 10.67 1.1 13.46 ns
valid
Delay time, EM_SDCLK rising to EM_WE
15 td(CLKH-WEV) 1.1 10.67 1.1 13.46 ns
valid
Delay time, EM_SDCLK rising to EM_SDCKE
21 td(CLKH-CKEV) 1.1 10.67 1.1 13.46 ns
valid
(2) E = SYSCLK period in ns. For example, when SYSCLK is set to 75 or 100 MHz, E = 13.33 or 10 ns, respectively. For more detail on the
EM_SDCLK speed see Section 5.7.6.2, EMIF Non-Mobile and Mobile Synchronous DRAM Memory Supported.
(3) When CVDD = 1.05 V, and DVDDEMIF = 3.3 V or 2.75 V, the max clock frequency on the EM_SDCLK pin is limited to 75 MHz
(EM_SDCLK = 75 MHz). For more information, see the EMIF chapter in the TMS320C5517 Digital Signal Processor Technical
Reference Manual [literature number SPRUH16].
(4) When DVDDEMIF = 1.8 V, the max clock frequency on the EM_SDCLK pin is limited to 50 MHz (EM_SDCLK = 50 MHz). For more
information, see the EMIF chapter in the TMS320C5517 Digital Signal Processor Technical Reference Manual [literature number
SPRUH16].
Table 5-19. Timing Requirements for EMIF Asynchronous Memory, DVDDEMIF = 1.8 V (1) (2) (see Figure 5-24,
Figure 5-26, and Figure 5-27)
CVDD = 1.05 V
MIN NOM MAX
READS and WRITES
2 tw(EM_WAIT) Pulse duration, EM_WAITx assertion and deassertion 2E ns
(2) E = SYSCLK period in ns. For example, when SYSCLK is set to 75 or 100 MHz, E = 13.33 or 10 ns, respectively.
TMS320C5517
Table 5-19. Timing Requirements for EMIF Asynchronous Memory, DVDDEMIF = 1.8 V(1)(2) (see Figure 5-24,
Figure 5-26, and Figure 5-27) (continued)
CVDD = 1.05 V
MIN NOM MAX
READS
12 tsu(EMDV-EMOEH) Setup time, EM_D[15:0] valid before EM_OE high 18 ns
13 th(EMOEH-EMDIV) Hold time, EM_D[15:0] valid after EM_OE high 0 ns
(3)
14 tsu (EMOEL-EMWAIT) Setup time, EM_WAITx asserted before end of Strobe Phase 4E + 18 ns
WRITES
28 tsu (EMWEL-EMWAIT) Setup time, EM_WAITx asserted before end of Strobe Phase (3) 4E + 18 ns
(3) Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAITx must be asserted to add extended
wait states. Figure 5-26 and Figure 5-27 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
Table 5-20. Timing Requirements for EMIF Asynchronous Memory, DVDDEMIF = 3.3/2.75 V (1) (2) (see
Figure 5-24, Figure 5-26, and Figure 5-27)
CVDD = 1.05 V
NO. DVDDEMIF = 3.3/2.75 V UNIT
MIN NOM MAX
READS and WRITES
READS
14 tsu (EMOEL-EMWAIT) Setup time, EM_WAITx asserted before end of Strobe Phase (3) 4E + 17 ns
WRITES
28 tsu (EMWEL-EMWAIT) Setup time, EM_WAITx asserted before end of Strobe Phase (3) 4E + 17 ns

TMS320C5517
Table 5-21. Switching Characteristics Over Recommended Operating Conditions for EMIF Asynchronous Memory, DV DDEMIF = 1.8 V (1) (2) (3)
(see
Figure 5-25 and Figure 5-27) (4)
CVDD = 1.05 V
NO. PARAMETER DVDDEMIF = 1.8 V UNIT
MIN TYP MAX
READS and WRITES
1 td(TURNAROUND) Turn around time (TA)*E - 18 (TA)*E (TA)*E + 18 ns
READS
EMIF read cycle time (EW = 0) (RS+RST+RH)*E - 18 (RS+RST+RH)*E (RS+RST+RH)*E + 18 ns
3 tc(EMRCYCLE)
EMIF read cycle time (EW = 1) (RS+RST+RH+(EWC*16))*E - 18 (RS+RST+RH+(EWC*16))*E (RS+RST+RH+(EWC*16))*E + 18 ns
Output setup time, EM_CS[5:2] low to EM_OE low (SS = 0) (RS)*E - 11 (RS)*E (RS)*E + 11 ns
4 tsu(EMCEL-EMOEL)
Output setup time, EM_CS[5:2] low to EM_OE low (SS = 1) -11 0 +11 ns
Output hold time, EM_OE high to EM_CS[5:2] high (SS = 0) (RH)*E - 11 (RH)*E (RH)*E + 11 ns
5 th(EMOEH-EMCEH)
Output hold time, EM_OE high to EM_CS[5:2] high (SS = 1) -11 0 +11 ns
6 tsu(EMBAV-EMOEL) Output setup time, EM_BA[1:0] valid to EM_OE low (RS)*E - 11 (RS)*E (RS)*E + 11 ns
7 th(EMOEH-EMBAIV) Output hold time, EM_OE high to EM_BA[1:0] invalid (RH)*E - 18 (RH)*E (RH)*E + 18 ns
8 tsu(EMBAV-EMOEL) Output setup time, EM_A[20:0] valid to EM_OE low (RS)*E - 11 (RS)*E (RS)*E + 11 ns
9 th(EMOEH-EMAIV) Output hold time, EM_OE high to EM_A[20:0] invalid (RH)*E - 18 (RH)*E (RH)*E + 18 ns
EM_OE active low pulse (EW = 0) (RST)*E - 18 (RST)*E (RST)*E + 18 ns
10 tw(EMOEL)
EM_OE active low pulse (EW = 1) (RST+(EWC*16))*E - 18 (RST+(EWC*16))*E (RST+(EWC*16))*E + 11 ns
11 td(EMWAITH-EMOEH) Delay time from EM_WAITx deasserted to EM_OE high 4E - 18 4E 4E + 18 ns
WRITES
EMIF write cycle time (EW = 0) (WS+WST+WH)*E - 18 (WS+WST+WH)*E (WS+WST+WH)*E + 18 ns
15 tc(EMWCYCLE) (WS+WST+WH+(EWC*16))*E +
EMIF write cycle time (EW = 1) (WS+WST+WH+(EWC*16))*E - 18 (WS+WST+WH+(EWC*16))*E ns
18
Output setup time, EM_CS[5:2] low to EM_WE low (SS = 0) (WS)*E - 18 (WS)*E (WS)*E + 18 ns
16 tsu(EMCSL-EMWEL)
Output setup time, EM_CS[5:2] low to EM_WE low (SS = 1) -18 0 +18 ns
Output hold time, EM_WE high to EM_CS[5:2] high (SS = 0) (WH)*E - 11 (WH)*E (WH)*E + 11 ns
17 th(EMWEH-EMCSH)
Output hold time, EM_WE high to EM_CS[5:2] high (SS = 1) -11 0 +11 ns
18 tsu(EMBAV-EMWEL) Output setup time, EM_BA[1:0] valid to EM_WE low (WS)*E - 11 (WS)*E (WS)*E + 11 ns
19 th(EMWEH-EMBAIV) Output hold time, EM_WE high to EM_BA[1:0] invalid (WH)*E - 11 (WH)*E (WH)*E + 11 ns
20 tsu(EMAV-EMWEL) Output setup time, EM_A[20:0] valid to EM_WE low (WS)*E - 11 (WS)*E (WS)*E + 11 ns
21 th(EMWEH-EMAIV) Output hold time, EM_WE high to EM_A[20:0] invalid (WH)*E - 11 (WH)*E (WH)*E + 11 ns
(2) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold, MEWC = Maximum external wait cycles. These
parameters are programmed via the Asynchronous Configuration and Asynchronous Wait Cycle Configuration Registers.
(4) EWC = external wait cycles determined by EM_WAITx input signal. EWC supports the following range of values EWC[256-1]. Note that the maximum wait time before timeout is specified
by bit field MEWC in the Asynchronous Wait Cycle Configuration Register.

TMS320C5517
Table 5-21. Switching Characteristics Over Recommended Operating Conditions for EMIF Asynchronous Memory, DV DDEMIF = 1.8 V(1)(2) (3)
(see
Figure 5-25 and Figure 5-27)(4) (continued)
CVDD = 1.05 V
MIN TYP MAX
EM_WE active low pulse (EW = 0) (WST)*E - 18 (WST)*E (WST)*E + 18 ns
22 tw(EMWEL)
EM_WE active low pulse (EW = 1) (WST+(EWC*16))*E - 18 (WST+(EWC*16))*E (WST+(EWC*16))*E + 18 ns
23 td(EMWAITH-EMWEH) Delay time from EM_WAITx deasserted to EM_WE high 3E - 18 4E 4E + 18 ns
24 tsu(EMDV-EMWEL) Output setup time, EM_D[15:0] valid to EM_WE low (WS)*E - 18 (WS)*E (WS)*E + 18 ns
25 th(EMWEH-EMDIV) Output hold time, EM_WE high to EM_D[15:0] invalid (WH)*E - 11 (WH)*E (WH)*E + 11 ns

TMS320C5517
Table 5-22. Switching Characteristics Over Recommended Operating Conditions for EMIF Asynchronous Memory, DV DDEMIF = 3.3/2.75 V (1) (2) (3)
(see Figure 5-25 and Figure 5-27) (4)

CVDD = 1.05 V
NO. PARAMETER DVDDEMIF = 3.3/2.75 V UNIT
MIN TYP MAX
READS and WRITES
READS
3 tc(EMRCYCLE)
4 tsu(EMCEL-EMOEL)
5 th(EMOEH-EMCEH)
Output hold time, EM_OE high to EM_CS[5:2] high (SS = 1) -9 0 +9 ns
8 tsu(EMBAV-EMOEL) Output setup time, EM_A[20:0] valid to EM_OE low (RS)*E - 9 (RS)*E (RS)*E + 9 ns
10 tw(EMOEL)
WRITES
17
Output setup time, EM_CS[5:2] low to EM_WE low (SS = 0) (WS)*E - 17 (WS)*E (WS)*E + 17 ns
16 tsu(EMCSL-EMWEL)
17 th(EMWEH-EMCSH)

TMS320C5517
Table 5-22. Switching Characteristics Over Recommended Operating Conditions for EMIF Asynchronous Memory, DV DDEMIF = 3.3/2.75 V(1)(2) (3)
(see Figure 5-25 and Figure 5-27)(4) (continued)

CVDD = 1.05 V
MIN TYP MAX
22 tw(EMWEL)

TMS320C5517
5.7.6.4 EMIF Electrical Data and Timing CVDD = 1.3/1.4 V, DVDDEMIF = 3.3/2.75/1.8 V
Table 5-23. Timing Requirements for EMIF SDRAM and mSDRAM Interface (1) (see Figure 5-22 and
Figure 5-23)
CVDD = 1.3/1.4 V
CVDD = 1.3/1.4 V
DVDDEMIF =
3.3/2.75 V
MIN MAX MIN MAX
Input setup time, read data valid on EM_D[15:0] before
19 tsu(DV-CLKH) 4.07 3.28 ns
EM_SDCLK rising
Input hold time, read data valid on EM_D[15:0] after EM_SDCLK
20 th(CLKH-DIV) 2.1 3.1 ns
rising
Table 5-24. Switching Characteristics Over Recommended Operating Conditions for EMIF SDRAM and
mSDRAM Interface (1) (2) (see Figure 5-22 and Figure 5-23)
CVDD = 1.3/1.4 V CVDD = 1.3/1.4 V
NO. PARAMETER DVDDEMIF = 3.3/2.75 V DVDDEMIF = 1.8 V UNIT
MIN TYP MAX MIN TYP MAX
1 tc(CLK) Cycle time, EMIF clock EM_SDCLK 10 (3) 20 (4) ns
Pulse duration, EMIF clock EM_SDCLK high
2 tw(CLK) 5 10 ns
or low
3 td(CLKH-CSV) 0.9 7.88 1.1 10.67 ns
EMA_CS[1:0] valid
5 td(CLKH-DQMV) 0.9 7.88 1.1 10.67 ns
EM_DQM[1:0] valid
Delay time, EM_SDCLK rising to EM_A[20:0]
7 td(CLKH-AV) 0.9 7.88 1.1 10.67 ns
and EM_BA[1:0] valid
Delay time, EM_SDCLK rising to EM_D[15:0]
9 td(CLKH-DV) 0.9 7.88 1.1 10.67 ns
valid
Delay time, EM_SDCLK rising to EM_SDRAS
11 td(CLKH-RASV) 0.9 7.88 1.1 10.67 ns
valid
Delay time, EM_SDCLK rising to EM_SDCAS
13 td(CLKH-CASV) 0.9 7.88 1.1 10.67 ns
valid
Delay time, EM_SDCLK rising to EM_WE
15 td(CLKH-WEV) 0.9 7.88 1.1 10.67 ns
valid
Delay time, EM_SDCLK rising to EM_SDCKE
21 td(CLKH-CKEV) 0.9 7.88 1.1 10.67 ns
valid
(2) E = SYSCLK period in ns. For example, when SYSCLK is set to 75 or 100 MHz, E = 13.33 or 10 ns, respectively. For more detail on the
EM_SDCLK speed see Section 5.7.6.2, EMIF Non-Mobile and Mobile Synchronous DRAM Memory Supported.
(3) The maximum clock frequency on the EM_SDCLK pin is limited to 100 MHz (EM_SDCLK = 100 MHz). For more information, see the
EMIF chapter in the TMS320C5517 Digital Signal Processor Technical Reference Manual [literature number SPRUH16].
(4) When DVDDEMIF = 1.8 V, the max clock frequency on the EM_SDCLK pin is limited to 50 MHz (EM_SDCLK = 50 MHz). For more
information, see the EMIF chapter in the TMS320C5517 Digital Signal Processor Technical Reference Manual [literature number
SPRUH16].

TMS320C5517
Table 5-25. Timing Requirements for EMIF Asynchronous Memory, DVDDEMIF = 1.8 V (1) (2) (see Figure 5-24,
Figure 5-26, and Figure 5-27)
CVDD = 1.3/1.4 V
MIN NOM MAX
READS and WRITES
READS
(3)
14 tsu (EMOEL-EMWAIT) Setup Time, EM_WAITx asserted before end of Strobe Phase 4E + 10 ns
WRITES
28 tsu (EMWEL-EMWAIT) Setup Time, EM_WAITx asserted before end of Strobe Phase (3) 4E + 10 ns

TMS320C5517
Table 5-26. Timing Requirements for EMIF Asynchronous Memory, DVDDEMIF = 3.3/2.75 V (1) (2) (see
Figure 5-24, Figure 5-26, and Figure 5-27)
CVDD = 1.3/1.4 V
NO. DVDDEMIF = 3.3/2.75 V UNIT
MIN NOM MAX
READS and WRITES
READS
(3)
14 tsu (EMOEL-EMWAIT) Setup Time, EM_WAITx asserted before end of Strobe Phase 4E + 9 ns
WRITES
28 tsu (EMWEL-EMWAIT) Setup Time, EM_WAITx asserted before end of Strobe Phase (3) 4E + 9 ns

TMS320C5517
Table 5-27. Switching Characteristics Over Recommended Operating Conditions for EMIF Asynchronous Memory, DV DDEMIF = 1.8 V (1) (2) (3) (4)
(see Figure 5-24, Figure 5-26, and Figure 5-27)

CVDD = 1.3/1.4 V
MIN TYP MAX
READS and WRITES
READS
3 tc(EMRCYCLE)
4 tsu(EMCSL-EMOEL)
5 th(EMOEH-EMCSH)
Output hold time, EM_OE high to EM_CE[5:2] high (SS = 1) -4 0 +4 ns
8 tsu(EMAV-EMOEL) Output setup time, EM_A[20:0] valid to EM_OE low (RS)*E - 4 (RS)*E (RS)*E + 4 ns
10 tw(EMOEL)
WRITES
10
Output setup time, EM_CS[5:2] low to EM_WE low (SS = 0) (WS)*E - 10 (WS)*E (WS)*E +10 ns
16 tsu(EMCSL-EMWEL)
17 th(EMWEH-EMCSH)

TMS320C5517
Table 5-27. Switching Characteristics Over Recommended Operating Conditions for EMIF Asynchronous Memory, DV DDEMIF = 1.8 V(1)(2) (3) (4)
(see Figure 5-24, Figure 5-26, and Figure 5-27) (continued)

CVDD = 1.3/1.4 V
MIN TYP MAX
22 tw(EMWEL)

TMS320C5517
Table 5-28. Switching Characteristics Over Recommended Operating Conditions for EMIF Asynchronous Memory, DV DDEMIF = 3.3/2.75 V (1) (2) (3)
(4)
(see Figure 5-24, Figure 5-26, and Figure 5-27)
CVDD = 1.3/1.4 V
MIN TYP MAX
READS and WRITES
READS
3 tc(EMRCYCLE)
4 tsu(EMCSL-EMOEL)
5 th(EMOEH-EMCSH)
Output hold time, EM_OE high to EM_CE[5:2] high (SS = 1) -4 0 +4 ns
8 tsu(EMAV-EMOEL) Output setup time, EM_A[20:0] valid to EM_OE low (RS)*E - 4 (RS)*E (RS)*E + 4 ns
10 tw(EMOEL)
WRITES
15 tc(EMWCYCLE)
EMIF write cycle time (EW = 1) (WS+WST+WH+(EWC*16))*E - 9 (WS+WST+WH+(EWC*16))*E (WS+WST+WH+(EWC*16))*E + 9 ns
Output setup time, EM_CS[5:2] low to EM_WE low (SS = 0) (WS)*E - 9 (WS)*E (WS)*E +9 ns
16 tsu(EMCSL-EMWEL)
17 th(EMWEH-EMCSH)
22 tw(EMWEL)

TMS320C5517
Table 5-28. Switching Characteristics Over Recommended Operating Conditions for EMIF Asynchronous Memory, DV DDEMIF = 3.3/2.75 V(1)(2) (3)
(4)
(see Figure 5-24, Figure 5-26, and Figure 5-27) (continued)
CVDD = 1.3/1.4 V
MIN TYP MAX

TMS320C5517
1
BASIC mSDRAM
WRITE OPERATION 2 2
EM_SDCLK
3 3
EM_CS[1:0]
5 5
EM_DQM[1:0]
7 7
EM_BA[1:0]
7 7
EM_A[20:0]
9
9
EM_D[15:0]
11 11
EM_SDRAS
13
EM_SDCAS
15 15
EM_WE
Figure 5-22. EMIF Basic SDRAM and mSDRAM Write Operation
1
BASIC mSDRAM
READ OPERATION 2 2
EM_SDCLK
3 3
EM_CS[1:0]
5 5
EM_DQM[1:0]
7 7
EM_BA[1:0]
7 7
EM_A[20:0]
19
2 EM_CLK Delay
17 20 17
EM_D[15:0]
11 11
EM_SDRAS
13 13
EM_SDCAS
EM_WE
Figure 5-23. EMIF Basic SDRAM and mSDRAM Read Operation

TMS320C5517
3
1
EM_CS[5:2]
EM_BA[1:0]
EM_A[20:0]
4 5
8 9
6 7
10
EM_OE
13
12
EM_D[15:0]
EM_WE
Figure 5-24. Asynchronous Memory Read Timing for EMIF
15
1
EM_CS[5:2]
EM_BA[1:0]
EM_A[20:0]
16 17
18 19
20 21
22
EM_WE
25
24
EM_D[15:0]
EM_OE
Figure 5-25. Asynchronous Memory Write Timing for EMIF

TMS320C5517
EM_CS[5:2] SETUP STROBE Extended Due to EM_WAITx STROBE HOLD
EM_BA[1:0]
EM_A[20:0]
EM_D[15:0]
14
11
EM_OE
2
2
EM_WAITx Asserted Deasserted
Figure 5-26. EM_WAITx Read Timing Requirements
EM_CS[5:2] SETUP STROBE Extended Due to EM_WAITx STROBE HOLD
EM_BA[1:0]
EM_A[20:0]
EM_D[15:0]
28
25
EM_WE
2
2
EM_WAITx Asserted Deasserted
Figure 5-27. EM_WAITx Write Timing Requirements

TMS320C5517
5.7.7 General-Purpose Input/Output (GPIO)

The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.
When configured as an output, you can write to an internal register to control the state driven on the
output pin. When configured as an input, you can detect the state of the input by reading the state of the
internal register. External input clocks on certain GPIOs can also be used to drive the timers on this
device. The GPIO can also be used to send interrupts to the CPU.
The GPIO peripheral supports the following:
• Up to 26 GPIOs plus 1 general-purpose output (XF and 4 Special-Purpose Outputs for Use With SAR)
• The 26 GPIO pins have internal pulldowns (IPDs) which can be individually disabled
• The 26 GPIOs can be configured to generate edge detected interrupts to the CPU on either the rising
or falling edge
The device GPIO pin functions are multiplexed with various other signals. For more detailed information
on what signals are multiplexed with the GPIO and how to configure them, see Section 4.2, Signal
Descriptions and Section 4.3, Pin Multiplexing of this document.
5.7.7.1 GPIO Peripheral Input/Output Electrical Data and Timing
Table 5-29. Timing Requirements for GPIO Inputs (1) (see Figure 5-28)
CVDD = 1.05 V
CVDD = 1.3 V/1.4
NO. V UNIT
MIN MAX
1 tw(ACTIVE) Pulse duration, GPIO input/external interrupt pulse active 2C (1) (2) ns
(1) (2)
2 tw(INACTIVE) Pulse duration, GPIO input/external interrupt pulse inactive C ns
(1) The pulse duration given is sufficient to get latched into the GPIO_IFR register and to generate an interrupt. However, if a user wants to
have the device recognize the GPIO changes through software polling of the GPIO Data In (GPIO_DIN) register, the GPIO duration
must be extended to allow the device enough time to access the GPIO register through the internal bus.
(2) C = SYSCLK period in ns. For example, when running parts at 100 MHz, use C = 10 ns.
Table 5-30. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs
(see Figure 5-28)
CVDD = 1.05 V
NO. PARAMETER CVDD = 1.3 V/1.4 V UNIT
MIN MAX
3 tw(GPOH) Pulse duration, GP[x] output high 3C (1) (2) ns
4 tw(GPOL) Pulse duration, GP[x] output low 3C (1) (2) ns
(1) This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the
GPIO is dependent upon internal bus activity.
(2) C = SYSCLK period in ns. For example, when running parts at 100 MHz, use C = 10 ns.

TMS320C5517
2
1
GP[x] Input
(With IOINTEDGy = 0)
2
1
GP[x] Input
(With IOINTEDGy = 1)
4
3
GP[x] Output
Figure 5-28. GPIO Port Timing
5.7.7.2 GPIO Peripheral Input Latency Electrical Data and Timing
Table 5-31. Timing Requirements for GPIO Input Latency (1)

CVDD = 1.05 V
CVDD = 1.3 V
MIN MAX
Polling GPIO_DIN register 5 cyc
1 tL(GPI) Latency, GP[x] input Polling GPIO_IFR register 7 cyc
Interrupt Detection 8 cyc
(1) The pulse duration given is sufficient to generate a CPU interrupt. However, if a user wants to have the device recognize the GP[x] input
changes through software polling of the GPIO register, the GP[x] input duration must be extended to allow device enough time to access
the GPIO register through the internal bus.

TMS320C5517
5.7.8 Inter-Integrated Circuit (I2C)

The inter-integrated circuit (I2C) module provides an interface between the device and other devices
compliant with Philips Semiconductors Inter-IC bus (I2C-bus™) specification version 2.1. External
components attached to this 2-wire serial bus can transmit and receive 2 to 8-bit data to and from the DSP
through the I2C module. The I2C port does not support CBUS compatible devices.
The I2C port supports the following features:
• Compatible with Philips I2C Specification Version 2.1 (January 2000)
• Data Transfer Rate from 10 kbps to 400 kbps (Philips Fast-Mode Rate)
• Noise Filter to Remove Noise 50 ns or Less
• Seven- and Ten-Bit Device Addressing Modes
• Master (Transmit and Receive) and Slave (Transmit and Receive) Functionality
• One Read DMA Event and One Write DMA Event, which can be used by the DMA Controller
• One Interrupt that can be used by the CPU
• Slew-Rate Limited Open-Drain Output Buffers
The I2C module clock must be in the range from 6.7 MHz to 13.3 MHz. This is necessary for proper
operation of the I2C module. With the I2C module clock in this range, the noise filters on the SDA and
SCL pins suppress noise that has a duration of 50 ns or shorter. The I2C module clock is derived from the
DSP clock divided by a programmable prescaler.
5.7.8.1 I2C Electrical Data and Timing
Table 5-32. Timing Requirements for I2C Timings (1) (see Figure 5-29)
CVDD = 1.05 V
CVDD = 1.3 V
CVDD = 1.4 V
NO. UNIT
STANDARD
FAST MODE
MODE
MIN MAX MIN MAX
1 tc(SCL) Cycle time, SCL 10 2.5 µs
Setup time, SCL high before SDA low (for a repeated START
2 tsu(SCLH-SDAL) 4.7 0.6 µs
condition)
Hold time, SCL low after SDA low (for a START and a
3 th(SCLL-SDAL) 4 0.6 µs
repeated START condition)
4 tw(SCLL) Pulse duration, SCL low 4.7 1.3 µs
5 tw(SCLH) Pulse duration, SCL high 4 0.6 µs
(2)
6 tsu(SDAV-SCLH) Setup time, SDA valid before SCL high 250 100 ns
7 th(SDA-SCLL) Hold time, SDA valid after SCL low 0 (3) 0 (3) 0.9 (4) µs
Pulse duration, SDA high between STOP and START
8 tw(SDAH) 4.7 1.3 µs
conditions
9 tr(SDA) Rise time, SDA (5) 1000 20 + 0.1Cb (6) 300 ns
(5)
10 tr(SCL) Rise time, SCL 1000 20 + 0.1Cb (6) 300 ns
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down. Also these pins are not 3.6 V-tolerant (their VIH cannot go above DVDDIO + 0.3 V).
(2) A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)= 250 ns must then be
met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns
(according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(4) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
(5) The rise and fall times are measured at 30% and 70% of DVDDIO. The fall time is only slightly influenced by the external bus load ©b)
and external pullup resistor. However, the rise time (tr) is mainly determined by the bus load capacitance and the value of the pullup
resistor. The pullup resistor must be selected to meet the I2C rise and fall time values specified.
(6) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
TMS320C5517
Table 5-32. Timing Requirements for I2C Timings(1) (see Figure 5-29) (continued)
CVDD = 1.05 V
CVDD = 1.3 V
CVDD = 1.4 V
NO. UNIT
STANDARD
FAST MODE
MODE
MIN MAX MIN MAX
(5) (6)
11 tf(SDA) Fall time, SDA 300 20 + 0.1Cb 300 ns
12 tf(SCL) Fall time, SCL (5) 300 20 + 0.1Cb (6) 300 ns
13 tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition) 4 0.6 µs
14 tw(SP) Pulse duration, spike (must be suppressed) 0 50 ns
15 Cb (6) Capacitive load for each bus line 400 400 pF
11 9
SDA
8 6 14
4
13
10 5
SCL
1 12 3
7 2
3
Stop Start Repeated Stop

Start
Figure 5-29. I2C Receive Timings

TMS320C5517
Table 5-33. Switching Characteristics for I2C Timings (1) (see Figure 5-30)
CVDD = 1.05 V
CVDD = 1.3 V
CVDD = 1.4 V
NO. PARAMETER UNIT
STANDARD
FAST MODE
MODE
MIN MAX MIN MAX
16 tc(SCL) Cycle time, SCL 10 2.5 µs
Delay time, SCL high to SDA low (for a repeated START
17 td(SCLH-SDAL) 4.7 0.6 µs
condition)
Delay time, SDA low to SCL low (for a START and a
18 td(SDAL-SCLL) 4 0.6 µs
repeated START condition)
19 tw(SCLL) Pulse duration, SCL low 4.7 1.3 µs
20 tw(SCLH) Pulse duration, SCL high 4 0.6 µs
21 td(SDAV-SCLH) Delay time, SDA valid to SCL high 250 100 ns
22 tv(SCLL-SDAV) Valid time, SDA valid after SCL low 0 0 0.9 µs
Pulse duration, SDA high between STOP and START
23 tw(SDAH) 4.7 1.3 µs
conditions
24 tr(SDA) Rise time, SDA (2) 1000 20 + 0.1Cb (1) 300 ns
(2)
25 tr(SCL) Rise time, SCL 1000 20 + 0.1Cb (1) 300 ns
26 tf(SDA) Fall time, SDA (2) 300 20 + 0.1Cb (1) 300 ns
(2) (1)
27 tf(SCL) Fall time, SCL 300 20 + 0.1Cb 300 ns
28 td(SCLH-SDAH) Delay time, SCL high to SDA high (for STOP condition) 4 0.6 µs
29 Cp Capacitance for each I2C pin 10 10 pF
(1) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
(2) The rise and fall times are measured at 30% and 70% of DVDDIO. The fall time is only slightly influenced by the external bus load ©b)
and external pullup resistor. However, the rise time (tr) is mainly determined by the bus load capacitance and the value of the pullup
resistor. The pullup resistor must be selected to meet the I2C rise and fall time values specified.
26 24
SDA
23 21
19
28
25 20
SCL
16 27 18
22 17
18
Stop Start Repeated Stop

Start
Figure 5-30. I2C Transmit Timings

TMS320C5517
5.7.9 Inter-IC Sound (I2S)

The device I2S peripherals allow serial transfer of full-duplex streaming data, usually audio data, between
the device and an external I2S peripheral device such as an audio codec.
The device supports three independent dual-channel I2S peripherals, each with the following features:
• Full-duplex (transmit and receive) dual-channel communication
• Double buffered data registers that allow for continuous data streaming
• I2S/Left-justified and DSP data format with a data delay of 1 or 2 bits
• Data word-lengths of 8, 10, 12, 14, 16, 18, 20, 24, or 32 bits
• Ability to sign-extend received data samples for easy use in signal processing algorithms
• Programmable polarity for both frame synchronization and bit clocks
• Stereo (in I2S/Left-justified or DSP data formats) or mono (in DSP data format) mode
• Detection of over-run, under-run, and frame-sync error conditions

TMS320C5517
5.7.9.1 Inter-IC Sound (I2S) Electrical Data and Timing
Table 5-34. Timing Requirements for I2S [I/O = 3.3 and 2.75 V] (1) (see Figure 5-31)
MASTER SLAVE
NO. CVDD = 1.05 V CVDD = 1.3/1.4 V CVDD = 1.05 V CVDD = 1.3/1.4 V UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
1 tc(CLK) Cycle time, I2S_CLK 2P (1) (2) 2P (1) (2) 2P (1) (2) 2P (1) (2) ns
(1) (2) (1) (2) (1) (2)
2 tw(CLKH) Pulse duration, I2S_CLK high P P P P (1) (2) ns
3 tw(CLKL) Pulse duration, I2S_CLK low P (1) (2) P (1) (2) P (1) (2) P (1) (2) ns
Setup time, I2S_RX valid before I2S CLK high
tsu(RXV-CLKH) 5 3 5 3 ns
(CLKPOL = 0)
7
Setup time, I2S_RX valid before I2S_CLK low
tsu(RXV-CLKL) 5 3 5 3 ns
(CLKPOL = 1)
Hold time, I2S_RX valid after I2S_CLK high
th(CLKH-RXV) 3 3 3 3 ns
(CLKPOL = 0)
8
Hold time, I2S_RX valid after I2S_CLK low
th(CLKL-RXV) 3 3 3 3 ns
(CLKPOL = 1)
Setup time, I2S_FS valid before I2S_CLK high
tsu(FSV-CLKH) – – 12.5 6.5 ns
(CLKPOL = 0)
9
Setup time, I2S_FS valid before I2S_CLK low
tsu(FSV-CLKL) – – 12.5 6.5 ns
(CLKPOL = 1)
Hold time, I2S_FS valid after I2S_CLK high
th(CLKH-FSV) – – tw(CLKH) + 0.7 (3) tw(CLKH) + 0.7 (3) ns
(CLKPOL = 0)
10
Hold time, I2S_FS valid after I2S_CLK low
th(CLKL-FSV) – – tw(CLKL) + 0.7 (3) tw(CLKL) + 0.7 (3) ns
(CLKPOL = 1)
(1) P = SYSCLK period in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns.
(2) Use whichever value is greater.
(3) In Slave Mode, I2S_FS is required to be latched on both edges of I2S input clock (I2S_CLK).

TMS320C5517
Table 5-35. Timing Requirements for I2S [I/O = 1.8 V] (1) (see Figure 5-31)
MASTER SLAVE
NO. CVDD = 1.05 V CVDD = 1.3/1.4 V CVDD = 1.05 V CVDD = 1.3/1.4 V UNIT
1 tc(CLK) Cycle time, I2S_CLK 2P (1) (2)
2P (1) (2)
2P (1) (2)
2P (1) (2)
ns
(1) (2) (1) (2) (1) (2) (1) (2)
2 tw(CLKH) Pulse duration, I2S_CLK high P P P P ns
3 tw(CLKL) Pulse duration, I2S_CLK low P (1) (2)
P (1) (2)
P (1) (2)
P (1) (2)
ns
Setup time, I2S_RX valid before I2S CLK
tsu(RXV-CLKH) 5 3 5 3.5 ns
high (CLKPOL = 0)
7
Setup time, I2S_RX valid before I2S_CLK
tsu(RXV-CLKL) 5 3 5 3.5 ns
low (CLKPOL = 1)
Hold time, I2S_RX valid after I2S_CLK high
th(CLKH-RXV) 3 3 3 3 ns
(CLKPOL = 0)
8
Hold time, I2S_RX valid after I2S_CLK low
th(CLKL-RXV) 3 3 3 3 ns
(CLKPOL = 1)
Setup time, I2S_FS valid before I2S_CLK
tsu(FSV-CLKH) – – 12.5 15 ns
high (CLKPOL = 0)
9
Setup time, I2S_FS valid before I2S_CLK
tsu(FSV-CLKL) – – 12.5 15 ns
low (CLKPOL = 1)
Hold time, I2S_FS valid after I2S_CLK high tw(CLKH) + tw(CLKH) +
th(CLKH-FSV) – – ns
(CLKPOL = 0) 0.7 (3) 0.71 (3)
10
Hold time, I2S_FS valid after I2S_CLK low tw(CLKL) + tw(CLKL) +
th(CLKL-FSV) – – ns
(CLKPOL = 1) 0.7 (3) 0.71 (3)
(3) In Slave Mode, I2S_FS is required to be latched on both edges of I2S input clock (I2S_CLK).

TMS320C5517
Table 5-36. Switching Characteristics Over Recommended Operating Conditions for I2S Output
[I/O = 3.3 and 2.75 V] (see Figure 5-31)
MASTER SLAVE
NO. PARAMETER CVDD = 1.05 V CVDD = 1.3/1.4 V CVDD = 1.05 V CVDD = 1.3/1.4 V UNIT
1 tc(CLK) Cycle time, I2S_CLK P (1) (2)
P (1) (2)
P (1) (2)
P (1) (2)
ns
(1) (2) (1) (2) (1) (2) (1) (2)
tw(CLKH) Pulse duration, I2S_CLK high (CLKPOL = 0) P P P P ns
2
tw(CLKL) Pulse duration, I2S_CLK low (CLKPOL = 1) P (1) (2)
P (1) (2)
P (1) (2)
P (1) (2)
ns
P (1) (2)
P (1) (2)
P (1) (2)
ns
3
tw(CLKH) Pulse duration, I2S_CLK high (CLKPOL = 1) P (1) (2)
P (1) (2)
P (1) (2)
P (1) (2)
ns
tdmax(CLKL-DXV) Output Delay time, I2S_CLK low to I2S_DX valid (CLKPOL = 0) 0 14.5 0 11 0 14.5 0 11 ns
4
tdmax(CLKH-DXV) Output Delay time, I2S_CLK high to I2S_DX valid (CLKPOL = 1) 0 14.5 0 11 0 14.5 0 11 ns
tdmax(CLKL-FSV) Delay time, I2S_CLK low to I2S_FS valid (CLKPOL = 0) -2 7 -1.74 5 – – ns
5
tdmax(CLKH-FSV) Delay time, I2S_CLK high to I2S_FS valid (CLKPOL = 1) -2 7 -1.74 5 – – ns

TMS320C5517
Table 5-37. Switching Characteristics Over Recommended Operating Conditions for I2S Output
[I/O = 1.8 V] (see Figure 5-31)
MASTER SLAVE
NO. PARAMETER CVDD = 1.05 V CVDD = 1.3/1.4 V CVDD = 1.05 V CVDD = 1.3/1.4 V UNIT
50 or 40 or 50 or 40 or
1 tc(CLK) Cycle time, I2S_CLK ns
2P (1) (2) 2P (1) (2) 2P (1) (2) 2P (1) (2)
tw(CLKH) Pulse duration, I2S_CLK high (CLKPOL = 0) P (1) (2)
P (1) (2)
P (1) (2)
P (1) (2)
ns
2 (1) (2) (1) (2) (1) (2) (1) (2)
tw(CLKL) Pulse duration, I2S_CLK low (CLKPOL = 1) P P P P ns
P (1) (2)
P (1) (2)
P (1) (2)
ns
3 (1) (2) (1) (2) (1) (2) (1) (2)
tw(CLKH) Pulse duration, I2S_CLK high (CLKPOL = 1) P P P P ns
tdmax(CLKL-DXV) Output Delay time, I2S_CLK low to I2S_DX valid (CLKPOL = 0) 0 17.7 0 14.5 0 17.7 0 14.5 ns
4
tdmax(CLKH-DXV) Output Delay time, I2S_CLK high to I2S_DX valid (CLKPOL = 1) 0 17.7 0 14.5 0 17.7 0 14.5 ns
tdmax(CLKL-FSV) Delay time, I2S_CLK low to I2S_FS valid (CLKPOL = 0) -2 7 -2 5 – – ns
5
tdmax(CLKH-FSV) Delay time, I2S_CLK high to I2S_FS valid (CLKPOL = 1) -2 7 -2 5 – – ns

TMS320C5517
1 3 2
I2S_CLK
(CLKPOL = 0)
I2S_CLK
(CLKPOL = 1)
I2S_FS
(Output, MODE = 1)
9 10
I2S_FS
(Input, MODE = 0)
I2S_DX
7 8
I2S_RX
Figure 5-31. I2S Input and Output Timings

TMS320C5517
5.7.10 Multichannel Serial Port Interface (McSPI)

The multichannel SPI (McSPI) is a master and slave synchronous serial bus. McSPI allows a duplex,
synchronous, serial communication to SPI-compliant external devices (slaves and masters).
The McSPI instances include the following main features:
• Serial clock with programmable frequency, polarity, and phase for each channel
• Wide selection of SPI word lengths ranging from 4 to 32 bits
• Up to three master channels or single channel in slave mode
• Master multichannel mode:
– Full duplex and half duplex
– Transmit-only and receive-only and transmit-and-receive modes
– Flexible I/O port controls per channel
– Two direct memory access (DMA) requests (read and write) per channel
• Single interrupt line for multiple interrupt source events
• Power management through wake-up capabilities
• Enable the addition of a programmable start-bit for SPI transfer per channel (start-bit mode)
• Support start-bit write command
• 128-bytes built-in FIFO available for a single channel
• Force CS mode for continuous transfers
5.7.10.1 McSPI Electrical Data and Timing

The multichannel SPI is a master and slave synchronous serial bus.
The following tables assume testing over the recommended operating conditions.
5.7.10.1.1 McSPI in Slave Mode
Table 5-38. McSPI Interface Timing Requirements – Slave Mode

NO. CVDD = 1.05 V CVDD = 1.3/1.4 V UNIT
MIN MAX MIN MAX
SS2 tsu(SIMOV-CLKAE) Setup time, McSPI_SIMO valid before McSPI_CLK 4 3 ns
active edge
SS3 th(SIMOV-CLKAE) Hold time, McSPI_SIMO valid after McSPI_CLK 3.8 2.8 ns
active edge
SS4 tsu(CS0V-CLKFE) Setup time, McSPI_CS0 valid before McSPI_CLK 6.9 6.9 ns
first edge
SS5 th(CS0I-CLKLE) Hold time, McSPI_CS0 invalid after McSPI_CLK last 6.9 6.9 ns
edge

TMS320C5517
Table 5-39. McSPI Interface Switching Characteristics — Slave Mode [I/O = 3.3 V]
NO. PARAMETER CVDD = 1.05 V CVDD = 1.3/1.4 V UNIT
MIN MAX MIN MAX
SS0 Clock period 14 22 MHz
SS1 tw(CLK) Pulse duration, McSPI_CLK high or low 0.45*P (1) 0.55*P (1) 0.45*P (1) 0.55*P (1) ns
SS6 Output Delay time, McSPI_CLK active edge to 0 31 0 19 ns
McSPI_SOMI valid
SS7 Delay time, McSPI_CSn active edge to McSPIn_SOMI 15 8.7 ns
shifted, Mode 0
SS7 Delay time, McSPI_CSn active edge to McSPIn_SOMI 15 8.7 ns
shifted, Mode 2
(1) P = McSPI_CLK clock period.
MIN MAX MIN MAX
(1) (1) (1) (1)
SS1 tw(CLK) Pulse duration, McSPI_CLK high or low 0.45*P 0.55*P 0.45*P 0.55*P ns
SS6 Output Delay time, McSPI_CLK active edge to 0 36 0 22.5 ns
McSPI_SOMI valid
SS7 Delay time, McSPI_CSn active edge to Modes 0 and 2 15 12 ns
McSPIn_SOMI shifted
MIN MAX MIN MAX
SS1 tw(CLK) Pulse duration, McSPI_CLK high or low 0.45*P (1) 0.55*P (1) 0.45*P (1) 0.55*P (1) ns
SS6 Output Delay time, McSPI_CLK active edge to 0 36 0 24 ns
McSPI_SOMI valid
SS7 Delay time, McSPI_CSn active edge to Modes 0 and 2 17 15 ns
McSPIn_SOMI shifted

TMS320C5517
Mode 0 and 2
McSPI_CS0(EPOL=1)
SS0
SS4 SS1 SS5
McSPI_CLK(POL=0)
SS0
SS1
McSPI_CLK(POL=1)
SS2
SS3
McSPI_SIMO Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0
SS7 SS6
McSPI_SOMI Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0
Mode 1 and 3
McSPI_CS0(EPOL=1)
SS0
SS1
McSPI_CLK(POL=0)
SS0
SS4 SS1 SS5
McSPI_CLK(POL=1)
SS3
SS2
McSPI_SIMO Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0
SS6
McSPI_SOMI Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0
Figure 5-32. McSPI Interface — Transmit and Receive in Slave Mode

TMS320C5517
5.7.10.1.2 McSPI in Master Mode
The following tables assume testing over the recommended operating conditions (see Figure 5-33).
Table 5-42. McSPI Interface Timing Requirements – Master Mode [I/O = 3.3, 2.75 V]
MIN MAX MIN MAX
SM2 Setup time, McSPI_SOMI valid before McSPI_CLK 4 3 ns
active edge
SM3 Hold time, McSPI_SOMI valid after McSPI_CLK active 3.8 2.8 ns
edge
Table 5-43. McSPI Interface Timing Requirements – Master Mode [I/O = 1.8 V]
MIN MAX MIN MAX
SM2 Setup time, McSPI_SOMI valid before McSPI_CLK 7.5 3 ns
active edge
SM3 Hold time, McSPI_SOMI valid after McSPI_CLK active 3.8 2.8 ns
edge
Table 5-44. McSPI Interface Switching Characteristics – Master Mode [I/O = 3.3 V]
MIN MAX MIN MAX
SM0 Clock period 22 42 MHz
(1) (1) (1) (1)
SM1 Pulse duration, McSPI_CLK high or low 0.45*P 0.55*P 0.45*P 0.55*P ns
SM4 Delay time, McSPI_CLK active edge to 0 18 -1 8.9 ns
McSPI_SIMO valid
SM5 Delay time, McSPI_CSx active to Modes 3.1 3.1 ns
McSPI_CLK first edge 0–3
SM6 Delay time, McSPI_CLK last edge to Modes 3.1 3.1 ns
McSPI_CSx inactive 0–3
SM7 Delay time, McSPI_CSx active edge to Modes 0 10 6 ns
McSPI_SIMO shifted and 2
(1) P = McSPI_CLK clock period

TMS320C5517
MIN MAX MIN MAX
SM1 Pulse duration, McSPI_CLK high or low 0.45*P (1) 0.55*P (1) 0.45*P (1) 0.55*P (1) ns
SM4 Delay time, McSPI_CLK active edge to McSPI_SIMO 0 18 -1 10 ns
valid
SM5 Delay time, McSPI_CSx active to Modes 0–3 3.1 3.1 ns
McSPI_CLK first edge
SM6 Delay time, McSPI_CLK last edge to Modes 0–3 3.1 3.1 ns
McSPI_CSx inactive
MIN MAX MIN MAX
SM1 Pulse duration, McSPI_CLK high or low 0.45*P (1) 0.55*P (1) 0.45*P (1) 0.55*P (1) ns
SM4 Delay time, McSPI_CLK active edge to 0 18.5 -1 10 ns
McSPI_SIMO valid
SM5 Delay time, McSPI_CSx active to Modes 0–3 2.75 3 ns
McSPI_CLK first edge
SM6 Delay time, McSPI_CLK last edge to Modes 0–3 2.75 3 ns
McSPI_CSx inactive

TMS320C5517
Mode 0 and 2
McSPI_CSx(EPOL=1)
SM0
SM5 SM1 SM6
McSPI_CLK(POL=0)
SM0
SM1
McSPI_CLK(POL=1)
SM7 SM4
McSPI_SIMO Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0
SM2
SM3
McSPI_SOMI Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0
Mode 1 and 3
McSPI_CSx(EPOL=1)
SM0
SM1
McSPI_CLK(POL=0)
SM0
SM5 SM1 SM6
McSPI_CLK(POL=1)
SM4
McSPI_SIMO Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0
SM2
SM3
McSPI_SOMI Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0
Figure 5-33. McSPI Interface — Transmit and Receive in Master Mode

TMS320C5517
5.7.11 Multichannel Buffered Serial Port (McBSP)

The McBSP provides these functions:
• Full-duplex communication
• Double-buffered data registers, which allow a continuous data stream
• Independent framing and clocking for receive and transmit
• Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially
connected analog-to-digital (A/D) and digital-to-analog (D/A) devices
• External shift clock or an internal, programmable frequency shift clock for data transfer
• Transmit and Receive FIFO Buffers allow the McBSP to operate at a higher sample rate by making it
more tolerant to DMA latency
If the internal clock is used, the CLKGDV field of the Sample Rate Generator Register (SRGR) must
always be set to a value of 3 or greater.
5.7.11.1 McBSP Electrical Data and Timing
Table 5-47. Timing Requirements for McBSP, DVDDIO 1.8 V (see Figure 5-34)
CVDD = 1.05 V CVDD = 1.3/1.4 V
NO. DVDDIO 1.8 V UNIT
MIN MAX MIN MAX
2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 15 9 ns
Pulse duration, CLKR/X high or CLKR/X (1) (1)
3 tw(CKRX) CLKR/X ext P-1 P-1 ns
low
Setup time, external FSR high before CLKR int 29.5 29.5
5 tsu(FRH-CKRL) ns
CLKR low CLKR ext 3.5 3.5
Hold time, external FSR high after CLKR CLKR int 4.5 4.5
6 th(CKRL-FRH) ns
low CLKR ext 4.5 4.5
CLKR int 18.5 18.5
7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low ns
CLKR ext 2.5 2.5
CLKR int -4 -4
8 th(CKRL-DRV) Hold time, DR valid after CLKR low ns
CLKR ext 5.5 5.5
Setup time, external FSX high before CLKX int 26.5 26.5
10 tsu(FXH-CKXL) ns
CLKX low CLKX ext 7.5 7.5
Hold time, external FSX high after CLKX CLKX int 0.5 0.5
11 th(CKXL-FXH) ns
low CLKX ext 2.5 2.5
(1) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.

TMS320C5517
Table 5-48. Timing Requirements for McBSP,

DVDDIO 3.3/2.75 V (see Figure 5-34)
CVDD = 1.05 V CVDD = 1.3/1.4 V
NO. DVDDIO 3.3/2.75 V UNIT
MIN MAX MIN MAX
2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 18 9 ns
Pulse duration, CLKR/X high or CLKR/X
3 tw(CKRX) CLKR/X ext P-1 (1) P-1 (1) ns
low
Setup time, external FSR high before CLKR int 24 24
5 tsu(FRH-CKRL) ns
CLKR low CLKR ext 4 4
Hold time, external FSR high after CLKR CLKR int 4 4
6 th(CKRL-FRH) ns
low CLKR ext 5 5
CLKR int 22.5 22.5
7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low ns
CLKR ext 2.5 2.5
CLKR int -3 -3
8 th(CKRL-DRV) Hold time, DR valid after CLKR low ns
CLKR ext 6 6
Setup time, external FSX high before CLKX int 23 23
10 tsu(FXH-CKXL) ns
CLKX low CLKX ext 7 7
Hold time, external FSX high after CLKX CLKX int 2 2
11 th(CKXL-FXH) ns
low CLKX ext 3 3
(1) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.

TMS320C5517
Table 5-49. Switching Characteristics Over Recommended Operating Conditions for McBSP,
DVDDIO 1.8 V
(see Figure 5-34)
CVDD = 1.05 V CVDD = 1.3/1.4 V
NO. PARAMETER DVDDIO 1.8 V UNIT
MIN MAX MIN MAX
Delay time, CLKS high to CLKR/X high for internal
1 td(CKSH-CKRXH) 5.5 25 5.5 25 ns
CLKR/X generated from CLKS input
2 tc(CKRX) Cycle time, CLKR/X CLKR/X int 15 9 ns
Pulse duration, CLKR/X high or
3 tw(CKRX) CLKR/X int C+2 (1) C+2 (1) ns
CLKR/X low
Delay time, CLKR high to internal
4 td(CKRH-FRV) CLKR int -6.5 6 -6.5 6 ns
FSR valid
Delay time, CLKX high to internal CLKX int -2 1 -2 1
9 td(CKXH-FXV) ns
FSX valid CLKX ext 4 23 4 23
Disable time, DX high impedance CLKX int -5 3 -5 3
12 tdis(CKXH-DXHZ) ns
following last data bit from CLKX high CLKX ext 3 24.5 3 24.5
CLKX int -4.5 4 -4.5 4
13 td(CKXH-DXV) Delay time, CLKX high to DX valid ns
CLKX ext 3.5 25.5 3.5 25.5
Delay time, FSX high to DX valid FSX int -4 4 -4 4
14 td(FXH-DXV) ONLY applies when in data ns
FSX ext -2 3 -2 3
delay 0 (XDATDLY = 00b) mode
(1) C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = SYSCLK period)
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse duration = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse duration = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above).

TMS320C5517
Table 5-50. Switching Characteristics Over Recommended Operating Conditions for McBSP,
DVDDIO 3.3/2.75 V
(see Figure 5-34)
CVDD = 1.05 V CVDD = 1.3/1.4 V
NO. PARAMETER DVDDIO 3.3/2.75 V UNIT
MIN MAX MIN MAX
Delay time, CLKS high to CLKR/X high for internal
1 td(CKSH-CKRXH) 4.25 24 4.5 24 ns
CLKR/X generated from CLKS input
2 tc(CKRX) Cycle time, CLKR/X CLKR/X int 18 9 ns
Pulse duration, CLKR/X high or
3 tw(CKRX) CLKR/X int C-2 (1) C-2 (1) ns
CLKR/X low
Delay time, CLKR high to internal
4 td(CKRH-FRV) CLKR int -4 8 -4 8 ns
FSR valid
Delay time, CLKX high to internal CLKX int -2 2 -2 2
9 td(CKXH-FXV) ns
FSX valid CLKX ext 3.5 20 3.5 20
Disable time, DX high impedance CLKX int -2.5 4 -2.5 4
12 tdis(CKXH-DXHZ) ns
following last data bit from CLKX high CLKX ext 3 21 -3 21
CLKX int -2.5 5 -2.5 5
13 td(CKXH-DXV) Delay time, CLKX high to DX valid ns
CLKX ext 3 22.5 3 22.5
Delay time, FSX high to DX valid FSX int -1.5 4 -1.5 4
14 td(FXH-DXV) ONLY applies when in data ns
FSX ext -1.5 3.5 -1.5 3.5
delay 0 (XDATDLY = 00b) mode
(1) C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = SYSCLK period)
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse duration = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse duration = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above).

TMS320C5517
CLKS
1
2
3
3
CLKR
4
4
FSR (int)
5
6
FSR (ext)
7
8
DR Bit(n-1) (n-2) (n-3)
2
3
3
CLKX
9
FSX (int)
11
10
FSX (ext)
FSX (XDATDLY=00b)
14 13 (A)
12 13 (A)
DX Bit 0 Bit(n-1) (n-2) (n-3)
A. Parameter No. 13 applies to the first data bit only when XDATDLY ≠ 0.
B. McBSP_CLKS and McBSP_CLKR are shared on the same pin. See Table 4-7, Multichannel Buffered Serial Ports
(McBSP) Signal Descriptions, for how each is selected.
Figure 5-34. McBSP Timing
Table 5-51. Timing Requirements for FSR When GSYNC = 1 (see Figure 5-35)
CVDD = 1.05 V CVDD = 1.3/1.4 V
NO. DVDDIO 3.3/2.75/1.8 V UNIT
MIN MAX MIN MAX
1 tsu(FRH-CKSH) Setup time, FSR high before CLKS high 5 5 ns
2 th(CKSH-FRH) Hold time, FSR high after CLKS high 4 4 ns
CLKS
1
2
FSR external
CLKR/X (no need to resync)
CLKR/X (needs resync)
Figure 5-35. FSR Timing When GSYNC = 1

TMS320C5517
5.7.12 Multimedia Card and Secure Digital (eMMC, MMC, SD, and SDHC)
The device includes two MMC and SD controllers which are compliant with eMMC V4.3, MMC V3.31,
Secure Digital Part 1 Physical Layer Specification V2.0, and Secure Digital Input Output (SDIO) V2.0
specifications. The MMC and SD card controller supports these industry standards and assumes the
reader is familiar with these standards.
Each MMC and SD Controller in the device has the following features:
• Multimedia Card and Secure Digital (eMMC, MMC, SD, and SDHC) protocol support
• Programmable clock frequency
• 256-bit Read and Write FIFO to lower system overhead
• Slave DMA transfer capability
The MMC and SD card controller transfers data between the CPU and DMA controller on one side and
MMC and SD card on the other side. The CPU and DMA controller can read and write the data in the card
by accessing the registers in the MMC and SD controller.
The MMC and SD controller on this device, does not support the SPI mode of operation.

TMS320C5517
5.7.12.1 MMC and SD Electrical Data and Timing
Table 5-52. Timing Requirements for MMC and SD (see Figure 5-36 and Figure 5-39)
CVDD = 1.3/1.4 V CVDD = 1.05 V
NO
FAST MODE STD MODE UNIT
.
MIN MAX MIN MAX
1 tsu(CMDV-CLKH) Setup time, MMCx_CMD data input valid before MMCx_CLK high 3 3 ns
2 th(CLKH-CMDV) Hold time, MMCx_CMD data input valid after MMCx_CLK high 3 3 ns
3 tsu(DATV-CLKH) Setup time, MMC_Dx data input valid before MMCx_CLK high 3 3.1 ns
4 th(CLKH-DATV) Hold time, MMC_Dx data input valid after MMCx_CLK high 3 3 ns
Table 5-53. Switching Characteristics Over Recommended Operating Conditions for MMC Output (1) (see
Figure 5-36 and Figure 5-39)
CVDD = 1.3/1.4 V CVDD = 1.05 V
NO
PARAMETER FAST MODE STD MODE UNIT
.
MIN MAX MIN MAX
7 f(CLK) Operating frequency, MMCx_CLK 0 50 (2) 0 25 (2) MHz
8 f(CLK_ID) Identification mode frequency, MMCx_CLK 0 400 0 400 kHz
9 tw(CLKL) Pulse duration, MMCx_CLK low 7 10 ns
10 tw(CLKH) Pulse duration, MMCx_CLK high 7 10 ns
11 tr(CLK) Rise time, MMCx_CLK 3 3 ns
12 tf(CLK) Fall time, MMCx_CLK 3 3 ns
13 td(MDCLKL-CMDIV) Delay time, MMCx_CLK low to MMC_CMD data output invalid -4.53 -4.77 ns
14 td(MDCLKL-CMDV) Delay time, MMCx_CLK low to MMC_CMD data output valid 4.1 5.4 ns
15 td(MDCLKL-DATIV) Delay time, MMCx_CLK low to MMC_Dx data output invalid -4.53 -4.77 ns
16 td(MDCLKL-DATV) Delay time, MMCx_CLK low to MMC_Dx data output valid 4.1 5.4 ns
(1) For MMC and SD, the parametric values are measured at DVDDIO = 3.3 V and 2.75 V.
(2) Use this value or SYS_CLK/2 whichever is smaller.
7 9 10
MMCx_CLK
14 13
MMCx_CMD VALID
Figure 5-36. MMC and SD Host Command Write Timing
9
7 10
MMCx_CLK
4 4
3 3
MMCx_Dx Start D0 D1 Dx End
Figure 5-37. MMC and SD Card Response Timing

TMS320C5517
9
7 10
MMCx_CLK
1
2
MMCx_CMD START XMIT Valid Valid Valid END
Figure 5-38. MMC and SD Host Write Timing
7 9 10
MMCx_CLK
16 15
MMCx_DAT VALID
Figure 5-39. MMC and SD Data Write Timing

TMS320C5517
5.7.13 Real-Time Clock (RTC)

The device includes a Real-Time Clock (RTC) with its own separate power supply and isolation circuits.
The RTC has the capability to wake up the device from idle states via alarms, periodic interrupts, or an
external WAKEUP input.
To prevent unintentional access to the RTC registers, gate-keeper registers must be programmed with a
specific signature—0x95A4_F1E0—before changing the RTC registers.
Note: The RTC Core (CVDDRTC) must be powered by an external power source even though RTC is not
used. None of the on-chip LDOs can power CVDDRTC.
The device RTC provides the following features:
• 100-year calendar up to year 2099.
• Counts milliseconds, seconds, minutes, hours, day of the week, date, month, and year with leap year
compensation
• Millisecond time correction
• Binary-coded-decimal (BCD) representation of time, calendar, and alarm
• 24-hour clock mode
• Second, minute, hour, or day alarm interrupt
• Periodic interrupt: every millisecond, second, minute, hour, or day
• Alarm interrupt: precise time of day
• Single interrupt to the DSP CPU
• 32.768-kHz crystal oscillator with frequency calibration
• Bidirectional IO pin that can be set up as:
– Input for an external device to wake up the DSP
– Output to wake up an external device
Control of the RTC is maintained through a set of I/O memory mapped registers (see Table 6-19). Note
that any write to these registers will be synchronized to the RTC 32.768-kHz clock; thus, the CPU must
run at least 3X faster than the RTC. Writes to these registers will not be evident until the next two 32.768-
kHz clock cycles later.
Furthermore, three conditions must be met to write to the RTC registers:
1. The RTC oscillator must be enabled.
2. A 1 must be written to the RTC system control register (RSCR) to bring the RTC out of isolation.
3. The gate-keeper registers (RGKR_LSW and RGKR_MSW) must contain the key 0x95A4_F1E0.
If these conditions are not met, the RTC remains isolated and protected from power glitches.
For more information, see the Static Power Management section of the TMS320C5517 Digital Signal
Processor Technical Reference Manual [literature number SPRUH16].
The RTC has its own power-on-reset (POR) circuit which resets the registers in the RTC core domain
when power is first applied to the CVDDRTC power pin. The RTC flops are not reset by the device's RESET
pin nor the digital core's POR (powergood signal).
The scratch registers in the RTC can be used to take advantage of this unique reset domain to keep track
of when the DSP boots and whether the RTC time registers have already been initialized to the current
clock time or whether the software needs to go into a routine to prompt the user to set the time and date.
5.7.13.1 RTC Electrical Data and Timing

For more detailed information on RTC electrical timings, specifically WAKEUP, see Section 5.7.3.3, Reset
Electrical Data and Timing.

TMS320C5517
5.7.14 SAR ADC (10-Bit)

The device includes a 10-bit SAR ADC using a switched capacitor architecture which converts an analog
input signal to a digital value at a maximum rate of 62.5-k samples per second (ksps) for use by the DSP.
This SAR module supports six channels that are connected to four general purpose analog pins (GPAIN
[3:0]) which can be used as general purpose outputs.
The device SAR supports the following features:
• Up to 62.5 ksps (2-MHz clock with 32 cycles per conversion)
• Single conversion and continuous back-to-back conversion modes
• Interrupt driven or polling conversion or DMA event generation
• Internal configurable bandgap reference voltages of 1 V or 0.8 V; or external Vref of VDDA_ANA
• One 3.6-V Tolerant analog input (GPAIN0) with internal voltage division for conversion of battery
voltage
• Software controlled power down
• Individually configurable general-purpose digital outputs
5.7.14.1 SAR ADC Electrical Data and Timing
Table 5-54. Switching Characteristics Over Recommended Operating Conditions for ADC Characteristics
CVDD = 1.4 V
CVDD = 1.3 V
MIN TYP MAX
1 tC(SCLC) Cycle time, ADC internal conversion clock 2 MHz
3 td(CONV) Delay time, ADC conversion time 32tC(SCLC) ns
4 SDNL Static differential non-linearity error (DNL measured for 9 bits) ±0.6 LSB
5 SINL Static integral non-linearity error ±1 LSB
6 Zset Zero-scale offset error (INL measured for 9 bits) 2 LSB
7 Fset Full-scale offset error 2 LSB
8 Analog input impedance 1 MΩ
9 Signal-to-noise ratio 54 dB

TMS320C5517
5.7.15 Serial Port Interface (SPI)

The device serial port interface (SPI) is a high-speed synchronous serial input/output port that allows a
serial bit stream of programmed length (1 to 32 bits) to be shifted into and out of the device at a
programmed bit-transfer rate. The SPI supports multi-chip operation of up to four SPI slave devices. The
SPI can operate as a master device only, slave mode is not supported. Note: The SPI is not supported by
the device DMA controller, so DMA cannot be used in transferring data between the SPI and the on-chip
RAM.
The SPI is normally used for communication between the DSP and external peripherals. Typical
applications include an interface to external I/O or peripheral expansion via devices such as shift registers,
display drivers, SPI EEPROMs, and analog-to-digital converters.
The SPI has the following features:
• Programmable divider for serial data clock generation
• Four pin interface (SPI_CLK, SPI_CSn, SPI_RX, and SPI_TX)
• Programmable data length (1 to 32 bits)
• 4 external chip select signals
• Programmable transfer or frame size (1 to 4096 characters)
• Optional interrupt generation on character completion
• Optional interrupt generation on frame completion
• Programmable SPI_CSn to SPI_TX delay from 0 to 3 SPI_CLK cycles
• Programmable signal polarities
• Programmable active clock edge
• Internal loopback mode for testing
5.7.15.1 SPI Electrical Data and Timing
Table 5-55. Timing Requirements for SPI Inputs (see Figure 5-40 through Figure 5-43)
CVDD = 1.3/1.4
CVDD = 1.05 V
NO. V UNIT
MIN MAX MIN MAX
4 tC(SCLK) Cycle time, SPI_CLK 4P (1) (2) 4P (1) (2) ns
5 tw(SCLKH) Pulse duration, SPI_CLK high 30 19 ns
6 tw(SCLKL) Pulse duration, SPI_CLK low 30 19 ns
tsu(SRXV- Setup time, SPI_RX valid before SPI_CLK high Modes 0, 2, and 3 16.1 13.9 ns
7
SCLK) Setup time, SPI_RX valid before SPI_CLK low Mode 1 16.1 13.9 ns
Hold time, SPI_RX valid after SPI_CLK high Modes 0 and 3 0 0 ns
8 th(SCLK-SRXV)
Hold time, SPI_RX valid after SPI_CLK low Modes 1 and 2 0 0 ns

TMS320C5517
Table 5-56. Switching Characteristics Over Recommended Operating Conditions for SPI Outputs [I/O =
2.75 and 3.3 V]
(see Figure 5-40 through Figure 5-43)
NO CVDD = 1.05 V CVDD = 1.3/1.4 V UNI
PARAMETER
. MIN MAX MIN MAX T
Delay time, SPI_CLK low to SPI_TX valid Modes 0 and 3 -4.2 8.9 -4.9 5.3 ns
1 td(SCLK-STXV)
Delay time, SPI_CLK high to SPI_TX valid Modes 1 and 2 -4.2 8.9 -4.9 5.3 ns
tc - 8 + tc - 8 +
2 td(SPICS-SCLK) Delay time, SPI_CS active to SPI_CLK active ns
D (1) D (1)
toh(SCLKI- 0.5tc - 0.5tc -
3 Output hold time, SPI_CS inactive to SPI_CLK inactive ns
SPICSI) 1.9 1.9
(1) D is the programable data delay in ns. Data delay can be programmed to 0, 1, 2, or 3 SPICLK clock cycles.
Table 5-57. Switching Characteristics Over Recommended Operating Conditions for SPI Outputs [I/O =
1.8 V]
(see Figure 5-40 through Figure 5-43)
NO CVDD = 1.05 V CVDD = 1.3/1.4 V UNI
PARAMETER
. MIN MAX MIN MAX T
Delay time, SPI_CLK low to SPI_TX valid Modes 0 and 3 -6.7 8.9 -6.7 5.8 ns
1 td(SCLK-STXV)
Delay time, SPI_CLK high to SPI_TX valid Modes 1 and 2 -6.7 8.9 -6.7 5.8 ns
tc - 9.2 + tc - 8 +
2 td(SPICS-SCLK) Delay time, SPI_CS active to SPI_CLK active ns
D (1) D (1)
toh(SCLKI- 0.5tc - 0.5tc -
3 Output hold time, SPI_CS inactive to SPI_CLK inactive ns
SPICSI) 1.9 1.9
(1) D is the programable data delay in ns. Data delay can be programmed to 0, 1, 2, or 3 SPICLK clock cycles.
4
5 6
SPI_CLK
1
SPI_TX B0 B1 Bn-2 Bn-1
SPI_RX B0 B1 Bn-2 Bn-1

2 7 8 3
SPI_CS
A. Character length is programmable between 1 and 32 bits; 8-bit character length shown.
B. Polarity of SPI_CSn is configurable, active-low polarity is shown.
Figure 5-40. SPI Mode 0 Transfer (CKPn = 0, CKPHn = 0)
4
5 6
SPI_CLK
1

2 7 8 3
SPI_CS

TMS320C5517
4
6 5
SPI_CLK
1

2 7 8 3
SPI_CS
4
6 5
SPI_CLK
1

2 7 8 3
SPI_CS

TMS320C5517
5.7.16 Timers
The device has three 32-bit software programmable Timers. Each timer can be used as a general-
purpose (GP) timer. Timer2 can be configured as either a GP or a Watchdog (WD) or both. General-
purpose timers are typically used to provide interrupts to the CPU to schedule periodic tasks or a delayed
task. A watchdog timer is used to reset the CPU in case it gets into an infinite loop. The GP timers are 32-
bit timers with a 13-bit prescaler that can divide the CPU clock and uses this scaled value as a reference
clock. These timers can be used to generate periodic interrupts. The Watchdog Timer is a 16-bit counter
with a 16-bit prescaler used to provide a recovery mechanism for the device in the event of a fault
condition, such as a non-exiting code loop.
The device Timers support the following:
• 32-bit Programmable Countdown Timer
• 13-bit Prescaler Divider
• Timer Modes:
– 32-bit General-Purpose Timer
– 32-bit Watchdog Timer (Timer2 only)
• Auto Reload Option
• Generates a single interrupt to the CPU, which can be configured as a timer interrupt (TINT) or as a
non-maskable interrupt (NMI). The interrupt is individually latched to determine which timer triggered
the interrupt.
• Generates an active low pulse to the hardware reset (Watchdog only)
• Interrupt can be used for DMA Event

TMS320C5517
5.7.17 Universal Asynchronous Receiver and Transmitter (UART)

The UART performs serial-to-parallel conversions on data received from an external peripheral device and
parallel-to-serial conversions on data transmitted to an external peripheral device via a serial bus.
The device has one UART peripheral with the following features:
• Programmable baud rates (frequency pre-scale values from 1 to 65535)
• Fully programmable serial interface characteristics:
– 5, 6, 7, or 8-bit characters
– Even, odd, or no PARITY bit generation and detection
– 1, 1.5, or 2 STOP bit generation
• 16-byte depth transmitter and receiver FIFOs:
– The UART can be operated with or without the FIFOs
– 1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA
• DMA signaling capability for both received and transmitted data
• CPU interrupt capability for both received and transmitted data
• False START bit detection
• Line break generation and detection
• Internal diagnostic capabilities:
– Loopback controls for communications link fault isolation
– Break, parity, overrun, and framing error simulation
• Programmable autoflow control using CTS and RTS signals
5.7.17.1 UART Electrical Data and Timing [Receive and Transmit]
Table 5-58. Timing Requirements for UART Receive (1) (2) (see Figure 5-44)
CVDD = 1.05/1.3/1.4 V
NO. UNIT
MIN MAX
4 tw(URXDB) Pulse duration, receive data bit (UART_RXD) [15/30 pF] U - 3.5 U+3 ns
5 tw(URXSB) Pulse duration, receive start bit [15/30 pF] U - 3.5 U+3 ns
(1) U = UART baud time = 1/programmed baud rate.
(2) These parametric values are measured at DVDDIO = 3.3 V, 2.75 V, and 1.8 V.
Table 5-59. Switching Characteristics Over Recommended Operating Conditions

for UART Transmit (1) (2)
(see Figure 5-44)
CVDD = 1.05/1.3/1.4 V
NO. PARAMETER UNIT
MIN MAX
1 f(baud) Maximum programmable bit rate fmax/16 MHz
2 tw(UTXDB) Pulse duration, transmit data bit (UART_TXD) [15/30 pF] U - 3.5 U+4 ns
3 tw(UTXSB) Pulse duration, transmit start bit [15/30 pF] U - 3.5 U+4 ns
(1) U = UART baud time = 1/programmed baud rate.
(2) These parametric values are measured at DVDDIO = 3.3 V, 2.75 V, and 1.8 V.

TMS320C5517
3
2
Start
UART_TXD Bit
Data Bits
5
4
Start
UART_RXD Bit
Data Bits
Figure 5-44. UART Transmit and Receive Timing

TMS320C5517
5.7.18 Universal Host-Port Interface (UHPI)

The device includes a user-configurable 16-bit universal host-port interface (UHPI16). The UHPI provides
a parallel port interface through which an external host processor can directly access the processor's
resources (configuration and program and data memories). The external host device is asynchronous to
the CPU clock and functions as a master to the UHPI interface. The UHPI enables a host device and the
processor to exchange information via internal memory. Dedicated address (UHPIA) and data (UHPID)
registers within the UHPI provide the data path between the external host interface and the processor
resources. A UHPI control register (UHPIC) is available to the host and the CPU for various configuration
and interrupt functions.
5.7.18.1 UHPI Electrical Data and Timing
Table 5-60. Timing Requirements for Host-Port Interface, DVDDIO = 3.3/2.75 V

DVDDIO = 3.3/2.75 V
MIN MAX MIN MAX
1 tsu(SELV-HSTBL) Setup time, select signals (1) valid before HSTROBE low 6.5 5 ns
2 th(HSTBL-SELV) Hold time, select signals (1) valid after HSTROBE low 3 2 ns
3 tw(HSTBL) Pulse duration, HSTROBE active low 19 17 ns
Pulse duration, HSTROBE inactive high between consecutive (2) (2)
4 tw(HSTBH) 2P 2P ns
accesses
11 tsu(HDV-HSTBH) Setup time, host data valid before HSTROBE high 7.8 5 ns
12 th(HSTBH-HDV) Hold time, host data valid after HSTROBE high 3.3 2.5 ns
Hold time, HSTROBE high after UHPI_HRDY high. HSTROBE
13 th(HRDYL-HSTBH) should not be inactivated until UHPI_HRDY is active (high); 2 2 ns
otherwise, UHPI writes will not complete properly.
(1) Select signals include: UHPI_HCNTL[1:0], UHPI_HR_NW and UHPI_HHWIL.
(2) P = SYSCLK period in ns. For example, when the CPU core is clocked at 200 MHz, P = 5 ns.
Table 5-61. Timing Requirements for Host-Port Interface, DVDDIO = 1.8 V

DVDDIO = 1.8 V
MIN MAX MIN MAX
1 tsu(SELV-HSTBL) Setup time, select signals (1) valid before HSTROBE low 7.3 5 ns
2 th(HSTBL-SELV) Hold time, select signals (1) valid after HSTROBE low 3 2 ns
3 tw(HSTBL) Pulse duration, HSTROBE active low 24 19 ns
Pulse duration, HSTROBE inactive high between consecutive
4 tw(HSTBH) 2P (2) 2P (2) ns
accesses
11 tsu(HDV-HSTBH) Setup time, host data valid before HSTROBE high 8.6 5 ns
12 th(HSTBH-HDV) Hold time, host data valid after HSTROBE high 3.3 2.5 ns
Hold time, HSTROBE high after UHPI_HRDY high. HSTROBE
13 th(HRDYL-HSTBH) should not be inactivated until UHPI_HRDY is active (high); 2 2 ns
otherwise, UHPI writes will not complete properly.
(1) Select signals include: UHPI_HCNTL[1:0], UHPI_HR_NW and UHPI_HHWIL.
(2) P = SYSCLK period in ns. For example, when the CPU core is clocked at 200 MHz, P = 5 ns.

TMS320C5517
Table 5-62. Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface,
DVDDIO = 3.3/2.75 V
DVDDIO = 3.3/2.75 V
CVDD = 1.05 CVDD =
NO. PARAMETER UNIT
V 1.3/1.4 V
MIN MAX MIN MAX
For UHPI Write, UHPI_HRDY can go
low (not ready) for these UHPI Write
conditions; otherwise, UHPI_HRDY
stays high (ready):
Case 1: Back-to-back HPIA writes (can
be either first or second half-word)
Case 2: HPIA write following a
PREFETCH command (can be either
first or second half-word)
Case 3: HPID write when FIFO is full or
flushing (can be either first or second
half-word)
Case 4: HPIA write and Write FIFO not
empty
For UHPI Read, UHPI_HRDY can go
low (not ready) for these UHPI Read
conditions:
Delay time, HSTROBE low to Case 1: UHPID read (with auto-
5 td(HSTBL-HRDYV) 0 22.3 0 15.5 ns
UHPI_HRDY valid increment) and data not in Read FIFO
(can only happen to first half-word of
HPID access)
Case 2: First half-word access of HPID
Read without auto-increment
For UHPI Read, UHPI_HRDY stays
high (ready) for these UHPI Read
conditions:
Case 1: HPID read with auto-increment
and data is already in Read FIFO
(applies to either half-word of HPID
access)
Case 2: HPID read without auto-
increment and data is already in Read
FIFO (always applies to second half-
word of HPID access)
Case 3: HPIC or HPIA read (applies to
either half-word access)
6 ten(HSTBL-HDLZ) Enable time, UHPI_HD driven from HSTROBE low 1.5 1.5 ns
7 td(HRDYL-HDV) Delay time, UHPI_HRDY high to HD valid 0 1.1 ns
8 toh(HSTBH-HDV) Output hold time, UHPI_HD valid after HSTROBE high 1.5 1.5 ns
14 tdis(HSTBH-HDHZ) Disable time, HD high-impedance from HSTROBE high 24.3 15.8 ns
For UHPI Read. Applies to conditions
where data is already residing in
HPID/FIFO:
Case 1: HPIC or HPIA read
Delay time, HSTROBE low to
15 td(HSTBL-HDV) Case 2: First half-word of HPID read 24.3 15.8 ns
HD valid
with auto-increment and data is already
in Read FIFO
Case 3: Second half-word of HPID
read with or without auto-increment
stays high (ready):
Case 1: HPID write when Write FIFO is
Delay time, HSTROBE high to
18 td(HSTBH-HRDYV) full (can happen to either half-word) 24.3 15.8 ns
UHPI_HRDY valid
Case 2: HPIA write (can happen to
either half-word)
Case 3: HPID write without auto-
increment (only happens to second
half-word)

TMS320C5517
Table 5-63. Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface,
DVDDIO = 1.8 V
DVDDIO = 1.8 V
CVDD = 1.05 CVDD =
NO. PARAMETER UNIT
V 1.3/1.4 V
MIN MAX MIN MAX
stays high (ready):
Case 1: Back-to-back HPIA writes (can
be either first or second half-word)
Case 2: HPIA write following a
PREFETCH command (can be either
first or second half-word)
Case 3: HPID write when FIFO is full or
flushing (can be either first or second
half-word)
Case 4: HPIA write and Write FIFO not
empty
For UHPI Read, UHPI_HRDY can go
low (not ready) for these UHPI Read
conditions:
Delay time, HSTROBE low to Case 1: UHPID read (with auto-
5 td(HSTBL-HRDYV) 0 26.5 0 19 ns
UHPI_HRDY valid increment) and data not in Read FIFO
(can only happen to first half-word of
HPID access)
Case 2: First half-word access of HPID
Read without auto-increment
For UHPI Read, UHPI_HRDY stays
high (ready) for these UHPI Read
conditions:
Case 1: HPID read with auto-increment
and data is already in Read FIFO
(applies to either half-word of HPID
access)
Case 2: HPID read without auto-
increment and data is already in Read
FIFO (always applies to second half-
word of HPID access)
Case 3: HPIC or HPIA read (applies to
either half-word access)
6 ten(HSTBL-HDLZ) Enable time, UHPI_HD driven from HSTROBE low 1.5 1.5 ns
7 td(HRDYL-HDV) Delay time, UHPI_HRDY high to HD valid 1.1 1.1 ns
8 toh(HSTBH-HDV) Output hold time, UHPI_HD valid after HSTROBE high 1.5 1.5 ns
14 tdis(HSTBH-HDHZ) Disable time, HD high-impedance from HSTROBE high 26.8 20.5 ns
For UHPI Read. Applies to conditions
where data is already residing in HPID
or FIFO:
Case 1: HPIC or HPIA read
Delay time, HSTROBE low to
15 td(HSTBL-HDV) Case 2: First half-word of HPID read 26.8 20.5 ns
HD valid
with auto-increment and data is already
in Read FIFO
Case 3: Second half-word of HPID
read with or without auto-increment
stays high (ready):
Case 1: HPID write when Write FIFO is
Delay time, HSTROBE high to
18 td(HSTBH-HRDYV) full (can happen to either half-word) 26.5 19 ns
UHPI_HRDY valid
Case 2: HPIA write (can happen to
either half-word)
Case 3: HPID write without auto-
increment (only happens to second
half-word)

TMS320C5517
UHPI_HCS
UHPI_HAS (D)
2 2
1 1
UHPI_HCNTL[1:0]
2 2
1 1
UHPI_HR_NW
2 2
1 1
UHPI_HHWIL
4
3 3
HSTROBE(A)(C)
15 15
14 14
6 8 6 8
UHPI_HD[15:0]
(output)
5 13 1st Half-W ord 2nd Half-W ord
7
UHPI_HRDY(B)
A. HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(UHPI_HDS1
XOR UHPI_HDS2)] OR UHPI_HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-
incrementing) and the state of the FIFO, transitions on UHPI_HRDY may or may not occur.
For more information on the UHPI peripheral, see the UHPI chapter in the TMS320C5517 Technical Reference
Manual [literature number SPRUH16].
C. Typical UHPI_HCS behavior is reflected when HSTROBE assertion is caused by UHPI_HDS1 or UHPI_HDS2.
UHPI_HCS timing requirements are reflected by parameters for HSTROBE.
D. For proper UHPI operation, UHPI_HAS must be pulled up via an external resistor.
Figure 5-45. UHPI Read Timing (UHPI_HAS Not Used, Tied High)

TMS320C5517
UHPI_HCS
UHPI_HAS (D)
1 1
2 2
UHPI_HCNTL[1:0]
1 1
2 2
UHPI_HR_NW
1 1
2 2
UHPI_HHWIL
3 3
4
HSTROBE(A)(C)
11 11
12 12
UHPI_HD[15:0]
(input) 1st Half-W ord 2nd Half-W ord
18
5 18 13
13
5
UHPI_HRDY(B)
A. HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(UHPI_HDS1
XOR UHPI_HDS2)] OR UHPI_HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-
incrementing) and the state of the FIFO, transitions on UHPI_HRDY may or may not occur.
For more information on the UHPI peripheral, see the UHPI chapter in the TMs320C5517 Technical Reference
Manual [literature number SPRUH16].
C. Typical UHPI_HCS behavior is reflected when HSTROBE assertion is caused by UHPI_HDS1 or UHPI_HDS2.
UHPI_HCS timing requirements are reflected by parameters for HSTROBE.
D. For proper UHPI operation, UHPI_HAS must be pulled up via an external resistor.
Figure 5-46. UHPI Write Timing (UHPI_HAS Not Used, Tied High)

TMS320C5517
5.7.19 Universal Serial Bus (USB) 2.0 Controller

The device USB2.0 peripheral supports the following features:
• USB2.0 peripheral at speeds high-speed (480Mb/s) and full-speed (12Mb/s)
• All transfer modes (control, bulk, interrupt, and isochronous mode)
• 4 Transmit (TX) and 4 Receive (RX) Endpoints in addition to Control Endpoint 0
• FIFO RAM
– 4K endpoint
– Programmable size
• Integrated USB2.0 High Speed PHY
• RNDIS mode for accelerating RNDIS type protocols using short packet termination over USB
The USB2.0 peripheral on this device, does not support:
• Host Mode (Peripheral and Device Modes supported only)
• On-Chip Charge Pump
• On-the-Go (OTG) Mode
5.7.19.1 USB 2.0 Electrical Data and Timing
Table 5-64. Switching Characteristics Over Recommended Operating Conditions for USB 2.0 (see
Figure 5-47)
CVDD = 1.05 V
CVDD = 1.3 V
CVDD = 1.4 V
NO. PARAMETER UNIT
FULL SPEED HIGH SPEED
12 Mbps 480 Mbps (1)
MIN MAX MIN MAX
(2)
1 tr(D) Rise time, USB_DP and USB_DM signals 4 20 0.5 ns
2 tf(D) Fall time, USB_DP and USB_DM signals (2) 4 20 0.5 ns
3 trfM Rise and Fall time, matching (3) 90 111 – – %
(2)
4 VCRS Output signal cross-over voltage 1.3 2 – – V
7 tw(EOPT) Pulse duration, EOP transmitter (4) 160 175 – – ns
8 tw(EOPR) Pulse duration, EOP receiver (4) 82 – ns
9 t(DRATE) Data Rate 12 480 Mb/s
10 ZDRV Driver Output Resistance 40.5 49.5 40.5 49.5 Ω
11 ZINP Receiver Input Impedance 100k - - Ω
(1) For more detailed information, see the Universal Serial Bus Specification, Revision 2.0, Chapter 7.
(2) Full Speed and High Speed CL = 50 pF
(3) tRFM = (tr/tf) x 100. [Excluding the first transaction from the Idle state.]
(4) Must accept as valid EOP
tper - tjr
USB_DM
90% VOH
VCRS
10% VOL
USB_DP
tf
tr
Figure 5-47. USB2.0 Integrated Transceiver Interface Timing

TMS320C5517
5.7.20 Emulation and Debug
5.7.20.1 Debugging Considerations
5.7.20.1.1 Pullup and Pulldown Resistors

Proper board design should ensure that input pins to the DSP are always at a valid logic level and not
floating. This may be achieved via pullup and pulldown resistors. The DSP features internal pullup (IPU)
and internal pulldown (IPD) resistors on many pins to eliminate the need, unless otherwise noted, for
external pullup and pulldown resistors.
An external pullup and pulldown resistor may need to be used in the following situations:
• Configuration Pins: An external pullup and pulldown resistor is recommended to set the desired value
or state (see the configuration pins listed in Table 5-5, Default Functions Affected by Device
Configuration Pins). Note that some configuration pins must be connected directly to ground or to a
specific supply voltage.
• Input Pins (I, I/O, I/O/Z): They are required to be driven at all times. To achieve the lowest power, input
pins must not be allowed to float. When they are configured as input or tri-stated, and not driven to a
known state, they may cause an excessive IO-supply current. Prevent this current by externally
terminating it or enabling IPD and IPU, if applicable.
• Other Input Pins: If the IPU and IPD does not match the desired value or state, use an external pullup
and pulldown resistor to pull the signal to the opposite rail.
For the configuration pins (listed in Table 5-5, Default Functions Affected by Device Configuration Pins), if
they are both routed out and 3-stated (not driven), it is strongly recommended that an external pullup and
pulldown resistor be implemented. In addition, applying external pullup and pulldown resistors on the
configuration pins adds convenience to the user in debugging and flexibility in switching operating modes.
When an external pullup or pulldown resistor is used on a pin, the pin’s internal pullup or pulldown resistor
should be disabled through the Pullup and Pulldown Inhibit Registers (PUDINHIBR1, 2, 3, 4, 5, 6, and 7)
to minimize power consumption.
Tips for choosing an external pullup and pulldown resistor:
• Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure
to include the leakage currents of all the devices connected to the net, as well as any internal pullup or
pulldown (IPU and IPD) resistors.
• Decide a target value for the net. For a pulldown resistor, this should be below the lowest VIL level of
all inputs connected to the net. For a pullup resistor, this should be above the highest VIH level of all
inputs on the net. A reasonable choice would be to target the VOL or VOH levels for the logic family of
the limiting device; which, by definition, have margin to the VIL and VIH levels.
• Select a pullup and pulldown resistor with the largest possible value; but, which can still ensure that the
net will reach the target pulled value when maximum current from all devices on the net is flowing
through the resistor. The current to be considered includes leakage current plus, any other internal and
external pullup and pulldown resistors on the net.
• For bidirectional nets, there is an additional consideration which sets a lower limit on the resistance
value of the external resistor. Verify that the resistance is small enough that the weakest output buffer
can drive the net to the opposite logic level (including margin).
• Remember to include tolerances when selecting the resistor value.
• For pullup resistors, also remember to include tolerances on the DVDD rail.
For most systems, a 1-kΩ resistor can be used to oppose the IPU and IPD while meeting the above
criteria. Users should confirm this resistor value is correct for their specific application.
For most systems, a 20-kΩ resistor can be used to compliment the IPU and IPD on the configuration pins
while meeting the above criteria. Users should confirm this resistor value is correct for their specific
application.

TMS320C5517
For more detailed information on input current (II), and the low- and high-level input voltages (VIL and VIH)
for the device DSP, see Section 5.3.2, Electrical Characteristics.
For the internal pullup and pulldown resistors for all device pins, see the peripheral and system-specific
signal descriptions table in this document.
5.7.20.1.2 Bus Holders

The device has special I/O bus-holder structures to ensure pins are not left floating when CVDD power is
removed while I/O power is applied. When CVDD is "ON", the bus-holders are disabled and the internal
pullups or pulldowns, if applicable, function normally. But when CVDD is "OFF" and the I/O supply is "ON",
the bus-holders become enabled and any applicable internal pullups and pulldowns are disabled.
The bus-holders are weak drivers on the pin and, for as long as CVDD is "OFF" and I/O power is "ON",
they hold the last state on the pin. If an external device is strongly driving the device I/O pin to the
opposite state then the bus-holder will flip state to match the external driver and DC current will stop.
This bus-holder feature prevents unnecessary power consumption when CVDD is "OFF"and I/O supply is
"ON". For example, current caused by undriven pins (input buffer oscillation) or DC current flowing through
pullups or pulldowns.
If external pullup or pulldown resistors are implemented, then care should be taken that those pullup and
pulldown resistors can exceed the internal bus-holder's max current and thereby cause the bus-holder to
flip state to match the state of the external pullup or pulldown. Otherwise, DC current will flow
unnecessarily. When CVDD power is applied, the bus holders are disabled (for further details on bus
holders, see Section 5.7.2.3, Digital I/O Behavior When Core Power (CVDD) is Down).
5.7.20.1.3 CLKOUT Pin

For debug purposes, the DSP includes a CLKOUT pin which can be used to tap different clocks within the
clock generator. The SRC bits of the CLKOUT Configuration Register (CLKOUTCR) can be used to
specify the source for the CLKOUT pin.
Note: The bootloader disables the CLKOUT pin via CLKOFF bit in the ST3_55 CPU register.
For more information on the ST3_55 CPU register, see the C55x 3.0 CPU Reference Guide (literature
number: SWPU073).

TMS320C5517
5.7.21 IEEE 1149.1 JTAG

The JTAG interface is used for Boundary-Scan testing and emulation of the device.
TRST should only to be deasserted when it is necessary to use a JTAG controller to debug the device or
exercise the device's boundary scan functionality.
The device includes an internal pulldown (IPD) on the TRST pin to ensure that TRST will always be
asserted upon power up and the device's internal emulation logic will always be properly initialized. An
external pulldown should also be added to ensure proper device operation when an emulation or
boundary scan JTAG controller is not connected to the JTAG pins. JTAG controllers from Texas
Instruments actively drive TRST high. However, some third-party JTAG controllers may not drive TRST
high but expect the use of a pullup resistor on TRST. When using this type of JTAG controller, assert
TRST to initialize the device after powerup and externally drive TRST high before attempting any
emulation or boundary scan operations. The device will not operate properly if TRST is not asserted low
during powerup.
5.7.21.1 JTAG Test_port Electrical Data and Timing
Table 5-65. Timing Requirements for JTAG Test Port (see Figure 5-48)
CVDD = 1.05 V
CVDD = 1.3 V
MIN MAX
2 tc(TCK) Cycle time, TCK 60 ns
3 tw(TCKH) Pulse duration, TCK high 24 ns
4 tw(TCKL) Pulse duration, TCK low 24 ns
5 tsu(TDIV-TCKH) Setup time, TDI valid before TCK high 10 ns
6 tsu(TMSV-TCKH) Setup time, TMS valid before TCK high 6 ns
7 th(TCKH-TDIV) Hold time, TDI valid after TCK high 5 ns
8 th(TCKH-TDIV) Hold time, TMS valid after TCK high 4 ns
Table 5-66. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port
(see Figure 5-48)
CVDD = 1.05 V
CVDD = 1.3 V
MIN MAX
1 td(TCKL-TDOV) Delay time, TCK low to TDO valid 30.5 ns
2
3 4
TCK
1 1
TDO
7
5
TDI
8
6
TMS
Figure 5-48. JTAG Test-Port Timing

TMS320C5517
6 Detailed Description
6.1 CPU
This fixed-point digital signal processor (DSP) is based on the C55x CPU 3.3 generation processor core.
The C55x DSP architecture achieves high performance and low power through increased parallelism and
total focus on power savings. The CPU supports an internal bus structure that is composed of one
program bus, three data read buses (one 32-bit data read bus and two 16-bit data read buses), two 16-bit
data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the
ability to perform up to four data reads and two data writes in a single cycle. Each DMA controller can
perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.
The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit
multiplication in a single cycle. A central 40-bit arithmetic and logic unit (ALU) is supported by an
additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize
parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data
Unit (DU) of the C55x CPU.
The C55x DSP generation supports a variable byte width instruction set for improved code density. The
Instruction Unit (IU) performs 32-bit program fetches from internal or external memory, stores them in a
128-byte Instruction Buffer Queue, and queues instructions for the Program Unit (PU). The Program Unit
decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline.
Predictive branching capability avoids pipeline flushes on execution of conditional instruction calls.
For more detailed information on the CPU, see the C55x CPU 3.0 CPU Reference Guide [literature
number SWPU073].
The C55x core of the device can address 16M bytes of unified data and program space. The core also
addresses 64K words of I/O space and includes three types of on-chip memory: 128 KB read-only
memory (ROM), 256 KB single-access random access memory (SARAM), 64 KB dual-access random
access memory (DARAM). The memory map is shown in Figure 6-1 .
6.2 Memory
6.2.1 Internal Memory
6.2.1.1 On-Chip Dual-Access RAM (DARAM)

The DARAM is located in the byte address range 000000h - 00FFFFh and is composed of eight blocks of
4K words each (see Table 6-1). Each DARAM block can support two accesses per cycle (two reads, two
writes, or a read and a write). The DARAM can be accessed by the internal program, data, or DMA buses.
Table 6-1. DARAM Blocks

CPU DMA CONTROLLER
MEMORY BLOCK
BYTE ADDRESS RANGE BYTE ADDRESS RANGE
000000h – 001FFFh 0001 0000h – 0001 1FFFh DARAM 0 (1)
002000h – 003FFFh 0001 2000h – 0001 3FFFh DARAM 1
00A000h – 00BFFFh 0001 A000h – 0001 BFFFh DARAM 5
00C000h – 00DFFFh 0001 C000h – 0001 DFFFh DARAM 6
00E000h – 00FFFFh 0001 E000h – 0001 FFFFh DARAM 7
(1) The first 192 bytes are reserved for memory-mapped registers (MMRs). See Figure 6-1 , Memory Map
Summary.
154 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated

TMS320C5517
6.2.1.2 On-Chip Single-Access RAM (SARAM)

The SARAM is located at the byte address range 010000h – 04FFFFh and is composed of 32 blocks of
4K words each (see Table 6-2). Each SARAM block can support one access per cycle (one read or one
write). SARAM can be accessed by the internal program, data, or DMA buses. SARAM is also accessed
by the USB DMA buses.
Table 6-2. SARAM Blocks

CPU DMA and USB CONTROLLER
MEMORY BLOCK
BYTE ADDRESS RANGE BYTE ADDRESS RANGE
010000h - 011FFFh 0009 0000h – 0009 1FFFh SARAM 0
01A000h - 01BFFFh 0009 A000h – 0009 BFFFh SARAM 5
01C000h - 01DFFFh 0009 C000h – 0009 DFFFh SARAM 6
01E000h - 01FFFFh 0009 E000h – 0009 FFFFh SARAM 7
020000h - 021FFFh 000A 0000h – 000A 1FFFh SARAM 8
02A000h - 02BFFFh 000A A000h – 000A BFFFh SARAM 13
02C000h - 02DFFFh 000A C000h – 000A DFFFh SARAM 14
02E000h - 02FFFFh 000A E000h – 000A FFFFh SARAM 15
030000h - 031FFFh 000B 0000h – 000B 1FFFh SARAM 16
03A000h - 03BFFFh 000B A000h – 000B BFFFh SARAM 21
03C000h - 03DFFFh 000B C000h – 000B DFFFh SARAM 22
03E000h - 03FFFFh 000B E000h – 000B FFFFh SARAM 23
040000h – 041FFFh 000C 0000h – 000C 1FFFh SARAM 24
04A000h – 04BFFFh 000C A000h – 000C BFFFh SARAM 29
04C000h – 04DFFFh 000C C000h – 000C DFFFh SARAM 30
04E000h – 04FFFFh 000C E000h – 000C FFFFh SARAM 31 (1)
(1) SARAM31 (byte address range: 0x4E000 – 0x4EFFF) is reserved for the bootloader. After the boot
process is complete, this memory space can be used.
Copyright © 2012–2014, Texas Instruments Incorporated Detailed Description 155

TMS320C5517
6.2.1.3 On-Chip Read-Only Memory (ROM)

The zero-wait-state ROM is located at the byte address range FE0000h – FFFFFFh. The ROM is
composed of four 16K-word blocks, for a total of 128K bytes of ROM. Each on-chip ROM block can
support one read per cycle. The ROM address space can be mapped by software to the EMIF external
memory or to the internal ROM.
The standard device includes a Bootloader program resident in the ROM.
When the MPNMC bit field of the ST3 status register is cleared (by default), the byte address range
FE0000h – FFFFFFh is used for the on-chip ROM. When the MPNMC bit field of the ST3 status register is
set through software, the on-chip ROM is disabled and not present in the memory map, and byte address
range FE0000h – FFFFFFh is directed to the EMIF's external memory space on EM_CS5. A hardware
reset always clears the MPNMC bit, so it is not possible to disable the ROM at reset. However, the
software reset instruction does not affect the MPNMC bit. The ROM can be accessed by the CPU
program and data buses.
6.2.1.4 I/O Memory

The device includes a 64K byte I/O space for the memory-mapped registers of the DSP peripherals and
system registers used for idle control, status monitoring and system configuration. I/O space is separate
from program and memory space and is accessed with separate instruction opcodes or via the DMA's.
Table 6-3 lists the memory-mapped registers of the device. Note that not all addresses in the 64K byte I/O
space are used; these addresses should be treated as RESERVED and not accessed by the CPU nor
DMA. For the expanded tables of each peripheral, see Section 6.2.4, Register Map.
Some of the DMA controllers have access to the I/O-Space memory-mapped registers of the following
peripherals registers: I2C, UART, I2S, MMC and SD, EMIF, McBSP, McSPI, USB, and SAR ADC.
Before accessing any peripheral memory-mapped register, make sure the peripheral being accessed is
not held in reset via the Peripheral Reset Control Register (PRCR) and its internal clock is enabled via the
Peripheral Clock Gating Control Registers (PCGCR1 and PCGCR2).
Table 6-3. Peripheral I/O-Space Control Registers

WORD ADDRESS PERIPHERAL
0x0000 – 0x0004 Idle Control
0x0005 – 0x0BFF Reserved
0x0C00 – 0x0C7F DMA0
0x0C80 – 0x0CFF Reserved
0x0D00 – 0x0D7F DMA1
0x0D80 – 0x0DFF Reserved
0x0E00 – 0x0E7F DMA2
0x0E80 – 0x0EFF Reserved
0x0F00 – 0x0F7F DMA3
0x0F80 – 0x0FFF Reserved
0x1000 – 0x10DD EMIF
0x10DE – 0x17FF Reserved
0x1800 – 0x181F Timer0
0x1820 – 0x183F Reserved
0x1840 – 0x185F Timer1
0x1860 – 0x187F Reserved
0x1880 – 0x189F Timer2
0x18A0 – 0x18FF Reserved
0x1900 – 0x197F RTC

TMS320C5517
Table 6-3. Peripheral I/O-Space Control Registers (continued)

WORD ADDRESS PERIPHERAL
0x1980 – 0x19FF Reserved
0x1A00 – 0x1A6C I2C
0x1A6D – 0x1AFF Reserved
0x1B00 – 0x1B1F UART
0x1B20 – 0x1BFF Reserved
0x1C00 – 0x1CFF System Control
0x1D00 – 0x1FFF through 0x2600 – 0x27FF Reserved
0x2800 – 0x2840 I2S0
0x2A00 – 0x2A40 I2S2
0x2A41 – 0x2AFF Reserved
0x2B00 – 0x2B40 I2S3
0x2B41 – 0x2DFF Reserved
0x2E00 – 0x2E81 UHPI
0x2E82 – 0x2FFF Reserved
0x3000 – 0x300F SPI
0x3400 – 0x3749 McSPI
0x3750 –0x39FF Reserved
0x3A00 – 0x3A7F MMC0 and SD0
0x3A80 – 0x3AFF Reserved
0x3B00 – 0x3B7F MMC1 and SD1
0x3B80 – 0x3FFF Reserved
0x4000 – 0x407F McBSP
0x4080 – 0x5FFF Reserved
0x6000 – 0x60FF McBSP DMA
0x7000 – 0x70FF SAR and Analog Control Registers
0x8000 – 0xFFFF USB
6.2.2 External Memory

The external memory space of the device is located at the byte address range 050000h – FFFFFFh. The
external memory space is divided into five chip select spaces: one dedicated to SDRAM and mobile
SDRAM (EMIF CS0 or CS[1:0] space), and the remainder (EMIF CS2 through CS5 space) dedicated to
asynchronous devices including flash. Each chip select space has a corresponding chip select pin (called
EM_CSx) that is activated during an access to the chip select space.
The external memory interface (EMIF) provides the means for the DSP to access external memories and
other devices including: mobile single data rate (SDR) synchronous dynamic RAM (SDRAM and
mSDRAM), NOR Flash, NAND Flash, and asynchronous static RAM (SRAM). Before accessing external
memory, you must configure the EMIF through its memory-mapped registers.
The EMIF provides a configurable 16- or 8-bit data bus, an address bus width of up to 21-bits, and 5
dedicated chip selects, along with memory control signals. To maximize power savings, the I/O pins of the
EMIF can be operated at an independent voltage from the other I/O pins on the device.

TMS320C5517
6.2.3 Memory Map

The device provides 16M bytes of total memory space composed of on-chip RAM, on-chip ROM, and
external memory space supporting a variety of memory types. The on-chip, dual-access RAM allows two
accesses to a given block during the same cycle. There are 8 blocks of 8K bytes of dual-access RAM.
The on-chip, single-access RAM allows one access to a given block per cycle. In addition, there are 32
blocks of 8K bytes of single-access RAM.
The remainder of the memory map is divided into five external spaces, and on-chip ROM. Each external
space has a chip select decode signal (called EM_CS0, EM_CS[2:5]) that indicates an access to the
selected space. The external memory interface (EMIF) supports access to asynchronous memories such
as SRAM, NAND, or NOR and Flash, and mobile single data rate (mSDR) and single data rate (SDR)
SDRAM.
The DSP memory is accessible by different master modules within the DSP, including the C55x CPU, the
four DMA controllers, the UHPI, and the CDMA of USB (see Figure 6-1). However, only the UHPI and
USB CDMA can access the SARAM.
CPU BYTE DMA/USB

ADDRESS(A) BYTE ADDRESS(A) MEMORY BLOCKS BLOCK SIZE
000000h 0001 0000h (B)
MMR (Reserved)
0000C0h 0001 00C0h
(D)
DARAM 64K Minus 192 Bytes
010000h 0009 0000h

SARAM 256K Bytes
050000h 0100 0000h

(C)(E) 8M Minus 320K Bytes SDRAM/mSDRAM
External-CS0 Space
800000h 0200 0000h

(C)
External-CS2 Space 4M Bytes Asynchronous
C00000h 0300 0000h

(C)
External-CS3 Space 2M Bytes Asynchronous
E00000h 0400 0000h

(C) 1M Bytes Asynchronous
External-CS4 Space
F00000h 0500 0000h

(C) 1M Minus 128K Bytes Asynchronous
External-CS5 Space
FE0000h 050E 0000h

(C) 128K Bytes Asynchronous (if MPNMC=1)
ROM External-CS5 Space
(if MPNMC=0) (if MPNMC=1) 128K Bytes ROM (if MPNMC=0)
FFFFFFh 050F FFFFh
A. Address shown represents the first byte address in each block.
B. The first 192 bytes are reserved for memory-mapped registers (MMRs).
C. Out of the four DMA controllers, only DMA controller 3 has access to the external memory space.
D. The USB controller and UHPI do not have access to DARAM.
E. The CS0 space can be accessed by CS0 only or by CS0 and CS1.
Figure 6-1. Memory Map

TMS320C5517
6.2.4 Register Map
6.2.4.1 DMA Peripheral Register Description

The following tables show the registers associated with the four direct memory access (DMA) controllers.
Table 6-4. System Registers Related to the DMA Controllers

CPU WORD
ACRONYM REGISTER NAME
ADDRESS
1C30h DMAIFR DMA Interrupt Flag Register
1C31h DMAIER DMA Interrupt Enable Register
1C1Ah DMA0CESRL DMA0 Channel Event Source Register Lower
1C1Bh DMA0CESRU DMA0 Channel Event Source Register Upper
1C1Ch DMA1CESRL DMA1 Channel Event Source Register Lower
1C1Dh DMA1CESRU DMA1 Channel Event Source Register Upper
1C36h DMA2CESRL DMA2 Channel Event Source Register Lower
1C37h DMA2CESRU DMA2 Channel Event Source Register Upper
1C38h DMA3CESRL DMA3 Channel Event Source Register Lower
1C39h DMA3CESRU DMA3 Channel Event Source Register Upper
Table 6-5. DMA Controller 0 (DMA0) Registers

CPU WORD
ADDRESS ACRONYM REGISTER NAME
0C00h DMACH0SSAL Channel 0 Source Start Address Register Lower
0C01h DMACH0SSAU Channel 0 Source Start Address Register Upper
0C02h DMACH0DSAL Channel 0 Destination Start Address Register Lower
0C03h DMACH0DSAU Channel 0 Destination Start Address Register Upper
0C04h DMACH0TCRL Channel 0 Transfer Control Register Lower
0C05h DMACH0TCRU Channel 0 Transfer Control Register Upper

TMS320C5517

CPU WORD
0D00h DMACH0SSAL Channel 0 Source Start Address Register Lower
0D01h DMACH0SSAU Channel 0 Source Start Address Register Upper
0D02h DMACH0DSAL Channel 0 Destination Start Address Register Lower
0D03h DMACH0DSAU Channel 0 Destination Start Address Register Upper
0D04h DMACH0TCRL Channel 0 Transfer Control Register Lower
0D05h DMACH0TCRU Channel 0 Transfer Control Register Upper

CPU WORD
0E00h DMACH0SSAL Channel 0 Source Start Address Register Lower
0E01h DMACH0SSAU Channel 0 Source Start Address Register Upper
0E02h DMACH0DSAL Channel 0 Destination Start Address Register Lower
0E03h DMACH0DSAU Channel 0 Destination Start Address Register Upper
0E04h DMACH0TCRL Channel 0 Transfer Control Register Lower
0E05h DMACH0TCRU Channel 0 Transfer Control Register Upper

TMS320C5517
Table 6-7. DMA Controller 2 (DMA2) Registers (continued)

CPU WORD

CPU WORD
0F00h DMACH0SSAL Channel 0 Source Start Address Register Lower
0F01h DMACH0SSAU Channel 0 Source Start Address Register Upper
0F02h DMACH0DSAL Channel 0 Destination Start Address Register Lower
0F03h DMACH0DSAU Channel 0 Destination Start Address Register Upper
0F04h DMACH0TCRL Channel 0 Transfer Control Register Lower
0F05h DMACH0TCRU Channel 0 Transfer Control Register Upper

TMS320C5517
6.2.4.2 EMIF Peripheral Register Description

Table 6-9 shows the EMIF registers.
Table 6-9. External Memory Interface (EMIF) Peripheral Registers (1)

CPU WORD ACRONYM
REGISTER NAME
ADDRESS
1000h REV Revision Register
1001h STATUS Status Register
1004h AWCCR1 Asynchronous Wait Cycle Configuration Register 1
1005h AWCCR2 Asynchronous Wait Cycle Configuration Register 2
1008h SDCR1 SDRAM and mSDRAM Configuration Register 1
1009h SDCR2 SDRAM and mSDRAM Configuration Register 2
100Ch SDRCR SDRAM and mSDRAM Refresh Control Register
1010h ACS2CR1 Asynchronous CS2 Configuration Register 1
101Ch ACS5CR1 Asynchronous CS5 Configuration Register 1
101Dh ACS5CR2 Asynchronous CS5 Configuration Register 2
1020h SDTIMR1 SDRAM and mSDRAM Timing Register 1
1021h SDTIMR2 SDRAM and mSDRAM Timing Register 2
103Ch SDSRETR SDRAM and mSDRAM Self Refresh Exit Timing Register
1040h EIRR EMIF Interrupt Raw Register
1044h EIMR EMIF Interrupt Mask Register
1048h EIMSR EMIF Interrupt Mask Set Register
104Ch EIMCR EMIF Interrupt Mask Clear Register
1060h NANDFCR NAND Flash Control Register
1064h NANDFSR1 NAND Flash Status Register 1
1065h NANDFSR2 NAND Flash Status Register 2
1068h PAGEMODCTRL1 Page Mode Control Register 1
1069h PAGEMODCTRL2 Page Mode Control Register 2
1070h NCS2ECC1 NAND Flash CS2 1-Bit ECC Register 1
107Ch NCS5ECC1 NAND Flash CS5 1-Bit ECC Register 1
107Dh NCS5ECC2 NAND Flash CS5 1-Bit ECC Register 2
10BCh NAND4BITECCLOAD NAND Flash 4-Bit ECC Load Register
10C0h NAND4BITECC1 NAND Flash 4-Bit ECC Register 1
(1) Before reading or writing to the EMIF registers, be sure to set the BYTEMODE bits to 00b in the EMIF system control register to enable
word accesses to the EMIF registers.
TMS320C5517
Table 6-9. External Memory Interface (EMIF) Peripheral Registers(1) (continued)

CPU WORD ACRONYM
REGISTER NAME
ADDRESS
10CCh NAND4BITECC7 NAND Flash 4-Bit ECC Register 7
10CDh NAND4BITECC8 NAND Flash 4-Bit ECC Register 8
10D0h NANDERRADD1 NAND Flash 4-Bit ECC Error Address Register 1
10D8h NANDERRVAL1 NAND Flash 4-Bit ECC Error Value Register 1
10D9h NANDERRVAL2 NAND Flash 4-Bit ECC Error Value Register 2
10DCh NANDERRVAL3 NAND Flash 4-Bit ECC Error Value Register 3
10DDh NANDERRVAL4 NAND Flash 4-Bit ECC Error Value Register 4
6.2.4.3 GPIO Peripheral Register Description

The external parallel port interface includes a 16-bit general purpose I/O that can be individually
programmed as input or output with interrupt capability. Control of the general purpose I/O is maintained
through a set of I/O memory-mapped registers shown in Table 6-10.
Table 6-10. GPIO Registers

CPU WORD
ADDRESS
1C06h IODIR1 GPIO Direction Register 1
1C07h IODIR2 GPIO Direction Register 2
1C08h IOINDATA1 GPIO Data In Register 1
1C09h IOINDATA2 GPIO Data In Register 2
1C0Ah IODATAOUT1 GPIO Data Out Register 1
1C0Bh IODATAOUT2 GPIO Data Out Register 2
1C0Ch IOINTEDG1 GPIO Interrupt Edge Trigger Enable Register 1
1C0Dh IOINTEDG2 GPIO Interrupt Edge Trigger Enable Register 2
1C0Eh IOINTEN1 GPIO Interrupt Enable Register 1
1C0Fh IOINTEN2 GPIO Interrupt Enable Register 2
1C10h IOINTFLG1 GPIO Interrupt Flag Register 1
1C11h IOINTFLG2 GPIO Interrupt Flag Register 2

TMS320C5517
6.2.4.4 I2C Peripheral Register Description

Table 6-11 shows the Inter-Integrated Circuit (I2C) registers.
Table 6-11. Inter-Integrated Circuit (I2C) Registers

CPU WORD ACRONYM REGISTER NAME
ADDRESS
1A00h ICOAR I2C Own Address Register
1A04h ICIMR I2C Interrupt Mask Register
1A08h ICSTR I2C Interrupt Status Register
1A0Ch ICCLKL I2C Clock Low-Time Divider Register
1A10h ICCLKH I2C Clock High-Time Divider Register
1A14h ICCNT I2C Data Count Register
1A18h ICDRR I2C Data Receive Register
1A1Ch ICSAR I2C Slave Address Register
1A20h ICDXR I2C Data Transmit Register
1A24h ICMDR I2C Mode Register
1A28h ICIVR I2C Interrupt Vector Register
1A2Ch ICEMDR I2C Extended Mode Register
1A30h ICPSC I2C Prescaler Register
1A34h ICPID1 I2C Peripheral Identification Register 1
1A38h ICPID2 I2C Peripheral Identification Register 2

TMS320C5517
6.2.4.5 I2S Peripheral Register Description

Table 6-12 through Table 6-14 show the I2S0, I2S2, and I2S3 registers.
Table 6-12. I2S0 Registers

CPU WORD
ADDRESS
2800h I2S0SCTRL I2S0 Serializer Control Register
2804h I2S0SRATE I2S0 Sample Rate Generator Register
2808h I2S0TXLT1 I2S0 Transmit Left Data Register 1
2809h I2S0TXLT2 I2S0 Transmit Left Data Register 2
280Ch I2S0TXRT1 I2S0 Transmit Right Data Register 1
280Dh I2S0TXRT2 I2S0 Transmit Right Data Register 2
2810h I2S0INTFL I2S0 Interrupt Flag Register
2814h I2S0INTMASK I2S0 Interrupt Mask Register
2828h I2S0RXLT1 I2S0 Receive Left Data Register 1
2829h I2S0RXLT2 I2S0 Receive Left Data Register 2
282Ch I2S0RXRT1 I2S0 Receive Right Data Register 1
282Dh I2S0RXRT2 I2S0 Receive Right Data Register 2

CPU WORD
ADDRESS
2A00h I2S2SCTRL I2S2 Serializer Control Register
2A04h I2S2SRATE I2S2 Sample Rate Generator Register
2A08h I2S2TXLT1 I2S2 Transmit Left Data Register 1
2A09h I2S2TXLT2 I2S2 Transmit Left Data Register 2
2A0Ch I2S2TXRT1 I2S2 Transmit Right Data Register 1
2A0Dh I2S2TXRT2 I2S2 Transmit Right Data Register 2
2A10h I2S2INTFL I2S2 Interrupt Flag Register
2A14h I2S2INTMASK I2S2 Interrupt Mask Register
2A28h I2S2RXLT1 I2S2 Receive Left Data Register 1
2A29h I2S2RXLT2 I2S2 Receive Left Data Register 2
2A2Ch I2S2RXRT1 I2S2 Receive Right Data Register 1
2A2Dh I2S2RXRT2 I2S2 Receive Right Data Register 2

CPU WORD
ADDRESS
2B00h I2S3SCTRL I2S3 Serializer Control Register
2B04h I2S3SRATE I2S3 Sample Rate Generator Register
2B08h I2S3TXLT1 I2S3 Transmit Left Data Register 1
2B09h I2S3TXLT2 I2S3 Transmit Left Data Register 2
2B0Ch I2S3TXRT1 I2S3 Transmit Right Data Register 1
2B0Dh I2S3TXRT2 I2S3 Transmit Right Data Register 2
2B10h I2S3INTFL I2S3 Interrupt Flag Register
2B14h I2S3INTMASK I2S3 Interrupt Mask Register
2B28h I2S3RXLT1 I2S3 Receive Left Data Register 1
2B29h I2S3RXLT2 I2S3 Receive Left Data Register 2
2B2Ch I2S3RXRT1 I2S3 Receive Right Data Register 1

TMS320C5517
Table 6-14. I2S3 Registers (continued)

CPU WORD
ADDRESS
2B2Dh I2S3RXRT2 I2S3 Receive Right Data Register 2
6.2.4.6 McBSP Peripheral Register Descriptions

Table 6-15 shows the McBSP peripheral registers.
Table 6-15. McBSP Module Registers

CPU WORD
ADDRESS
4000h DRRL Data Receive Register Lower
4001h DRRU Data Receive Register Upper
4004h DXRL Data Transmit Register Lower
4005h DXRU Data Transmit Register Upper
4008h SPCRL Serial Port Control Register Lower
4009h SPCRU Serial Port Control Register Upper
400Ch RCRL Receive Control Register Lower
400Dh RCRU Receive Control Register Upper
4010h XCRL Transmit Control Register Lower
4011h XCRU Transmit Control Register Upper
4014h SRGRL Sample Rate Generator Register Lower
4015h SRGRU Sample Rate Generator Register Upper
4018h MCRL Multichannel Control Register Lower
4019h MCRU Multichannel Control Register Upper
401Ch RCERA Enhanced Receive Channel Enable Register Partition A
401Dh RCERB Enhanced Receive Channel Enable Register Partition B
4020h XCERA Enhanced Transmit Channel Enable Register Partition A
4021h XCERB Enhanced Transmit Channel Enable Register Partition B
4024h PCRL Pin Control Register Lower
4025h PCRU Pin Control Register Upper
4028h RCERC Enhanced Receive Channel Enable Register Partition C
4029h RCERD Enhanced Receive Channel Enable Register Partition D
402Ch XCERC Enhanced Transmit Channel Enable Register Partition C
402Dh XCERD Enhanced Transmit Channel Enable Register Partition D
4030h RCERE Enhanced Receive Channel Enable Register Partition E
4031h RCERF Enhanced Receive Channel Enable Register Partition F
4034h XCERE Enhanced Transmit Channel Enable Register Partition E
4035h XCERF Enhanced Transmit Channel Enable Register Partition F
4038h RCERG Enhanced Receive Channel Enable Register Partition G
4039h RCERH Enhanced Receive Channel Enable Register Partition H
403Ch XCERG Enhanced Transmit Channel Enable Register Partition G
403Dh XCERH Enhanced Transmit Channel Enable Register Partition H

TMS320C5517
6.2.4.7 McSPI Peripheral Register Descriptions

Table 6-16 shows the McSPI peripheral registers.
Table 6-16. McSPI Module Registers

CPU WORD
ADDRESS
3500h REVISIONL Revision Register Lower
3510h SYSCONFIGL System Configuration Register Lower
3514h SYSSTATUSL System Status Register Lower
3518h IRQSTATUSL Interrupt Status Register Lower
3519h IRQSTATUSU Interrupt Status Register Upper
351Ch IRQENABLEL Interrupt Enable Register Lower
351Dh IRQENABLEU Interrupt Enable Register Upper
3520h WAKEUPENABLEL Wakeup Enable Register Lower
3528h MODULCTRLL Module Control Register Lower
352Ch CH0CONFL Channel 0 Configuration Register Lower
352Dh CH0CONFU Channel 0 Configuration Register Upper
3530h CH0STATL Channel 0 Status Register Lower
3534h CH0CTRLL Channel 0 Control Register Lower
3538h CH0TXL Channel 0 Transmitter Register Lower
3539h CH0TXU Channel 0 Transmitter Register Upper
353Ch CH0RXL Channel 0 Receiver Register Lower
353Dh CH0RXU Channel 0 Receiver Register Upper
3540h CH1CONFL Channel 1 Configuration Register Lower
3541h CH1CONFU Channel 1 Configuration Register Upper
3548h CH1CTRLL Channel 1 Control Register Lower
354Ch CH1TXL Channel 1 Transmitter Register Lower
354Dh CH1TXU Channel 1 Transmitter Register Upper
3550h CH1RXL Channel 1 Receiver Register Lower
3551h CH1RXU Channel 1 Receiver Register Upper
3554h CH2CONFL Channel 2 Configuration Register Lower
3555h CH2CONFU Channel 2 Configuration Register Upper
355Ch CH2CTRLL Channel 2 Control Register Lower
3560h CH2TXL Channel 2 Transmitter Register Lower
3561h CH2TXU Channel 2 Transmitter Register Upper
3564h CH2RXL Channel 2 Receiver Register Lower
3565h CH2RXU Channel 2 Receiver Register Upper
357Ch XFERLEVELL Transfer Levels Register Lower
357Dh XFERLEVELU Transfer Levels Register Upper
3580h DAFTXL DMA Address Aligned FIFO Transmitter Register Lower
3581h DAFTXU DMA Address Aligned FIFO Transmitter Register Upper
35A0h DAFRXL DMA Address Aligned FIFO Receiver Register Lower
35A1h DAFRXU DMA Address Aligned FIFO Receiver Register Upper

TMS320C5517
6.2.4.8 MMC and SD Peripheral Register Description

Table 6-17 and Table 6-18 show the MMC and SD registers. The MMC0 and SD0 registers start at
address 0x3A00 and the MMC1 and SD1 registers start at address 0x3B00.
Table 6-17. MMC0 and SD0 Registers

CPU WORD ACRONYM
REGISTER NAME
ADDRESS
3A00h MMCCTL MMC Control Register
3A04h MMCCLK MMC Memory Clock Control Register
3A08h MMCST0 MMC Status Register 0
3A0Ch MMCST1 MMC Status Register 1
3A10h MMCIM MMC Interrupt Mask Register
3A14h MMCTOR MMC Response Time-Out Register
3A18h MMCTOD MMC Data Read Time-Out Register
3A1Ch MMCBLEN MMC Block Length Register
3A20h MMCNBLK MMC Number of Blocks Register
3A24h MMCNBLC MMC Number of Blocks Counter Register
3A28h MMCDRRL MMC Data Receive Register Lower
3A29h MMCDRRU MMC Data Receive Register Upper
3A2Ch MMCDXRL MMC Data Transmit Register Lower
3A2Dh MMCDXRU MMC Data Transmit Register Upper
3A30h MMCCMDL MMC Command Register Lower
3A31h MMCCMDU MMC Command Register Upper
3A34h MMCARGL MMC Argument Register Lower
3A35h MMCARGU MMC Argument Register Upper
3A38h MMCRSP0 MMC Response Register 0
3A3Ch MMCRSP2 MMC Response Register 2
3A3Dh MMCRSP3 MMC Response Register 3
3A48h MMCDRSP MMC Data Response Register
3A50h MMCCIDX MMC Command Index Register
3A64h SDIOCTL SDIO Control Register
3A68h SDIOST0 SDIO Status Register 0
3A6Ch SDIOIEN SDIO Interrupt Enable Register
3A70h SDIOIST SDIO Interrupt Status Register
3A74h MMCFIFOCTL MMC FIFO Control Register

TMS320C5517
Table 6-18. MMC1 and SD1 Registers

CPU WORD
ADDRESS
3B00h MMCCTL MMC Control Register
3B04h MMCCLK MMC Memory Clock Control Register
3B08h MMCST0 MMC Status Register 0
3B0Ch MMCST1 MMC Status Register 1
3B10h MMCIM MMC Interrupt Mask Register
3B14h MMCTOR MMC Response Time-Out Register
3B18h MMCTOD MMC Data Read Time-Out Register
3B1Ch MMCBLEN MMC Block Length Register
3B20h MMCNBLK MMC Number of Blocks Register
3B24h MMCNBLC MMC Number of Blocks Counter Register
3B28h MMCDRRL MMC Data Receive Register Lower
3B29h MMCDRRU MMC Data Receive Register Upper
3B2Ch MMCDXRL MMC Data Transmit Register Lower
3B2Dh MMCDXRU MMC Data Transmit Register Upper
3B30h MMCCMDL MMC Command Register Lower
3B31h MMCCMDU MMC Command Register Upper
3B34h MMCARGL MMC Argument Register Lower
3B35h MMCARGU MMC Argument Register Upper
3B38h MMCRSP0 MMC Response Register 0
3B3Ch MMCRSP2 MMC Response Register 2
3B3Dh MMCRSP3 MMC Response Register 3
3B48h MMCDRSP MMC Data Response Register
3B50h MMCCIDX MMC Command Index Register
3B64h SDIOCTL SDIO Control Register
3B68h SDIOST0 SDIO Status Register 0
3B6Ch SDIOIEN SDIO Interrupt Enable Register
3B70h SDIOIST SDIO Interrupt Status Register
3B74h MMCFIFOCTL MMC FIFO Control Register

TMS320C5517
6.2.4.9 RTC Peripheral Register Description

Table 6-19 shows the RTC registers.
Table 6-19. Real-Time Clock (RTC) Registers

CPU WORD ACRONYM
REGISTER NAME
ADDRESS
1900h RTCINTEN RTC Interrupt Enable Register
1901h RTCUPDATE RTC Update Register
1904h RTCMIL Milliseconds Register
1905h RTCMILA Milliseconds Alarm Register
1908h RTCSEC Seconds Register
1909h RTCSECA Seconds Alarm Register
190Ch RTCMIN Minutes Register
190Dh RTCMINA Minutes Alarm Register
1910h RTCHOUR Hours Register
1911h RTCHOURA Hours Alarm Register
1914h RTCDAY Days Register
1915h RTCDAYA Days Alarm Register
1918h RTCMONTH Months Register
1919h RTCMONTHA Months Alarm Register
191Ch RTCYEAR Years Register
191Dh RTCYEARA Years Alarm Register
1920h RTCINTFL RTC Interrupt Flag Register
1921h RTCNOPWR RTC Lost Power Status Register
1924h RTCINTREG RTC Interrupt Register
1928h RTCDRIFT RTC Compensation Register
192Ch RTCOSC RTC Oscillator Register
1930h RTCPMGT RTC Power Management Register
1960h RTCSCR1 RTC LSW Scratch Register 1
1961h RTCSCR2 RTC MSW Scratch Register 2
1964h RTCSCR3 RTC LSW Scratch Register 3
1965h RTCSCR4 RTC MSW Scratch Register 4
196Ch RGKR_LSW RTC LSW Gate-Keeper Register
196Dh RGKR_MSW RTC MSW Gate-Keeper Register
6.2.4.10 SAR ADC Peripheral Register Description

Table 6-20 shows the SAR ADC peripheral registers.
Table 6-20. SAR Analog Control Registers

CPU WORD
ACRONYM REGISTER DESCRIPTION
ADDRESS
7012h SARCTRL SAR A/D Control Register
7014h SARDATA SAR A/D Data Register
7016h SARCLKCTRL SAR A/D Clock Control Register
7018h SARPINCTRL SAR A/D Reference and Pin Control Register
701Ah SARGPOCTRL SAR A/D GPO Control Register

TMS320C5517
6.2.4.11 SPI Peripheral Register Descriptions

Table 6-21 shows the SPI registers.
Table 6-21. SPI Module Registers

CPU
WORD ACRONYM REGISTER NAME
ADDRESS
3000h SPICDR Clock Divider Register
3001h SPICCR Clock Control Register
3002h SPIDCR1 Device Configuration Register 1
3003h SPIDCR2 Device Configuration Register 2
3004h SPICMD1 Command Register 1
3005h SPICMD2 Command Register 2
3006h SPISTAT1 Status Register 1
3007h SPISTAT2 Status Register 2
3008h SPIDAT1 Data Register 1
3009h SPIDAT2 Data Register 2

TMS320C5517
6.2.4.12 System Registers

The system registers are used to configure the device and monitor its status. Brief descriptions of the
various system registers are shown in Table 6-22.
Table 6-22. Idle Control, Status, and System Registers

CPU WORD ACRONYM COMMENTS
Register Description
ADDRESS
0001h ICR Idle Control Register
0002h ISTR Idle Status Register
1C00h EBSR see Section 5.7.3.5.1 of this
External Bus Selection Register
document.
1C02h PCGCR1 Peripheral Clock Gating Control Register 1
1C03h PCGCR2 Peripheral Clock Gating Control Register 2
1C04h PSRCR Peripheral Software Reset Counter Register
1C05h PRCR Peripheral Reset Control Register
1C14h TIAFR Timer Interrupt Aggregation Flag Register
1C15h MSIAFR McSPI Interrupt Aggregation Flag Register
1C16h OSRCR Output Slew Rate Control Register
1C17h PUDINHIBR1 Pullup and Pulldown Inhibit Register 1
1C1Ah DMA0CESR1 DMA0 Channel Event Source Register 1
1C1Bh DMA0CESR2 DMA0 Channel Event Source Register 2
1C1Ch DMA1CESR1 DMA1 Channel Event Source Register 1
1C1Dh DMA1CESR2 DMA1 Channel Event Source Register 2
1C1Eh CCR1 Clock Configuration Register 1
1C1Fh CCR2 Clock Configuration Register 2
1C20h PMR PLL Multiplier Register
1C21h PICR PLL Input Control Register
1C22h PCR PLL Control Register
1C23h PODCR PLL Output Divider Control Register
1C24h CLKOUTCR CLKOUT Configuration Register
1C26h ECDR EMIF Clock Divider Register
1C27h RSCR RTC System Control Register
1C28h RAMSLPMDCNTLR1 RAM Sleep Mode Control Register 1
1C2Ah RAMSLPMDCNTLR2 RAM Sleep Mode Control Register 2
1C2Bh RAMSLPMDCNTLR3 RAM Sleep Mode Control Register 3
1C2Ch RAMSLPMDCNTLR4 RAM Sleep Mode Control Register 4
1C2Dh RAMSLPMDCNTLR5 RAM Sleep Mode Control Register 5
1C2Eh PLLSSCR1 PLL Spread Spectrum Control Register 1
1C2Fh PLLSSCR2 PLL Spread Spectrum Control Register 2
1C30h DMAIFR DMA Interrupt Flag Aggregation Register
1C31h DMAIER DMA Interrupt Enable Register
1C32h USBSCR USB System Control Register
1C33h ESCR EMIF System Control Register
1C34h BMR BootMode Register
1C36h DMA2CESR1 DMA2 Channel Event Source Register 1

TMS320C5517
Table 6-22. Idle Control, Status, and System Registers (continued)

CPU WORD ACRONYM COMMENTS
Register Description
ADDRESS
1C3Ah CLKSTOP1 Peripheral Clock Stop Request and Acknowledge Register
1
1C3Bh CLKSTOP2 Peripheral Clock Stop Request and Acknowledge Register
2
1C3Ch MSPIFCDR McSPI Reference Clock Divider Register
1C3Dh MSIAER McSPI Aggregation Interrupt Mask Register
1C3Eh TISR Timer Interrupt Selection Register
1C40h DIEIDR0 Die ID Register 0
1C4Ch PUDINHIBR4 Pullup and Pulldown Inhibit Register 4
1C4Dh PUDINHIBR5 Pullup and Pulldown Inhibit Register 5
1C4Eh UHPICR UHPI Configuration Register
1C4Fh PUDINHIBR6 Pullup and Pulldown Inhibit Register 6
1C58h JTAGIDLSW JTAG ID Code LSW Register
1C59h JTAGIDMSW JTAG ID Code MSW Register
7004h LDOCNTL see Section 5.7.2.1.1.2.1 of
LDO Control Register
this document.

TMS320C5517
6.2.4.13 Timers Peripheral Register Description

Table 6-23 through Table 6-26 show the Timer and Watchdog registers.
Table 6-23. Watchdog Timer Registers (Timer2 only)

CPU WORD
ADDRESS
1880h WDKCKLK Watchdog Kick Lock Register
1882h WDKICK Watchdog Kick Register
1884h WDSVLR Watchdog Start Value Lock Register
1886h WDSVR Watchdog Start Value Register
1888h WDENLOK Watchdog Enable Lock Register
188Ah WDEN Watchdog Enable Register
188Ch WDPSLR Watchdog Prescaler Lock Register
188Eh WDPS Watchdog Prescaler Register
Table 6-24. General-Purpose Timer 0 Registers

CPU WORD
ADDRESS
1810h T0CR Timer 0 Control Register
1812h TIM0PRD1 Timer 0 Period Register 1
1814h TIM0CNT1 Timer 0 Counter Register 1
1816h T0INSR Timer 0 Input Selection Register

CPU WORD
ADDRESS

CPU WORD
ADDRESS
Table 6-27. Timer Interrupt Selection Register

CPU WORD
ADDRESS
1C3Eh TISR Timer Interrupt Selection Register

TMS320C5517
6.2.4.14 UART Peripheral Register Description

Table 6-28 shows the UART registers.
Table 6-28. UART Registers

CPU WORD ACRONYM
REGISTER NAME
ADDRESS
1B00h RBR Receiver Buffer Register (read only)
1B00h THR Transmitter Holding Register (write only)
1B02h IER Interrupt Enable Register
1B04h IIR Interrupt Identification Register (read only)
1B04h FCR FIFO Control Register (write only)
1B06h LCR Line Control Register
1B08h MCR Modem Control Register
1B0Ah LSR Line Status Register
1B0Eh SCR Scratch Register
1B10h DLL Divisor LSB Latch
1B12h DLH Divisor MSB Latch
1B18h PWREMU_MGMT Power and Emulation Management Register

TMS320C5517
6.2.4.15 UHPI Peripheral Register Descriptions

Table 6-29 shows the UHPI peripheral registers.
Table 6-29. UHPI Module Registers

CPU
WORD ACRONYM REGISTER NAME
ADDRESS
2E00h PIDL Peripheral Identification Register Lower
2E01h PIDU Peripheral Identification Register Upper
2E04h PWREMU_MGMT Power Management and Emulation Register
2E08h GPINT_CTRLL GPINT Control Register Lower
2E09h GPINT_CTRLU GPINT Control Register Upper
2E0Ch GPIO_ENL GPIO Enable Register Lower
2E0Dh GPIO_ENU GPIO Enable Register Upper
2E10h GPIO_DIR1L GPIO Direction Register 1 Lower
2E11h GPIO_DIR1U GPIO Direction Register 1 Upper
2E14h GPIO_DAT1L GPIO Data Register 1 Lower
2E15h GPIO_DAT1U GPIO Data Register 1 Upper
2E1Ch GPIO_DAT2L GPIO Data Register 2 Lower
2E1Dh GPIO_DAT2U GPIO Data Register 2 Upper
2E24h GPIO_DAT3L GPIO Data Register 3 Lower
2E25h GPIO_DAT3U GPIO Data Register 3 Upper
2E30h UHPICL Universal Host-Port Interface Control Register
2E34h UHPIAWL Universal Host-Port Interface Write Address Register Lower
2E35h UHPIAWU Universal Host-Port Interface Write Address Register Upper
2E38h UHPIARL Universal Host-Port Interface Read Address Register Lower
2E39h UHPIARU Universal Host-Port Interface Read Address Register Upper

TMS320C5517
6.2.4.16 USB2.0 Peripheral Register Descriptions

Table 6-30 lists of the USB2.0 peripheral registers.
Table 6-30. Universal Serial Bus (USB) Registers (1)

CPU WORD ACRONYM
REGISTER DESCRIPTION
ADDRESS
8000h REVID1 Revision Identification Register 1
8001h REVID2 Revision Identification Register 2
8004h CTRLR Control Register
800Ch EMUR Emulation Register
8010h MODE1 Mode Register 1
8011h MODE2 Mode Register 2
8014h AUTOREQ Auto Request Register
801Ch TEARDOWN1 Teardown Register 1
801Dh TEARDOWN2 Teardown Register 2
8020h INTSRCR1 USB Interrupt Source Register 1
8021h INTSRCR2 USB Interrupt Source Register 2
8024h INTSETR1 USB Interrupt Source Set Register 1
8025h INTSETR2 USB Interrupt Source Set Register 2
8028h INTCLRR1 USB Interrupt Source Clear Register 1
8029h INTCLRR2 USB Interrupt Source Clear Register 2
802Ch INTMSKR1 USB Interrupt Mask Register 1
802Dh INTMSKR2 USB Interrupt Mask Register 2
8030h INTMSKSETR1 USB Interrupt Mask Set Register 1
8031h INTMSKSETR2 USB Interrupt Mask Set Register 2
8034h INTMSKCLRR1 USB Interrupt Mask Clear Register 1
8035h INTMSKCLRR2 USB Interrupt Mask Clear Register 2
8038h INTMASKEDR1 USB Interrupt Source Masked Register 1
8039h INTMASKEDR2 USB Interrupt Source Masked Register 2
803Ch EOIR USB End of Interrupt Register
8040h INTVECTR1 USB Interrupt Vector Register 1
8041h INTVECTR2 USB Interrupt Vector Register 2
8050h GREP1SZR1 Generic RNDIS EP1Size Register 1
8051h GREP1SZR2 Generic RNDIS EP1Size Register 2
8054h GREP2SZR1 Generic RNDIS EP2 Size Register 1
805Ch GREP4SZR1 Generic RNDIS EP4 Size Register 1
805Dh GREP4SZR2 Generic RNDIS EP4 Size Register 2
(1) Before reading or writing to the USB registers, be sure to set the BYTEMODE bits to "00b" in the USB system control register to enable
word accesses to the USB registers .

TMS320C5517
Table 6-30. Universal Serial Bus (USB) Registers(1) (continued)

CPU WORD ACRONYM
ADDRESS
Common USB Registers
8401h FADDR_POWER Function Address Register, Power Management Register
8402h INTRTX Interrupt Register for Endpoint 0 plus Transmit Endpoints 1 to 4
8405h INTRRX Interrupt Register for Receive Endpoints 1 to 4
8406h INTRTXE Interrupt enable register for INTRTX
8409h INTRRXE Interrupt Enable Register for INTRRX
840Ah INTRUSB_INTRUSBE Interrupt Register for Common USB Interrupts, Interrupt Enable Register
840Dh FRAME Frame Number Register
840Eh Index Register for Selecting the Endpoint Status and Control Registers, Register to
INDEX_TESTMODE
Enable the USB 2.0 Test Modes
USB Indexed Registers
8411h Maximum Packet Size for Peripheral and Host Transmit Endpoint. (Index register set
TXMAXP_INDX
to select Endpoints 1-4)
8412h Control Status Register for Endpoint 0 in Peripheral Mode. (Index register set to
PERI_CSR0_INDX
select Endpoint 0)
Control Status Register for Peripheral Transmit Endpoint. (Index register set to select
PERI_TXCSR_INDX
Endpoints 1-4)
8415h Maximum Packet Size for Peripheral and Host Receive Endpoint. (Index register set
RXMAXP_INDX
to select Endpoints 1-4)
8416h Control Status Register for Peripheral Receive Endpoint. (Index register set to select
PERI_RXCSR_INDX
Endpoints 1-4)
8419h Number of Received Bytes in Endpoint 0 FIFO. (Index register set to select Endpoint
COUNT0_INDX
0)
Number of Bytes in Host Receive Endpoint FIFO. (Index register set to select
RXCOUNT_INDX
Endpoints 1- 4)
841Ah - Reserved
841Dh - Reserved
841Eh CONFIGDATA_INDC Returns details of core configuration. (index register set to select Endpoint 0)
(Upper byte of 841Eh)
USB FIFO Registers
8421h FIFO0R1 Transmit and Receive FIFO Register 1 for Endpoint 0
842Ah FIFO2R2 Transmit and Receive FIFO Register 2 for Endpoint 2
842Dh FIFO3R1 Transmit and Receive FIFO Register 1 for Endpoint 3
842Eh FIFO3R2 Transmit and Receive FIFO Register 2 for Endpoint 3
Dynamic FIFO Control Registers
8461h - Reserved
8462h Transmit Endpoint FIFO Size, Receive Endpoint FIFO Size (Index register set to
TXFIFOSZ_RXFIFOSZ
select Endpoints 1-4)
8465h TXFIFOADDR Transmit Endpoint FIFO Address (Index register set to select Endpoints 1-4)
8466h RXFIFOADDR Receive Endpoint FIFO Address (Index register set to select Endpoints 1-4)
846Dh Hardware Version Register (See TMS320C5517 Digital Signal Processor Technical
HWVERS
Reference Manual [SPRUH16].)

TMS320C5517

CPU WORD ACRONYM
ADDRESS
Control and Status Register for Endpoint 0
8501h - Reserved
8502h PERI_CSR0 Control Status Register for Peripheral Endpoint 0
8505h - Reserved
8506h - Reserved
8509h COUNT0 Number of Received Bytes in Endpoint 0 FIFO
850Ah - Reserved
850Dh - Reserved
CONFIGDATA Returns details of core configuration.
850Eh
(Upper byte of 850Eh)
8511h TXMAXP Maximum Packet Size for Peripheral and Host Transmit Endpoint
8512h PERI_TXCSR Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
8515h RXMAXP Maximum Packet Size for Peripheral and Host Receive Endpoint
8516h PERI_RXCSR Control Status Register for Peripheral Receive Endpoint (peripheral mode)
8519h RXCOUNT Number of Bytes in the Receiving Endpoint's FIFO
851Ah - Reserved
851Dh - Reserved
851Eh - Reserved
8529h RXCOUNT Number of Bytes in Host Receive endpoint FIFO
852Ah - Reserved
852Dh - Reserved
852Eh - Reserved
853Ah - Reserved
853Dh - Reserved
853Eh - Reserved
854Ah - Reserved
854Dh - Reserved
854Eh - Reserved

TMS320C5517

CPU WORD ACRONYM
ADDRESS
CPPI DMA (CMDA) Registers
9000h DMAREVID1 CDMA Revision Identification Register 1
9001h DMAREVID2 CDMA Revision Identification Register 2
9004h TDFDQ CDMA Teardown Free Descriptor Queue Control Register
9008h DMAEMU CDMA Emulation Control Register
9800h TXGCR1[0] Transmit Channel 0 Global Configuration Register 1
9808h RXGCR1[0] Receive Channel 0 Global Configuration Register 1
980Ch RXHPCR1A[0] Receive Channel 0 Host Packet Configuration Register 1 A
980Dh RXHPCR2A[0] Receive Channel 0 Host Packet Configuration Register 2 A
9810h RXHPCR1B[0] Receive Channel 0 Host Packet Configuration Register 1 B
A000h DMA_SCHED_CTRL1 CDMA Scheduler Control Register 1
A001h DMA_SCHED_CTRL2 CDMA Scheduler Control Register 1
A800h + 4 × N ENTRYLSW[N] CDMA Scheduler Table Word N Registers LSW (N = 0 to 63)
A801h + 4 × N ENTRYMSW[N] CDMA Scheduler Table Word N Registers MSW (N = 0 to 63)

TMS320C5517

CPU WORD ACRONYM
ADDRESS
Queue Manager (QMGR) Registers
C000h QMGRREVID1 Queue Manager Revision Identification Register 1
C001h QMGRREVID2 Queue Manager Revision Identification Register 2
C008h DIVERSION1 Queue Manager Queue Diversion Register 1
C009h DIVERSION2 Queue Manager Queue Diversion Register 2
C020h FDBSC0 Queue Manager Free Descriptor and Buffer Starvation Count Register 0
C02Ch FDBSC6 Queue Manager Free Descriptor and Buffer Starvation Count Register 6
C02Dh FDBSC7 Queue Manager Free Descriptor and Buffer Starvation Count Register 7
C080h LRAM0BASE1 Queue Manager Linking RAM Region 0 Base Address Register 1
C084h LRAM0SIZE Queue Manager Linking RAM Region 0 Size Register
C085h - Reserved
C090h PEND0 Queue Manager Queue Pending 0
D000h + 16 × R QMEMRBASE1[R] Queue Manager Memory Region R Base Address Register 1 (R = 0 to 15)
D001h + 16 × R QMEMRBASE2[R] Queue Manager Memory Region R Base Address Register 2 (R = 0 to 15)
D004h + 16 × R QMEMRCTRL1[R] Queue Manager Memory Region R Control Register 1 (R = 0 to 15)
D005h + 16 × R QMEMRCTRL2[R] Queue Manager Memory Region R Control Register 2 (R = 0 to 15)
E000h + 16 × N CTRL1A Queue Manager Queue N Control Register 1A (N = 0 to 63)
E001h + 16 × N CTRL2A Queue Manager Queue N Control Register 2A (N = 0 to 63)
E004h + 16 × N CTRL1B Queue Manager Queue N Control Register 1B (N = 0 to 63)
E005h + 16 × N CTRL2B Queue Manager Queue N Control Register 2B (N = 0 to 63)
E008h + 16 × N CTRL1C Queue Manager Queue N Control Register 1C (N = 0 to 63)
E009h + 16 × N CTRL2C Queue Manager Queue N Control Register 2C (N = 0 to 63)
E00Ch + 16 × N CTRL1D Queue Manager Queue N Control Register 1D (N = 0 to 63)
E00Dh + 16 × N CTRL2D Queue Manager Queue N Control Register 2D (N = 0 to 63)
E800h + 16 × N QSTAT1A Queue Manager Queue N Status Register 1A (N = 0 to 63)
E801h + 16 × N QSTAT2A Queue Manager Queue N Status Register 2A (N = 0 to 63)
E804h + 16 × N QSTAT1B Queue Manager Queue N Status Register 1B (N = 0 to 63)
E805h + 16 × N QSTAT2B Queue Manager Queue N Status Register 2B (N = 0 to 63)
E808h + 16 × N QSTAT1C Queue Manager Queue N Status Register 1C (N = 0 to 63)
E809h + 16 × N QSTAT2C Queue Manager Queue N Status Register 2C (N = 0 to 63)

TMS320C5517
6.3 Identification
6.3.1 JTAG Identification
Table 6-31. JTAG Identification Register

CPU WORD ADDRESS ACRONYM REGISTER NAME COMMENTS
Read-only. Provides 32-bit
N/A JTAGID JTAG Identification Register
JTAG ID of the device.
The JTAG ID register is a read-only register that identifies to the customer the JTAG and Device ID. The
register hex value for the device is: 0x0B95 602F. For the actual register bit names and their associated
bit field descriptions, see Figure 6-2 and Table 6-32.
31-28 27-12 11-1 0

VARIANT (4-Bit) PART NUMBER (16-Bit) MANUFACTURER (11-Bit) LSB
R-0000 R-1011 1001 0101 0110 R-0000 0010 111 R-1
LEGEND: R = Read, W = Write, n = value at reset
Figure 6-2. JTAG ID Register Description - Register Value - 0x0B95 602F
Table 6-32. JTAG Identification Register Selection Bit Descriptions

BIT NAME DESCRIPTION
31:28 VARIANT Variant (4-Bit) value: 0000
27:12 PART NUMBER Part Number (16-Bit) value: 1011 1001 0101 0110
11:1 MANUFACTURER Manufacturer (11-Bit) value: 0000 0010 111
0 LSB LSB. This bit is read as a "1".

TMS320C5517
6.4 Boot Modes

The device supports the following boot modes:
• NOR Flash
• NAND Flash
• SPI 16- and 24-bit EEPROM or Flash
• I2C 16-bit EEPROM
• eMMC Controller/MMC/SD/SDHC Card
• USB
• UART
• McSPI
• UHPI
The boot mode or method is determined by checking the value of the BootMode[5:0] bits in the BootMode
register ([1C34h]) and the CLKSELSTAT bit in the CCR2 register ([1C1Fh]), which reflect the
configurations of the EM_A[20:15] or GP[26:21] pins and CLK_SEL pin at reset. See Section 5.7.3.4.2,
BootMode Implementation and Requirements.
Figure 6-3. BootMode Register [1C34h]

15 11 10 5 4 0
Reserved BootMode[5:0] Reserved
R-0 R-EM_A[20:15]/GP[26:21] R-0
Table 6-33. BootMode Register Field Descriptions

15:11 Reserved Reserved
Read-only bits that reflect the latched state of the EM_A[20:19] or GP[26:25] pins on the 10th clock
edge after RESET pin goes high. (1) The Bootloader reads this register value to determine the
frequency of the clock input to the system clock generator. The bootloader requires this frequency
to appropriately program the system clock generator and other peripheral clock dividers.
00:
CLK_SEL = 0: 12 MHz via the on-chip USB oscillator
CLK_SEL = 1: 11.2896 MHz via the CLK_IN pin
01:
10:9 BootMode[5:4]
CLK_SEL = 1: 12.00 MHz or 12.288 MHz via the CLK_IN pin
10:
11:
(1) The RESET pin is asynchronous to the selected system clock (CLKIN or USB_OSC). The pin could be 10, 11, or even 12 clock cycles
after the rising edge of RESETN due to possible metastability.
TMS320C5517
Table 6-33. BootMode Register Field Descriptions (continued)

Read-only bits that reflect the latched state of the EM_A[18:15] or GP[24:21] pins on the first clock
edge after RESET pin goes high. The Bootloader determines boot mode based on this value.
0000: Boot mode: 16-bit NOR flash data boot, system clock generator is in bypass mode.
0001: Boot mode: 16-bit or 8-bit NAND flash data boot, system clock generator is in bypass mode.
0010: Boot mode: UART 9600 baud boot, system clock generator output = input clock x 3
0101: Boot mode: SPI 16-bit or 24-bit address Boot (SPI_CLK < 1 MHz), system clock generator
output = input clock x 3
0110: Boot mode: SPI 16-bit or 24-bit address Boot (SPI_CLK < 10 MHz), system clock generator
output = input clock x 3
0111: Polling Mode 2: Check for valid boot image from peripherals in the following order: NOR,
8:5 BootMode[3:0] NAND, SPI, I2C, SD/SDHC/MMC/eMMC Controller 0, McSPI, and UART/USB (infinite retry). (2)
1000: Boot mode: I2C 16-bit address Boot, 400 kHz, system clock generator is in bypass mode.
1001: Boot mode: SD or SDHC, MMC, or eMMC Controller 0 card boot, system clock generator is
in bypass mode
1010: Boot mode: SD or SDHC, MMC, or eMMC Controller 1 card boot, system clock generator is
in bypass mode
1011: Polling Mode 1: Check for valid boot image from peripherals in the following order: NOR,
NAND, SPI, I2C, SD/SDHC/MMC/eMMC Controller 0, SD/SDHC/MMC/eMMC Controller 1, and
UART/USB (infinite retry). (2)
1100: Boot mode: UHPI 16-bit multiplexed mode boot, system clock generator output = input clock
x3
1101: Boot mode: McSPI 24-bit address serial flash at 10-MHz mode
1110: Boot mode: McSPI 24-bit address serial flash at 40-MHz mode
1111: Boot mode: USB boot, system clock generator output = input clock x 3
4:0 Reserved Reserved
(2) If MMCx_CMD is low, the bootloader continues to check for a valid boot image in the card controller. MMCx_CMD must be high or
toggle in order to move from the card controller to the next peripheral for a valid boot image.

TMS320C5517
Figure 6-4. Clock Configuration Register 2 (CCR2) [1C1Fh]

15 6 5 4 3 2 1 0
Reserved Reserved Reserved CLKSELSTAT Reserved SYSCLKSEL
R-0 R-x R/W-0 R-0 R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -x = value undetermined
Table 6-34. Clock Configuration Register 2 (CCR2) Field Descriptions

BIT NAME VALUE DESCRIPTION
15:6 RESERVED 0 Reserved
5:4 RESERVED 0 Reserved
3 RESERVED 0 Reserved. This bit must be written to 0.
CLK_SEL pin status bit. This reflects the state of the CLK_SEL pin.
2 CLKSELSTAT 0 CLK_SEL pin is low (USB Oscillator clock selected).
1h CLK_SEL pin is high (CLKIN input clock selected).
1 RESERVED 0 Reserved. This bit must be written to 0.
System clock source select bit. This bit is used to select between the two main clocking modes
for the DSP: bypass and PLL mode.
In bypass mode, the system clock generator is bypassed and the system clock is set to either
0 SYSCLKSEL CLKIN or the USB oscillator output (as determined by the CLKSEL pin).
In PLL mode, the system clock is set to the output of the system clock generator.
0 Bypass mode is selected.
1 PLL mode is selected.

TMS320C5517
6.4.1 Invocation Sequence

The boot sequence is a process by which the device's on-chip memory is loaded with program and data
sections from an external image file (in flash memory, for example). The boot sequence also allows,
optionally, for some of the device's internal registers to be programmed with predetermined values. The
boot sequence is started automatically after each device reset. For more details on device reset, see
Section 5.7.3, Reset.
This device can boot from EMIF, UART, SPI, I2C, eMMC, MMC, SD, SDHC, UHPI, McSPI, or USB
interface. For a complete description of the boot options, see Using the TMS320C5517 Bootloader
[literature number SPRABP1].
The peripheral interface that the device boots from is determined by the configuration of the EM_A[20:15]
or GP[26:21] pins at reset. The values of EM_A[20:15] or GP[26:21] are latched at reset into the
BootMode[5:0] bits in the BootMode register (1C34h) and the Bootloader reads the bits to determine a
peripheral interface for booting.
The on-chip Bootloader allows the DSP registers to be configured during the boot process, if the optional
register configuration section is present in the boot image. For more information on the boot modes
supported, see Section 6.4, Boot Modes.
See Figure 6-5, Boot Timing, and the notes at the bottom of the figure, for an illustration of the boot
sequence.
POWERGOOD
(internal)
(3)
RESETN (1)
(2)
(POWERGOOD &&
RESETN)
(internal)
CLKIN or
USB_Osc
System Reset
(internal)
(DSP & Periphs)
22 clocks

(1) Enter the boot sequence described in boot sequence Step 1.
(2) The maximum wait time from reset between (1) and (2) until the reset is released is 20 ms.
(3) The bootloaded code starts. The best-case time is 200 ms from the start of the boot sequence (see note 2) due to the BG_CAP
settling time in Step 18. The worst-case time is the loading time for the bootloaded code when it exceeds 200 ms.
Figure 6-5. Boot Timing

TMS320C5517
The device bootloader follows the following steps:

1. Immediately after reset, the CPU fetches the reset vector from 0xFFFF00. MP or MC is 0 by default, so
0xFFFF00 is mapped to internal ROM. The PLL is in bypass mode. The input clock is assumed to be
in the range of 11.2896–19.2 MHz.
2. Set CLKOUT slew rate control to slow slew rate.
3. Idle all peripherals and HWA.
4. Apply manufacturing trim to the bandgap references.
5. Disable CLKOUT.
6. The Bootloader configures the system clock generator based on boot mode (see Section 6.4, Boot
Modes, for details on boot mode) and enables TIMER0 to count the settling time of BG_CAP.
Bootloader will try this main loop infinitely if it cannot get the correct boot signature.
[Main Loop]
7. If McSPI boot, test for 24-bit McSPI flash boot on SPI_CS[0] using a clock-rate close to, but not over,
10 MHz, or a clock-rate close to, but not over, 40 MHz based on the boot mode. Set Serial Port 1
Mode on the External Bus Selection Register to 1:
(a) Check the first two bytes read from the boot table for a boot signature match using 24-bit address
mode.
(b) If the boot signature is not valid, go to step 18.
(c) Set Register Configuration, if present in boot image.
(d) Attempt McSPI Serial Memory boot and go to step 19.
8. If UHPI boot, the external host has to communicate in 16-bit multiplexed mode:
Note: The bootloader sets up the UHPI slave to handshake with an external UHPI master.
(a) The external host power up the device and must wait for the settling time of BG_CAP to elapse
before executing the next step.
(b) The bootloader waits for the external host to finish transferring the data.
(c) External Host writes to device on-chip memory. The code or data sections are directly loaded to
the desired locations on device by the external host.
(d) External Host interrupts the device through the DSP_INT in the UHPIC register after code transfer
complete.
(e) Bootloader branches to the entry point. The entry point is located in the last block of SARAM, word
addresses 0x27FFA and 0x27FFB. To ensure data integrity, the external host writes two 16-bit
signatures in 0x27FFC and 0x27FFD with respective values of 0x1234 and 0xABCD. If the
address of the entry point is in DARAM space or incorrect signatures are detected in 0x27FFC and
0x27FFD, go to step 18.
(f) Go to step 19.
9. If NOR boot, test for NOR boot on all asynchronous CS spaces (EM_CS[2:5]) with 16-bit access:
Note: The booatloader requires NOR flash that supports a reset command (0xF0 on data).
(a) Check the first 2 bytes read from boot signature.
(d) Attempt NOR boot and go to step 19.
10. If NAND boot, test for NAND boot on all asynchronous CS spaces (EM_CS[2:5]) with 16-bit access:
(a) Check the first 2 bytes read from boot table for a boot signature match. If the boot signature is not
valid, read the first 2 bytes again using 8-bit access on all asynchronous CS spaces (EM_CS[2:5])
(b) If the boot signature is still not valid, go to step 18.
(d) Attempt NAND boot and go to step 19.

TMS320C5517
11. If SPI boot, test for 16- and 24-bit SPI EEPROM or Flash boot on SPI_CS[0] using a clock-rate close
to, but not over, 1 MHz, or a clock-rate close to, but not over, 10 MHz based on the boot mode. Set
Parallel Port Mode on the External Bus Selection Register to 5, then set to 6:
(a) Check the first 2 bytes read from boot table for a boot signature match using 16-bit address mode.
(b) If the boot signature is not valid, read the first 2 bytes again using 24-bit address mode.
(c) If the boot signature is not valid from either case (16-bit and 24-bit address modes), go to step 18.
(d) Set Register Configuration, if present in boot image.
(e) Attempt SPI Serial Memory boot and go to step 19.
12. If I2C boot, test for 16-bit I2C EEPROM boot with a 7-bit slave address 0x50 and 400-kHz clock rate.
(a) Check the first 2 bytes read from boot table for a boot signature match using 16-bit address mode.
(d) Attempt I2C EEPROM boot and go to step 19.
13. If eMMC, MMC, SD, or SDHC Controller 0 boot, program SD0 and search for the filename
“bootimg.bin" under the first partition’s root directory. For SD or SDHC, the device must comply with
SD/SDHC specification v1.1 or v2.0 for FAT16 or FAT32 using SD or SDHC unsecure mode.
If eMMC, the bootloader will check the boot partition for a bootable image before checking the root
directory for "bootimg.bin". For eMMC or MMC, the device must comply with eMMC/MMC specification
v4.3 for FAT32 using eMMC or MMC nonencrypted mode.
(a) Check the first 2 bytes read from boot table for a boot signature match.
(d) Attempt eMMC, MMC, SD, or SDHC boot and go to step 19.
14. If eMMC, MMC, SD, or SDHC Controller 1 boot, program SD1 and search for the filename
“bootimg.bin" under the first partition’s root directory. For SD or SDHC, the device must comply with
SD/SDHC specification v1.1 or v2.0 for FAT16 or FAT32 using SD or SDHC unsecure mode.
If eMMC, the bootloader will check the boot partition for a bootable image before checking the root
directory for "bootimg.bin". For eMMC or MMC the device must comply with eMMC/MMC specification
v4.3 for FAT32 using eMMC or MMC nonencrypted mode.
Note: Do not boot from eMMC if no valid image is present. Booting from eMMC without a valid image
will put the card into an inactive state.
(a) Check the first two bytes read from boot table for a boot signature match.
(d) Attempt eMMC, MMC, SD, or SDHC boot and go to step 19.
15. If UART boot, set PLL to multiply the input clock by 3 and adjust TIMER0 for the settling time of
BG_CAP. Program UART with 9600-, 57600-, or 115200-baud based on boot mode, 8-bit data, odd
parity, one stop-bit, and auto flow control using CTS or RTS:
(b) If the boot signature is not valid, return to the beginning of step 15.
(c) Attempt UART boot and go to step 19.

TMS320C5517
16. If USB boot, set PLL to multiply the input clock by 3 and adjust TIMER0 for the settling time of
BG_CAP. Use USB on endpoint 1. The device has vendor-ID 0x0451 and product-ID 0x9010 and uses
Bulk Endpoint 1 OUT to receive the boot image from the USB host:
(b) If the boot signature is not valid, return to the beginning of step 16.
(c) Attempt USB boot and go to step 19.
17. If polling mode, there is a fixed order of supported boot devices on which a valid image is checked.
– Polling Mode 1:
(a) NOR
(b) NAND
(c) SPI
(d) I2C
(e) SD/SDHC, MMC/eMMC Controller 0 (see note below)
(f) SD/SDHC, MMC/eMMC Controller 1 (see note below)
(g) UART/USB
– Polling Mode 2:
(a) NOR
(b) NAND
(c) SPI
(d) I2C
(e) SD/SDHC, MMC/eMMC Controller 0 (see note below)
(f) McSPI
(g) UART/USB
The first device with a valid boot image is used to load and execute user code. If none of these
devices has a valid boot image, the bootloader modifies the CPU clock setup as follows:
– If CLK_SEL=0, the bootloader powers up the PLL and sets its frequency to 36 MHz (12 MHz
multiplied by 3).
– If CLK_SEL=1, the bootloader powers up the PLL and sets it to multiply CLKIN by 3.
This change in the CPU clock setup is required to meet the minimum frequency needed by the USB
module. After the CPU clock setup changes, the bootloader enters an endless loop and checks for
data received on the UART/USB. If a valid boot image is received, the image is used to load and
execute user code. If no valid boot image is received, the bootloader continues to monitor the boot
devices. If the time since the trim setup exceeds 200 ms during this endless loop, the bootloader re-
enables the low-voltage detection circuit to ensure the circuit is not disabled for an extended period.
Note: If MMCx_CMD is low, the bootloader continues to check for a valid boot image in the card
controller. MMCx_CMD must be high or toggle in order to move from the card controller to the next
peripheral for a valid boot image.
18. If the boot signature is not valid, toggle XF when the retry count reaches 100.
19. Copy the boot image sections to system memory. Then set the XF port low to indicate that boot-up is
complete. Ensure the settling time of BG_CAP has elapsed since step 6 before proceeding to execute
the bootloaded code.
20. Jump to the specified entry point.
6.4.2 DSP Resources Used By the Bootloader

The Bootloader uses SARAM block 31 for the storing of temporary data. This block of memory is reserved
during the boot process. However, after the boot process is complete, it can be used by the user
application.

TMS320C5517
7 Device and Documentation Support

7.1 Device Support
7.1.1 Development Support

TI offers an extensive line of development tools for the TMS320C55x DSP platform, including tools to
evaluate the performance of the processors, generate code, develop algorithm implementations, and fully
integrate and debug software and hardware modules. The tool's support documentation is electronically
available within the Code Composer Studio Integrated Development Environment (IDE).
The following products support development of TMS320C55x fixed-point DSP-based applications:
Software Development Tools:
Code Composer Studio Integrated Development Environment (IDE): Version 5.5.0 or later
C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP/BIOS Version 5.33 or later), which provides the basic
run-time target software needed to support any DSP application.
Hardware Development Tools:
Extended Development System ( XDS™) Emulator
For a complete listing of development-support tools for the TMS320C55x DSP platform, visit the Texas
Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For
information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
7.1.2 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX,
TMP, or TMS (for example, TMS320C5517AZCHA20). Texas Instruments recommends two of three
possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary
stages of product development from engineering prototypes (TMX or TMDX) through fully qualified
production devices or tools (TMS or TMDS).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device's electrical
specifications.
TMP Final silicon die that conforms to the device's electrical specifications but has not completed
quality and reliability verification.
TMS Fully-qualified production device.
Support tool development evolutionary flow:

TMDX Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS Fully qualified development-support product.
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
190 Device and Documentation Support Copyright © 2012–2014, Texas Instruments Incorporated
TMS320C5517
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, ZCH), and the temperature range (for example, "Blank" is the commercial
temperature range).
Figure 7-1 provides a legend for reading the complete device name for any DSP platform member.
TMS 320 C 5517 A ZCH 20
PREFIX DEVICE MAXIMUM OPERATING FREQUENCY

TMX = Experimental device 20 = 75 MHz at 1.05 V, 175 MHz at 1.3 V, 200 MHz at 1.4 V
TMS = Qualified device
DEVICE FAMILY
320 = TMS320™ DSP family TEMPERATURE RANGE
Blank = –10° C to 70° C, Commercial Temperature
TECHNOLOGY A = –40° C to 85° C, Industrial Temperature
C = Dual-supply CMOS
PACKAGE TYPE
DEVICE
ZCH = 196-pin plastic BGA, with Pb-Free
C55x™ DSP: 5517
soldered balls [Green]
SILICON REVISION
A = Revision 2.1
A. For actual device part numbers (P/Ns) and ordering information, see the TI website (http://www.ti.com)
Figure 7-1. Device Nomenclature
Copyright © 2012–2014, Texas Instruments Incorporated Device and Documentation Support 191
TMS320C5517
7.2 Documentation Support
7.2.1 Related Documentation

The following documents describe the DSP. To access the documents, click the literature number (e.g.,
SPRUH16) or wiki link.
The current documentation that describes the DSP, related peripherals, and other technical collateral, is
available in the product folder at www.ti.com.
SPRUH16 TMS320C5517 Digital Signal Processor Technical Reference Manual. Collection of
documents providing detailed information on the device including system control, FFT
implementation, and memory access. Detailed information on the device as well as a
functional description of the peripherals supported is also included.
SPRZ383 TMS320C5517 Fixed-Point Digital Signal Processor Silicon Errata. Describes the known
exceptions to the functional specifications for this device.
SPRABP1 Using the TMS320C5517 Bootloader. Describes features of the on-chip ROM for this
device, as well as descriptions of how to interface with possible boot devices and generating
a boot image to store on an external device.
SWPU073 TMS320C55x DSP v3.x CPU Reference Guide. Describes more detailed information on the
C55x CPU.
Wiki C5505/15/35 Schematic Checklist. Describes recommendations for the device applicable to
unused pins, clocking, power, reset, and peripherals. Description also includes critical
connections, DDR2 routing checklist, and debug considerations, and more.
7.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help
developers get started with Embedded Processors from Texas Instruments and to foster
innovation and growth of general knowledge about the hardware and software surrounding
these devices.
7.4 Trademarks
C5000, eXpressDSP, Code Composer Studio, DSP/BIOS, RTDX, XDS510, XDS560, XDS, E2E are
trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
7.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
7.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
192 Device and Documentation Support Copyright © 2012–2014, Texas Instruments Incorporated
TMS320C5517
8 Mechanical Packaging and Orderable Information

The following packaging information and addendum reflect the most current data available for the
designated device. This data is subject to change without notice and without revision of this document.
Copyright © 2012–2014, Texas Instruments Incorporated Mechanical Packaging and Orderable Information 193
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TMS320C5517AZCH20 ACTIVE NFBGA ZCH 196 184 RoHS & Green SNAGCU Level-3-260C-168 HR -10 to 70 17AZCH20
TMS320C5517AZCHA20 ACTIVE NFBGA ZCH 196 184 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 17AZCHA20
TMS32C5517AZCHA20R ACTIVE NFBGA ZCH 196 1000 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 17AZCHA20
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE AND DISCLAIMER
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TMS320C5517 Fixed-Point Digital Signal Processor

2 Device Overview Copyright © 2012–2014, Texas Instruments Incorporated

Copyright © 2012–2014, Texas Instruments Incorporated Device Overview 3

1.4 Functional Block Diagram

JTAG Interface C55x DSP CPU

Input PLL/Clock FFT Hardware

Power 64KB DARAM

Switched Central Resource (SCR)

DMA I2S 10-Bit

Connectivity Program/Data Storage System

Figure 1-1. Functional Block Diagram

4 Device Overview Copyright © 2012–2014, Texas Instruments Incorporated

Copyright © 2012–2014, Texas Instruments Incorporated Table of Contents 5

6 Revision History Copyright © 2012–2014, Texas Instruments Incorporated

Table 3-1. Characteristics of the Processor

2 32-Bit General-Purpose (GP) Timers

Table 3-1. Characteristics of the Processor (continued)

8 Device Comparison Copyright © 2012–2014, Texas Instruments Incorporated

4 Terminal Configuration and Functions

I2S2_FS/ I2S2_DX/ UART_CTS/ UART_TXD/

I2S2_CLK/ I2S2_RX/ UART_RTS/ UART_RXD/

MMC0_D1/ MMC0_CMD/ MMC1_D1/ MMC1_CLK/ MMC1_D0/

MMC0_D0/ MMC0_CLK/ MMC0_D3/

EM_A[12]/ EM_A[11]/ MMC1_D2/

USB_ USB_ USB_ USB_

EM_WAIT2 RTC_ VSSA_PLL GPAIN0 DSP_ RSV16 RSV3

Figure 4-1. Pin Diagram

Copyright © 2012–2014, Texas Instruments Incorporated Terminal Configuration and Functions 9

4.2 Signal Descriptions

10 Terminal Configuration and Functions Copyright © 2012–2014, Texas Instruments Incorporated

4.2.1 Oscillator and PLL

Copyright © 2012–2014, Texas Instruments Incorporated Terminal Configuration and Functions 11

4.2.2 Real-Time Clock (RTC)

Real-time clock output pin. This pin operates at DVDDRTC voltage.

12 Terminal Configuration and Functions Copyright © 2012–2014, Texas Instruments Incorporated

4.2.3 RESET, Interrupts, and JTAG

Table 4-3. RESET, Interrupts, and JTAG Signal Descriptions (continued)

14 Terminal Configuration and Functions Copyright © 2012–2014, Texas Instruments Incorporated

Table 4-3. RESET, Interrupts, and JTAG Signal Descriptions (continued)

IPU An external pullup to DVDDIO is required to provide a signal rise time of

Copyright © 2012–2014, Texas Instruments Incorporated Terminal Configuration and Functions 15

4.2.4 External Memory Interface (EMIF)

Table 4-4. EMIF Signal Descriptions

Table 4-4. EMIF Signal Descriptions (continued)

This pin is the EMIF external address pin 14.

This pin is the EMIF external address pin 13.

This pin is the EMIF external address pin 10.

This pin is the EMIF external address pin 9.

This pin is the EMIF external address pin 8.

This pin is the EMIF external address pin 7.

Copyright © 2012–2014, Texas Instruments Incorporated Terminal Configuration and Functions 17

Table 4-4. EMIF Signal Descriptions (continued)

This pin is the EMIF external address pin 6.

This pin is the EMIF external address pin 5.

This pin is the EMIF external address pin 4.

This pin is the EMIF external address pin 3.

This pin is the EMIF external address pin 2.