70005144e 1314001 PDF

dsPIC33EVXXXGM00X/10X FAMILY
16-Bit, 5V Digital Signal Controllers with

PWM, SENT, Op Amps and Advanced Analog Features
Operating Conditions PWM
• 4.5V to 5.5V, -40°C to +85°C, DC to 70 MIPS • Up to Six Pulse-Width Modulation (PWM) Outputs
• 4.5V to 5.5V, -40°C to +125°C, DC to 60 MIPS (three generators)
• 4.5V to 5.5V, -40°C to +150°C, DC to 40 MIPS • Primary Master Time Base Inputs allow
Time Base Synchronization from Internal/External
Core: 16-Bit dsPIC33E CPU Sources
• Dead Time for Rising and Falling Edges
• Code-Efficient (C and Assembly) Architecture • 7.14 ns PWM Resolution
• 16-Bit Wide Data Path • PWM Support for:
• Two 40-Bit Wide Accumulators - DC/DC, AC/DC, inverters, Power Factor
• Single-Cycle (MAC/MPY) with Dual Data Fetch Correction (PFC) and lighting
• Single-Cycle, Mixed-Sign MUL plus Hardware - Brushless Direct Current (BLDC), Permanent
Divide Magnet Synchronous Motor (PMSM),
• 32-Bit Multiply Support AC Induction Motor (ACIM), Switched
• Intermediate Security for Memory: Reluctance Motor (SRM)
- Provides a Boot Flash Segment in addition to - Programmable Fault inputs
the existing General Flash Segment - Flexible trigger configurations for
• Error Code Correction (ECC) for Flash Analog-to-Digital conversion
• Added Two Alternate Register Sets for Fast - Supports PWM lock, PWM output chopping
Context Switching and dynamic phase shifting
Clock Management Advanced Analog Features

• Internal, 15% Low-Power RC (LPRC) – 32 kHz • ADC module:
• Internal, 1% Fast RC (FRC) – 7.37 MHz - Configurable as 10-bit, 1.1 Msps with
• Internal, 10% Backup FRC (BFRC) – 7.37 MHz four S&H or 12-bit, 500 ksps with one S&H
• Programmable PLLs and Oscillator Clock Sources - Up to 36 analog inputs
• Fail-Safe Clock Monitor (FSCM) • Flexible and Independent ADC Trigger Sources
• Additional FSCM Source (BFRC), Intended to • Up to Four Op Amp/Comparators with Direct
Provide a Clock Fail Switch Source for the Connection to the ADC module:
System Clock - Additional dedicated comparator and
• Independent Watchdog Timer (WDT) 7-bit Digital-to-Analog Converter (DAC)
• System Windowed Watchdog Timer (DMT) - Two comparator voltage reference outputs
• Fast Wake-up and Start-up - Programmable references with 128 voltage
points
Power Management - Programmable blanking and filtering
• Charge Time Measurement Unit (CTMU):
• Low-Power Management modes (Sleep, Idle - Supports mTouch® capacitive touch sensing
and Doze)
- Provides high-resolution time
• Power Consumption Minimized Executing measurement (1 ns)
NOP String
- On-chip temperature measurement
• Integrated Power-on Reset (POR) and Brown-out
- Temperature sensor diode
Reset (BOR)
- Nine sources of edge input triggers (CTED1,
• 0.5 mA/MHz Dynamic Current (typical)
CTED2, OCPWM, TMR1, SYSCLK, OSCLK,
• 50 µA at +25°C IPD Current (typical) FRC, BFRC and LPRC)
 2013-2016 Microchip Technology Inc. DS70005144E-page 1

Timers/Output Compare/Input Capture Input/Output

• Nine General Purpose Timers: • GPIO Registers to Support Selectable
- Five 16-bit and up to two 32-bit Slew Rate I/Os
timers/counters; Timer3 can provide ADC • Peripheral Pin Select (PPS) to allow Function
trigger Remap
• Four Output Compare modules Configurable as • Sink/Source: 8 mA or 12 mA, Pin-Specific for
Timers/Counters Standard VOH/VOL
• Four Input Capture modules • Selectable Open-Drain, Pull-ups and Pull-Downs
• Change Notice Interrupts on All I/O Pins
Communication Interfaces
• Two Enhanced Addressable Universal
Qualification and Class B Support
Asynchronous Receiver/Transmitter (UART) • AEC-Q100 REVG (Grade 1: -40°C to +125°C)
modules (6.25 Mbps): Compliant
- With support for LIN/J2602 bus and IrDA® • AEC-Q100 REVG (Grade 0: -40°C to +150°C)
- High and low speed (SCI) Compliant
• Two SPI modules (15 Mbps): • Class B Safety Library, IEC 60730
- 25 Mbps data rate without using PPS
• One I2C module (up to 1 Mbaud) with SMBus Class B Fault Handling Support
Support
• Backup FRC
• Two SENT J2716 (Single-Edge Nibble
• Windowed WDT uses LPRC
Transmission-Transmit/Receive) module for
Automotive Applications • Windowed Deadman Timer (DMT) uses System
Clock (System Windowed Watchdog Timer)
• One CAN module:
• H/W Clock Monitor Circuit
- 32 buffers, 16 filters and three masks
• Oscillator Frequency Monitoring through CTMU
(OSCI, SYSCLK, FRC, BFRC, LPRC)
Direct Memory Access (DMA)
• Dedicated PWM Fault Pin
• 4-Channel DMA with User-Selectable Priority • Lockable Clock Configuration
Arbitration
• UART, Serial Peripheral Interface (SPI), ADC, Debugger Development Support
Input Capture, Output Compare and Controller
Area Network (CAN) • In-Circuit and In-Application Programming
• Three Complex and Five Simple Breakpoints
• Trace and Run-Time Watch
DS70005144E-page 2  2013-2016 Microchip Technology Inc.

dsPIC33EVXXXGM00X/10X PRODUCT FAMILIES
 2013-2016 Microchip Technology Inc.
The device names, pin counts, memory sizes and peripheral availability of each device are listed in Table 1. The following pages show the devices’ pinout diagrams.
TABLE 1: dsPIC33EVXXXGM00X/10X FAMILY DEVICES
General Purpose I/O (GPIO)

Peripheral Pin Select (PPS)
Program Memory Bytes
Op Amp/Comparators
External Interrupts
16-Bit Timers (T1)
Output Compare
DMA Channels
10/12-Bit ADC
Input Capture
32-Bit Timers
SRAM Bytes
ADC Inputs
Packages
Security
CTMU
UART
SENT
PWM
CAN
Pins
SPI
I2C
Device
dsPIC33EV32GM002 0
32K 4K
dsPIC33EV32GM102 1
dsPIC33EV64GM002 0
64K 8K
dsPIC33EV64GM102 1 SPDIP, SOIC,
4 5 2 4 4 3x2 2 2 1 2 1 11 3/4 1 Intermediate Y 21 3 28
dsPIC33EV128GM002 0 SSOP, QFN-S
128K 8K
dsPIC33EV128GM102 1
dsPIC33EV256GM002 0
256K 16K
dsPIC33EV256GM102 1
dsPIC33EV32GM004 0
32K 4K
dsPIC33EV32GM104 1
dsPIC33EV64GM004 0
64K 8K
dsPIC33EV64GM104 1
4 5 2 4 4 3x2 2 2 1 2 1 24 4/5 1 Intermediate Y 35 3 44 TQFP, QFN
dsPIC33EV128GM004 0
128K 8K
dsPIC33EV128GM104 1
dsPIC33EV256GM004 0
256K 16K
dsPIC33EV256GM104 1
dsPIC33EV32GM006 0
32K 4K
dsPIC33EV32GM106 1
dsPIC33EV64GM006 0
64K 8K
dsPIC33EV64GM106 1
DS70005144E-page 3
4 5 2 4 4 3x2 2 2 1 2 1 36 4/5 1 Intermediate Y 53 3 64 TQFP, QFN

dsPIC33EV128GM006 0
128K 8K
dsPIC33EV128GM106 1
dsPIC33EV256GM006 0
256K 16K
dsPIC33EV256GM106 1
Pin Diagrams
28-Pin SPDIP/SOIC/SSOP(1,2,3)
MCLR 1 28 AVDD
OA2OUT/AN0/C2IN4-/C4IN3-/RPI16/RA0 2 27 AVSS
OA2IN+/AN1/C2IN1+/RPI17/RA1 3 26 RPI47/PWM1L1/T5CK/RB15
dsPIC33EV128GM002/102
PGED3/OA2IN-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 4 25 RPI46/PWM1H1/T3CK/RB14
PGEC3/OA1OUT/AN3/C1IN4-/C4IN2-/RPI33/CTED1/RB1 5 24 RPI45/PWM1L2/CTPLS/RB13
PGEC1/OA1IN+/AN4/C1IN3-/C1IN1+/C2IN3-/RPI34/RB2 6 23 RPI44/PWM1H2/RB12
PGED1/OA1IN-/AN5/C1IN1-/CTMUC/RP35/RB3 7 22 RP43/PWM1L3/RB11
VSS 8 21 RP42/PWM1H3/RB10
OSC1/CLKI/AN32/RPI18/RA2 9 20 VCAP
OSC2/CLKO/RPI19/RA3 10 19 VSS
FLT32/RP36/RB4 11 18 OA5IN-/AN27/C5IN1-/ASDA1/SDI1/RP41/RB9
OA5IN+/AN24/C5IN3-/C5IN1+/RP20/T1CK/RA4 12 17 AN26/CVREF1O/ASCL1/SDO1/RP40/T4CK/RB8
VDD 13 16 OA5OUT/AN25/C5IN4-/C4IN1+/SCK1/RP39/INT0/RB7
PGED2/SDA1/RP37/RB5 14 15 PGEC2/SCL1/RP38/RB6
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.5 “Peripheral
Pin Select (PPS)” for available peripherals and information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: If the op amp is selected when OPAEN (CMxCON<10>) = 1, the OAx input is used; otherwise, the ANx input is
used.

Pin Diagrams (Continued)
28-Pin QFN-S(1,2,3,4)
OA2OUT/AN0/C2IN4-/C4IN3-/RPI16/RA0
OA2IN+/AN1/C2IN1+/RPI17/RA1
RPI46/PWM1H1/T3CK/RB14
RPI47/PWM1L1/T5CK/RB15
MCLR
AVDD
AVSS
28 27 26 25 24 23 22
PGED3/OA2IN-/AN2/C21N1-/SS1/RPI32/CTED2/RB0 1 21 RPI45/PWM1L2/CTPLS/RB13
PGEC3/OA1OUT/AN3/C1IN4-/C4IN2-/RPI33/CTED1/RB1 2 20 RPI44/PWM1H2/RB12
PGEC1/OA1IN+/AN4/C1IN3-/C1IN1+/C2IN3-/RPI34/RB2 3 dsPIC33EV 32GM002/102 19 RP43/PWM1L3/RB11
dsPIC33EV 64GM002/102
PGED1/OA1IN-/AN5/C1IN1-/CTMUC/RP35/RB3 4 dsPIC33EV 128GM002/102 18 RP42/PWM1H3/RB10
VSS 5 dsPIC33EV256GM002/102 17 VCAP
OSC1/CLKI/AN32/RPI18/RA2 6 16 VSS
OSC2/CLKO/RPI19/RA3 7 15 OA5IN-/AN27/C5IN1-/ASDA1/SDI1/RP41/RB9
8 9 10 11 12 13 14
OA 5 IN+/AN24/C5IN3-/C5 IN1+/RP20/T1CK/RA4
OA5OUT/AN25/C5IN4-/C4IN1+/SCK1/RP39/INT0/RB7
PGED2/SDA1/RP37/RB5
PGEC2/SCL1/RP38/RB6
FLT32/RP36/RB4
VDD
AN26/CVREF1O/ASCL1/SDO1/RP40/T4CK/RB8
used.
4: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to
VSS externally.

44-Pin TQFP(1,2,3)
OA5IN+/AN24/C5IN3-/C5IN1+/SDO1/RP20/T1CK/RA4
AN26/CVREF1O/ASCL1/RP40/T4CK/RB8
OA5OUT/AN25/C5IN4-/RP39/INT0/RB7
AN31/CVREF2O/RPI53/RC5
AN30/CVREF+/RPI52/RC4
PGED2/SDA1/RP37/RB5
PGEC2/SCL1/RP38/RB6
AN29/SCK1/RPI51/RC3
AN28/SDI1/RPI25/RA9
VDD
VSS
44
43
42
41
40
39
38
37
36
35
34
OA5IN-/AN27/C5IN1-/ASDA1/RP41/RB9 1 33 FLT32/RP36/RB4
AN53/RP54/RC6 2 32 RPI24/RA8
AN52/RP55/RC7 3 31 OSC2/CLKO/RPI19/RA3
AN51/RP56/RC8 4 30 OSC1/CLKI/AN32/RPI18/RA2
AN54/RP57/RC9 5
dsPIC33EV32GM004/104 29 VSS
VSS 6 dsPIC33EV128GM004/104 28 VDD
VCAP 7 dsPIC33EV256GM004/104 27 OA3IN+/AN8/C3IN3-/C3IN1+/RPI50/U1RTS/BCLK1/FLT3/RC2
RP42/PWM1H3/RB10 8 26 OA3IN-/AN7/C3IN1-/C4IN1-/RP49/RC1
RP43/PWM1L3/RB11 9 25 OA3OUT/AN6/C3IN4-/C4IN4-/C4IN1+/RP48/RC0
RPI44/PWM1H2/RB12 10 24 PGED1/OA1IN-/AN5/C1IN1-/CTMUC/RP35/RB3
RPI45/PWM1L2/CTPLS/RB13 11 23 PGEC1/OA1IN+/AN4/C1IN3-/C1IN1+/C2IN3-/RPI34/RB2
12
13
14
15
16
17
18
19
20
21
22
MCLR
AN56/RA10
AN55/RA7
PGED3/OA2IN-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
PGEC3/OA1OUT/AN3/C1IN4-/C4IN2-/RPI33/CTED1/RB1
AVDD
AVSS
used.

OA5IN+/AN24/C5IN3-/C5IN1+/SDO1/RP20/T1CK/RA4
44-Pin QFN(1,2,3,4)
AN26/CVREF1O/ASCL1/RP40/T4CK/RB8
AN31/CVREF2O/RPI53/RC5
AN30/CVREF+/RPI52/RC4
PGED2/SDA1/RP37/RB5
PGEC2/SCL1/RP38/RB6
AN29/SCK1/RPI51/RC3
AN28/SDI1/RPI25/RA9
VDD
VSS
44 43 42 41 40 39 38 37 36 35 34
OA5IN-/AN27/C5IN1-/ASDA1/RP41/RB9 1 33 FLT32/RP36/RB4
AN53/RP54/RC6 2 32 RPI24/RA8
AN52/RP55/RC7 3 31 OSC2/CLKO/RPI19/RA3
AN51/RP56/RC8 4 30 OSC1/CLKI/AN32/RPI18/RA2
AN54/RP57/RC9 5 dsPIC33EV64GM004/104 29 VSS
VSS 6
dsPIC33EV128GM004/104 28 VDD
VCAP 7 27 OA3IN+/AN8/C3IN3-/C3IN1+/RPI50/U1RTS/BCLK1/FLT3/RC2
RP42/PWM1H3/RB10 8 26 OA3IN-/AN7/C3IN1-/C4IN1-/RP49/RC1
RP43/PWM1L3/RB11 9 25 OA3OUT/AN6/C3IN4-/C4IN4-/C4IN1+/RP48/RC0
RPI44/PWM1H2/RB12 10 24 PGED1/OA1IN-/AN5/C1IN1-/CTMUC/RP35/RB3
RPI45/PWM1L2/CTPLS/RB13 11 23 PGEC1/OA1IN+/AN4/C1IN3-/C1IN1+/C2IN3-/RPI34/RB2
12 13 14 15 16 17 18 19 20 21 22
PGEC3/OA1OUT/AN3/C1IN4-/C4IN2-/RPI33/CTED1/RB1
AN56/RA10
AN55/RA7
PGED3/OA2IN-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
MCLR
AVSS
AVDD
used.
VSS externally.

64-Pin TQFP(1,2,3)
OA5IN-/AN27//C5IN1-/ASDA1/RP41/RB9
RPI45/PWM1L2/CTPLS/RB13
RPI44/PWM1H2/RB12
RP42/PWM1H3/RB10
RP43/PWM1L3/RB11
AN54/RP57/RC9
AN51/RP56/RC8
AN52/RP55/RC7
AN53/RP54/RC6
AN56/RA10
RPI96/RF0
RP70/RD6
RP69/RD5
RP97/RF1
VCAP
VDD
64
63
62
61
60
59
58
57
56
54
53
52
51
50
49
55
AN55/RA7 1 48 AN26/CVREF1O/ASCL1/RP40/T4CK/RB8
RPI46/PWM1H1/T3CK/RB14 2 47 RPI61/RC13
RPI47/PWM1L1/T5CK/RB15 3 46 OA5OUT/AN25/C5IN4-/RP39/INT0/RB7
AN19/RP118/RG6 4 45 AN48/CVREF2O/RPI58/RC10
AN18/RPI119/RG7 5 44 PGEC2/SCL1/RP38/RB6
AN17/RP120/RG8 6 43 PGED2/SDA1/RP37/RB5
MCLR 7 dsPIC33EV32GM006/106 42 RPI72/RD8
AN16/RPI121/RG9 8 dsPIC33EV64GM006/106 41 VSS
VSS 9 dsPIC33EV128GM006/106 40 OSC2/CLKO/RPI63/RC15
VDD 10 dsPIC33EV256GM006/106 39 OSC1/CLKI/AN49/RPI60/RC12
AN10/RPI28/RA12 11 38 VDD
AN9/RPI27/RA11 12 37 AN31/RPI53/RC5
OA2OUT/AN0/C2IN4-/C4IN3-/RPI16/RA0 13 36 AN30/CVREF+/RPI52/RC4
OA2IN+/AN1/C2IN1+/RPI17/RA1 14 35 AN29/SCK1/RPI51/RC3
PGED3/OA2IN-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 15 34 AN28/SDI1/RPI25/RA9
PGEC3/OA1OUT/AN3/C1IN4-/C4IN2-/RPI33/CTED1/RB1 16 33 OA5IN+/AN24/C5IN3-/C5IN1+/SDO1/RP20/T1CK/RA4
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AVDD
VDD
AVSS
OA3IN+/AN8/C3IN3-/C3IN1+/RPI50/U1RTS/BCLK1/FLT3/RC2
AN11/C1IN2-/U1CTS/FLT4/RC11
VSS
AN12/C2IN2-/C5IN2-/U2RTS/BCLK2/FLT5/RE12
AN13/C3IN2-/U2CTS/FLT6/RE13
AN14/RPI94/FLT7/RE14
FLT32/RP36/RB4
PGEC1/OA1IN+/AN4/C1IN3-/C1IN1+/C2IN3-/RPI34/RB2
PGED1/OA1IN-/AN5/C1IN1-/(CTMUC)/RP35/RB3
OA3OUT/AN6/C3IN4-/C4IN4-/C4IN1+/RP48/RC0
RPI24/RA8
OA3IN-/AN7/C3IN1-/C4IN1-/RP49/RC1
used.

64-Pin QFN(1,2,3,4)
OA5IN-/AN27/C5IN1-/ASDA1/RP41/RB9
RPI45/PWM1L2/CTPLS/RB13
RPI44/PWM1H2/RB12
RP42/PWM1H3/RB10
RP43/PWM1L3/RB11
AN54/ RP57/RC9
AN51/RP56/RC8
AN52/RP55/RC7
AN53/RP54/RC6
AN56/RA10
RPI96/RF0
RP70/RD6
RP69/RD5
RP97/RF1
VCAP
VDD
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AN55/RA7 1 48 AN26/CVREF1O/ASCL1/RP40/T4CK/RB8
RPI46/PWM1H1/T3CK/RB14 2 47 RPI61/RC13
RPI47/PWM1L1/T5CK/RB15 3 46 OA5OUT/AN25/C5IN4-/RP39/INT0/RB7
AN19/RP118/RG6 4 45 AN48/CVREF2O/RPI58/RC10
AN18/RPI119/RG7 5 44 PGEC2/SCL1/RP38/RB6
AN17/RP120/RG8 6 dsPIC33EV32GM006/106 43 PGED2/SDA1/RP37/RB5
MCLR 7 42 RPI72/RD8
AN16/RPI121/RG9 8 41 VSS
VSS 9 dsPIC33EV128GM006/106 40 OSC2/CLKO/RPI63/RC15
VDD 10 dsPIC33EV256GM006/106 39 OSC1/CLKI/AN49/RPI60/RC12
AN10/RPI28/RA12 11 38 VDD
AN9/RPI27/RA11 12 37 AN31/RPI53/RC5
OA2OUT/AN0/C2IN4-/C4IN3-/RPI16/RA0 13 36 AN30/CVREF+/RPI52/RC4
OA2IN+/AN1/C2IN1+/RPI17/RA1 14 35 AN29/SCK1/RPI51/RC3
PGED3/OA2IN-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 15 34 AN28/SDI1/RPI25/RA9
PGEC3/OA1OUT/AN3/C1IN4-/C4IN2-/RPI33/CTED1/RB1 16 33 OA5 IN+/AN24/C5IN3-/C5IN1+/SDO1/RP20/T1CK/RA4
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PGEC1/OA1IN+/AN4/C1IN3-/C1IN1+/C2IN3-/RPI34/RB2
PGED1/OA1IN-/AN5/C1IN1-/(CTMUC)/RP35/RB3
OA3OUT/AN6/C3IN4-/C4IN4-/C4IN1+/RP48/RC0
OA3IN-/AN7/C3IN1-/C4IN1-/RP49/RC1
OA3IN+/AN8/C3IN3-/C3IN1+/RPI50/U1RTS/BCLK1/FLT3/RC2
AN11/C1IN2-/U1CTS/FLT4/RC11
AN12/C2IN2-/C5IN2-/U2RTS/BCLK2/FLT5/RE12
AN13/C3IN2-/U2CTS/FLT6/RE13
RPI24/RA8
FLT32/RP36/RB4
AVDD
VDD
AVSS
VSS
used.
VSS externally.

Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 13
2.0 Guidelines for Getting Started with 16-Bit Digital Signal Controllers .......................................................................................... 17
3.0 CPU ............................................................................................................................................................................................ 21
4.0 Memory Organization ................................................................................................................................................................. 31
5.0 Flash Program Memory .............................................................................................................................................................. 83
6.0 Resets ....................................................................................................................................................................................... 91
7.0 Interrupt Controller ..................................................................................................................................................................... 95
8.0 Direct Memory Access (DMA) .................................................................................................................................................. 109
9.0 Oscillator Configuration ............................................................................................................................................................ 123
10.0 Power-Saving Features ............................................................................................................................................................ 133
11.0 I/O Ports ................................................................................................................................................................................... 143
12.0 Timer1 ...................................................................................................................................................................................... 173
13.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 175
14.0 Deadman Timer (DMT) ............................................................................................................................................................ 181
15.0 Input Capture............................................................................................................................................................................ 189
16.0 Output Compare ....................................................................................................................................................................... 193
17.0 High-Speed PWM Module ....................................................................................................................................................... 199
18.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 221
19.0 Inter-Integrated Circuit (I2C) ..................................................................................................................................................... 229
20.0 Single-Edge Nibble Transmission (SENT) ............................................................................................................................... 237
21.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 247
22.0 Controller Area Network (CAN) Module (dsPIC33EVXXXGM10X Devices Only).................................................................... 253
23.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 279
24.0 10-Bit/12-Bit Analog-to-Digital Converter (ADC) ...................................................................................................................... 285
25.0 Op Amp/Comparator Module ................................................................................................................................................... 301
26.0 Comparator Voltage Reference................................................................................................................................................ 313
27.0 Special Features ...................................................................................................................................................................... 317
28.0 Instruction Set Summary .......................................................................................................................................................... 327
29.0 Development Support............................................................................................................................................................... 337
30.0 Electrical Characteristics .......................................................................................................................................................... 341
31.0 High-Temperature Electrical Characteristics ............................................................................................................................ 403
32.0 Characteristics for Industrial/Extended Temperature Devices (-40°C to +125°C).................................................................... 413
33.0 Characteristics for High-Temperature Devices (+150°C) ......................................................................................................... 439
34.0 Packaging Information.............................................................................................................................................................. 461
Appendix A: Revision History............................................................................................................................................................. 485
Index ................................................................................................................................................................................................. 487
The Microchip Web Site ..................................................................................................................................................................... 495
Customer Change Notification Service .............................................................................................................................................. 495
Customer Support .............................................................................................................................................................................. 495
Product Identification System............................................................................................................................................................. 497

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Referenced Sources
This device data sheet is based on the following
individual chapters of the “dsPIC33/PIC24 Family
Reference Manual”, which are available from the
Microchip web site (www.microchip.com). The follow-
ing documents should be considered as the general
reference for the operation of a particular module or
device feature:
• “Introduction” (DS70573)
• “CPU” (DS70359)
• “Data Memory” (DS70595)
• “dsPIC33E/PIC24E Program Memory” (DS70000613)
• “Flash Programming” (DS70609)
• “Interrupts” (DS70000600)
• “Oscillator” (DS70580)
• “Reset” (DS70602)
• “Watchdog Timer and Power-Saving Modes” (DS70615)
• “I/O Ports” (DS70000598)
• “Timers” (DS70362)
• “CodeGuard™ Intermediate Security” (DS70005182)
• “Deadman Timer (DMT)” (DS70005155)
• “Input Capture” (DS70000352)
• “Output Compare” (DS70005157)
• “High-Speed PWM”(DS70645)
• “Analog-to-Digital Converter (ADC)” (DS70621)
• “Universal Asynchronous Receiver Transmitter (UART)” (DS70000582)
• “Serial Peripheral Interface (SPI)” (DS70005185)
• “Inter-Integrated Circuit™ (I2C™)” (DS70000195)
• “Enhanced Controller Area Network (ECAN™)”(DS70353)
• “Direct Memory Access (DMA)” (DS70348)
• “Programming and Diagnostics” (DS70608)
• “Op Amp/Comparator” (DS70000357)
• “Device Configuration” (DS70000618)
• “Charge Time Measurement Unit (CTMU)” (DS70661)
• “Single-Edge Nibble Transmission (SENT) Module” (DS70005145)

1.0 DEVICE OVERVIEW This document contains device-specific information for

the dsPIC33EVXXXGM00X/10X family Digital Signal
Note 1: This data sheet summarizes the features Controller (DSC) devices.
of the dsPIC33EVXXXGM00X/10X family dsPIC33EVXXXGM00X/10X family devices contain
of devices. It is not intended to be a extensive Digital Signal Processor (DSP) functionality
comprehensive reference source. To with a high-performance, 16-bit MCU architecture.
complement the information in this data
sheet, refer to the related section in the Figure 1-1 shows a general block diagram of the core
“dsPIC33/PIC24 Family Reference Man- and peripheral modules. Table 1-1 lists the functions of
ual”, which is available from the Microchip the various pins shown in the pinout diagrams.
web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
FIGURE 1-1: dsPIC33EVXXXGM00X/10X FAMILY BLOCK DIAGRAM
PORTA
CPU
16
Refer to Figure 3-1 for CPU diagram details.
PORTB
PORTC
Power-up
Timer
OSC1/CLKI Oscillator PORTD
Timing Start-up
Generation Timer
POR/BOR PORTE
MCLR
Watchdog 16
Timer/
Deadman
VDD, VSS Timer PORTF
AVDD, AVSS
Input Output PORTG

SENT1/2 CAN1(1) ADC I2C1
Capture Compare
Remappable
Pins
Op Amp/ PORTS
CTMU PWM Timers Comparator SPI1/2 UART1/2
Peripheral Modules
Note 1: This feature or peripheral is only available on dsPIC33EVXXXGM10X devices.

TABLE 1-1: PINOUT I/O DESCRIPTIONS

Pin Buffer
Pin Name PPS Description
Type Type
AN0-AN19 I Analog No Analog input channels.
AN24-AN32
AN48, AN49
AN51-AN56
CLKI I ST/ No External clock source input. Always associated with OSC1 pin
CMOS function.
CLKO O — No Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
Always associated with OSC2 pin function.
OSC1 I ST/ No Oscillator crystal input. ST buffer when configured in RC mode; CMOS
CMOS otherwise.
OSC2 I/O — No Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
REFCLKO O — Yes Reference clock output.
IC1-IC4 I ST Yes Capture Inputs 1 to 4.
OCFA I ST Yes Compare Fault A input (for compare channels).
OC1-OC4 O — Yes Compare Outputs 1 to 4.
INT0 I ST No External Interrupt 0.
INT1 I ST Yes External Interrupt 1.
INT2 I ST Yes External Interrupt 2.
RA0-RA4, RA7-RA12 I/O ST Yes PORTA is a bidirectional I/O port.
RB0-RB15 I/O ST Yes PORTB is a bidirectional I/O port.
RC0-RC13, RC15 I/O ST Yes PORTC is a bidirectional I/O port.
RD5-RD6, RD8 I/O ST Yes PORTD is a bidirectional I/O port.
RE12-RE15 I/O ST Yes PORTE is a bidirectional I/O port.
RF0-RF1 I/O ST No PORTF is a bidirectional I/O port.
RG6-RG9 I/O ST Yes PORTG is a bidirectional I/O port.
T1CK I ST No Timer1 external clock input.
T2CK I ST Yes Timer2 external clock input.
CTPLS O ST No CTMU pulse output.
CTED1 I ST No CTMU External Edge Input 1.
CTED2 I ST No CTMU External Edge Input 2.
U1CTS I ST Yes UART1 Clear-to-Send.
U1RTS O — Yes UART1 Ready-to-Send.
U1RX I ST Yes UART1 receive.
U1TX O — Yes UART1 transmit.
U2CTS I ST Yes UART2 Clear-to-Send.
U2RTS O — Yes UART2 Ready-to-Send.
U2RX I ST Yes UART2 receive.
U2TX O — Yes UART2 transmit.
SCK1 I/O ST No Synchronous serial clock input/output for SPI1.
SDI1 I ST No SPI1 data in.
SDO1 O — No SPI1 data out.
SS1 I/O ST No SPI1 slave synchronization or frame pulse I/O.
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
PPS = Peripheral Pin Select TTL = TTL input buffer

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Buffer
Type Type
SCK2 I/O ST Yes Synchronous serial clock input/output for SPI2.
SDI2 I ST Yes SPI2 data in.
SDO2 O — Yes SPI2 data out.
SS2 I/O ST Yes SPI2 slave synchronization or frame pulse I/O.
SCL1 I/O ST No Synchronous serial clock input/output for I2C1.
SDA1 I/O ST No Synchronous serial data input/output for I2C1.
ASCL1 I/O ST No Alternate synchronous serial clock input/output for I2C1.
ASDA1 I/O ST No Alternate synchronous serial data input/output for I2C1.
C1RX I ST Yes CAN1 bus receive pin.
C1TX O — Yes CAN1 bus transmit pin.
SENT1TX O — Yes SENT1 transmit pin.
SENT1RX I — Yes SENT1 receive pin.
SENT2TX O — Yes SENT2 transmit pin.
SENT2RX I — Yes SENT2 receive pin.
CVREF O Analog No Comparator Voltage Reference output.
C1IN1+, C1IN2-, I Analog No Comparator 1 inputs.
C1IN1-, C1IN3-
C1OUT O — Yes Comparator 1 output.
C2IN1-, C2IN3-
C2IN1-, C3IN3-
C4IN1-, C4IN3-
C5IN1-, C5IN3-
FLT1-FLT2 I ST Yes PWM Fault Inputs 1 and 2.
FLT3-FLT8 I ST NO PWM Fault Inputs 3 to 8.
FLT32 I ST NO PWM Fault Input 32.
DTCMP1-DTCMP3 I ST Yes PWM Dead-Time Compensation Inputs 1 to 3.
PWM1L-PWM3L O — No PWM Low Outputs 1 to 3.
PWM1H-PWM3H O — No PWM High Outputs 1 to 3.
SYNCI1 I ST Yes PWM Synchronization Input 1.
SYNCO1 O — Yes PWM Synchronization Output 1.
PGED1 I/O ST No Data I/O pin for Programming/Debugging Communication Channel 1.
PGEC1 I ST No Clock input pin for Programming/Debugging Communication Channel 1.
MCLR I/P ST No Master Clear (Reset) input. This pin is an active-low Reset to the
device.

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Buffer
Type Type
AVDD P P No Positive supply for analog modules. This pin must be connected at all
times.
AVSS P P No Ground reference for analog modules.
VDD P — No Positive supply for peripheral logic and I/O pins.
VCAP P — No CPU logic filter capacitor connection.
VSS P — No Ground reference for logic and I/O pins.

2.0 GUIDELINES FOR GETTING 2.2 Decoupling Capacitors

STARTED WITH 16-BIT The use of decoupling capacitors on every pair of
DIGITAL SIGNAL power supply pins, such as VDD, VSS, AVDD and
CONTROLLERS AVSS, is required.
Consider the following criteria when using decoupling
Note 1: This data sheet summarizes the features capacitors:
of the dsPIC33EVXXXGM00X/10X family
of devices. It is not intended to be a • Value and type of capacitor: A value of 0.1 µF
comprehensive reference source. To (100 nF), 10V-20V is recommended. This
complement the information in this data capacitor should be a Low Equivalent Series
sheet, refer to the related section in the Resistance (low-ESR), and have resonance
“dsPIC33/PIC24 Family Reference Man- frequency in the range of 20 MHz and higher. It is
ual”, which is available from the Microchip recommended to use ceramic capacitors.
web site (www.microchip.com). • Placement on the Printed Circuit Board (PCB):
The decoupling capacitors should be placed as
close to the pins as possible. It is recommended
to place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within
one-quarter inch (6 mm) in length.
2.1 Basic Connection Requirements • Handling high-frequency noise: If the board is
Getting started with the dsPIC33EVXXXGM00X/10X experiencing high-frequency noise, above tens of
family of 16-bit microcontrollers (MCUs) requires MHz, add a second ceramic-type capacitor in
attention to a minimal set of device pin connections parallel to the above described decoupling
before proceeding with development. The following is a capacitor. The value of the second capacitor can
list of pin names, which must always be connected: be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
• All VDD and VSS pins capacitor. In high-speed circuit designs, consider
(see Section 2.2 “Decoupling Capacitors”) implementing a decade pair of capacitances as
• All AVDD and AVSS pins (regardless if ADC module close to the power and ground pins as possible.
is not used) For example, 0.1 µF in parallel with 0.001 µF.
(see Section 2.2 “Decoupling Capacitors”) • Maximizing performance: On the board layout
• VCAP from the power supply circuit, run the power and
(see Section 2.3 “CPU Logic Filter Capacitor return traces to the decoupling capacitors first,
Connection (VCAP)”) and then to the device pins. This ensures that the
• MCLR pin decoupling capacitors are first in the power chain.
(see Section 2.4 “Master Clear (MCLR) Pin”) Equally important is to keep the trace length
• PGECx/PGEDx pins used for In-Circuit Serial between the capacitor and the power pins to a
Programming™ (ICSP™) and debugging purposes minimum, thereby reducing the PCB track
(see Section 2.5 “ICSP Pins”) inductance.
• OSC1 and OSC2 pins when external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
Note: The AVDD and AVSS pins must be

connected, regardless of the ADC voltage
reference source.

FIGURE 2-1: RECOMMENDED The placement of this capacitor should be close to the
MINIMUM CONNECTION VCAP pin. It is recommended that the trace length
should not exceed one-quarter inch (6 mm).
VDD 10 µF 0.1 µF
Tantalum Ceramic 2.4 Master Clear (MCLR) Pin
The MCLR pin provides two specific device
VCAP
VSS
VDD
R
functions:
R1
MCLR • Device Reset
• Device Programming and Debugging
C
dsPIC33EV During device programming and debugging, the
resistance and capacitance that can be added to the
VSS VDD
pin must be considered. Device programmers and
debuggers drive the MCLR pin. Consequently,
VDD VSS
0.1 µF 0.1 µF specific voltage levels (VIH and VIL) and fast signal
AVDD
AVSS
VDD
VSS
Ceramic Ceramic transitions must not be adversely affected. Therefore,

specific values of R and C will need to be adjusted
0.1 µF 0.1 µF based on the application and PCB requirements.
Ceramic Ceramic
For example, as shown in Figure 2-1, it is
L1(1)
recommended that the capacitor, C, be isolated from
Note 1: As an option, instead of a hard-wired connection, an the MCLR pin during programming and debugging
inductor (L1) can be substituted between VDD and operations.
AVDD to improve ADC noise rejection. The inductor
impedance should be less than 1 and the inductor Place the components as shown in Figure 2-2 within
capacity greater than 10 mA. one-quarter inch (6 mm) from the MCLR pin.
Where:
F CNV FIGURE 2-2: EXAMPLE OF MCLR PIN

f = -------------- (i.e., ADC Conversion Rate/2) CONNECTIONS
2
1
f = ----------------------- VDD
 2 LC 
2
L =  ----------------------
1 R(1)
  2f C  R1(2)
MCLR
2.2.1 TANK CAPACITORS JP

dsPIC33EV
On boards with power traces running longer than six C
inches in length, it is suggested to use a tank capacitor
for integrated circuits including DSCs to supply a local
power source. The value of the tank capacitor should
Note 1: R  10 k is recommended. A suggested
be determined based on the trace resistance that
starting value is 10 k. Ensure that the MCLR
connects the power supply source to the device, and pin VIH and VIL specifications are met.
the maximum current drawn by the device in the appli-
2: R1  470 will limit any current flow into
cation. In other words, select the tank capacitor so that MCLR from the external capacitor, C, in the
it meets the acceptable voltage sag at the device. event of MCLR pin breakdown due to Electro-
Typical values range from 4.7 µF to 47 µF. static Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
2.3 CPU Logic Filter Capacitor VIH and VIL specifications are met.
Connection (VCAP)
A low-ESR (<1 Ohms) capacitor is required on the VCAP
pin, which is used to stabilize the internal voltage regulator
output. The VCAP pin must not be connected to VDD, and
must have a capacitor greater than 4.7 µF (10 µF is
recommended), with at least a 16V rating connected to
the ground. The type can be ceramic or tantalum. See
Section 30.0 “Electrical Characteristics” for additional
information.

2.5 ICSP Pins FIGURE 2-3: SUGGESTED PLACEMENT

OF THE OSCILLATOR
The PGECx and PGEDx pins are used for ICSP and
CIRCUIT
debugging purposes. It is recommended to keep the
trace length between the ICSP connector and the ICSP
pins on the device as short as possible. If the ICSP con- Main Oscillator
nector is expected to experience an ESD event, a
series resistor is recommended, with the value in the Guard Ring
range of a few tens of Ohms, not exceeding 100 Ohms.
Pull-up resistors, series diodes and capacitors on the Guard Trace
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communi- Oscillator Pins
cations to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits and pin Voltage Input High
(VIH) and Voltage Input Low (VIL) requirements. 2.7 Oscillator Value Conditions on
Ensure that the “Communication Channel Select” (i.e.,
Device Start-up
PGECx/PGEDx pins) programmed into the device If the PLL of the target device is enabled and
matches the physical connections for the ICSP to configured for the device start-up oscillator, the
MPLAB® PICkit™ 3, MPLAB ICD 3 or MPLAB maximum oscillator source frequency must be limited
REAL ICE™. to 5 MHz < FIN < 13.6 MHz to comply with device PLL
For more information on MPLAB ICD 2, ICD 3 and start-up conditions. This intends that, if the external
REAL ICE connection requirements, refer to the oscillator frequency is outside this range, the
following documents that are available on the application must start up in the FRC mode first. The
Microchip web site (www.microchip.com). default PLL settings after a POR with an oscillator
frequency outside this range will violate the device
• “Using MPLAB® ICD 3” (poster) (DS51765)
operating speed.
• “MPLAB® ICD 3 Design Advisory” (DS51764)
Once the device powers up, the application firmware
• “MPLAB® REAL ICE™ In-Circuit Emulator User’s
can initialize the PLL SFRs, CLKDIV and PLLFBD, to a
Guide” (DS51616)
suitable value, and then perform a clock switch to the
• “Using MPLAB® REAL ICE™ In-Circuit Emulator” Oscillator + PLL clock source.
(poster) (DS51749)
Note: Clock switching must be enabled in the
device Configuration Word.
2.6 External Oscillator Pins
Many DSCs have options for at least two oscillators: a 2.8 Unused I/Os
high-frequency primary oscillator and a low-frequency
secondary oscillator. For more information, see Unused I/O pins should be configured as outputs and
Section 9.0 “Oscillator Configuration”. driven to a logic low state.
The oscillator circuit should be placed on the same Alternatively, connect a 1k to 10k resistor between VSS
side of the board as the device. Also, place the and unused pins, and drive the output to logic low.
oscillator circuit close to the respective oscillator pins,
not exceeding one-half inch (12 mm) distance
between them. The load capacitors should be placed
next to the oscillator itself, on the same side of the
board. Use a grounded copper pour around the
oscillator circuit to isolate them from surrounding
circuits. The grounded copper pour should be routed
directly to the MCU ground. Do not run any signal
traces or power traces inside the ground pour. Also, if
using a two-sided board, avoid any traces on the
other side of the board where the crystal is placed as
shown in Figure 2-3.

NOTES:

3.0 CPU 3.2 Instruction Set

The device instruction set has two classes of instruc-
Note 1: This data sheet summarizes the features
tions: the MCU class of instructions and the DSP class
of instructions. These two instruction classes are
of devices. It is not intended to be a seamlessly integrated into the architecture and exe-
comprehensive reference source. To cute from a single execution unit. The instruction set
complement the information in this data includes many addressing modes and was designed
sheet, refer to “CPU” (DS70359) in the for optimum C compiler efficiency.
“dsPIC33/PIC24 Family Reference
Manual”, which is available from the 3.3 Data Space Addressing
Microchip web site (www.microchip.com).
The Base Data Space can be addressed as 4K words
2: Some registers and associated bits or 8 Kbytes and is split into two blocks, referred to as X
described in this section may not be and Y data memory. Each memory block has its own
available on all devices. Refer to independent Address Generation Unit (AGU). The
Section 4.0 “Memory Organization” in MCU class of instructions operates solely through the
this data sheet for device-specific register X memory AGU, which accesses the entire memory
and bit information. map as one linear Data Space. On dsPIC33EV
devices, certain DSP instructions operate through the
The CPU has a 16-bit (data) modified Harvard archi-
X and Y AGUs to support dual operand reads, which
tecture with an enhanced instruction set, including
splits the data address space into two parts. The X and
significant support for digital signal processing. The Y Data Space boundary is device-specific.
CPU has a 24-bit instruction word with a variable length
opcode field. The Program Counter (PC) is 23 bits wide The upper 32 Kbytes of the Data Space (DS) memory
and addresses up to 4M x 24 bits of user program map can optionally be mapped into Program Space (PS)
memory space. at any 16K program word boundary. The Program-to-
Data Space mapping feature, known as Program Space
An instruction prefetch mechanism helps maintain Visibility (PSV), lets any instruction access Program
throughput and provides predictable execution. Most Space as if it were Data Space. Moreover, the Base Data
instructions execute in a single-cycle effective execu- Space address is used in conjunction with a Data Space
tion rate, with the exception of instructions that change Read or Write Page register (DSRPAG or DSWPAG) to
the program flow, the double-word move (MOV.D) form an Extended Data Space (EDS) address. The EDS
instruction, PSV accesses and the table instructions. can be addressed as 8M words or 16 Mbytes. For more
Overhead-free program loop constructs are supported information on EDS, PSV and table accesses, refer to
using the DO and REPEAT instructions, both of which “Data Memory” (DS70595) and “dsPIC33E/PIC24E
are interruptible at any point. Program Memory” (DS70000613) in the “dsPIC33/
PIC24 Family Reference Manual”.
3.1 Registers On dsPIC33EV devices, overhead-free circular buffers
The dsPIC33EVXXXGM00X/10X family devices have (Modulo Addressing) are supported in both X and Y
sixteen, 16-bit Working registers in the programmer’s address spaces. The Modulo Addressing removes the
model. Each of the Working registers can act as a software boundary checking overhead for DSP
Data, Address or Address Offset register. The sixteenth algorithms. The X AGU Circular Addressing can be
Working register (W15) operates as a Software Stack used with any of the MCU class of instructions. The X
Pointer for interrupts and calls. AGU also supports Bit-Reversed Addressing to greatly
simplify input or output data reordering for radix-2 FFT
In addition, the dsPIC33EVXXXGM00X/10X devices
algorithms. Figure 3-1 illustrates the block diagram of
include two alternate Working register sets, which
the dsPIC33EVXXXGM00X/10X family devices.
consist of W0 through W14. The alternate registers can
be made persistent to help reduce the saving and 3.4 Addressing Modes
restoring of register content during Interrupt Service
Routines (ISRs). The alternate Working registers can The CPU supports these addressing modes:
be assigned to a specific Interrupt Priority Level (IPL1 • Inherent (no operand)
through IPL6) by configuring the CTXTx<2:0> bits in • Relative
the FALTREG Configuration register. • Literal
• Memory Direct
The alternate Working registers can also be accessed
• Register Direct
manually by using the CTXTSWP instruction.
• Register Indirect
The CCTXI<2:0> and MCTXI<2:0> bits in the CTXTSTAT
Each instruction is associated with a predefined
register can be used to identify the current, and most
addressing mode group, depending upon its functional
recent, manually selected Working register sets. requirements. As many as six addressing modes are
supported for each instruction.

FIGURE 3-1: dsPIC33EVXXXGM00X/10X FAMILY CPU BLOCK DIAGRAM
X Address Bus
Y Data Bus
X Data Bus
16 16 16
16
Interrupt Data Latch Data Latch
PSV and Table
Controller Data Access Y Data X Data
8 16
24 Control Block RAM RAM
Address Address 16 24
24 Latch Latch
16 16
Y Address Bus
24 PCU PCH PCL X RAGU
Program Counter 16 X WAGU
Stack Loop
Control Control
Address Latch Logic Logic
Y AGU
Program Memory
16 EA MUX
Data Latch
16
ROM Latch
16 24
IR
24
Literal Data
16
16 x 16
W Register Array
16
16 16
Divide
DSP Support
Engine
16-Bit ALU
Control Signals Instruction

Decode and 16 16
to Various Blocks
Control
Power, Reset Ports

and Oscillator
Modules
Peripheral
Modules

3.5 Programmer’s Model In addition to the registers contained in the programmer’s

model, the dsPIC33EVXXXGM00X/10X family devices
The programmer’s model for the dsPIC33EVXXXGM00X/ contain control registers for Modulo Addressing and Bit-
10X family is shown in Figure 3-2. All registers in the Reversed Addressing, and interrupts. These registers
programmer’s model are memory-mapped and can be are described in subsequent sections of this document.
manipulated directly by instructions. Table 3-1 lists a
description of each register. All registers associated with the programmer’s model
are memory-mapped, as shown in Table 4-1.
TABLE 3-1: PROGRAMMER’S MODEL REGISTER DESCRIPTIONS

Register(s) Name Description
W0 through W15(1) Working Register Array
W0 through W14(1) Alternate Working Register Array 1
W0 through W14(1) Alternate Working Register Array 2
ACCA, ACCB 40-Bit DSP Accumulators
PC 23-Bit Program Counter
SR ALU and DSP Engine STATUS Register
SPLIM Stack Pointer Limit Value Register
TBLPAG Table Memory Page Address Register
DSRPAG Extended Data Space (EDS) Read Page Register
RCOUNT REPEAT Loop Counter Register
DCOUNT DO Loop Count Register
DOSTARTH(2), DOSTARTL(2) DO Loop Start Address Register (High and Low)
DOENDH, DOENDL DO Loop End Address Register (High and Low)
CORCON Contains DSP Engine, DO Loop Control and Trap Status bits
Note 1: Memory-mapped W0 through W14 represents the value of the register in the currently active CPU context.
2: The DOSTARTH and DOSTARTL registers are read-only.

FIGURE 3-2: PROGRAMMER’S MODEL
D15 D0
D15 D0
D15 D0
W0 (WREG) W0 W0
W1 W1 W1
W2 W2 W2
W3 W3 W3
W4 W4 W4
DSP Operand W5 W5 W5 Alternate
Registers W6 W6 W6 Working/Address
Working/Address Registers
Registers W7 W7 W7
W8 W8 W8
DSP Address W9 W9 W9
Registers W10 W10 W10
W11 W11 W11
W12 W12 W12
W13 W13 W13
Frame Pointer/W14 W14 W14
Stack Pointer/W15 0
PUSH.s and POP.s Shadows
SPLIM 0 Stack Pointer Limit
Nested DO Stack
AD39 AD31 AD15 AD0
DSP ACCA
Accumulators(1) ACCB
PC23 PC0
0 0 Program Counter
7 0
TBLPAG Data Table Page Address
9 0
DSRPAG X Data Space Read Page Address
15 0
RCOUNT REPEAT Loop Counter
15 0
DCOUNT DO Loop Counter and Stack
23 0
0 DOSTART 0 DO Loop Start Address and Stack
23 0
0 DOEND 0 DO Loop End Address and Stack
15 0
CORCON CPU Core Control Register
SRL
OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C STATUS Register

3.6 CPU Control Registers
REGISTER 3-1: SR: CPU STATUS REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/C-0 R/C-0 R-0 R/W-0
(3) (3)
OA OB SA SB OAB SAB DA DC
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

(1,2) (1,2) (1,2)
IPL2 IPL1 IPL0 RA N OV Z C
bit 7 bit 0
Legend: C = Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 OA: Accumulator A Overflow Status bit

1 = Accumulator A has overflowed
0 = Accumulator A has not overflowed
bit 14 OB: Accumulator B Overflow Status bit
1 = Accumulator B has overflowed
0 = Accumulator B has not overflowed
bit 13 SA: Accumulator A Saturation ‘Sticky’ Status bit(3)
1 = Accumulator A is saturated or has been saturated at some time
0 = Accumulator A is not saturated
bit 12 SB: Accumulator B Saturation ‘Sticky’ Status bit(3)
1 = Accumulator B is saturated or has been saturated at some time
0 = Accumulator B is not saturated
bit 11 OAB: OA || OB Combined Accumulator Overflow Status bit
1 = Accumulator A or B has overflowed
0 = Accumulator A and B have not overflowed
bit 10 SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit
1 = Accumulator A or B is saturated or has been saturated at some time
0 = Accumulator A and B have not been saturated
bit 9 DA: DO Loop Active bit
1 = DO loop is in progress
0 = DO loop is not in progress
bit 8 DC: MCU ALU Half Carry/Borrow bit
1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized
data) of the result occurred
Note 1: The IPL<2:0> bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL3 = 1. User interrupts are disabled when IPL3 = 1.
2: The IPL<2:0> Status bits are read-only when the NSTDIS bit (INTCON1<15>) = 1.
3: A data write to the SR register can modify the SA and SB bits by either a data write to SA and SB or by
clearing the SAB bit. To avoid a possible SA or SB bit write race condition, the SA and SB bits should not
be modified using the bit operations.

REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED)

bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(1,2)
111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled
110 = CPU Interrupt Priority Level is 6 (14)
bit 4 RA: REPEAT Loop Active bit
1 = REPEAT loop is in progress
0 = REPEAT loop is not in progress
bit 3 N: MCU ALU Negative bit
1 = Result was negative
0 = Result was non-negative (zero or positive)
bit 2 OV: MCU ALU Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the magnitude that
causes the sign bit to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = Overflow has not occurred for signed arithmetic
bit 1 Z: MCU ALU Zero bit
1 = An operation that affects the Z bit has set it at some time in the past
0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)
bit 0 C: MCU ALU Carry/Borrow bit
1 = A carry-out from the Most Significant bit (MSb) of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: The IPL<2:0> bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority
3: A data write to the SR register can modify the SA and SB bits by either a data write to SA and SB or by
clearing the SAB bit. To avoid a possible SA or SB bit write race condition, the SA and SB bits should not
be modified using the bit operations.

REGISTER 3-2: CORCON: CORE CONTROL REGISTER

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0
VAR — US1 US0 EDT(1) DL2 DL1 DL0
bit 15 bit 8
R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R-0 R/W-0 R/W-0

SATA SATB SATDW ACCSAT IPL3(2) SFA RND IF
bit 7 bit 0

bit 15 VAR: Variable Exception Processing Latency Control bit

1 = Variable exception processing latency is enabled
0 = Fixed exception processing latency is enabled
bit 14 Unimplemented: Read as ‘0’
bit 13-12 US<1:0>: DSP Multiply Unsigned/Signed Control bits
11 = Reserved
10 = DSP engine multiplies are mixed-sign
01 = DSP engine multiplies are unsigned
00 = DSP engine multiplies are signed
bit 11 EDT: Early DO Loop Termination Control bit(1)
1 = Terminates executing the DO loop at the end of the current loop iteration
0 = No effect
bit 10-8 DL<2:0>: DO Loop Nesting Level Status bits
111 = 7 DO loops are active
•
•
•
001 = 1 DO loop is active
000 = 0 DO loops are active
bit 7 SATA: ACCA Saturation Enable bit
1 = Accumulator A saturation is enabled
0 = Accumulator A saturation is disabled
bit 6 SATB: ACCB Saturation Enable bit
1 = Accumulator B saturation is enabled
0 = Accumulator B saturation is disabled
bit 5 SATDW: Data Space Write from DSP Engine Saturation Enable bit
1 = Data Space write saturation is enabled
0 = Data Space write saturation is disabled
bit 4 ACCSAT: Accumulator Saturation Mode Select bit
1 = 9.31 saturation (super saturation)
0 = 1.31 saturation (normal saturation)
Note 1: This bit is always read as ‘0’.

2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.

REGISTER 3-2: CORCON: CORE CONTROL REGISTER (CONTINUED)

bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(2)
1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less
bit 2 SFA: Stack Frame Active Status bit
1 = Stack frame is active; W14 and W15 address 0x0000 to 0xFFFF, regardless of DSRPAG and
DSWPAG values
0 = Stack frame is not active; W14 and W15 address of EDS or Base Data Space
bit 1 RND: Rounding Mode Select bit
1 = Biased (conventional) rounding is enabled
0 = Unbiased (convergent) rounding is enabled
bit 0 IF: Integer or Fractional Multiplier Mode Select bit
1 = Integer mode is enabled for DSP multiply
0 = Fractional mode is enabled for DSP multiply
Note 1: This bit is always read as ‘0’.


REGISTER 3-3: CTXTSTAT: CPU W REGISTER CONTEXT STATUS REGISTER

U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0
— — — — — CCTXI2 CCTXI1 CCTXI0
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R-0 R/W-0 R/W-0

— — — — — MCTXI2 MCTXI1 MCTXI0
bit 7 bit 0
Legend:
bit 15-11 Unimplemented: Read as ‘0’

bit 10-8 CCTXI<2:0>: Current (W Register) Context Identifier bits
111 = Reserved
•
•
•
011 = Reserved
010 = Alternate Working Register Set 2 is currently in use
001 = Alternate Working Register Set 1 is currently in use
000 = Default register set is currently in use
bit 2-0 MCTXI<2:0>: Manual (W Register) Context Identifier bits
111 = Reserved
•
•
•
011 = Reserved
010 = Alternate Working Register Set 2 was most recently manually selected
001 = Alternate Working Register Set 1 was most recently manually selected
000 = Default register set was most recently manually selected

3.7 Arithmetic Logic Unit (ALU) 3.8 DSP Engine

The dsPIC33EVXXXGM00X/10X family ALU is 16 bits The DSP engine consists of a high-speed, 17-bit x 17-bit
wide and is capable of addition, subtraction, bit shifts multiplier, a 40-bit barrel shifter and a 40-bit adder/
and logic operations. Unless otherwise mentioned, subtracter (with two target accumulators, round and
arithmetic operations are two’s complement in nature. saturation logic).
Depending on the operation, the ALU can affect the The DSP engine can also perform inherent accumulator-
values of the Carry (C), Zero (Z), Negative (N), to-accumulator operations that require no additional
Overflow (OV) and Digit Carry (DC) Status bits in the data. These instructions are ADD, SUB and NEG.
SR register. The C and DC Status bits operate as
Borrow and Digit Borrow bits, respectively, for The DSP engine has options selected through bits in
subtraction operations. the CPU Core Control register (CORCON) as follows:
The ALU can perform 8-bit or 16-bit operations, • Fractional or Integer DSP Multiply (IF)
depending on the mode of the instruction that is used. • Signed, Unsigned or Mixed-Sign DSP Multiply (US)
The data for the ALU operation can come from the W • Conventional or Convergent Rounding (RND)
register array or from the data memory, depending on • Automatic Saturation On/Off for ACCA (SATA)
the addressing mode of the instruction. Similarly, the
• Automatic Saturation On/Off for ACCB (SATB)
output data from the ALU can be written to the W
register array or a data memory location. • Automatic Saturation On/Off for Writes to Data
Memory (SATDW)
For information on the SR bits affected by each
• Accumulator Saturation mode Selection
instruction, refer to the “16-bit MCU and DSC
(ACCSAT)
Programmer’s Reference Manual” (DS70157).
The core CPU incorporates hardware support for both TABLE 3-2: DSP INSTRUCTIONS
multiplication and division. This includes a dedicated SUMMARY
hardware multiplier and support hardware for 16-bit
divisor division. Algebraic ACC Write
Instruction
Operation Back
3.7.1 MULTIPLIER
CLR A=0 Yes
Using the high-speed, 17-bit x 17-bit multiplier, the ALU 2
ED A = (x – y) No
supports unsigned, signed or mixed-sign operation in
several MCU multiplication modes: EDAC A = A + (x – y)2 No
• 16-bit x 16-bit signed MAC A = A + (x • y) Yes

• 16-bit x 16-bit unsigned MAC A = A + x2 No
• 16-bit signed x 5-bit (literal) unsigned MOVSAC No change in A Yes
• 16-bit signed x 16-bit unsigned
MPY A=x•y No
• 16-bit unsigned x 5-bit (literal) unsigned 2
• 16-bit unsigned x 16-bit signed MPY A=x No
• 8-bit unsigned x 8-bit unsigned MPY.N A=–x•y No
MSC A=A–x•y Yes
3.7.2 DIVIDER
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
• 32-bit signed/16-bit signed divide
• 32-bit unsigned/16-bit unsigned divide
• 16-bit signed/16-bit signed divide
• 16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0
and the remainder in W1. The 16-bit signed and
unsigned DIV instructions can specify any W register
for both the 16-bit divisor (Wn) and any W register
(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.
The divide algorithm takes the single-cycle per bit of
the divisor, so both 32-bit/16-bit and 16-bit/16-bit
instructions take the same number of cycles to
execute.

4.0 MEMORY ORGANIZATION 4.1 Program Address Space

Note: This data sheet summarizes the features The program address memory space of the
of the dsPIC33EVXXXGM00X/10X family dsPIC33EVXXXGM00X/10X family devices is 4M
of devices. It is not intended to be a instructions. The space is addressable by a 24-bit
comprehensive reference source. To com- value derived either from the 23-bit PC, during program
plement the information in this data sheet, execution or from table operation, or from DS
refer to “dsPIC33E/PIC24E Program remapping, as described in Section 4.7 “Interfacing
Memory” (DS70000613) in the “dsPIC33/ Program and Data Memory Spaces”.
PIC24 Family Reference Manual”, which is User application access to the program memory space
available from the Microchip web site is restricted to the lower half of the address range
(www.microchip.com). (0x000000 to 0x02ABFF). The exception is the use of
the TBLRD operations, which use TBLPAG<7> to read
The dsPIC33EVXXXGM00X/10X family architecture Device ID sections of the configuration memory space
features separate program and data memory spaces and the TBLWT operations, which are used to set up the
and buses. This architecture also allows the direct write latches located in configuration memory space.
access of program memory from the Data Space (DS)
during code execution. The program memory maps, which are presented by
the device family and memory size, are shown in
Figure 4-1 through Figure 4-4.
FIGURE 4-1: PROGRAM MEMORY MAP FOR dsPIC33EV32GM00X/10X DEVICES(1)
GOTO Instruction 0x000000

Reset Address 0x000002
0x000004
Interrupt Vector Table 0x0001FE
0x000200
User Program
User Memory Space
Flash Memory
(10944 instructions) 0x00577E
0x005780
Device Configuration
0x0057FE
0x005800
Unimplemented
(Read ‘0’s)
0x7FFFFE
0x800000
Executive Code Memory
0x800BFE
0x800C00
Reserved
0x800F80
Configuration Memory Space
User OTP Memory

0x800FFE
0x801000
Reserved
0xF9FFFE
0xFA0000
Write Latches 0xFA0002
0xFA0004
Reserved
0xFEFFFE
0xFF0000
DEVID
0xFF0002
0xFF0004
Reserved
0xFFFFFE
Note 1: Memory areas are not shown to scale.


0x000004
0x000200
User Program
User Memory Space

Flash Memory
(21696 instructions) 0x00AB7E
0x00AB80
0x00ABFE
0x00AC00
Unimplemented
(Read ‘0’s)
0x7FFFFE
0x800000
0x800BFE
0x800C00
Reserved
0x800F80
User OTP Memory

0x800FFE
0x801000
Reserved
0xF9FFFE
0xFA0000
Write Latches 0xFA0002
0xFA0004
Reserved
0xFEFFFE
0xFF0000
DEVID
0xFF0002
0xFF0004
Reserved
0xFFFFFE


0x000004
0x000200
User Program
User Memory Space

Flash Memory
(44736 instructions) 0x01577E
0x015780
0x0157FE
0x015800
Unimplemented
(Read ‘0’s)
0x7FFFFE
0x800000
0x800BFE
0x800C00
Reserved
0x800F80
User OTP Memory

0x800FFE
0x801000
Reserved
0xF9FFFE
0xFA0000
Write Latches
0xFA0002
0xFA0004
Reserved
0xFEFFFE
0xFF0000
DEVID
0xFF0002
0xFF0004
Reserved
0xFFFFFE


0x000004
0x000200
User Program
User Memory Space

Flash Memory
(87232 instructions) 0x02AB7E
0x02AB80
0x02ABFE
0x02AC00
Unimplemented
(Read ‘0’s)
0x7FFFFE
0x800000
0x800BFE
0x800C00
Reserved
0x800F80
User OTP Memory

0x800FFE
0x801000
Reserved
0xF9FFFE
0xFA0000
Write Latches
0xFA0002
0xFA0004
Reserved
0xFEFFFE
0xFF0000
DEVID
0xFF0002
0xFF0004
Reserved
0xFFFFFE

4.1.1 PROGRAM MEMORY 4.1.2 INTERRUPT AND TRAP VECTORS

ORGANIZATION All dsPIC33EVXXXGM00X/10X family devices reserve
The program memory space is organized in word- the addresses between 0x000000 and 0x000200 for
addressable blocks. Although it is treated as 24 bits hard-coded program execution vectors. A hardware
wide, it is more appropriate to think of each address of Reset vector is provided to redirect code execution
the program memory as a lower and upper word, with from the default value of the PC on device Reset to the
the upper byte of the upper word being unimplemented. actual start of code. A GOTO instruction is programmed
The lower word always has an even address, while the by the user application at address, 0x000000 of Flash
upper word has an odd address (see Figure 4-5). memory, with the actual address for the start of code at
address, 0x000002 of Flash memory.
Program memory addresses are always word-aligned
on the lower word and addresses are incremented or For more information on the Interrupt Vector Tables,
decremented by two during the code execution. This see Section 7.1 “Interrupt Vector Table”.
arrangement provides compatibility with the Data
Memory Space Addressing and makes data in the
program memory space accessible.
FIGURE 4-5: PROGRAM MEMORY ORGANIZATION
msw Most Significant Word Least Significant Word PC Address

Address (lsw Address)
23 16 8 0
0x000001 00000000 0x000000
0x000003 00000000 0x000002
0x000005 00000000 0x000004
0x000007 00000000 0x000006
Program Memory Instruction Width

‘Phantom’ Byte
(read as ‘0’)

4.2 Data Address Space All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, there-
The dsPIC33EVXXXGM00X/10X family CPU has a fore, care must be taken when mixing byte and word
separate, 16-bit wide data memory space. The Data operations or translating from 8-bit MCU code. If a
Space (DS) is accessed using separate Address Gen- misaligned read or write is attempted, an address error
eration Units (AGUs) for read and write operations. The trap is generated. If the error occurred on a read, the
data memory maps, which are presented by device instruction underway is completed. If the error occurred
family and memory size, are shown in Figure 4-6 and on a write, the instruction is executed but the write does
Figure 4-8. not occur. In either case, a trap is then executed,
All Effective Addresses (EAs) in the data memory space allowing the system and/or user application to examine
are 16 bits wide and point to bytes within the DS. This the machine state prior to execution of the address
arrangement gives a Base Data Space address range of Fault.
64 Kbytes or 32K words. All byte loads into any W register are loaded into the
The Base Data Space address is used in conjunction LSB; the MSB is not modified.
with a Data Space Read or Write Page register A Sign-Extend (SE) instruction is provided to allow user
(DSRPAG or DSWPAG) to form an Extended Data applications to translate 8-bit signed data to 16-bit
Space (EDS), which has a total address range of signed values. Alternatively, for 16-bit unsigned data,
16 Mbytes. user applications can clear the MSB of any W register
dsPIC33EVXXXGM00X/10X family devices implement by executing a Zero-Extend (ZE) instruction on the
up to 20 Kbytes of data memory (4 Kbytes of data appropriate address.
memory for Special Function Registers and up to
16 Kbytes of data memory for RAM). If an EA points to 4.2.3 SFR SPACE
a location outside of this area, an all zero word or byte The first 4 Kbytes of the Near Data Space, from 0x0000
is returned. to 0x0FFF, is primarily occupied by Special Function
Registers (SFRs). These are used by the
4.2.1 DATA SPACE WIDTH dsPIC33EVXXXGM00X/10X family core and peripheral
The data memory space is organized in byte- modules for controlling the operation of the device.
addressable, 16-bit wide blocks. Data is aligned in SFRs are distributed among the modules that they
data memory and registers as 16-bit words, but all DS control and are generally grouped together by module.
EAs resolve to bytes. The Least Significant Bytes Much of the SFR space contains unused addresses;
(LSBs) of each word have even addresses, while the these are read as ‘0’.
Most Significant Bytes (MSBs) have odd addresses.
Note: The actual set of peripheral features and
4.2.2 DATA MEMORY ORGANIZATION interrupts varies by the device. Refer to the
AND ALIGNMENT corresponding device tables and pinout
diagrams for device-specific information.
To maintain backward compatibility with PIC® MCU
devices and improve Data Space memory usage
4.2.4 NEAR DATA SPACE
efficiency, the dsPIC33EVXXXGM00X/10X family
instruction set supports both word and byte operations. The 8-Kbyte area, between 0x0000 and 0x1FFF, is
As a consequence of byte accessibility, all the Effective referred to as the Near Data Space. Locations in this
Address calculations are internally scaled to step space are directly addressable through a 13-bit abso-
through word-aligned memory. For example, the core lute address field within all memory direct instructions.
recognizes that Post-Modified Register Indirect Additionally, the whole DS is addressable using MOV
Addressing mode [Ws++] results in a value of Ws + 1 instructions, which support Memory Direct Addressing
for byte operations and Ws + 2 for word operations. mode with a 16-bit address field, or by using Indirect
Addressing mode using a Working register as an
A data byte read, reads the complete word that con-
Address Pointer.
tains the byte, using the LSb of any EA to determine
which byte to select. The selected byte is placed onto
the LSB of the data path. That is, data memory and reg-
isters are organized as two parallel, byte-wide entities
with shared (word) address decode, but separate write
lines. Data byte writes only write to the corresponding
side of the array or register that matches the byte
address.

FIGURE 4-6: DATA MEMORY MAP FOR 32-Kbyte DEVICES(1)
MSB LSB
Address 16 Bits Address
MSB LSB
0x0001 0x0000
4-Kbyte SFR Space
SFR Space
0x0FFF 0x0FFE
0x1001 0x1000
X Data RAM (X)
8-Kbyte
Near Data
4-Kbyte 0x17FF 0x17FE
Space
SRAM Space 0x1801 0x1800
Y Data RAM (Y)
0x1FFF 0x1FFE
0x2001 0x2000
0x7FFF 0x7FFE
0x8000
0x8001
X Data Optionally
Unimplemented (X) Mapped
into Program
Memory Space
(via PSV)
0xFFFF 0xFFFE

FIGURE 4-7: DATA MEMORY MAP FOR 64-Kbyte/128-Kbyte DEVICES(1)
MSB LSB
MSB LSB
0x0001 0x0000
4-Kbyte SFR Space
SFR Space
0x0FFF 0x0FFE
0x1001 0x1000
8-Kbyte
Near Data
X Data RAM (X) Space
8-Kbyte 0x1FFF 0x1FFE

SRAM Space 0x2001 0x2000
Y Data RAM (Y)
0x2FFF 0x2FFE
0x3001 0x3000
0x7FFF 0x7FFE
0x8000
0x8001
X Data Optionally
Unimplemented (X) Mapped
into Program
Memory Space
(via PSV)
0xFFFF 0xFFFE

FIGURE 4-8: DATA MEMORY MAP FOR 256-Kbyte DEVICES(1)
MSB LSB
MSB LSB
0x0001 0x0000
4-Kbyte
SFR Space
SFR Space
0x0FFF 0x0FFE
0x1001 0x1000 8-Kbyte
Near Data
Space
0x1FFF 0x1FFE
X Data RAM (X)
0x2001 0x2000
16-Kbyte
SRAM Space
0x2FFF 0x2FFE
0x3001 0x3000
Y Data RAM (Y)
0x4FFF 0x4FFE
0x5001 0x5000
0x7FFF 0x7FFE
0x8001 0x8000
X Data Optionally
Mapped
Unimplemented (X) into Program
Memory Space
(via PSV)
0xFFFF 0xFFFE

4.2.5 X AND Y DATA SPACES The Y DS is used in concert with the X DS by the MAC
class of instructions (CLR, ED, EDAC, MAC, MOVSAC,
The dsPIC33EVXXXGM00X/10X family core has two
MPY, MPY.N and MSC) to provide two concurrent data
Data Spaces: X and Y. These Data Spaces can be
read paths.
considered either separate (for some DSP instructions)
or as one unified, linear address range (for MCU Both the X and Y Data Spaces support Modulo
instructions). The Data Spaces are accessed using two Addressing mode for all instructions, subject to
Address Generation Units (AGUs) and separate data addressing mode restrictions. Bit-Reversed Addressing
paths. This feature allows certain instructions to mode is only supported for writes to the X Data Space.
concurrently fetch two words from RAM, thereby All data memory writes, including in DSP instructions,
enabling efficient execution of DSP algorithms, such as view Data Space as combined X and Y address space.
Finite Impulse Response (FIR) filtering and Fast The boundary between the X and Y Data Spaces is
Fourier Transform (FFT). device-dependent and is not user-programmable.
The X DS is used by all instructions and supports all
addressing modes. The X DS has separate read and
write data buses. The X read data bus is the read data
path for all instructions that view the DS as combined X
and Y address space. It is also the X data prefetch path
for the dual operand DSP instructions (MAC class).

4.3 Special Function Register Maps

TABLE 4-1: CPU CORE REGISTER MAP
All
SFR
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Name
s
W0 0000 W0 (WREG) 0000

W1 0002 W1 0000
W2 0004 W2 0000
W3 0006 W3 0000
W4 0008 W4 0000
W5 000A W5 0000
W6 000C W6 0000
W7 000E W7 0000
W8 0010 W8
0000
W9 0012 W9 0000
W10 0014 W10 0000
W11 0016 W11 0000
W12 0018 W12 0000
W13 001A W13 0000
W14 001C W14 0000
W15 001E W15 0800
SPLIM 0020 SPLIM xxxx
ACCAL 0022 ACCAL xxxx
ACCAH 0024 ACCAH xxxx
ACCAU 0026 Sign Extension of ACCA<39> ACCAU xxxx
ACCBL 0028 ACCBL xxxx
ACCBH 002A ACCBH xxxx
ACCBU 002C Sign Extension of ACCB<39> ACCBU xxxx
PCL 002E Program Counter Low Word Register — 0000
PCH 0030 — — — — — — — — — Program Counter High Word Register 0000
DSRPAG 0032 — — — — — — Data Space Read Page Register 0001
DSWPAG 0034 — — — — — — — Data Space Write Page Register
DS70005144E-page 41
0001
RCOUNT 0036 REPEAT Loop Counter Register 0 xxxx
DCOUNT 0038 DCOUNT<15:1> 0 xxxx
DOSTARTL 003A DOSTARTL<15:1> 0 xxxx
DOSTARTH 003C — — — — — — — — — — DOSTARTH<5:0> 00xx
DOENDL 003E DOENDL<15:1> — xxxx
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-1: CPU CORE REGISTER MAP (CONTINUED)
DS70005144E-page 42
All
SFR
Name
s
DOENDH 0040 — — — — — — — — — — DOENDH<5:0> 00xx

SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C 0000
CORCON 0044 VAR — US1 US0 EDT DL2 DL1 DL0 SATA SATB SATDW ACCSAT IPL3 SFA RND IF 0020
MODCON 0046 XMODEN YMODEN — — BWM3 BWM2 BWM1 BWM0 YWM3 YWM2 YWM1 YWM0 XWM3 XWM2 XWM1 XWM0 0000
XMODSRT 0048 XMODSRT<15:1> 0 xxxx
XMODEND 004A XMODEND<15:1> 1 xxxx
YMODSRT 004C YMODSRT<15:1> 0 xxxx
YMODEND 004E YMODEND<15:1> 1 xxxx
XBREV 0050 BREN XBREV14 XBREV13 XBREV12 XBREV11 XBREV10 XBREV9 XBREV8 XBREV7 XBREV6 XBREV5 XBREV4 XBREV3 XBREV2 XBREV1 XBREV0 8xxx
DISICNT 0052 — — DISICNT<13:0> xxxx
TBLPAG 0054 — — — — — — — — TBLPAG<7:0> 0000
MSTRPR 0058 MSTRPR<15:0> 0000
CTXTSTAT 005A — — — — — CCTXI2 CCTXI1 CCTXI0 — — — — — MCTXI2 MCTXI1 MCTXI0 0000
TABLE 4-2: TIMERS REGISTER MAP

SFR All
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Resets
TMR1 0100 Timer1 Register 0000

PR1 0102 Period Register 1 FFFF
T1CON 0104 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — TSYNC TCS — 0000
TMR3HLD 0108 Timer3 Holding Register (For 32-bit timer operations only) 0000
TMR3 010A Timer3 Register 0000
PR2 010C Period Register 2 FFFF
PR3 010E Period Register 3 FFFF
T2CON 0110 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T32 — TCS — 0000
T3CON 0112 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — — TCS — 0000
TMR5HLD 0116 Timer5 Holding Register (For 32-bit operations only) 0000
PR4 011A Period Register 4 FFFF
PR5 011C Period Register 5 FFFF
T4CON 011E TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T32 — TCS — 0000
T5CON 0120 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — — TCS — 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS70005144E-page 43
DS70005144E-page 44
TABLE 4-3: INPUT CAPTURE 1 THROUGH INPUT CAPTURE 4 REGISTER MAP
SFR All
Name Resets
IC1CON1 0140 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000
IC1CON2 0142 — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
IC1BUF 0144 Input Capture 1 Buffer Register xxxx
IC1TMR 0146 Input Capture 1 Timer Register 0000
IC2CON2 014A — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
IC2BUF 014C Input Capture 2 Buffer Register xxxx
IC2TMR 014E Input Capture 2 Timer Register 0000
IC3CON2 0152 — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
IC3BUF 0154 Input Capture 3 Buffer Register xxxx
IC3TMR 0156 Input Capture 3 Timer Register 0000
IC4CON2 015A — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
IC4BUF 015C Input Capture 4 Buffer Register xxxx
IC4TMR 015E Input Capture 4 Timer Register 0000
TABLE 4-4: I2C1 REGISTER MAP

SFR All
Name Resets
I2C1CON1 0200 I2CEN — I2CSIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000
I2C1CON2 0202 — — — — — — — — — PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 1000
I2C1STAT 0204 ACKSTAT TRSTAT ACKTIM — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000
I2C1ADD 0206 — — — — — — I2C1 Address Register 0000
I2C1MSK 0208 — — — — — — I2C1 Address Mask Register 0000
I2C1BRG 020A Baud Rate Generator Register 0000
I2C1TRN 020C — — — — — — — — I2C1 Transmit Register 00FF
I2C1RCV 020E — — — — — — — — I2C1 Receive Register 0000
TABLE 4-5: UART1 AND UART2 REGISTER MAP

SFR All
Name Resets
U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL1 PDSEL0 STSEL 0000
U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110
U1TXREG 0224 — — — — — — — UART1 Transmit Register xxxx
U1RXREG 0226 — — — — — — — UART1 Receive Register 0000
U1BRG 0228 UART1 Baud Rate Generator Prescaler Register 0000
U2MODE 0230 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL1 PDSEL0 STSEL 0000
U2STA 0232 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110
U2TXREG 0234 — — — — — — — UART2 Transmit Register xxxx
U2RXREG 0236 — — — — — — — UART2 Receive Register 0000
U2BRG 0238 UART2 Baud Rate Generator Prescaler Register 0000
TABLE 4-6: SPI1 AND SPI2 REGISTER MAP
SFR All
Name Resets
SPI1STAT 0240 SPIEN — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF 0000
SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000
SPI1CON2 0244 FRMEN SPIFSD FRMPOL — — — — — — — — — — — FRMDLY SPIBEN 0000
SPI1BUF 0248 SPI1 Transmit and Receive Buffer Register 0000
SPI2STAT 0260 SPIEN — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF 0000
SPI2CON1 0262 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000
SPI2CON2 0264 FRMEN SPIFSD FRMPOL — — — — — — — — — — — FRMDLY SPIBEN 0000
SPI2BUF 0268 SPI2 Transmit and Receive Buffer Register 0000
DS70005144E-page 45
DS70005144E-page 46
TABLE 4-7: ADC1 REGISTER MAP
SFR All
Name Resets
ADC1BUF0 0300 ADC1 Data Buffer 0 xxxx

ADC1BUF5 030A ADC1 Data Buffer 5 xxxx
ADC1BUF6 030C ADC1 Data Buffer 6 xxxx
ADC1BUF7 030E ADC1 Data Buffer 7 xxxx
ADC1BUFA 0314 ADC1 Data Buffer 10 xxxx
ADC1BUFB 0316 ADC1 Data Buffer 11 xxxx
ADC1BUFC 0318 ADC1 Data Buffer 12 xxxx
ADC1BUFD 031A ADC1 Data Buffer 13 xxxx
ADC1BUFE 031C ADC1 Data Buffer 14 xxxx
ADC1BUFF 031E ADC1 Data Buffer 15 xxxx
AD1CON1 0320 ADON — ADSIDL ADDMABM — AD12B FORM1 FORM0 SSRC2 SSRC1 SSRC0 SSRCG SIMSAM ASAM SAMP DONE 0000
AD1CON2 0322 VCFG2 VCFG1 VCFG0 — — CSCNA CHPS1 CHPS0 BUFS SMPI4 SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS 0000
AD1CON3 0324 ADRC — — SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 0000
AD1CHS123 0326 — — — CH123SB2 CH123SB1 CH123NB1 CH123NB0 CH123SB0 — — — CH123SA2 CH123SA1 CH123NA1 CH123NA0 CH123SA0 0000
AD1CHS0 0328 CH0NB — CH0SB5 CH0SB4 CH0SB3 CH0SB2 CH0SB1 CH0SB0 CH0NA — CH0SA5 CH0SA4 CH0SA3 CH0SA2 CH0SA1 CH0SA0 0000
AD1CSSH 032E CSS<31:24> — — — — CSS<19:16> 0000
AD1CSSL 0330 CSS<15:0> 0000
AD1CON4 0332 — — — — — — — ADDMAEN — — — — — DMABL2 DMABL1 DMABL0 0000
TABLE 4-8: CTMU REGISTER MAP

All
SFR
Name
s
CTMUCON1 033A CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG — — — — — — — — 0000
CTMUCON2 033C EDG1MOD EDG1POL EDG1SEL3 EDG1SEL2 EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT EDG2MOD EDG2POL EDG2SEL3 EDG2SEL2 EDG2SEL1 EDG2SEL0 — — 0000
CTMUICON 033E ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 — — — — — — — — 0000
TABLE 4-9: CAN1 REGISTER MAP WHEN WIN (C1CTRL<0>) = 0 OR 1 FOR dsPIC33EVXXXGM10X DEVICES
SFR All
Name Resets
C1CTRL1 0400 — — CSIDL ABAT CANCKS REQOP2 REQOP1 REQOP0 OPMODE2 OPMODE1 OPMODE0 — CANCAP — — WIN 0480
C1CTRL2 0402 — — — — — — — — — — — DNCNT<4:0> 0000
C1VEC 0404 — — — FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 — ICODE6 ICODE5 ICODE4 ICODE3 ICODE2 ICODE1 ICODE0 0000
C1FCTRL 0406 DMABS2 DMABS1 DMABS0 — — — — — — — FSA5 FSA4 FSA3 FSA2 FSA1 FSA0 0000
C1FIFO 0408 — — FBP5 FBP4 FBP3 FBP2 FBP1 FBP0 — — FNRB5 FNRB4 FNRB3 FNRB2 FNRB1 FNRB0 0000
C1INTF 040A — — TXBO TXBP RXBP TXWAR RXWAR EWARN IVRIF WAKIF ERRIF — FIFOIF RBOVIF RBIF TBIF 0000
C1INTE 040C — — — — — — — — IVRIE WAKIE ERRIE — FIFOIE RBOVIE RBIE TBIE 0000
C1EC 040E TERRCNT7 TERRCNT6 TERRCNT5 TERRCNT4 TERRCNT3 TERRCNT2 TERRCNT1 TERRCNT0 RERRCNT7 RERRCNT6 RERRCNT5 RERRCNT4 RERRCNT3 RERRCNT2 RERRCNT1 RERRCNT0 0000
C1CFG1 0410 — — — — — — — — SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 0000
C1CFG2 0412 — WAKFIL — — — SEG2PH2 SEG2PH1 SEG2PH0 SEG2PHTS SAM SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2 PRSEG1 PRSEG0 0000
C1FEN1 0414 FLTEN<15:0> FFFF
C1FMSKSEL1 0418 F7MSK1 F7MSK0 F6MSK1 F6MSK0 F5MSK1 F5MSK0 F4MSK1 F4MSK0 F3MSK1 F3MSK0 F2MSK1 F2MSK0 F1MSK1 F1MSK0 F0MSK1 F0MSK0 0000
C1FMSKSEL2 041A F15MSK1 F15MSK0 F14MSK1 F14MSK0 F13MSK1 F13MSK0 F12MSK1 F12MSK0 F11MSK1 F11MSK0 F10MSK1 F10MSK0 F9MSK1 F9MSK0 F8MSK1 F8MSK0 0000
TABLE 4-10: CAN1 REGISTER MAP WHEN WIN (C1CTRL<0>) = 0 FOR dsPIC33EVXXXGM10X DEVICES
SFR All
Name Resets
0400- See definition when WIN = x

041E
C1RXFUL1 0420 RXFUL<15:0> 0000
C1RXFUL2 0422 RXFUL<31:16> 0000
C1RXOVF1 0428 RXOVF<15:0> 0000
C1RXOVF2 042A RXOVF<31:16> 0000
C1TR01CON 0430 TXEN1 TXABT1 TXLARB1 TXERR1 TXREQ1 RTREN1 TX1PRI1 TX1PRI0 TXEN0 TXABAT0 TXLARB0 TXERR0 TXREQ0 RTREN0 TX0PRI1 TX0PRI0 0000
C1TR67CON 0436 TXEN7 TXABT7 TXLARB7 TXERR7 TXREQ7 RTREN7 TX7PRI1 TX7PRI0 TXEN6 TXABAT6 TXLARB6 TXERR6 TXREQ6 RTREN6 TX6PRI1 TX6PRI0 xxxx
DS70005144E-page 47
C1RXD 0440 CAN1 Receive Data Word Register xxxx

C1TXD 0442 CAN1 Transmit Data Word Register xxxx
DS70005144E-page 48
TABLE 4-11: CAN1 REGISTER MAP WHEN WIN (C1CTRL<0>) = 1 FOR dsPIC33EVXXXGM10X DEVICES
SFR All
Name Resets
0400- See definition when WIN = x

041E
C1BUFPNT1 0420 F3BP3 F3BP2 F3BP1 F3BP0 F2BP3 F2BP2 F2BP1 F2BP0 F1BP3 F1BP2 F1BP1 F1BP0 F0BP3 F0BP2 F0BP1 F0BP0 0000
C1RXM0SID 0430 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 — MIDE — EID17 EID16 xxxx
C1RXM0EID 0432 EID<15:0> xxxx
C1RXM1EID 0436 EID<15:0> xxxx
C1RXM2EID 043A EID<15:0> xxxx
C1RXF0SID 0440 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 — EXIDE — EID17 EID16 xxxx
C1RXF0EID 0442 EID<15:0> xxxx
C1RXF2EID 044A EID<15:0> xxxx
C1RXF3SID 044C SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 — EXIDE — EID17 EID16 xxxx
C1RXF3EID 044E EID<15:0> xxxx
TABLE 4-11: CAN1 REGISTER MAP WHEN WIN (C1CTRL<0>) = 1 FOR dsPIC33EVXXXGM10X DEVICES (CONTINUED)
SFR All
Name Resets
TABLE 4-12: SENT1 RECEIVER REGISTER MAP
SFR All
Name Resets
SENT1CON1 0500 SNTEN — SNTSIDL — RCVEN TXM TXPOL CRCEN PPP SPCEN — PS — NIBCNT2 NIBCNT1 NIBCNT0 0000
SENT1CON2 0504 TICKTIME<15:0> (Transmit modes) or SYNCMAX<15:0> (Receive mode) FFFF
SENT1CON3 0508 FRAMETIME<15:0> (Transmit modes) or SYNCMIN<15:0> (Receive mode) FFFF
SENT1STAT 050C — — — — — — — — PAUSE NIB2 NIB1 NIB0 CRCERR FRMERR RXIDLE SYNCTXEN 0000
SENT1SYNC 0510 Synchronization Time Period Register (Transmit mode) 0000
SENT1DATL 0514 DATA4<3:0> DATA5<3:0> DATA6<3:0> CRC<3:0> 0000
SENT1DATH 0516 STAT<3:0> DATA1<3:0> DATA2<3:0> DATA3<3:0> 0000
TABLE 4-13: SENT2 RECEIVER REGISTER MAP

SFR All
Name Resets
SENT2CON1 0520 SNTEN — SNTSIDL — RCVEN TXM TXPOL CRCEN PPP SPCEN — PS — NIBCNT2 NIBCNT1 NIBCNT0 0000
SENT2CON2 0524 TICKTIME<15:0> (Transmit modes) or SYNCMAX<15:0> (Receive mode)
DS70005144E-page 49
FFFF
SENT2CON3 0528 FRAMETIME<15:0> (Transmit modes) or SYNCMIN<15:0> (Receive mode) FFFF
SENT2STAT 052C — — — — — — — — PAUSE NIB2 NIB1 NIB0 CRCERR FRMERR RXIDLE SYNCTXEN 0000
SENT2SYNC 0530 Synchronization Time Period Register (Transmit mode) 0000
SENT2DATL 0534 DATA4<3:0> DATA5<3:0> DATA6<3:0> CRC<3:0> 0000
SENT2DATH 0536 STAT<3:0> DATA1<3:0> DATA2<3:0> DATA3<3:0> 0000
TABLE 4-14: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EVXXXGM002/102 DEVICES
DS70005144E-page 50
SFR All
Name Resets
RPOR0 0670 — — RP35R5 RP35R4 RP35R3 RP35R2 RP35R1 RP35R0 — — RP20R5 RP20R4 RP20R3 RP20R2 RP20R1 RP20R0 0000
RPOR10 0684 — — RP176R<5:0> — — — — — — — — 0000
RPOR13 068A — — — — — — — — — — RP181R<5:0> 0000
SFR All
Name Resets
RPOR5 067A — — RP49R5 RP49R4 RP49R3 RP49R2 RP49R1 RP49R0 — — RP48R5 RP48R4 RP48R3 RP48R2 RP48R1 RP48R0 0000
RPOR6 067C — — RP55R5 RP55R4 RP55R3 RP55R2 RP55R1 RP55R0 — — RP54R5 RP54R4 RP54R3 RP54R2 RP54R1 RP54R0 0000
RPOR7 067E — — RP57R5 RP57R4 RP57R3 RP57R2 RP57R1 RP57R0 — — RP56R5 RP56R4 RP56R3 RP56R2 RP56R1 RP56R0 0000
RPOR10 0684 — — RP176R<5:0> — — — — — — — — 0000
RPOR13 068A — — — — — — — — — — RP181R<5:0> 0000
SFR All
Name Resets
RPOR5 067A — — RP49R5 RP49R4 RP49R3 RP49R2 RP49R1 RP49R0 — — RP48R5 RP48R4 RP48R3 RP48R2 RP48R1 RP48R0 0000
RPOR6 067C — — RP55R5 RP55R4 RP55R3 RP55R2 RP55R1 RP55R0 — — RP54R5 RP54R4 RP54R3 RP54R2 RP54R1 RP54R0 0000
RPOR7 067E — — RP57R5 RP57R4 RP57R3 RP57R2 RP57R1 RP57R0 — — RP56R5 RP56R4 RP56R3 RP56R2 RP56R1 RP56R0 0000
RPOR13 068A — — — — — — — — — — RP181R<5:0> 0000
DS70005144E-page 51
DS70005144E-page 52
TABLE 4-17: PERIPHERAL INPUT REMAP REGISTER MAP
SFR All
Name Resets
RPINR0 06A0 INT1R<7:0> — — — — — — — — 0000

RPINR1 06A2 — — — — — — — — INT2R<7:0> 0000
RPINR3 06A6 — — — — — — — — T2CKR<7:0> 0000
RPINR7 06AE IC2R7 IC2R6 IC2R5 IC2R4 IC2R3 IC2R2 IC2R1 IC2R0 IC1R7 IC1R6 IC1R5 IC1R4 IC1R3 IC1R2 IC1R1 IC1R0 0000
RPINR8 06B0 IC4R7 IC4R6 IC4R5 IC4R4 IC4R3 IC4R2 IC4R1 IC4R0 IC3R7 IC3R6 IC3R5 IC3R4 IC3R3 IC3R2 IC3R1 IC3R0 0000
RPINR11 06B6 — — — — — — — — OCFAR<7:0> 0000
RPINR12 06B8 FLT2R7 FLT2R6 FLT2R5 FLT2R4 FLT2R3 FLT2R2 FLT2R1 FLT2R0 FLT1R7 FLT1R6 FLT1R5 FLT1R4 FLT1R3 FLT1R2 FLT1R1 FLT1R0 0000
RPINR18 06C4 — — — — — — — — U1RXR<7:0> 0000
RPINR19 06C6 — — — — — — — — U2RXR<7:0> 0000
RPINR22 06CC SCK2R7 SCK2R6 SCK2R5 SCK2R4 SCK2R3 SCK2R2 SCK2R1 SCK2R0 SDI2R7 SDI2R6 SDI2R5 SDI2R4 SDI2R3 SDI2R2 SDI2R1 SDI2R0 0000
RPINR23 06CE — — — — — — — — SS2R<7:0> 0000
RPINR26 06D4 — — — — — — — — C1RXR<7:0>(1) 0000
RPINR37 06EA SYNCI1R<7:0> — — — — — — — — 0000
RPINR38 06EC DTCMP1R<7:0> — — — — — — — — 0000
RPINR39 06EE DTCMP3R7 DTCMP3R6 DTCMP3R5 DTCMP3R4 DTCMP3R3 DTCMP3R2 DTCMP3R1 DTCMP3R0 DTCMP2R7 DTCMP2R6 DTCMP2R5 DTCMP2R4 DTCMP2R3 DTCMP2R2 DTCMP2R1 DTCMP2R0 0000
RPINR44 06F8 SENT1R<7:0> — — — — — — — — 0000
RPINR45 06FA — — — — — — — — SENT2R<7:0> 0000
Note 1: This feature is available only on dsPIC33EVXXXGM10X devices.
TABLE 4-18: DMT REGISTER MAP

SFR All
Name Resets
DMTCON 0700 ON — — — — — — — — — — — — — — —
0000
DMTPRECLR 0704 STEP1<7:0> — — — — — — — — 0000
DMTCLR 0708 — — — — — — — — STEP2<7:0> 0000
DMTSTAT 070C — — — — — — — — BAD1 BAD2 DMTEVENT — — — — WINOPN 0000
DMTCNTL 0710 COUNTER<15:0> 0000
DMTCNTH 0712 COUNTER<31:16> 0000
DMTHOLDREG 0714 UPRCNT<15:0> 0000
DMTPSCNTL 0718 PSCNT<15:0> 0000
DMTPSCNTH 071A PSCNT<31:16> 0000
DMTPSINTVL 071C PSINTV<15:0> 0000
DMTPSINTVH 071E PSINTV<31:16> 0000
TABLE 4-19: NVM REGISTER MAP
SFR All
Name Resets
NVMCON 0728 WR WREN WRERR NVMSIDL — — RPDF URERR — — — — NVMOP3 NVMOP2 NVMOP1 NVMOP0 0000
NVMADR 072A NVMADR<15:0> 0000
NVMADRU 072C — — — — — — — — NVMADRU<23:16> 0000
NVMKEY 072E — — — — — — — — NVMKEY<7:0> 0000
NVMSRCADRL 0730 NVMSRCADR<15:1> 0 0000
NVMSRCADRH 0732 — — — — — — — — NVMSRCADR<23:16> 0000
TABLE 4-20: SYSTEM CONTROL REGISTER MAP

SFR All
Name Resets
RCON 0740 TRAPR IOPUWR — — VREGSF — CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR Note 1
OSCCON 0742 — COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0 CLKLOCK IOLOCK LOCK — CF — — OSWEN Note 2
CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 DOZEN FRCDIV2 FRCDIV1 FRCDIV0 PLLPOST1 PLLPOST0 — PLLPRE4 PLLPRE3 PLLPRE2 PLLPRE1 PLLPRE0 0000
PLLFBD 0746 — — — — — — — PLLDIV<8:0> 0000
OSCTUN 0748 — — — — — — — — — — TUN<5:0> 0000
Note 1: RCON register Reset values are dependent on the type of Reset.
2: OSCCON register Reset values are dependent on the Configuration fuses.
TABLE 4-21: REFERENCE CLOCK REGISTER MAP

SFR All
Name Resets
REFOCON 074E ROON — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 — — — — — — — — 0000
DS70005144E-page 53
DS70005144E-page 54
TABLE 4-22: PMD REGISTER MAP FOR dsPIC33EVXXXGM00X/10X FAMILY DEVICES
SFR All
Name Resets
PMD1 0760 T5MD T4MD T3MD T2MD T1MD — PWMMD — I2C1MD U2MD U1MD SPI2MD SPI1MD — C1MD(1) AD1MD 0000
PMD2 0762 — — — — IC4MD IC3MD IC2MD IC1MD — — — — OC4MD OC3MD OC2MD OC1MD 0000
PMD3 0764 — — — — — CMPMD — — — — — — — — — — 0000
PMD4 0766 — — — — — — — — — — — REFOMD CTMUMD — — 0000
PMD6 076A — — — — — PWM3MD PWM2MD PWM1MD — — — — — — — — 0000
PMD7 076C — — — — — — — — — — — DMA0MD — — — — 0000
DMA1MD
DMA2MD
DMA3MD
PMD8 076E — — — SENT2MD SENT1MD — — DMTMD — — — — — — — — 0000
TABLE 4-23: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EVXXXGM00X/10X FAMILY DEVICES
SFR All
Name Resets
IFS0 0800 NVMIF DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF 0000
IFS1 0802 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF — — — INT1IF CNIF CMPIF MI2C1IF SI2C1IF 0000
IFS2 0804 — — — — — — — — — IC4IF IC3IF DMA3IF C1IF C1RXIF(1) SPI2IF SPI2EIF 0000
IFS3 0806 — — — — — — PSEMIF — — — — — — — — — 0000
IFS4 0808 — — CTMUIF — — — — — — C1TXIF(1) — — — U2EIF U1EIF — 0000
IFS5 080A PWM2IF PWM1IF — — — — — — — — — — — — — — 0000
IFS6 080C — — — — — — — — — — — — — — — PWM3IF 0000
IFS8 0810 — ICDIF — — — — — — — — — — — — — — 0000
IFS10 0814 — — I2C1BCIF — — — — — — — — — — — — 0000
IFS11 0816 — — — — — ECCSBEIF SENT2IF SENT2EIF SENT1IF SENT1EIF — — — — — — 0000
IEC0 0820 NVMIE DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE 0000
IEC1 0822 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE — — — INT1IE CNIE CMPIE MI2C1IE SI2C1IE 0000
IEC2 0824 — — — — — — — — — IC4IE IC3IE DMA3IE C1IE C1RXIE(1) SPI2IE SPI2EIE 0000
IEC3 0826 — — — — — — PSEMIE — — — — — — — — — 0000
IEC4 0828 — — CTMUIE — — — — — — C1TXIE(1) — — — U2EIE U1EIE — 0000
IEC5 082A PWM2IE PWM1IE — — — — — — — — — — — — — — 0000
IEC6 082C — — — — — — — — — — — — — — — PWM3IE 0000
IEC8 0830 — ICDIE — — — — — — — — — — — — — — 0000
IEC10 0834 — — I2C1BCIE — — — — — — — — — — — — — 0000
IEC11 0836 — — — — — ECCSBEIE SENT2IE SENT2EIE SENT1IE SENT1EIE — — — — — — 0000
IPC0 0840 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 4444
IPC1 0842 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 — IC2IP2 IC2IP1 IC2IP0 — DMA0IP2 DMA0IP1 DMA0IP0 4444
IPC2 0844 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPI1EIP2 SPI1EIP1 SPI1EIP0 — T3IP2 T3IP1 T3IP0 4444
IPC3 0846 — NVMIP2 NVMIP1 NVMIP0 — DMA1IP2 DMA1IP1 DMA1IP0 — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 4444
IPC4 0848 — CNIP2 CNIP1 CNIP0 — CMPIP2 CMPIP1 CMPIP0 — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0 4444
IPC5 084A — — — — — — — — — — — — — INT1IP<2:0> 0004
IPC6 084C — T4IP2 T4IP1 T4IP0 — OC4IP2 OC4IP1 OC4IP0 — OC3IP2 OC3IP1 OC3IP0 — DMA2IP2 DMA2IP1 DMA2IP0 4444
IPC7 084E — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0 4444
IPC8 0850 — C1IP2 C1IP1 C1IP0 — C1RXIP2(1) C1RXIP1(1) C1RXIP0(1) — SPI2IP2 SPI2IP1 SPI2IP0 — SPI2EIP2 SPI2EIP1 SPI2EIP0 4444
DS70005144E-page 55
IPC9 0852 — — — — — IC4IP2 IC4IP1 IC4IP0 — IC3IP2 IC3IP1 IC3IP0 — DMA3IP2 DMA3IP1 DMA3IP0 0444
IPC14 085C — — — — — — — — — PSEMIP<2:0> — — — — 0040
IPC16 0860 — — — — — U2EIP2 U2EIP1 U2EIP0 — U1EIP2 U1EIP1 U1EIP0 — — — — 0440
IPC17 0862 — — — — — C1TXIP<2:0>(1) — — — — — — — — 0400
Legend: — = unimplemented, read as ‘0’ Reset values are shown in hexadecimal.
DS70005144E-page 56
TABLE 4-23: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EVXXXGM00X/10X FAMILY DEVICES (CONTINUED)
SFR All
Name Resets
IPC19 0866 — — — — — — — — — CTMUIP<2:0> — — — — 0040

IPC23 086E — PWM2IP2 PWM2IP1 PWM2IP0 — PWM1IP2 PWM1IP1 PWM1IP0 — — — — — — — — 4400
IPC24 0870 — — — — — — — — — — — — — PWM3IP<2:0> 0004
IPC35 0886 — — — — — ICDIP<2:0> — — — — — — — — 0400
IPC43 0896 — — — — — — — — — I2C1BCIP<2:0> — — — — 0040
IPC45 089A — SENT1IP2 SENT1IP1 SENT1IP0 — SENT1EIP2 SENT1EIP1 SENT1EIP0 — — — — — — — — 4400
IPC46 089C — — — — — ECCSBEIP2 ECCSBEIP1 ECCSBEIP0 — SENT2IP2 SENT2IP1 SENT2IP0 — SENT2EIP2 SENT2EIP1 SENT2EIP0 0444
INTCON1 08C0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL — 0000
INTCON2 08C2 GIE DISI SWTRAP — — — — AIVTEN — — — — — INT2EP INT1EP INT0EP 0000
INTCON3 08C4 DMT — — — — — — — — — DAE DOOVR — — — — 0000
INTCON4 08C6 — — — — — — — — — — — — — — ECCDBE SGHT 0000
INTTREG 08C8 — — — — — ILR3 ILR2 ILR1 VECNUM7 VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 0000
Legend: — = unimplemented, read as ‘0’ Reset values are shown in hexadecimal.
TABLE 4-24: OUTPUT COMPARE REGISTER MAP

SFR All
Name Resets
OC1CON1 0900 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 — — ENFLTA — — OCFLTA TRIGMODE OCM2 OCM1 OCM0 0000
OC1CON2 0902 FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C
OC1RS 0904 Output Compare 1 Secondary Register xxxx
OC1R 0906 Output Compare 1 Register xxxx
OC1TMR 0908 Output Compare 1 Timer Value Register xxxx
OC2CON1 090A — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 — — ENFLTA — — OCFLTA TRIGMODE OCM2 OCM1 OCM0 0000
OC2CON2 090C FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C
OC2RS 090E Output Compare 2 Secondary Register xxxx
OC3CON1 0914 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 — — ENFLTA — — OCFLTA TRIGMODE OCM2 OCM1 OCM0 0000
OC3R 091A Output Compare 3 Register xxxx
OC3TMR 091C Output Compare 3 Timer Value Register xxxx
OC4CON1 091E — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 — — ENFLTA — — OCFLTA TRIGMODE OCM2 OCM1 OCM0 0000
DS70005144E-page 57
DS70005144E-page 58
TABLE 4-25: OP AMP/COMPARATOR REGISTER MAP
SFR All
Name Resets
CMSTAT 0A80 PSIDL — — C5EVT C4EVT C3EVT C2EVT C1EVT — — — C5OUT C4OUT C3OUT C2OUT C1OUT 0000
CVR1CON 0A82 CVREN CVROE — — CVRSS VREFSEL — — — CVR6 CVR5 CVR4 CVR3 CVR2 CVR1 CVR0 0000
CM1CON 0A84 CON COE CPOL — — OPAEN CEVT COUT EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 0000
CM1MSKSRC 0A86 — — — — SELSRCC3 SELSRCC2 SELSRCC1 SELSRCC0 SELSRCB3 SELSRCB2 SELSRCB1 SELSRCB0 SELSRCA3 SELSRCA2 SELSRCA1 SELSRCA0 0000
CM1MSKCON 0A88 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN 0000
CM1FLTR 0A8A — — — — — — — — — CFSEL2 CFSEL1 CFSEL0 CFLTREN CFDIV2 CFDIV1 CFDIV0 0000
CM2CON 0A8C CON COE CPOL — — OPAEN CEVT COUT EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 0000
CM2MSKSRC 0A8E — — — — SELSRCC3 SELSRCC2 SELSRCC1 SELSRCC0 SELSRCB3 SELSRCB2 SELSRCB1 SELSRCB0 SELSRCA3 SELSRCA2 SELSRCA1 SELSRCA0 0000
CM2FLTR 0A92 — — — — — — — — — CFSEL2 CFSEL1 CFSEL0 CFLTREN CFDIV2 CFDIV1 CFDIV0 0000
CM3CON 0A94 CON COE CPOL — — OPAEN CEVT COUT EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 0000
CM3MSKSRC 0A96 — — — — SELSRCC3 SELSRCC2 SELSRCC1 SELSRCC0 SELSRCB3 SELSRCB2 SELSRCB1 SELSRCB0 SELSRCA3 SELSRCA2 SELSRCA1 SELSRCA0 0000
CM3FLTR 0A9A — — — — — — — — — CFSEL2 CFSEL1 CFSEL0 CFLTREN CFDIV2 CFDIV1 CFDIV0 0000
CM4CON 0A9C CON COE CPOL — — — CEVT COUT EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 0000
CM4MSKSRC 0A9E — — — — SELSRCC3 SELSRCC2 SELSRCC1 SELSRCC0 SELSRCB3 SELSRCB2 SELSRCB1 SELSRCB0 SELSRCA3 SELSRCA2 SELSRCA1 SELSRCA0 0000
CM4MSKCON 0AA0 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN 0000
CM4FLTR 0AA2 — — — — — — — — — CFSEL2 CFSEL1 CFSEL0 CFLTREN CFDIV2 CFDIV1 CFDIV0 0000
CM5CON 0AA4 CON COE CPOL — — OPAEN CEVT COUT EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 0000
CM5MSKSRC 0AA6 — — — — SELSRCC3 SELSRCC2 SELSRCC1 SELSRCC0 SELSRCB3 SELSRCB2 SELSRCB1 SELSRCB0 SELSRCA3 SELSRCA2 SELSRCA1 SELSRCA0 0000
CM5MSKCON 0AA8 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN 0000
CM5FLTR 0AAA — — — — — — — — — CFSEL2 CFSEL1 CFSEL0 CFLTREN CFDIV2 CFDIV1 CFDIV0 0000
CVR2CON 0AB4 CVREN CVROE(1) — — CVRSS VREFSEL — — — CVR6 CVR5 CVR4 CVR3 CVR2 CVR1 CVR0 0000
Note 1: CVROE (CVR2CON<14>) is not available on 28-pin devices.
TABLE 4-26: DMAC REGISTER MAP
SFR All
Name Resets
DMA0CON 0B00 CHEN SIZE DIR HALF NULLW — — — — — AMODE1 AMODE0 — — MODE1 MODE0 0000
DMA0REQ 0B02 FORCE — — — — — — — IRQSEL7 IRQSEL6 IRQSEL5 IRQSEL4 IRQSEL3 IRQSEL2 IRQSEL1 IRQSEL0 00FF
DMA0STAL 0B04 STA<15:0> 0000
DMA0STAH 0B06 — — — — — — — — STA<23:16> 0000
DMA0STBL 0B08 STB<15:0> 0000
DMA0STBH 0B0A — — — — — — — — STB<23:16> 0000
DMA0PAD 0B0C PAD<15:0> 0000
DMA0CNT 0B0E — — CNT<13:0> 0000
DMA1STAL 0B14 STA<15:0> 0000
DMA1STAH 0B16 — — — — — — — — STA<23:16> 0000
DMA1STBL 0B18 STB<15:0> 0000
DMA1STBH 0B1A — — — — — — — — STB<23:16> 0000
DMA1CNT 0B1E — — CNT<13:0> 0000
DMA2STAL 0B24 STA<15:0> 0000
DMA2STAH 0B26 — — — — — — — — STA<23:16> 0000
DMA2STBL 0B28 STB<15:0> 0000
DMA2STBH 0B2A — — — — — — — — STB<23:16> 0000
DMA2CNT 0B2E — — CNT<13:0> 0000
DMA3STAL 0B34 STA<15:0> 0000
DMA3STAH 0B36 — — — — — — — — STA<23:16> 0000
DMA3STBL 0B38 STB<15:0> 0000
DS70005144E-page 59
DMA3STBH 0B3A — — — — — — — — STB<23:16> 0000

DMA3CNT 0B3E — — CNT<13:0> 0000
DMAPWC 0BF0 — — — — — — — — — — — — PWCOL<3:0> 0000
DMARQC 0BF2 — — — — — — — — — — — — RQCOL<3:0> 0000
DMAPPS 0BF4 — — — — — — — — — — — — PPST<3:0> 0000
DS70005144E-page 60
TABLE 4-26: DMAC REGISTER MAP (CONTINUED)
SFR All
Name Resets
DMALCA 0BF6 — — — — — — — — — — — — LSTCH<3:0> 000F

DSADRL 0BF8 DSADR<15:0> 0000
DSADRH 0BFA — — — — — — — — DSADR<23:16> 0000
TABLE 4-27: PWM REGISTER MAP

SFR All
Name Resets
PTCON 0C00 PTEN — PTSIDL SESTAT SEIEN EIPU SYNCPOL SYNCOEN SYNCEN SYNCSRC2 SYNCSRC1 SYNCSRC0 SEVTPS3 SEVTPS2 SEVTPS1 SEVTPS0 0000
PTCON2 0C02 — — — — — — — — — — — — — PCLKDIV<2:0> 0000
PTPER 0C04 PTPER<15:0> FFF8
SEVTCMP 0C06 SEVTCMP<15:0> 0000
MDC 0C0A MDC<15:0> 0000
CHOP 0C1A CHPCLKEN — — — — — CHOPCLK9 CHOPCLK8 CHOPCLK7 CHOPCLK6 CHOPCLK5 CHOPCLK4 CHOPCLK3 CHOPCLK2 CHOPCLK1 CHOPCLK0 0000
PWMKEY 0C1E PWMKEY<15:0> 0000
TABLE 4-28: PWM GENERATOR 1 REGISTER MAP

SFR All
Name Resets
PWMCON1 0C20 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC1 DTC0 DTCP — — CAM XPRES IUE 0000
IOCON1 0C22 PENH PENL POLH POLL PMOD1 PMOD0 OVRENH OVRENL OVRDAT1 OVRDAT0 FLTDAT1 FLTDAT0 CLDAT1 CLDAT0 SWAP OSYNC 0000
FCLCON1 0C24 — CLSRC4 CLSRC3 CLSRC2 CLSRC1 CLSRC0 CLPOL CLMOD FLTSRC4 FLTSRC3 FLTSRC2 FLTSRC1 FLTSRC0 FLTPOL FLTMOD1 FLTMOD0 0000
PDC1 0C26 PDC1<15:0> 0000

PHASE1 0C28 PHASE1<15:0> 0000
DTR1 0C2A — — DTR1<13:0> 0000
ALTDTR1 0C2C — — ALTDTR1<13:0> 0000
TRIG1 0C32 TRGCMP<15:0> 0000
TRGCON1 0C34 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0 — — — — — — TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0 0000
PWMCAP1 0C38 PWMCAP1<15:0> 0000
LEBCON1 0C3A PHR PHF PLR PLF FLTLEBEN CLLEBEN — — — — BCH BCL BPHH BPHL BPLH BPLL 0000
LEBDLY1 0C3C — — — — LEB<11:0> 0000
AUXCON1 0C3E — — — — BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0 — — CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN 0000

SFR All
Name Resets
PDC2 0C46 PDC2<15:0> 0000
PHASE2 0C48 PHASE2<15:0> 0000
DTR2 0C4A — — DTR2<13:0> 0000
TRIG2 0C52 TRGCMP<15:0> 0000
LEBDLY2 0C5C — — — — LEB<11:0> 0000

SFR All
Name Resets
PDC3 0C66 PDC3<15:0> 0000
PHASE3 0C68 PHASE3<15:0> 0000
DTR3 0C6A — — DTR3<13:0> 0000
TRIG3 0C72 TRGCMP<15:0> 0000
DS70005144E-page 61
LEBDLY3 0C7C — — — — LEB<11:0> 0000
DS70005144E-page 62
TABLE 4-31: PORTA REGISTER MAP FOR dsPIC33EVXXXGMX06 DEVICES
SFR All
Name Resets
TRISA 0E00 — — — TRISA<12:7> — — TRISA4 — — TRISA<1:0> 1F93

PORTA 0E02 — — — RA<12:7> — — RA4 — — RA<1:0> 0000
LATA 0E04 — — — LATA<12:7> — — LATA4 — — LATA<1:0> 0000
ODCA 0E06 — — — ODCA<12:7> — — ODCA4 — — ODCA<1:0> 0000
CNENA 0E08 — — — CNIEA<12:7> — — CNIEA4 — — CNIEA<1:0> 0000
CNPUA 0E0A — — — CNPUA<12:7> — — CNPUA4 — — CNPUA<1:0> 0000
CNPDA 0E0C — — — CNPDA<12:7> — — CNPDA4 — — CNPDA<1:0> 0000
ANSELA 0E0E — — — ANSA<12:9> — ANSA7 — — ANSA4 — — ANSA<1:0> 1E93
SR1A 0E10 — — — — — — SR1A9 — — — — SR1A4 — — — — 0000
SR0A 0E12 — — — — — — SR0A9 — — — — SR0A4 — — — — 0000

SFR All
Name Resets
TRISA 0E00 — — — — — TRISA<10:7> — — TRISA<4:0> DF9F

PORTA 0E02 — — — — — RA<10:7> — — RA<4:0> 0000
LATA 0E04 — — — — — LATA<10:7> — — LATA<4:0> 0000
ODCA 0E06 — — — — — ODCA<10:7> — — ODCA<4:0> 0000
CNENA 0E08 — — — — — CNIEA<10:7> — — CNIEA<4:0> 0000
CNPUA 0E0A — — — — — CNPUA<10:7> — — CNPUA<4:0> 0000
CNPDA 0E0C — — — — — CNPDA<10:7> — — CNPDA<4:0> 0000
ANSELA 0E0E — — — — — ANSA<10:9> — ANSA7 — — ANSA4 — ANSA<2:0> 1813
SR1A 0E10 — — — — — — SR1A9 — — — — SR1A4 — — — —
0000
SR0A 0E12 — — — — — — SR0A9 — — — — SR0A4 — — — — 0000

SFR All
Name Resets
TRISA 0E00 — — — — — — — — — — — TRISA<4:0> DF9F

PORTA 0E02 — — — — — — — — — — — RA<4:0> 0000
LATA 0E04 — — — — — — — — — — — LATA<4:0> 0000
ODCA 0E06 — — — — — — — — — — — ODCA<4:0> 0000
CNENA 0E08 — — — — — — — — — — — CNIEA<4:0> 0000
CNPUA 0E0A — — — — — — — — — — — CNPUA<4:0> 0000
CNPDA 0E0C — — — — — — — — — — — CNPDA<4:0> 0000
ANSELA 0E0E — — — — — — — — — — — ANSA4 — ANSA<2:0> 1813
SR1A 0E10 — — — — — — — — — — — SR1A4 — — — — 0000
SR0A 0E12 — — — — — — — — — — — SR0A4 — — — — 0000
TABLE 4-34: PORTB REGISTER MAP FOR dsPIC33EVXXXGMX06 DEVICES
SFR All
Name Resets
TRISB 0E14 TRISB<15:0> FFFF

PORTB 0E16 RB<15:0> xxxx
LATB 0E18 LATB<15:0> xxxx
ODCB 0E1A ODCB<15:0> 0000
CNENB 0E1C CNIEB<15:0> 0000
CNPUB 0E1E CNPUB<15:0> 0000
CNPDB 0E20 CNPDB<15:0> 0000
ANSELB 0E22 — — — — — — ANSB<9:7> — — — ANSB<3:0> 038F
SR1B 0E24 — — — — — — SR1B<9:7> — — SR1B4 — — — — 0000
SR0B 0E26 — — — — — — SR0B<9:7> — — SR0B4 — — — — 0000
DS70005144E-page 63
DS70005144E-page 64
SFR All
Name Resets
TRISB 0E14 TRISB<15:0> DF9F

SR1B 0E24 — — — — — — SR1B<9:7> — — SR1B4 — — — — 0000
SR0B 0E26 — — — — — — SR0B<9:7> — — SR0B4 — — — — 0000

SFR All
Name Resets
TRISB 0E14 TRISB<15:0> DF9F

SR1B 0E24 — — — — — — SR1B<9:7> — — SR1B4 — — — — 0000

SR0B 0E26 — — — — — — SR0B<9:7> — — SR0B4 — — — — 0000
TABLE 4-37: PORTC REGISTER MAP FOR dsPIC33EVXXXGMX06 DEVICES

SFR All
Name Resets
TRISC 0E28 TRISC15 — TRISC<13:0> BFFF

PORTC 0E2A RC15 — RC<13:0> xxxx
LATC 0E2C LATC15 — LATC<13:0> xxxx
ODCC 0E2E ODCC15 — ODCC<13:0> 0000
CNENC 0E30 CNIEC15 — CNIEC<13:0> 0000
CNPUC 0E32 CNPUC15 — CNPUC<13:0> 0000
CNPDC 0E34 CNPDC15 — CNPDC<13:0> 0000
ANSELC 0E36 — — — ANSC<12:0> 1FFF
SR1C 0E38 — — — — — — SR1C<9:6> — — SR1C3 — — — 0000
SR0C 0E3A — — — — — — SR0C<9:6> — — SR0C3 — — — 0000
TABLE 4-38: PORTC REGISTER MAP FOR dsPIC33EVXXXGMX04 DEVICES
SFR All
Name Resets
TRISC 0E28 — — — — — — TRISC<9:0> BFFF

PORTC 0E2A — — — — — — RC<9:0> xxxx
LATC 0E2C — — — — — — LATC<9:0> xxxx
ODCC 0E2E — — — — — — ODCC<9:0> 0000
CNENC 0E30 — — — — — — CNIEC<9:0> 0000
CNPUC 0E32 — — — — — — CNPUC<9:0> 0000
CNPDC 0E34 — — — — — — CNPDC<9:0> 0000
ANSELC 0E36 — — — — — — ANSC<9:0> 0807
SR1C 0E38 — — — — — — SR1C<9:6> — — SR1C3 — — — 0000
SR0C 0E3A — — — — — — SR0C<9:6> — — SR0C3 — — — 0000
DS70005144E-page 65
TABLE 4-39: PORTD REGISTER MAP FOR dsPIC33EVXXXGMX06 DEVICES
DS70005144E-page 66
SFR All
Name Resets
TRISD 0E3C — — — — — — — TRISD8 — TRISD<6:5> — — — — — 0160

PORTD 0E3E — — — — — — — RD8 — RD<6:5> — — — — — xxxx
LATD 0E40 — — — — — — — LATD8 — LATD<6:5> — — — — — xxxx
ODCD 0E42 — — — — — — — ODCD8 — ODCD<6:5> — — — — — 0000
CNEND 0E44 — — — — — — — CNIED8 — CNIED<6:5> — — — — — 0000
CNPUD 0E46 — — — — — — — CNPUD8 — CNPUD<6:5> — — — — — 0000
CNPDD 0E48 — — — — — — — CNPDD8 — CNPDD<6:5> — — — — — 0000
TABLE 4-40: PORTE REGISTER MAP FOR dsPIC33EVXXXGMX06 DEVICES

SFR All
Name Resets
TRISE 0E50 TRISE<15:12> — — — — — — — — — — — — F000

PORTE 0E52 RE<15:12> — — — — — — — — — — — — xxxx
LATE 0E54 LATE<15:12> — — — — — — — — — — — — xxxx
ODCE 0E56 ODCE<15:12> — — — — — — — — — — — — 0000
CNENE 0E58 CNIEE<15:12> — — — — — — — — — — — — 0000
CNPUE 0E5A CNPUE<15:12> — — — — — — — — — — — — 0000
CNPDE 0E5C CNPDE<15:12> — — — — — — — — — — — — 0000
ANSELE 0E5E ANSE<15:12> — — — — — — — — — — — — F000
TABLE 4-41: PORTF REGISTER MAP FOR dsPIC33EVXXXGMX06 DEVICES

SFR All
Name Resets
TRISF 0E64 — — — — — — — — — — — — — — TRISF<1:0> 0003

PORTF 0E66 — — — — — — — — — — — — — — RF<1:0> xxxx
LATF 0E68 — — — — — — — — — — — — — — LATF<1:0> xxxx
ODCF 0E6A — — — — — — — — — — — — — — ODCF<1:0> 0000
CNENF 0E6C — — — — — — — — — — — — — — CNIEF<1:0> 0000
CNPUF 0E6E — — — — — — — — — — — — — — CNPUF<1:0> 0000
CNPDF 0E70 — — — — — — — — — — — — — — CNPDF<1:0> 0000
TABLE 4-42: PORTG REGISTER MAP FOR dsPIC33EVXXXGMX06 DEVICES
SFR All
Name Resets
TRISG 0E78 — — — — — — TRISG<9:6> — — — — — — 03C0

PORTG 0E7A — — — — — — RG<9:6> — — — — — — xxxx
LATG 0E7C — — — — — — LATG<9:6> — — — — — — xxxx
ODCG 0E7E — — — — — — ODCG<9:6> — — — — — — 0000
CNENG 0E80 — — — — — — CNIEG<9:6> — — — — — — 0000
CNPUG 0E82 — — — — — — CNPUG<9:6> — — — — — — 0000
CNPDG 0E84 — — — — — — CNPDG<9:6> — — — — — — 0000
ANSELG 0E86 — — — — — — ANSG<9:6> — — — — — — 0000
DS70005144E-page 67
4.3.1 PAGED MEMORY SCHEME The Data Space Page registers are located in the SFR
space. Construction of the EDS address is shown in
The dsPIC33EVXXXGM00X/10X family architecture
Figure 4-9 and Figure 4-10. When DSRPAG<9> = 0
extends the available DS through a paging scheme,
and the base address bit, EA<15> = 1, the
which allows the available DS to be accessed using
DSRPAG<8:0> bits are concatenated onto EA<14:0> to
MOV instructions in a linear fashion for pre- and post-
form the 24-bit EDS read address. Similarly, when the
modified Effective Addresses (EAs). The upper half of
base address bit, EA<15> = 1, the DSWPAG<8:0>
the Base Data Space address is used in conjunction
bits are concatenated onto EA<14:0> to form the 24-
with the Data Space Page registers, the 10-bit Data
bit EDS write address.
Space Read Page register (DSRPAG) or the 9-bit Data
Space Write Page register (DSWPAG), to form an EDS
address, or Program Space Visibility (PSV) address.
FIGURE 4-9: EXTENDED DATA SPACE (EDS) READ ADDRESS GENERATION
Byte
16-Bit DS EA Select
EA<15> = 0 No EDS Access 0 EA

(DSRPAG = Don’t Care)
EA<15>
Generate Y
DSRPAG<9> 1 EA
PSV Address = 1?
N
Select
DSRPAG
0 DSRPAG<8:0>
9 Bits 15 Bits
24-Bit EDS EA Byte

Select
Note: DS read access when DSRPAG = 0x000 will force an address error trap.

FIGURE 4-10: EXTENDED DATA SPACE (EDS) WRITE ADDRESS GENERATION
Byte
16-Bit DS EA Select
EA<15> = 0
(DSWPAG = Don’t Care)
Generate No EDS Access 0 EA

PSV Address
EA<15>
1 EA
DSWPAG<8:0>
9 Bits 15 Bits
24-Bit EDS EA Byte

Select
Note: DS read access when DSRPAG = 0x000 will force an address error trap.
The paged memory scheme provides access to The Program Space (PS) can be accessed with a
multiple 32-Kbyte windows in the EDS and PSV DSRPAG of 0x200 or greater. Only reads from PS are
memory. The Data Space Page registers, DSxPAG, in supported using the DSRPAG. Writes to PS are not
combination with the upper half of the Data Space supported, therefore, the DSWPAG is dedicated to DS,
address, can provide up to 16 Mbytes of additional including EDS. The Data Space and EDS can be read
address space in the EDS and 8 Mbytes (DSRPAG from and written to using DSRPAG and DSWPAG,
only) of PSV address space. The paged data memory respectively.
space is shown in Figure 4-11.

FIGURE 4-11: PAGED DATA MEMORY SPACE
DS70005144E-page 70
Local Data Space EDS Program Space Table Address Space
(DSRPAG<9:0>/DSWPAG<8:0>) (Instruction & Data) (TBLPAG<7:0>)
DS_Addr<14:0>
0x0000
Page 0
Reserved
(Will produce an DS_Addr<15:0>
0x7FFF address error trap) 0x0000
(TBLPAG = 0x00)
0x0000 lsw Using
EDS Page 0x001
Program Memory TBLRDL/TBLWTL,
(DSRPAG = 0x001) (lsw – <15:0>)
(DSWPAG = 0x001) MSB Using
0x7FFF 0x00_0000 TBLRDH/TBLWTH
0xFFFF
DS_Addr<15:0> 0x0000
0x0000 EDS Page 0x1FF
SFR Registers (DSRPAG = 0x1FF)
0x0FFF 0x7FFF (DSWPAG = 0x1FF)
0x0000
0x1000 (TBLPAG = 0x7F)
0x0000
EDS Page 0x200 lsw Using
Up to 8-Kbyte (DSRPAG = 0x200) 0x7F_FFFF TBLRDL/TBLWTL,
RAM No Writes Allowed MSB Using
0x7FFF TBLRDH/TBLWTH
0x2FFF PSV 0xFFFF
0x3000 Program
0x7FFF Program Memory
Memory
0x8000 (MSB – <23:16>)
(lsw)
32-Kbyte 0x0000 0x00_0000
EDS Window EDS Page 0x2FF
(DSRPAG = 0x2FF)
0xFFFF
No Writes Allowed
0x7FFF
0x0000
EDS Page 0x300
(DSRPAG = 0x300)
No Writes Allowed
0x7FFF
PSV
Program
Memory
0x7F_FFFF
(MSB)
0x0000
EDS Page 0x3FF
(DSRPAG = 0x3FF)
No Writes Allowed
0x7FFF
Allocating different Page registers for read and write In general, when an overflow is detected, the DSxPAG
access allows the architecture to support data register is incremented and the EA<15> bit is set to
movement between different pages in the data keep the base address within the EDS or PSV window.
memory. This is accomplished by setting the DSRPAG When an underflow is detected, the DSxPAG register is
register value to the page from which you want to read, decremented and the EA<15> bit is set to keep the
and configure the DSWPAG register to the page to base address within the EDS or PSV window. This
which it needs to be written. Data can also be moved creates a linear EDS and PSV address space, but only
from different PSV to EDS pages by configuring the when using the Register Indirect Addressing modes.
DSRPAG and DSWPAG registers to address PSV and Exceptions to the operation described above arise
EDS space, respectively. The data can be moved when entering and exiting the boundaries of Page 0,
between pages by a single instruction. EDS and PSV spaces. Table 4-43 lists the effects of
When an EDS or PSV page overflow or underflow overflow and underflow scenarios at different
occurs, EA<15> is cleared as a result of the register boundaries.
indirect EA calculation. An overflow or underflow of the In the following cases, when an overflow or underflow
EA in the EDS or PSV pages can occur at the page occurs, the EA<15> bit is set and the DSxPAG is not
boundaries when: modified; therefore, the EA will wrap to the beginning of
• The initial address, prior to modification, the current page:
addresses an EDS or a PSV page. • Register Indirect with Register Offset Addressing
• The EA calculation uses Pre- or Post-Modified • Modulo Addressing
Register Indirect Addressing. However, this does
• Bit-Reversed Addressing
not include Register Offset Addressing.
TABLE 4-43: OVERFLOW AND UNDERFLOW SCENARIOS AT PAGE 0, EDS AND

PSV SPACE BOUNDARIES(2,3,4)
Before After
O/U,
Operation DS Page DS
R/W DSxPAG DSxPAG Page Description
EA<15> Description EA<15>
O, DSRPAG = 0x1FF 1 EDS: Last Page DSRPAG = 0x1FF 0 See Note 1
Read
O, DSRPAG = 0x2FF 1 PSV: Last lsw DSRPAG = 0x300 1 PSV: First MSB
Read [++Wn] Page Page
or
O, [Wn++] DSRPAG = 0x3FF 1 PSV: Last MSB DSRPAG = 0x3FF 0 See Note 1
Read Page
O, DSWPAG = 0x1FF 1 EDS: Last Page DSWPAG = 0x1FF 0 See Note 1
Write
U, DSRPAG = 0x001 1 PSV Page DSRPAG = 0x001 0 See Note 1
Read
[--Wn]
U, DSRPAG = 0x200 1 PSV: First lsw DSRPAG = 0x200 0 See Note 1
or
Read Page
[Wn--]
U, DSRPAG = 0x300 1 PSV: First MSB DSRPAG = 0x2FF 1 PSV: Last lsw
Read Page Page
Legend: O = Overflow, U = Underflow, R = Read, W = Write
Note 1: The Register Indirect Addressing now addresses a location in the Base Data Space (0x0000-0x8000).
2: An EDS access with DSxPAG = 0x000 will generate an address error trap.
3: Only reads from PS are supported using DSRPAG. An attempt to write to PS using DSWPAG will generate
an address error trap.
4: Pseudolinear Addressing is not supported for large offsets.

4.3.2 EXTENDED X DATA SPACE The remaining pages, including both EDS and PSV
pages, are only accessible using the DSRPAG or
The lower portion of the base address space range,
DSWPAG registers in combination with the upper
between 0x0000 and 0x2FFF, is always accessible
32 Kbytes, 0x8000 to 0xFFFF, of the base address,
regardless of the contents of the Data Space Page
where the base address bit, EA<15> = 1.
registers; it is indirectly addressable through the
register indirect instructions. It can be regarded as For example, when DSRPAG = 0x001 or
being located in the default EDS Page 0 (i.e., EDS DSWPAG = 0x001, accesses to the upper 32 Kbytes,
address range of 0x000000 to 0x002FFF with the base 0x8000 to 0xFFFF of the Data Space, will map to the
address bit, EA<15> = 0, for this address range). EDS address range of 0x008000 to 0x00FFFF. When
However, Page 0 cannot be accessed through the DSRPAG = 0x002 or DSWPAG = 0x002, accesses to
upper 32 Kbytes, 0x8000 to 0xFFFF, of Base Data the upper 32 Kbytes of the Data Space will map to the
Space, in combination with DSRPAG = 0x000 or EDS address range of 0x010000 to 0x017FFF and so
DSWPAG = 0x000. Consequently, the DSRPAG and on, as shown in the EDS memory map in Figure 4-12.
DSWPAG registers are initialized to 0x001 at Reset. For more information on the PSV page access using
Note 1: DSxPAG should not be used to access Data Space Page registers, refer to Section 5.0
Page 0. An EDS access with DSxPAG “Program Space Visibility from Data Space” in
set to 0x000 will generate an address “dsPIC33E/PIC24E Program Memory” (DS70000613)
error trap. of the “dsPIC33/PIC24 Family Reference Manual”.
2: Clearing the DSxPAG in software has no
effect.
FIGURE 4-12: EDS MEMORY MAP
EA<15:0>
0x0000
SFR/DS (PAGE 0)
Conventional
DS Address 0x8000 0x008000
DS PAGE 1
0xFFFF
0x010000
PAGE 2
0x018000
PAGE 3
DSRPAG<9> = 0
EDS EA Address (24 bits)
(DSRPAG<8:0>, EA<14:0>)
(DSWPAG<8:0>, EA<14:0>)
0xFE8000
PAGE 1FD
0xFF0000
PAGE 1FE
0xFF8000
PAGE 1FF

4.3.3 DATA MEMORY ARBITRATION AND below that of the CPU maintain the same priority
BUS MASTER PRIORITY relationship relative to each other. The priority schemes
for bus masters with different MSTRPR values are
EDS accesses from bus masters in the system are
listed in Table 4-44.
arbitrated.
Figure 4-13 shows the arbiter architecture.
The arbiter for data memory (including EDS) arbitrates
between the CPU, the DMA and the MPLAB® ICD The bus master priority control allows the user
module. In the event of coincidental access to a bus by application to manipulate the real-time response of the
the bus masters, the arbiter determines which bus system, either statically during initialization or
master access has the highest priority. The other bus dynamically in response to real-time events.
masters are suspended and processed after the
access of the bus by the bus master with the highest TABLE 4-44: DATA MEMORY BUS
priority. ARBITER PRIORITY
By default, the CPU is Bus Master 0 (M0) with the MSTRPR<15:0> Bit Setting(1)
highest priority and the MPLAB ICD is Bus Master 4 Priority
(M4) with the lowest priority. The remaining bus master 0x0000 0x0020
(DMA Controller) is allocated to M3 (M1 and M2 are M0 (highest) CPU DMA
reserved and cannot be used). The user application
may raise or lower the priority of the DMA Controller to M1 Reserved CPU
be above that of the CPU by setting the appropriate bits M2 Reserved Reserved
in the EDS Bus Master Priority Control (MSTRPR) M3 DMA Reserved
register. All bus masters with raised priorities will
M4 (lowest) MPLAB® ICD MPLAB ICD
maintain the same priority relationship relative to each
other (i.e., M1 being highest and M3 being lowest, with Note 1: All other values of MSTRPR<15:0> are
M2 in between). Also, all the bus masters with priorities reserved.
FIGURE 4-13: ARBITER ARCHITECTURE
DMA Reserved MPLAB® ICD CPU
MSTRPR<15:0>
M0 M1 M2 M3 M4
Data Memory Arbiter
SRAM

4.3.4 SOFTWARE STACK FIGURE 4-14: CALL STACK FRAME

The W15 register serves as a dedicated Software 0x0000 15 0
Stack Pointer (SSP) and is automatically modified by CALL SUBR
exception processing, subroutine calls and returns;
however, W15 can be referenced by any instruction in
Stack Grows Toward

the same manner as all other W registers. This simpli-
Higher Address
fies reading, writing and manipulating the SSP (for
example, creating stack frames). PC<15:0> W15 (before CALL)
Note: To protect against misaligned stack b‘000000000’ PC<22:16>
accesses, W15<0> is fixed to ‘0’ by the <Free Word> W15 (after CALL)
hardware.
W15 is initialized to 0x1000 during all Resets. This
address ensures that the SSP points to valid RAM in all
dsPIC33EVXXXGM00X/10X family devices and per-
mits stack availability for non-maskable trap exceptions.
4.4 Instruction Addressing Modes
These can occur before the SSP is initialized by the
user software. You can reprogram the SSP during The addressing modes shown in Table 4-45 form the
initialization to any location within the Data Space. basis of the addressing modes optimized to support the
The SSP always points to the first available free word specific features of the individual instructions. The
and fills the software stack, working from lower toward addressing modes provided in the MAC class of
higher addresses. Figure 4-14 illustrates how it pre- instructions differ from those in the other instruction types.
decrements for a stack pop (read) and post-increments
for a stack push (writes). 4.4.1 FILE REGISTER INSTRUCTIONS
When the PC is pushed onto the stack, PC<15:0> are Most file register instructions use a 13-bit address field
pushed onto the first available stack word, then (f) to directly address data present in the first
PC<22:16> are pushed into the second available stack 8192 bytes of data memory (Near Data Space). Most
location. For a PC push during any CALL instruction, file register instructions employ a Working register, W0,
the MSB of the PC is zero-extended before the push, which is denoted as WREG in these instructions. The
as shown in Figure 4-14. During exception processing, destination is typically either the same file register or
the MSB of the PC is concatenated with the lower 8 bits WREG (with the exception of the MUL instruction),
of the CPU STATUS Register (SR). This allows the which writes the result to a register or register pair. The
contents of SRL to be preserved automatically during MOV instruction allows additional flexibility and can
interrupt processing. access the entire Data Space.
Note 1: To maintain system SSP (W15) coher- 4.4.2 MCU INSTRUCTIONS

ency, W15 is never subject to (EDS) pag- The three-operand MCU instructions are of the form:
ing, and is therefore, restricted to an
address range of 0x0000 to 0xFFFF. The Operand 3 = Operand 1 <function> Operand 2
same applies to the W14 when used as a where, Operand 1 is always a Working register (that
Stack Frame Pointer (SFA = 1). is, the addressing mode can only be Register Direct),
2: As the stack can be placed in, and can which is referred to as Wb. Operand 2 can be a
access X and Y spaces, care must be W register fetched from data memory or a 5-bit literal.
taken regarding its use, particularly with The result location can be either a W register or a data
regard to local automatic variables in a memory location. The following addressing modes are
‘C’ development environment. supported by MCU instructions:
• Register Direct
• Register Indirect
• Register Indirect Post-Modified
• Register Indirect Pre-Modified
• 5-Bit or 10-Bit Literal
Note: Not all instructions support all of the
addressing modes given above. Individual
instructions can support different subsets
of these addressing modes.

TABLE 4-45: FUNDAMENTAL ADDRESSING MODES SUPPORTED

Addressing Mode Description
File Register Direct The address of the file register is specified explicitly.
Register Direct The contents of a register are accessed directly.
Register Indirect The contents of Wn form the Effective Address (EA).
Register Indirect Post-Modified The contents of Wn form the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Register Indirect Pre-Modified Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
(Register Indexed)
Register Indirect with Literal Offset The sum of Wn and a literal forms the EA.
4.4.3 MOVE AND ACCUMULATOR 4.4.4 MAC INSTRUCTIONS

INSTRUCTIONS The dual source operand DSP instructions (CLR, ED,
Move instructions and the DSP accumulator class of EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also referred
instructions provide a greater addressing flexibility than to as MAC instructions, use a simplified set of addressing
other instructions. In addition to the addressing modes modes to allow the user application to effectively
supported by most MCU instructions, move and accu- manipulate the Data Pointers through register indirect
mulator instructions also support Register Indirect with tables.
Register Offset Addressing mode, also referred to as The Two-Source Operand Prefetch registers must be
Register Indexed mode. members of the set, {W8, W9, W10, W11}. For data
Note: For the MOV instructions, the addressing reads, W8 and W9 are always directed to the X RAGU,
mode specified in the instruction can differ and W10 and W11 are always directed to the Y AGU.
for the source and destination EA. How- The Effective Addresses generated (before and after
ever, the 4-bit Wb (Register Offset) field is modification) must, therefore, be valid addresses within
shared by both source and destination X Data Space for W8 and W9, and Y Data Space for
(but typically only used by one). W10 and W11.
In summary, the following addressing modes are Note: Register Indirect with Register Offset
supported by move and accumulator instructions: Addressing mode is available only for W9 (in
X Data Space) and W11 (in Y Data Space).
• Register Direct
• Register Indirect In summary, the following addressing modes are
supported by the MAC class of instructions:
• Register Indirect Post-Modified
• Register Indirect Pre-Modified • Register Indirect
• Register Indirect with Register Offset (Indexed) • Register Indirect Post-Modified by 2
• Register Indirect with Literal Offset • Register Indirect Post-Modified by 4
• 8-Bit Literal • Register Indirect Post-Modified by 6
• 16-Bit Literal • Register Indirect with Register Offset (Indexed)
Note: Not all instructions support all the 4.4.5 OTHER INSTRUCTIONS
addressing modes given above. Individual
instructions may support different subsets Besides the addressing modes outlined previously, some
of these addressing modes. instructions use literal constants of various sizes. For
example, BRA (Branch) instructions use 16-bit signed
literals to specify the Branch destination directly, whereas
the DISI instruction uses a 14-bit unsigned literal field. In
some instructions, such as ULNK, the source of an
operand or result is implied by the opcode itself. Certain
operations, such as a NOP, do not have any operands.

4.5 Modulo Addressing The length of a circular buffer is not directly specified. It
is determined by the difference between the corre-
Modulo Addressing mode is a method of providing an sponding start and end addresses. The maximum
automated means to support circular data buffers using possible length of the circular buffer is 32K words
hardware. The objective is to remove the need for (64 Kbytes).
software to perform data address boundary checks
when executing tightly looped code, as is typical in 4.5.2 W ADDRESS REGISTER
many DSP algorithms. SELECTION
Modulo Addressing can operate in either Data or The Modulo and Bit-Reversed Addressing Control
Program Space (since the Data Pointer mechanism is register, MODCON<15:0>, contains enable flags, as well
essentially the same for both). One circular buffer can as a W register field to specify the W Address registers.
be supported in each of the X (which also provides the The XWM and YWM fields select the registers that
pointers into Program Space) and Y Data Spaces. operate with Modulo Addressing:
Modulo Addressing can operate on any W Register
Pointer. However, it is not advisable to use W14 or W15 • If XWM = 1111, X RAGU and X WAGU Modulo
for Modulo Addressing, since these two registers are Addressing is disabled
used as the SFP and SSP, respectively. • If YWM = 1111, Y AGU Modulo Addressing is
disabled
In general, any particular circular buffer can be config-
ured to operate in only one direction, as there are The X Address Space Pointer W register (XWM) to
certain restrictions on the buffer start address (for which Modulo Addressing is to be applied is stored in
incrementing buffers) or end address (for decrementing MODCON<3:0> (see Table 4-1). Modulo Addressing is
buffers), based upon the direction of the buffer. enabled for X Data Space when XWM is set to any
value other than ‘1111’ and the XMODEN bit
The only exception to the usage restrictions is for
(MODCON<15>) is set
buffers that have a power-of-two length. As these
buffers satisfy the start and end address criteria, they The Y Address Space Pointer W register (YWM) to
can operate in a Bidirectional mode (that is, address which Modulo Addressing is to be applied is stored in
boundary checks are performed on both the lower and MODCON<7:4>. Modulo Addressing is enabled for Y
upper address boundaries). Data Space when YWM is set to any value other than
‘1111’ and the YMODEN bit (MODCON<14>) is set.
4.5.1 START AND END ADDRESS Figure 4-15 shows an example of Modulo Addressing
The Modulo Addressing scheme requires that a operation.
starting and ending address be specified and loaded
into the 16-bit Modulo Buffer Address registers:
XMODSRT, XMODEND, YMODSRT and YMODEND
(see Table 4-1).
Note: Y Data Space Modulo Addressing EA
calculations assume word-sized data
(LSb of every EA is always clear).
FIGURE 4-15: MODULO ADDRESSING OPERATION EXAMPLE

Byte
Address MOV #0x1100, W0
0x1100 MOV W0, XMODSRT ;set modulo start address
MOV #0x1163, W0
MOV W0, MODEND ;set modulo end address
MOV #0x8001, W0
MOV W0, MODCON ;enable W1, X AGU for modulo
MOV #0x0000, W0 ;W0 holds buffer fill value
0x1163 MOV #0x1110, W1 ;point W1 to buffer
DO AGAIN, #0x31 ;fill the 50 buffer locations

Start Addr = 0x1100 MOV W0, [W1++] ;fill the next location
End Addr = 0x1163 AGAIN: INC W0, W0 ;increment the fill value
Length = 32 Words

4.5.3 MODULO ADDRESSING If the length of a bit-reversed buffer is M = 2N bytes,

APPLICABILITY the last ‘N’ bits of the data buffer start address must
be zeros.
Modulo Addressing can be applied to the Effective
Address (EA) calculation associated with any W XB<14:0> is the Bit-Reversed Addressing modifier, or
register. Address boundaries check for addresses ‘pivot point’, which is typically a constant. In the case of
equal to: an FFT computation, its value is equal to half of the FFT
data buffer size.
• The upper boundary addresses for incrementing
buffers Note: All bit-reversed EA calculations assume
• The lower boundary addresses for decrementing word-sized data (LSb of every EA is
buffers always clear). The XB value is scaled
accordingly to generate compatible (byte)
The address boundaries check for addresses less than
addresses.
or greater than the upper (for incrementing buffers) and
lower (for decrementing buffers) boundary addresses When enabled, Bit-Reversed Addressing is executed
(not just equal to). Address changes can, therefore, only for Register Indirect with Pre-Increment or Post-
jump beyond boundaries and still be adjusted correctly. Increment Addressing and word-sized data writes. It
does not function for any other addressing mode or for
Note: The modulo corrected Effective Address
byte-sized data and normal addresses are generated
is written back to the register only when
instead. When Bit-Reversed Addressing is active, the
Pre-Modify or Post-Modify Addressing
W Address Pointer is always added to the address
mode is used to compute the Effective
modifier (XB) and the offset associated with the Regis-
Address. When an address offset, such as
ter Indirect Addressing mode is ignored. In addition, as
[W7 + W2] is used, Modulo Addressing
word-sized data is a requirement, the LSb of the EA is
correction is performed, but the contents
ignored (and always clear).
of the register remain unchanged.
Note: Modulo Addressing and Bit-Reversed
4.6 Bit-Reversed Addressing Addressing can be enabled simultaneously
using the same W register, but Bit-
Bit-Reversed Addressing mode is intended to simplify Reversed Addressing operation will always
data reordering for radix-2 FFT algorithms. It is take precedence for data writes when
supported by the X AGU for data writes only. enabled.
The modifier, which can be a constant value or register If Bit-Reversed Addressing has already been enabled
contents, is regarded as having its bit order reversed. by setting the BREN (XBREV<15>) bit, a write to the
The address source and destination are kept in normal XBREV register should not be immediately followed by
order. Thus, the only operand requiring reversal is the an indirect read operation using the W register that has
modifier. been designated as the Bit-Reversed Pointer.
4.6.1 BIT-REVERSED ADDRESSING The operation of Bit-Reversed Addressing is shown in

Figure 4-16 and Table 4-46.
IMPLEMENTATION
Bit-Reversed Addressing mode is enabled when all of
these conditions are met:
• BWM<3:0> bits (W register selection) in the
MODCON register are any value other than
‘1111’ (the stack cannot be accessed using
Bit-Reversed Addressing)
• The BREN bit is set in the XBREV register
• The addressing mode used is Register Indirect
with Pre-Increment or Post-Increment

FIGURE 4-16: BIT-REVERSED ADDRESSING EXAMPLE
Sequential Address
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0
Bit Locations Swapped Left-to-Right

Around Center of Binary Value
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0

Bit-Reversed Address
Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer
TABLE 4-46: BIT-REVERSED ADDRESSING SEQUENCE (16-ENTRY)

Normal Address Bit-Reversed Address
A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal
0 0 0 0 0 0 0 0 0 0
0 0 0 1 1 1 0 0 0 8
0 0 1 0 2 0 1 0 0 4
0 0 1 1 3 1 1 0 0 12
0 1 0 0 4 0 0 1 0 2
0 1 0 1 5 1 0 1 0 10
0 1 1 0 6 0 1 1 0 6
0 1 1 1 7 1 1 1 0 14
1 0 0 0 8 0 0 0 1 1
1 0 0 1 9 1 0 0 1 9
1 0 1 0 10 0 1 0 1 5
1 0 1 1 11 1 1 0 1 13
1 1 0 0 12 0 0 1 1 3
1 1 0 1 13 1 0 1 1 11
1 1 1 0 14 0 1 1 1 7
1 1 1 1 15 1 1 1 1 15

4.7 Interfacing Program and Data Table instructions allow an application to read or write
Memory Spaces to small areas of the program memory. This capability
makes the method ideal for accessing data tables that
The dsPIC33EVXXXGM00X/10X family architecture need to be updated periodically. It also allows access
uses a 24-bit wide Program Space and a 16-bit wide to all bytes of the program word. The remapping
Data Space. The architecture is also a modified Harvard method allows an application to access a large block of
scheme, meaning that data can also be present in the data on a read-only basis, which is ideal for look-ups
Program Space. To use this data successfully, it must be from a large table of static data. The application can
accessed in a way that preserves the alignment of only access the least significant word of the program
information in both the spaces. word.
Aside from normal execution, the architecture of the Table 4-47 shows the construction of the Program
dsPIC33EVXXXGM00X/10X family devices provides Space address.
two methods by which Program Space can be
How the data is accessed from Program Space is
accessed during operation:
• Using table instructions to access individual bytes
or words anywhere in the Program Space
• Remapping a portion of the Program Space into
the Data Space (Program Space Visibility)
TABLE 4-47: PROGRAM SPACE ADDRESS CONSTRUCTION

Access Program Space Address
Access Type
Space <23> <22:16> <15> <14:1> <0>
Instruction Access User 0 PC<22:1> 0
(Code Execution) 0xx xxxx xxxx xxxx xxxx xxx0
TBLRD/TBLWT User TBLPAG<7:0> Data EA<15:0>
(Byte/Word Read/Write) 0xxx xxxx xxxx xxxx xxxx xxxx
Configuration TBLPAG<7:0> Data EA<15:0>
1xxx xxxx xxxx xxxx xxxx xxxx

FIGURE 4-17: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1) 0 Program Counter 0
23 Bits
EA 1/0
Table Operations(2) 1/0 TBLPAG
8 Bits 16 Bits
24 Bits
User/Configuration Byte Select

Space Select
Note 1: The Least Significant bit (LSb) of Program Space addresses is always fixed as ‘0’ to maintain word alignment
of data in the Program and Data Spaces.
2: Table operations are not required to be word-aligned. Table Read operations are permitted in the configura-
tion memory space.

4.7.1 DATA ACCESS FROM PROGRAM • TBLRDH (Table Read High):

MEMORY USING TABLE - In Word mode, this instruction maps the entire
INSTRUCTIONS upper word of a program address (P<23:16>)
to a data address. The ‘phantom’ byte
The TBLRDL and TBLWTL instructions offer a direct
(D<15:8>) is always ‘0’.
method of reading or writing the lower word of any
address within the Program Space without going - In Byte mode, this instruction maps the upper
through the Data Space. The TBLRDH and TBLWTH or lower byte of the program word to D<7:0>
instructions are the only method to read or write the of the data address, as in the TBLRDL
upper 8 bits of a Program Space word as data. instruction. The data is always ‘0’ when the
upper ‘phantom’ byte is selected (Byte Select
The PC is incremented by two for each successive = 1).
24-bit program word. This allows program memory
addresses to directly map to Data Space addresses. Similarly, two table instructions, TBLWTH and TBLWTL,
Program memory can thus be regarded as two 16-bit are used to write individual bytes or words to a Program
wide word address spaces, residing side by side, each Space address. The details of their operation are
with the same address range. The TBLRDL and explained in Section 5.0 “Flash Program Memory”.
TBLWTL instructions access the space that contains For all table operations, the area of program memory
the least significant data word. TBLRDH and TBLWTH space to be accessed is determined by the Table Page
access the space that contains the upper data byte. register (TBLPAG). TBLPAG covers the entire program
Two table instructions are provided to move byte or memory space of the device, including user application
word-sized (16-bit) data to and from Program Space. and configuration spaces. When TBLPAG<7> = 0, the
Both function as either byte or word operations. table page is located in the user memory space. When
TBLPAG<7> = 1, the page is located in configuration
• TBLRDL (Table Read Low): space. Accessing the program memory with table
- In Word mode, this instruction maps the instructions is shown in Figure 4-18.
lower word of the Program Space location
(P<15:0>) to a data address (D<15:0>).
- In Byte mode, either the upper or lower byte of
the lower program word is mapped to the lower
byte of a data address. The upper byte is
selected when Byte Select is ‘1’; the lower byte
is selected when it is ‘0’.
FIGURE 4-18: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS

Program Space
TBLPAG
02
23 15 0
0x000000 23 16 8 0
00000000
00000000
0x020000 00000000
0x030000 00000000
‘Phantom’ Byte
TBLRDH.B (Wn<0> = 0)
TBLRDL.B (Wn<0> = 1)
TBLRDL.B (Wn<0> = 0)
TBLRDL.W
The address for the table operation is determined by the data EA
within the page defined by the TBLPAG register.
Only read operations are shown; write operations are also valid
0x800000 in the user memory area.

NOTES:

5.0 FLASH PROGRAM MEMORY devices and then program the device just before
shipping the product. This also allows the most recent
Note 1: This data sheet summarizes the firmware or a custom firmware to be programmed.
features of the dsPIC33EVXXXGM00X/ Enhanced ICSP uses an on-board bootloader, known as
10X family of devices. It is not intended the Program Executive (PE), to manage the programming
to be a comprehensive reference process. Using an SPI data frame format, the Program
source. To complement the information Executive can erase, program and verify program
in this data sheet, refer to “Flash Pro- memory. For more information on Enhanced ICSP, refer
gramming” (DS70609) in the “dsPIC33/ to the specific device programming specification.
PIC24 Family Reference Manual”, which
is available from the Microchip web site RTSP is accomplished using the TBLRD (Table Read)
(www.microchip.com). and TBLWT (Table Write) instructions. With RTSP, the
user application can write program memory data as a
2: Some registers and associated bits double program memory word, a row of 64 instructions
described in this section may not be (192 bytes) and erase program memory in blocks of
available on all devices. Refer to 512 instruction words (1536 bytes) at a time.
5.1 Table Instructions and Flash
Programming
The dsPIC33EVXXXGM00X/10X family devices
contain internal Flash program memory for storing and The Flash memory read and the double-word
executing application code. The memory is readable, programming operations make use of the TBLRD and
writable and erasable during normal operation over the TBLWT instructions, respectively. These allow direct read
entire VDD range. and write access to the program memory space from the
data memory while the device is in normal operating
The Flash memory can be programmed in the following mode. The 24-bit target address in the program memory
three ways: is formed using bits<7:0> of the TBLPAG register and
• In-Circuit Serial Programming™ (ICSP™) the Effective Address (EA) from a W register, specified
• Run-Time Self-Programming (RTSP) in the table instruction, as shown in Figure 5-1.
• Enhanced In-Circuit Serial Programming The TBLRDL and the TBLWTL instructions are used to
(Enhanced ICSP) read or write to bits<15:0> of the program memory.
TBLRDL and TBLWTL can access program memory in
ICSP allows for a dsPIC33EVXXXGM00X/10X family
both Word and Byte modes.
device to be serially programmed while in the end
application circuit. This is done with two lines for The TBLRDH and TBLWTH instructions are used to read
programming clock and programming data (PGECx/ or write to bits<23:16> of the program memory.
PGEDx) lines, and three other lines for power (VDD), TBLRDH and TBLWTH can also access program
ground (VSS) and Master Clear (MCLR). This allows memory in Word or Byte mode.
customers to manufacture boards with unprogrammed
FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS
24 Bits
Using
Program Counter
0 Program Counter 0
Working Reg EA
Using
Table Instruction
1/0 TBLPAG Reg
8 Bits 16 Bits
User/Configuration Byte
Space Select 24-Bit EA Select

5.2 RTSP Operation FIGURE 5-2: UNCOMPRESSED/

COMPRESSED FORMAT
RTSP allows the user application to erase a single
page of memory, program a row and to program two 15 7 0
instruction words at a time. See Table 1 in the LSW1 Even Byte
“dsPIC33EVXXXGM00X/10X Product Families” Address
Increasing
Address
section for the page sizes of each device.memory array 0x00 MSB1
is organized into rows of 64 instructions or 192 bytes.
LSW2
RTSP allows the user application to era
The Flash program memory array is organized into 0x00 MSB2
rows of 64 instructions or 192 bytes. RTSP allows the
user application to erase a page of program memory, UNCOMPRESSED FORMAT (RPDF = 0)
which consists of eight rows (512 instructions) at a
time, and to program one row or two adjacent words at
15 7 0
a time. The 8-row erase pages and single row write
LSW1 Even Byte
rows are edge-aligned, from the beginning of program
Address
Increasing
Address
memory, on boundaries of 1536 bytes and 192 bytes,
MSB2 MSB1
respectively. Table 30-13 in Section 30.0 “Electrical
Characteristics” lists the typical erase and LSW2
programming times.
The basic sequence for RTSP word programming is to COMPRESSED FORMAT (RPDF = 1)
use the TBLWTL and TBLWTH instructions to load two of
the 24-bit instructions into the write latches found in
configuration memory space. See Figure 4-1 to 5.3 Programming Operations
Figure 4-5 for write latch addresses. Programming is
A complete programming sequence is necessary for
performed by unlocking and setting the control bits in
programming or erasing the internal Flash in RTSP
the NVMCON register.
mode. The processor stalls (waits) until the program-
Row programming is performed by loading 192 bytes ming operation is finished. Setting the WR bit
into data memory and then loading the address of the (NVMCON<15>) starts the operation and the WR bit is
first byte in that row into the NVMSRCADR register. automatically cleared when the operation is finished.
Once the write has been initiated, the device will auto-
matically load the write latches and increment the 5.3.1 PROGRAMMING ALGORITHM FOR
NVMSRCADR and the NVMADR(U) registers until all FLASH PROGRAM MEMORY
bytes have been programmed. The RPDF bit
Programmers can program two adjacent words
(NVMCON<9>) selects the format of the stored data in
(24 bits x 2) of program Flash memory at a time on
RAM to be either compressed or uncompressed. See
every other word address boundary (0x000002,
Figure 5-2 for data formatting. Compressed data helps
0x000006, 0x00000A, etc.). To do this, erase the page
to reduce the amount of required RAM by using the
that contains the desired address of the location the
upper byte of the second word for the MSB of the second
user wants to change. For protection against accidental
instruction.
operations, the write initiate sequence for NVMKEY
For more information on erasing and programming the must be used to allow any erase or program operation
Flash memory, refer to “Flash Programming” to proceed. After the programming command has been
(DS70609) in the “dsPIC33/PIC24 Family Reference executed, the user application must wait for the
Manual”. programming time until programming is complete. The
Note 1: Before reprogramming either of the two two instructions following the start of the programming
words in a double-word pair, the user sequence should be NOPs.
must erase the Flash memory page in Refer to “Flash Programming” (DS70609) in the
which it is located. “dsPIC33/PIC24 Family Reference Manual” for details
2: Before reprogramming any word in a row, and code examples on programming using RTSP.
the user must erase the Flash memory
page in which it is located.

5.4 Error Correcting Code (ECC) 5.5 Flash Memory Resources

In order to improve program memory performance and Many useful resources are provided on the main
durability, these devices include Error Correcting Code product page of the Microchip web site for the devices
functionality (ECC) as an integral part of the Flash listed in this data sheet. This product page contains the
memory controller. ECC can determine the presence of latest updates and additional information.
single-bit errors in program data, including which bit is
in error, and correct the data automatically without user 5.5.1 KEY RESOURCES
intervention. ECC cannot be disabled. • Code Samples
When data is written to program memory, ECC • Application Notes
generates a 7-bit Hamming code parity value for every • Software Libraries
two (24-bit) instruction words. The data is stored in
• Webinars
blocks of 48 data bits and 7 parity bits; parity data is not
memory-mapped and is inaccessible. When the data is • All Related “dsPIC33/PIC24 Family Reference
read back, the ECC calculates the parity on it and Manual” Sections
compares it to the previously stored parity value. If a • Development Tools
parity mismatch occurs, there are two possible
outcomes: 5.6 Control Registers
• Single-bit errors are automatically identified and The following five SFRs are used to read and write the
corrected on read-back. An optional device-level program Flash memory: NVMCON, NVMKEY,
interrupt (ECCSBEIF) is also generated. NVMADR, NVMADRU and NVMSRCADR.
• Double-bit errors will generate a generic hard trap
The NVMCON register (Register 5-1) selects the
and the read data is not changed. If special
operation to be performed (page erase, word/row
exception handling for the trap is not
program, inactive panel erase) and initiates the
implemented, a device Reset will also occur.
program/erase cycle.
To use the single-bit error interrupt, set the ECC
NVMKEY (Register 5-4) is a write-only register that is
Single-Bit Error Interrupt Enable bit (ECCSBEIE) and
used for write protection. To start a programming or
configure the ECCSBEIP bits to set the appropriate
erase sequence, the user application must
interrupt priority.
consecutively write 0x55 and 0xAA to the NVMKEY
Except for the single-bit error interrupt, error events are register.
not captured or counted by hardware. This functionality
There are two NVM Address registers: NVMADRU and
can be implemented in the software application, but it
NVMADR. These two registers, when concatenated,
is the user’s responsibility to do so.
form the 24-bit Effective Address (EA) of the selected
word/row for programming operations or the selected
page for erase operations. The NVMADRU register is
used to hold the upper 8 bits of the EA, while the
NVMADR register is used to hold the lower 16 bits of
the EA. For row programming operation, data to be
written to program Flash memory is written into data
memory space (RAM) at an address defined by the
NVMSRCADR register (location of the first element in
row programming data).

REGISTER 5-1: NVMCON: NONVOLATILE MEMORY (NVM) CONTROL REGISTER

R/SO-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0
WR(1) WREN(1) WRERR(1) NVMSIDL(2) — — RPDF URERR
bit 15 bit 8
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — — NVMOP3(1,3,4) NVMOP2(1,3,4) NVMOP1(1,3,4) NVMOP0(1,3,4)
bit 7 bit 0
Legend: SO = Settable Only bit

bit 15 WR: Write Control bit(1)

1 = Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is
cleared by hardware once the operation is complete
0 = Program or erase operation is complete and inactive
bit 14 WREN: Write Enable bit(1)
1 = Flash program or erase operations are enabled
0 = Flash program or erase operations are inhibited
bit 13 WRERR: Write Sequence Error Flag bit(1)
1 = An improper program or erase sequence attempt, or termination has occurred (bit is set automatically
on any set attempt of the WR bit)
0 = The program or erase operation completed normally
bit 12 NVMSIDL: NVM Stop in Idle Control bit(2)
1 = Primary Flash operation discontinues when the device enters Idle mode
0 = Primary Flash operation continues when the device enters Idle mode.
bit 9 RPDF: Row Programming Data Format Control bit
1 = Row data to be stored in RAM is in a compressed format
0 = Row data to be stored in RAM is in an uncompressed format
bit 8 URERR: Row Programming Data Underrun Error Flag bit
1 = Row programming operation has been terminated due to a data underrun error
0 = No data underrun has occurred
Note 1: These bits can only be reset on a POR.

2: If this bit is set, there will be minimal power savings (IIDLE), and upon exiting Idle mode, there is a delay
(TVREG) before Flash memory becomes operational.
3: All other combinations of NVMOP<3:0> are unimplemented.
4: Execution of the PWRSAV instruction is ignored while any of the NVM operations are in progress.
5: Two adjacent words on a 4-word boundary are programmed during execution of this operation.

REGISTER 5-1: NVMCON: NONVOLATILE MEMORY (NVM) CONTROL REGISTER (CONTINUED)

bit 3-0 NVMOP<3:0>: NVM Operation Select bits(1,3,4)
1111 = Reserved
1110 = User memory and executive memory bulk erase operation
1101 = Reserved
1100 = Reserved
1011 = Reserved
1010 = Reserved
1001 = Reserved
1000 = Reserved
0111 = Reserved
0101 = Reserved
0100 = Reserved
0011 = Memory page erase operation
0010 = Memory row program operation
0001 = Memory double-word(5)
0000 = Reserved
Note 1: These bits can only be reset on a POR.

2: If this bit is set, there will be minimal power savings (IIDLE), and upon exiting Idle mode, there is a delay
(TVREG) before Flash memory becomes operational.
3: All other combinations of NVMOP<3:0> are unimplemented.
4: Execution of the PWRSAV instruction is ignored while any of the NVM operations are in progress.
5: Two adjacent words on a 4-word boundary are programmed during execution of this operation.

REGISTER 5-2: NVMADRU: NONVOLATILE MEMORY UPPER ADDRESS REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

NVMADRU<23:16>
bit 7 bit 0
Legend:

bit 7-0 NVMADRU<23:16>: NVM Memory Upper Write Address bits
Selects the upper 8 bits of the location to program or erase in program Flash memory. This register may be
read or written to by the user application.
REGISTER 5-3: NVMADR: NONVOLATILE MEMORY LOWER ADDRESS REGISTER

NVMADR<15:8>
bit 15 bit 8

NVMADR<7:0>
bit 7 bit 0
Legend:
bit 15-0 NVMADR<15:0>: NVM Memory Lower Write Address bits

Selects the lower 16 bits of the location to program or erase in program Flash memory. This register
may be read or written to by the user application.

REGISTER 5-4: NVMKEY: NONVOLATILE MEMORY KEY REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0

NVMKEY<7:0>
bit 7 bit 0
Legend:

bit 7-0 NVMKEY<7:0>: NVM Key Register bits (write-only)

REGISTER 5-5: NVMSRCADRH: NVM DATA MEMORY UPPER ADDRESS REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

NVMSRCADR<23:16>
bit 7 bit 0
Legend:

bit 7-0 NVMSRCADRH<23:16>: Data Memory Upper Address bits
REGISTER 5-6: NVMSRCADRL: NVM DATA MEMORY LOWER ADDRESS REGISTER

NVMSRCADR<15:8>
bit 15 bit 8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x r-0

NVMSRCADR<7:1> —
bit 7 bit 0
Legend: r = Reserved bit

bit 15-1 NVMSRCADRL<15:1>: Data Memory Lower Address bits

bit 0 Reserved: Maintain as ‘0’

6.0 RESETS A simplified block diagram of the Reset module is

Note 1: This data sheet summarizes the features Any active source of Reset will make the SYSRST
of the dsPIC33EVXXXGM00X/10X family signal active. On system Reset, some of the registers
of devices. It is not intended to be a associated with the CPU and peripherals are forced to
comprehensive reference source. To com- a known Reset state and some are unaffected.
plement the information in this data sheet,
refer to “Reset” (DS70602) in the Note: Refer to the specific peripheral section or
“dsPIC33/PIC24 Family Reference Man- Section 4.0 “Memory Organization” of
ual”, which is available from the Microchip this device data sheet for register Reset
web site (www.microchip.com). states.
2: Some registers and associated bits All types of device Reset set a corresponding status bit
described in this section may not be in the RCON register to indicate the type of Reset (see
available on all devices. Refer to Register 6-1).
A POR clears all the bits, except for the POR and BOR
bits (RCON<1:0>) that are set. The user application
can set or clear any bit at any time during code
The Reset module combines all Reset sources and execution. The RCON bits only serve as status bits.
controls the device Master Reset Signal, SYSRST. The Setting a particular Reset status bit in software does
following is a list of device Reset sources: not cause a device Reset to occur.
• POR: Power-on Reset The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
• BOR: Brown-out Reset
The function of these bits is discussed in the other
• MCLR: Master Clear Pin Reset sections of this device data sheet.
• SWR: RESET Instruction
Note: The status bits in the RCON register
• WDTO: Watchdog Timer Time-out Reset
should be cleared after they are read.
• CM: Configuration Mismatch Reset Therefore, the next RCON register value
• TRAPR: Trap Conflict Reset after a device Reset is meaningful.
• IOPUWR: Illegal Condition Device Reset
- Illegal Opcode Reset
Note: In all types of Resets, to select the device
- Uninitialized W Register Reset
clock source, the contents of OSCCON are
- Security Reset initialized from the FNOSCx Configuration
- Illegal Address Mode Reset bits in the FOSCSEL Configuration register.

FIGURE 6-1: RESET SYSTEM BLOCK DIAGRAM
RESET Instruction
Glitch Filter
MCLR
WDT
Module
Sleep or Idle
BOR
Internal
Regulator SYSRST
VDD
VDD Rise POR

Detect
Trap Conflict
Illegal Opcode
Uninitialized W Register
Security Reset
Configuration Mismatch
Illegal Address Mode Reset

REGISTER 6-1: RCON: RESET CONTROL REGISTER(1)

R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0
TRAPR IOPUWR — — VREGSF — CM VREGS
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1

(2)
EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR
bit 7 bit 0
Legend:
bit 15 TRAPR: Trap Reset Flag bit

1 = A Trap Conflict Reset has occurred
0 = A Trap Conflict Reset has not occurred
bit 14 IOPUWR: Illegal Opcode or Uninitialized W Register Access Reset Flag bit
1 = An Illegal Opcode detection or an Illegal Address mode, or Uninitialized W register used as an
Address Pointer caused a Reset
0 = An Illegal Opcode Reset or Uninitialized W Register Reset has not occurred
bit 11 VREGSF: Flash Voltage Regulator Standby During Sleep bit
1 = Flash voltage regulator is active during Sleep mode
0 = Flash voltage regulator goes into Standby mode during Sleep mode
bit 9 CM: Configuration Mismatch Flag bit
1 = A Configuration Mismatch Reset has occurred.
0 = A Configuration Mismatch Reset has not occurred
bit 8 VREGS: Voltage Regulator Standby During Sleep bit
1 = Voltage regulator is active during Sleep
0 = Voltage regulator goes into Standby mode during Sleep
bit 7 EXTR: External Reset (MCLR) Pin bit
1 = A Master Clear (pin) Reset has occurred
0 = A Master Clear (pin) Reset has not occurred
bit 6 SWR: Software RESET (Instruction) Flag bit
1 = A RESET instruction has been executed
0 = A RESET instruction has not been executed
bit 5 SWDTEN: Software Enable/Disable of WDT bit(2)
1 = WDT is enabled
0 = WDT is disabled
bit 4 WDTO: Watchdog Timer Time-out Flag bit
1 = WDT time-out has occurred
0 = WDT time-out has not occurred
Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTEN<1:0> Configuration bits are ‘11’ (unprogrammed), the WDT is always enabled, regardless
of the SWDTEN bit setting.

REGISTER 6-1: RCON: RESET CONTROL REGISTER(1) (CONTINUED)

bit 3 SLEEP: Wake-up from Sleep Flag bit
1 = Device has been in Sleep mode
0 = Device has not been in Sleep mode
bit 2 IDLE: Wake-up from Idle Flag bit
1 = Device was in Idle mode
0 = Device was not in Idle mode
bit 1 BOR: Brown-out Reset Flag bit
1 = A Brown-out Reset has occurred
0 = A Brown-out Reset has not occurred
bit 0 POR: Power-on Reset Flag bit
1 = A Power-on Reset has occurred
0 = A Power-on Reset has not occurred
Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTEN<1:0> Configuration bits are ‘11’ (unprogrammed), the WDT is always enabled, regardless
of the SWDTEN bit setting.

7.0 INTERRUPT CONTROLLER 7.1 Interrupt Vector Table

Note 1: This data sheet summarizes the features The dsPIC33EVXXXGM00X/10X family IVT, shown
of the dsPIC33EVXXXGM00X/10X in Figure 7-2, resides in program memory, starting at
family of devices. It is not intended to be location, 000004h. The IVT contains seven non-
a comprehensive reference source. To maskable trap vectors and up to 187 sources of
complement the information in this interrupt. In general, each interrupt source has its own
data sheet, refer to “Interrupts” vector. Each interrupt vector contains a 24-bit wide
(DS70000600) in the “dsPIC33/PIC24 address. The value programmed into each interrupt
Family Reference Manual”, which is vector location is the starting address of the associated
available from the Microchip web site Interrupt Service Routine (ISR).
(www.microchip.com). Interrupt vectors are prioritized in terms of their natural
2: Some registers and associated bits priority. This priority is linked to their position in the
described in this section may not be vector table. Lower addresses generally have a higher
available on all devices. Refer to natural priority. For example, the interrupt associated
Section 4.0 “Memory Organization” in with Vector 0 takes priority over interrupts at any other
this data sheet for device-specific register vector address.
7.2 Alternate Interrupt Vector Table
The dsPIC33EVXXXGM00X/10X family interrupt con-
troller reduces the numerous peripheral interrupt The Alternate Interrupt Vector Table (AIVT), shown in
request signals to a single interrupt request signal to Figure 7-1, is available if the Boot Segment (BS) is
the dsPIC33EVXXXGM00X/10X CPU. The Interrupt defined, the AIVTEN bit is set in the INTCON2 register
Vector Table (IVT) provides 246 interrupt sources and if the AIVTDIS Configuration bit is set to ‘1’. The
(unused sources are reserved for future use) that can AIVT begins at the start of the last page of the Boot
be programmed with different priority levels. Segment.
The interrupt controller has the following features:
• Interrupt Vector Table with up to 246 Vectors
• Alternate Interrupt Vector Table (AIVT)
• Up to Eight Processor Exceptions and Software
Traps
• Seven User-Selectable Priority Levels
• Interrupt Vector Table (IVT) with a Unique Vector
for Each Interrupt or Exception Source
• Fixed Priority within a Specified User Priority Level
• Fixed Interrupt Entry and Return Latencies
• Software can Generate any Peripheral Interrupt
• Alternate Interrupt Vector Table (AIVT) is
available if Boot Security is Enabled and
AIVTEN = 1

FIGURE 7-1: dsPIC33EVXXXGM00X/10X FAMILY ALTERNATE INTERRUPT VECTOR TABLE
Reserved BSLIM<12:0>(1) + 0x000000

Oscillator Fail Trap Vector BSLIM<12:0>(1) + 0x000004
Address Error Trap Vector BSLIM<12:0>(1) + 0x000006
Generic Hard Trap Vector BSLIM<12:0>(1) + 0x000008
Stack Error Trap Vector BSLIM<12:0>(1) + 0x00000A
Math Error Trap Vector BSLIM<12:0>(1) + 0x00000C
DMAC Error Trap Vector BSLIM<12:0>(1) + 0x00000E
Generic Soft Trap Vector BSLIM<12:0>(1) + 0x000010
Interrupt Vector 0 BSLIM<12:0>(1) + 0x000014
: :
: :
: :
BSLIM<12:0>(1) + 0x00007C
IVT
Interrupt Vector 52
Interrupt Vector 53 BSLIM<12:0>(1) + 0x00007E
Interrupt Vector 54 BSLIM<12:0>(1) + 0x000080 See Table 7-1 for
: : Interrupt Vector Details
: :
: :
Interrupt Vector 116 BSLIM<12:0>(1) + 0x0000FC
Interrupt Vector 117 BSLIM<12:0>(1) + 0x00007E
: :
: :
: :
Interrupt Vector 244 BSLIM<12:0>(1) + 0x0001FC
Interrupt Vector 245 BSLIM<12:0>(1) + 0x0001FE
Note 1: The address depends on the size of the Boot Segment defined by BSLIM<12:0>:
[(BSLIM<12:0> – 1) x 0x400] + Offset.

FIGURE 7-2: dsPIC33EVXXXGM00X/10X FAMILY INTERRUPT VECTOR TABLE
Reset – GOTO Instruction 0x000000

Reset – GOTO Address 0x000002
Oscillator Fail Trap Vector 0x000004
Decreasing Natural Order Priority
Address Error Trap Vector 0x000006

Generic Hard Trap Vector 0x000008
Stack Error Trap Vector 0x00000A
Math Error Trap Vector 0x00000C
DMAC Error Trap Vector 0x00000E
Generic Soft Trap Vector 0x000010
Reserved 0x000012
Interrupt Vector 0 0x000014
: :
: :
: :
Interrupt Vector 52 0x00007C
IVT
Interrupt Vector 53 0x00007E

Interrupt Vector 54 0x000080 See Table 7-1 for
: : Interrupt Vector Details
: :
: :
Interrupt Vector 116 0x0000FC
Interrupt Vector 117 0x0000FE
: :
: :
: :
Interrupt Vector 244 0x0001FC
Interrupt Vector 245 0x0001FE
START OF CODE 0x000200

TABLE 7-1: INTERRUPT VECTOR DETAILS

Vector IRQ Interrupt Bit Location
Interrupt Source IVT Address
No. No. Flag Enable Priority
Highest Natural Order Priority
External Interrupt 0 (INT0) 8 0 0x000014 IFS0<0> IEC0<0> IPC0<2:0>
Input Capture 1 (IC1) 9 1 0x000016 IFS0<1> IEC0<1> IPC0<6:4>
Output Compare 1 (OC1) 10 2 0x000018 IFS0<2> IEC0<2> IPC0<10:8>
Timer1 (T1) 11 3 0x00001A IFS0<3> IEC0<3> IPC0<14:12>
DMA Channel 0 (DMA0) 12 4 0x00001C IFS0<4> IEC0<4> IPC1<2:0>
Input Capture 2 (IC2) 13 5 0x00001E IFS0<5> IEC0<5> IPC1<6:4>
Timer2 (T2) 15 7 0x000022 IFS0<7> IEC0<7> IPC1<14:12>
Timer3 (T3) 16 8 0x000024 IFS0<8> IEC0<8> IPC2<2:0>
SPI1 Error (SPI1E) 17 9 0x000026 IFS0<9> IEC0<9> IPC2<6:4>
SPI1 Transfer Done (SPI1) 18 10 0x000028 IFS0<10> IEC0<10> IPC2<10:8>
UART1 Receiver (U1RX) 19 11 0x00002A IFS0<11> IEC0<11> IPC2<14:12>
UART1 Transmitter (U1TX) 20 12 0x00002C IFS0<12> IEC0<12> IPC3<2:0>
ADC1 Convert Done (AD1) 21 13 0x00002E IFS0<13> IEC0<13> IPC3<6:4>
DMA Channel 1 (DMA1) 22 14 0x000030 IFS0<14> IEC0<14> IPC3<10:8>
NVM Write Complete (NVM) 23 15 0x000032 IFS0<15> IEC0<15> IPC3<14:12>
I2C1 Slave Event (SI2C1) 24 16 0x000034 IFS1<0> IEC1<0> IPC4<2:0>
I2C1 Master Event (MI2C1) 25 17 0x000036 IFS1<1> IEC1<1> IPC4<6:4>
Comparator Combined Event 26 18 0x000038 IFS1<2> IEC1<2> IPC4<10:8>
(CMP1)
Input Change Interrupt (CN) 27 19 0x00003A IFS1<3> IEC1<3> IPC4<14:12>
External Interrupt 1 (INT1) 28 20 0x00003C IFS1<4> IEC1<4> IPC5<2:0>
DMA Channel 2 (DMA2) 32 24 0x000044 IFS1<8> IEC1<8> IPC6<2:0>
Timer4 (T4) 35 27 0x00004A IFS1<11> IEC1<11> IPC6<14:12>
Timer5 (T5) 36 28 0x00004C IFS1<12> IEC1<12> IPC7<2:0>
External Interrupt 2 (INT2) 37 29 0x00004E IFS1<13> IEC1<13> IPC7<6:4>
UART2 Receiver (U2RX) 38 30 0x000050 IFS1<14> IEC1<14> IPC7<10:8>
UART2 Transmitter (U2TX) 39 31 0x000052 IFS1<15> IEC1<15> IPC7<14:12>
SPI2 Error (SPI2E) 40 32 0x000054 IFS2<0> IEC2<0> IPC8<2:0>
SPI2 Transfer Done (SPI2) 41 33 0x000056 IFS2<1> IEC2<1> IPC8<6:4>
CAN1 RX Data Ready (C1RX)(1) 42 34 0x000058 IFS2<2> IEC2<2> IPC8<10:8>
CAN1 Event (C1)(1) 43 35 0x00005A IFS2<3> IEC2<3> IPC8<14:12>
DMA Channel 3 (DMA3) 44 36 0x00005C IFS2<4> IEC2<4> IPC9<2:0>
Input Capture 3 (IC3) 45 37 0x00005E IFS2<5> IEC2<5> IPC9<6:4>
Input Capture 4 (IC4) 46 38 0x000060 IFS2<6> IEC2<6> IPC9<10:8>
Reserved 54 46 0x000070 — — —
PWM Special Event Match 65 57 0x000086 IFS3<9> IEC3<9> IPC14<6:4>
Interrupt (PSEM)
Reserved 69 61 0x00008E — — —
Reserved 71-72 63-64 0x000092-0x000094 — — —
Note 1: This interrupt source is available on dsPIC33EVXXXGM10X devices only.

TABLE 7-1: INTERRUPT VECTOR DETAILS (CONTINUED)

Vector IRQ Interrupt Bit Location
Interrupt Source IVT Address
No. No. Flag Enable Priority
UART1 Error Interrupt (U1E) 73 65 0x000096 IFS4<1> IEC4<1> IPC16<6:4>
UART2 Error Interrupt (U2E) 74 66 0x000098 IFS4<2> IEC4<2> IPC16<10:8>
Reserved 76-77 68–69 0x00009C-0x00009E — — —
(1)
CAN1 TX Data Request (C1TX) 78 70 0x0000A0 IFS4<6> IEC4<6> IPC17<10:8>
Reserved 80 72 0x0000A4 — — —
Reserved 82 74 0x0000A8 — — —
Reserved 84 76 0x0000AC — — —
CTMU Interrupt (CTMU) 85 77 0x0000AE IFS4<13> IEC4<13> IPC19<6:4>
Reserved 86-88 78-80 0x0000B0-0x0000B4 — — —
Reserved 92-94 84-86 0x0000BC-0x0000C0 — — —
Reserved 100-101 92-93 0x0000CC-0x0000CE — — —
PWM Generator 1 (PWM1) 102 94 0x0000D0 IFS5<14> IEC5<14> IPC23<10:8>
Reserved 108-149 100-141 0x0000DC-0x00012E — — —
ICD Application (ICD) 150 142 0x000142 IFS8<14> IEC8<14> IPC35<10:8>
Reserved 152 144 0x000134 — — —
Bus Collision (I2C1) — 173 0x00016E IFS10<13> IEC10<13> IPC43<4:6>
SENT1 Error (SENT1ERR) — 182 0x000180 IFS11<6> IEC11<6> IPC45<10:8>
SENT1 TX/RX (SENT1) — 183 0x000182 IFS11<7> IEC11<7> IPC45<14:12>
SENT2 Error (SENT2ERR) — 184 0x000184 IFS11<8> IEC11<8> IPC46<2:0>
SENT2 TX/RX (SENT2) — 185 0x000186 IFS11<9> IEC11<9> IPC46<6:4>
ECC Single-Bit Error (ECCSBE) — 186 0x000188 IFS11<10> IEC11<10> IPC45<10:8>
Reserved 159-245 187-245 0x000142-0x0001FE — — —
Lowest Natural Order Priority
Note 1: This interrupt source is available on dsPIC33EVXXXGM10X devices only.

7.3 Reset Sequence 7.4.3 IECx

A device Reset is not a true exception because the The IECx registers maintain all of the interrupt enable
interrupt controller is not involved in the Reset process. bits. These control bits are used to individually enable
The dsPIC33EVXXXGM00X/10X family devices clear interrupts from the peripherals or external signals.
their registers in response to a Reset, which forces the
PC to zero. The device then begins program execution 7.4.4 IPCx
at location, 0x000000. A GOTO instruction at the Reset The IPCx registers are used to set the Interrupt Priority
address can redirect program execution to the Level (IPL) for each source of interrupt. Each user
appropriate start-up routine. interrupt source can be assigned to one of eight priority
levels.
Note: Any unimplemented or unused vector
locations in the IVT should be pro- 7.4.5 INTTREG
grammed with the address of a default
interrupt handler routine that contains a The INTTREG register contains the associated
RESET instruction. interrupt vector number and the new CPU Interrupt
Priority Level, which are latched into Vector Number
(VECNUM<7:0>) and Interrupt Priority Level bit
7.4 Interrupt Control and Status (ILR<3:0>) fields in the INTTREG register. The new
Interrupt Priority Level is the priority of the pending
Registers
interrupt.
dsPIC33EVXXXGM00X/10X family devices implement The interrupt sources are assigned to the IFSx, IECx
the following registers for the interrupt controller: and IPCx registers in the same sequence as they are
• INTCON1 listed in Table 7-1. For example, the INT0 (External
• INTCON2 Interrupt 0) is shown as having Vector Number 8 and a
natural order priority of 0. Thus, the INT0IF bit is found
• INTCON3
in IFS0<0>, the INT0IE bit in IEC0<0> and the INT0IP
• INTCON4 bits in the first position of IPC0 (IPC0<2:0>).
• IFSx
• IECx 7.4.6 STATUS/CONTROL REGISTERS
• IPCx Although these registers are not specifically part of the
• INTTREG interrupt control hardware, two of the CPU Control
registers contain bits that control interrupt functionality.
7.4.1 INTCON1 THROUGH INTCON4 For more information on these registers, refer to
Global interrupt control functions are controlled from “CPU” (DS70359) in the “dsPIC33/PIC24 Family
the INTCON1, INTCON2, INTCON3 and INTCON4 Reference Manual”.
registers. • The CPU STATUS Register, SR, contains the
INTCON1 contains the Interrupt Nesting Disable bit IPL<2:0> bits (SR<7:5>). These bits indicate the
(NSTDIS), as well as the control and status flags for the current CPU Interrupt Priority Level. The user
processor trap sources. software can change the current CPU Interrupt
Priority Level by writing to the IPLx bits.
The INTCON2 register controls external interrupt
• The CORCON register contains the IPL3 bit
request signal behavior and also contains the Global
which, together with IPL<2:0>, also indicates the
Interrupt Enable bit (GIE).
current CPU Interrupt Priority Level. IPL3 is a
INTCON3 contains the status flags for the DMT (Dead- read-only bit so that trap events cannot be
man Timer), DMA and DO stack overflow status trap masked by the user software.
sources.
All Interrupt registers are described in Register 7-3 to
The INTCON4 register contains the ECC Double-Bit Register 7-7.
Error (ECCDBE) and Software-Generated Hard Trap
(SGHT) status bit.
7.4.2 IFSx
The IFSx registers maintain all of the interrupt request
flags. Each source of interrupt has a status bit, which is
set by the respective peripherals or external signal and
is cleared through software.

REGISTER 7-1: SR: CPU STATUS REGISTER(1)

R/W-0 R/W-0 R/W-0 R/W-0 R/C-0 R/C-0 R-0 R/W-0
OA OB SA SB OAB SAB DA DC
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

(2,3) IPL1(2,3) IPL0(2,3)
IPL2 RA N OV Z C
bit 7 bit 0

bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3)

111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled
Note 1: For complete register details, see Register 3-1.

2: The IPL<2:0> bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority

REGISTER 7-2: CORCON: CORE CONTROL REGISTER(1)

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0
VAR — US1 US0 EDT DL2 DL1 DL0
bit 15 bit 8
R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R-0 R/W-0 R/W-0

SATA SATB SATDW ACCSAT IPL3(2) SFA RND IF
bit 7 bit 0

bit 15 VAR: Variable Exception Processing Latency Control bit

1 = Variable exception processing latency is enabled
0 = Fixed exception processing latency is enabled
bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(2)
1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less
Note 1: For complete register details, see Register 3-2.


REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1

NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE
bit 15 bit 8
R/W-0 R-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0

SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL —
bit 7 bit 0
Legend: HC = Hardware Clearable bit

bit 15 NSTDIS: Interrupt Nesting Disable bit

1 = Interrupt nesting is disabled
0 = Interrupt nesting is enabled
bit 14 OVAERR: Accumulator A Overflow Trap Flag bit
1 = Trap was caused by overflow of Accumulator A
0 = Trap was not caused by overflow of Accumulator A
bit 13 OVBERR: Accumulator B Overflow Trap Flag bit
1 = Trap was caused by overflow of Accumulator B
0 = Trap was not caused by overflow of Accumulator B
bit 12 COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit
1 = Trap was caused by catastrophic overflow of Accumulator A
0 = Trap was not caused by catastrophic overflow of Accumulator A
bit 11 COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit
1 = Trap was caused by catastrophic overflow of Accumulator B
0 = Trap was not caused by catastrophic overflow of Accumulator B
bit 10 OVATE: Accumulator A Overflow Trap Enable bit
1 = Trap overflow of Accumulator A
0 = Trap is disabled
bit 9 OVBTE: Accumulator B Overflow Trap Enable bit
1 = Trap overflow of Accumulator B
bit 8 COVTE: Catastrophic Overflow Trap Enable bit
1 = Trap on catastrophic overflow of Accumulator A or B is enabled
bit 7 SFTACERR: Shift Accumulator Error Status bit
1 = Math error trap was caused by an invalid accumulator shift
0 = Math error trap was caused by an invalid accumulator shift
bit 6 DIV0ERR: Divide-by-Zero Error Status bit
1 = Math error trap was caused by a divide-by-zero
0 = Math error trap was not caused by a divide-by-zero
bit 5 DMACERR: DMAC Trap Flag bit
1 = DMAC trap has occurred
0 = DMAC trap has not occurred
bit 4 MATHERR: Math Error Status bit
1 = Math error trap has occurred
0 = Math error trap has not occurred

REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED)

bit 3 ADDRERR: Address Error Trap Status bit
1 = Address error trap has occurred
0 = Address error trap has not occurred
bit 2 STKERR: Stack Error Trap Status bit
1 = Stack error trap has occurred
0 = Stack error trap has not occurred
bit 1 OSCFAIL: Oscillator Failure Trap Status bit
1 = Oscillator failure trap has occurred
0 = Oscillator failure trap has not occurred


R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0
GIE DISI SWTRAP — — — — AIVTEN
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — INT2EP INT1EP INT0EP
bit 7 bit 0
Legend:
bit 15 GIE: Global Interrupt Enable bit

1 = Interrupts and associated IECx bits are enabled
0 = Interrupts are disabled, but traps are still enabled
bit 14 DISI: DISI Instruction Status bit
1 = DISI instruction is active
0 = DISI instruction is not active
bit 13 SWTRAP: Software Trap Status bit
1 = Software trap is enabled
0 = Software trap is disabled
bit 8 AIVTEN: Alternate Interrupt Vector Table is Enabled bit
1 = AIVT is enabled
0 = AIVT is disabled
bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge


R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
DMT — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— — DAE DOOVR — — — —
bit 7 bit 0
Legend:
bit 15 DMT: Deadman Timer (Soft) Trap Status bit

1 = Deadman Timer trap has occurred
0 = Deadman Timer trap has not occurred
bit 5 DAE: DMA Address Error Soft Trap Status bit
1 = DMA address error soft trap has occurred
0 = DMA address error soft trap has not occurred
bit 4 DOOVR: DO Stack Overflow Soft Trap Status bit
1 = DO stack overflow soft trap has occurred
0 = DO stack overflow soft trap has not occurred


U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R-0, HS, SC R-0, HS, SC
— — — — — — ECCDBE(1) SGHT
bit 7 bit 0
Legend: HS = Hardware Settable bit SC = Software Clearable bit


bit 1 ECCDBE: ECC Double-Bit Error Trap bit(1)
1 = ECC double-bit error trap has occurred
0 = ECC double-bit error trap has not occurred
bit 0 SGHT: Software-Generated Hard Trap Status bit
1 = Software-generated hard trap has occurred
0 = Software-generated hard trap has not occurred
Note 1: ECC double-bit error causes a generic hard trap.

REGISTER 7-7: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER

U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0
— — — — — ILR3 ILR2 ILR1
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

VECNUM7 VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0
bit 7 bit 0
Legend:

bit 10-8 ILR<3:0>: New CPU Interrupt Priority Level bits
1111 = CPU Interrupt Priority Level is 15
•
•
•
bit 7-0 VECNUM<7:0>: Vector Number of Pending Interrupt bits
11111111 = 255, Reserved; do not use
•
•
•
00001001 = 9, Input Capture 1 (IC1)
00001000 = 8, External Interrupt 0 (INT0)
00000111 = 7, Reserved; do not use
00000110 = 6, Generic soft error trap
00000101 = 5, DMAC error trap
00000100 = 4, Math error trap
00000011 = 3, Stack error trap
00000010 = 2, Generic hard trap
00000001 = 1, Address error trap
00000000 = 0, Oscillator fail trap

8.0 DIRECT MEMORY ACCESS The DMA Controller transfers data between Peripheral
Data registers and Data Space SRAM. For the
(DMA)
simplified DMA block diagram, refer to Figure 8-1.
Note 1: This data sheet summarizes the features In addition, DMA can access the entire data memory
of the dsPIC33EVXXXGM00X/10X family space. The data memory bus arbiter is utilized when
of devices. It is not intended to be a either the CPU or DMA attempts to access SRAM,
comprehensive reference source. To resulting in potential DMA or CPU stalls.
The DMA Controller supports 4 independent channels.
sheet, refer to “Direct Memory Access
Each channel can be configured for transfers to or from
(DMA)” (DS70348) in the “dsPIC33/
selected peripherals. The peripherals supported by the
PIC24 Family Reference Manual”, which
DMA Controller include:
is available from the Microchip web site
(www.microchip.com). • CAN
2: Some registers and associated bits • Analog-to-Digital Converter (ADC)
described in this section may not be • Serial Peripheral Interface (SPI)
available on all devices. Refer to • UART
Section 4.0 “Memory Organization” in • Input Capture
this data sheet for device-specific register • Output Compare
Refer to Table 8-1 for a complete list of supported
peripherals.
FIGURE 8-1: PERIPHERAL TO DMA CONTROLLER
Data Memory
PERIPHERAL DMA Arbiter
(see Figure 4-13)
SRAM

In addition, DMA transfers can be triggered by timers • Peripheral Indirect Addressing mode (peripheral
as well as external interrupts. Each DMA channel is generates destination address)
unidirectional. Two DMA channels must be allocated to • CPU Interrupt after Half or Full Block Transfer
read and write to a peripheral. If more than one channel Complete
receives a request to transfer data, a simple fixed • Byte or Word Transfers
priority scheme, based on channel number, dictates
• Fixed Priority Channel Arbitration
which channel completes the transfer and which
channel or channels are left pending. Each DMA • Manual (software) or Automatic (peripheral DMA
channel moves a block of data, after which, it generates requests) Transfer Initiation
an interrupt to the CPU to indicate that the block is • One-Shot or Auto-Repeat Block Transfer modes
available for processing. • Ping-Pong mode (automatic switch between two
The DMA Controller provides these functional SRAM start addresses after each block transfer
capabilities: complete)
• DMA Request for Each Channel can be Selected
• Four DMA Channels
from any Supported Interrupt Source
• Register Indirect with Post-Increment Addressing
• Debug Support Features
mode
• Register Indirect without Post-Increment The peripherals that can utilize DMA are listed in
Addressing mode Table 8-1.
TABLE 8-1: DMA CHANNEL TO PERIPHERAL ASSOCIATIONS

DMAxPAD Register DMAxPAD Register
Peripheral to DMA DMAxREQ Register
(Values to Read from (Values to Write to
Association IRQSEL<7:0> Bits
Peripheral) Peripheral)
External Interrupt 0 (INT0) 00000000 — —
Input Capture 1 (IC1) 00000001 0x0144 (IC1BUF) —
Input Capture 2 (IC2) 00000101 0x014C (IC2BUF) —
Input Capture 3 (IC3) 00100101 0x0154 (IC3BUF) —
Input Capture 4 (IC4) 00100110 0x015C (IC4BUF) —
Output Compare 1 (OC1) 00000010 — 0x0906 (OC1R)
0x0904 (OC1RS)
0x090E (OC2RS)
Output Compare 3 (OC3) 00011001 — 0x091A (OC3R)
0x0918 (OC3RS)
0x0922 (OC4RS)
Timer2 (TMR2) 00000111 — —
Timer3 (TMR3) 00001000 — —
Timer4 (TMR4) 00011011 — —
Timer5 (TMR5) 00011100 — —
SPI1 Transfer Done 00001010 0x0248 (SPI1BUF) 0x0248 (SPI1BUF)
SPI2 Transfer Done 00100001 0x0268 (SPI2BUF) 0x0268 (SPI2BUF)
UART1 Receiver (UART1RX) 00001011 0x0226 (U1RXREG) —
UART1 Transmitter (UART1TX) 00001100 — 0x0224 (U1TXREG)
UART2 Receiver (UART2RX) 00011110 0x0236 (U2RXREG) —
UART2 Transmitter (UART2TX) 00011111 — 0x0234 (U2TXREG)
RX Data Ready (CAN1) 00100010 0x0440 (C1RXD) —
TX Data Request (CAN1) 01000110 — 0x0442 (C1TXD)
ADC1 Convert Done (ADC1) 00001101 0x0300 (ADC1BUF0) —

Figure 8-2 illustrates the DMA Controller block diagram.
FIGURE 8-2: DMA CONTROLLER BLOCK DIAGRAM
SRAM Peripheral Indirect Address
DMA Controller
DMA IRQ to DMA
DMA Ready and Interrupt
Control
DMA
Arbiter Channels Peripheral 1 Controller
Modules
0 1 2 3 CPU DMA
DMA X-Bus
CPU Peripheral X-Bus
CPU DMA CPU DMA

Non-DMA DMA DMA
CPU Ready Ready
Peripheral
Peripheral 2 Peripheral 3
IRQ to DMA and IRQ to DMA and

Interrupt Controller Interrupt Controller
Modules Modules
Note: CPU and DMA address buses are not shown for clarity.
8.1 DMAC Controller Registers Additional status registers (DMAPWC, DMARQC,

DMAPPS, DMALCA and DSADRH/L) are common to
Each DMAC Channel x (where x = 0 to 3) contains the all DMAC channels. These status registers provide
following registers: information on write and request collisions, as well as
• 16-Bit DMA Channel x Control Register (DMAxCON) on last address and channel access information.
• 16-Bit DMA Channel x IRQ Select Register The DMA Interrupt Flags (DMAxIF) are located in an
(DMAxREQ) IFSx register in the interrupt controller. The
• 32-Bit DMA Channel x Start Address Register A corresponding DMA Interrupt Enable bits (DMAxIE)
High/Low (DMAxSTAH/L) are located in an IECx register in the interrupt
• 32-Bit DMA Channel x Start Address Register B controller and the corresponding DMA Interrupt
High/Low (DMAxSTBH/L) Priority bits (DMAxIP) are located in an IPCx register
in the interrupt controller.
• 16-Bit DMA Channel x Peripheral Address
Register (DMAxPAD)
• 14-Bit DMA Channel x Transfer Count Register
(DMAxCNT)

REGISTER 8-1: DMAxCON: DMA CHANNEL x CONTROL REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
CHEN SIZE DIR HALF NULLW — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0

— — AMODE1 AMODE0 — — MODE1 MODE0
bit 7 bit 0
Legend:
bit 15 CHEN: DMA Channel Enable bit

1 = Channel is enabled
0 = Channel is disabled
bit 14 SIZE: DMA Data Transfer Size bit
1 = Byte
0 = Word
bit 13 DIR: DMA Transfer Direction bit (source/destination bus select)
1 = Reads from RAM address, writes to peripheral address
0 = Reads from peripheral address, writes to RAM address
bit 12 HALF: DMA Block Transfer Interrupt Select bit
1 = Initiates interrupt when half of the data has been moved
0 = Initiates interrupt when all of the data has been moved
bit 11 NULLW: Null Data Peripheral Write Mode Select bit
1 = Null data write to peripheral in addition to RAM write (DIR bit must also be clear)
0 = Normal operation
bit 5-4 AMODE<1:0>: DMA Channel Addressing Mode Select bits
11 = Reserved
10 = Peripheral Indirect mode
01 = Register Indirect without Post-Increment mode
00 = Register Indirect with Post-Increment mode
bit 1-0 MODE<1:0>: DMA Channel Operating Mode Select bits
11 = One-Shot Ping-Pong modes are enabled (one block transfer from/to each DMA buffer)
10 = Continuous Ping-Pong modes are enabled
01 = One-Shot Ping-Pong modes are disabled
00 = Continuous Ping-Pong modes are disabled

REGISTER 8-2: DMAxREQ: DMA CHANNEL x IRQ SELECT REGISTER

R/S-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
(1)
FORCE — — — — — — —
bit 15 bit 8

IRQSEL7 IRQSEL6 IRQSEL5 IRQSEL4 IRQSEL3 IRQSEL2 IRQSEL1 IRQSEL0
bit 7 bit 0
Legend: S = Settable bit

bit 15 FORCE: Force DMA Transfer bit(1)

1 = Forces a single DMA transfer (Manual mode)
0 = Automatic DMA transfer initiation by DMA request
bit 7-0 IRQSEL<7:0>: DMA Peripheral IRQ Number Select bits
01000110 = TX data request (CAN1)(2)
00100110 = Input Capture 4 (IC4)
00100010 = RX data ready (CAN1)
00100001 = SPI2 transfer done (SPI2)
00011111 = UART2 Transmitter (UART2TX)
00011110 = UART2 Receiver (UART2RX)
00011100 = Timer5 (TMR5)
00011011 = Timer4 (TMR4)
00011010 = Output Compare 4 (OC4)
00001101 = ADC1 convert done (ADC1)
00001100 = UART1 Transmitter (UART1TX)
00001011 = UART1 Receiver (UART1RX)
00001010 = SPI1 transfer done (SPI1)
00001000 = Timer3 (TMR3)
00000111 = Timer2 (TMR2)
00000000 = External Interrupt 0 (INT0)
Note 1: The FORCE bit cannot be cleared by user software. The FORCE bit is cleared by hardware when the
forced DMA transfer is complete or the channel is disabled (CHEN = 0).
2: This select bit is only available on dsPIC33EVXXXGM10X devices.

REGISTER 8-3: DMAxSTAH: DMA CHANNEL x START ADDRESS REGISTER A (HIGH)

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

STA<23:16>
bit 7 bit 0
Legend:

bit 7-0 STA<23:16>: DMA Primary Start Address bits (source or destination)
REGISTER 8-4: DMAxSTAL: DMA CHANNEL x START ADDRESS REGISTER A (LOW)

STA<15:8>
bit 15 bit 8

STA<7:0>
bit 7 bit 0
Legend:
bit 15-0 STA<15:0>: DMA Primary Start Address bits (source or destination)

REGISTER 8-5: DMAxSTBH: DMA CHANNEL x START ADDRESS REGISTER B (HIGH)

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

STB<23:16>
bit 7 bit 0
Legend:

bit 7-0 STB<23:16>: DMA Secondary Start Address bits (source or destination)
REGISTER 8-6: DMAxSTBL: DMA CHANNEL x START ADDRESS REGISTER B (LOW)

STB<15:8>
bit 15 bit 8

STB<7:0>
bit 7 bit 0
Legend:
bit 15-0 STB<15:0>: DMA Secondary Start Address bits (source or destination)

REGISTER 8-7: DMAxPAD: DMA CHANNEL x PERIPHERAL ADDRESS REGISTER(1)

PAD<15:8>
bit 15 bit 8

PAD<7:0>
bit 7 bit 0
Legend:
bit 15-0 PAD<15:0>: DMA Peripheral Address Register bits
Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the
DMA channel and should be avoided.
REGISTER 8-8: DMAxCNT: DMA CHANNEL x TRANSFER COUNT REGISTER(1)

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — CNT<13:8>(2)
bit 15 bit 8

(2)
CNT<7:0>
bit 7 bit 0
Legend:

bit 13-0 CNT<13:0>: DMA Transfer Count Register bits(2)
Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the
DMA channel and should be avoided.
2: The number of DMA transfers = CNT<13:0> + 1.

REGISTER 8-9: DSADRH: DMA MOST RECENT RAM HIGH ADDRESS REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

DSADR<23:16>
bit 7 bit 0
Legend:

bit 7-0 DSADR<23:16>: Most Recent DMA Address Accessed by DMA bits
REGISTER 8-10: DSADRL: DMA MOST RECENT RAM LOW ADDRESS REGISTER
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
DSADR<15:8>
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

DSADR<7:0>
bit 7 bit 0
Legend:
bit 15-0 DSADR<15:0>: Most Recent DMA Address Accessed by DMA bits

REGISTER 8-11: DMAPWC: DMA PERIPHERAL WRITE COLLISION STATUS REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0

— — — — PWCOL3 PWCOL2 PWCOL1 PWCOL0
bit 7 bit 0
Legend:

bit 3 PWCOL3: Channel 3 Peripheral Write Collision Flag bit
1 = Write collision is detected
0 = Write collision is not detected

REGISTER 8-12: DMARQC: DMA REQUEST COLLISION STATUS REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0

— — — — RQCOL3 RQCOL2 RQCOL1 RQCOL0
bit 7 bit 0
Legend:

bit 3 RQCOL3: Channel 3 Transfer Request Collision Flag bit
1 = User force and interrupt-based request collision is detected
0 = User force and interrupt-based request collision is not detected

REGISTER 8-13: DMALCA: DMA LAST CHANNEL ACTIVE STATUS REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R-1 R-1 R-1 R-1

— — — — LSTCH<3:0>
bit 7 bit 0
Legend:

bit 3-0 LSTCH<3:0>: Last DMAC Channel Active Status bits
1111 = No DMA transfer has occurred since system Reset
1110 = Reserved
•
•
•
0100 = Reserved
0011 = Last data transfer was handled by Channel 3

REGISTER 8-14: DMAPPS: DMA PING-PONG STATUS REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0

— — — — PPST3 PPST2 PPST1 PPST0
bit 7 bit 0
Legend:

bit 3 PPST3: Channel 3 Ping-Pong Mode Status Flag bit
1 = DMA3STB register is selected
0 = DMA3STA register is selected
bit 0 PPST0: Channel 0 Ping-Pong mode Status Flag bit

NOTES:

9.0 OSCILLATOR CONFIGURATION The dsPIC33EVXXXGM00X/10X family oscillator

system provides:
• On-Chip Phase-Locked Loop (PLL) to Boost
of the dsPIC33EVXXXGM00X/10X
Internal Operating Frequency on Select Internal
family of devices. It is not intended to be
and External Oscillator Sources
a comprehensive reference source. To
complement the information in this data • On-the-Fly Clock Switching between Various
sheet, refer to “Oscillator” (DS70580) in Clock Sources
the “dsPIC33/PIC24 Family Reference • Doze mode for System Power Savings
Manual”, which is available from the • Fail-Safe Clock Monitor (FSCM) that Detects
Microchip web site (www.microchip.com). Clock Failure and Permits Safe Application
2: Some registers and associated bits Recovery or Shutdown.
described in this section may not be • Backup FRC (BFRC) Function that Provides a
available on all devices. Refer to System Clock when there is a Failure in the FRC
Section 4.0 “Memory Organization” in Clock
this data sheet for device-specific register • Configuration bits for Clock Source Selection
A simplified diagram of the oscillator system is shown
in Figure 9-1.
FIGURE 9-1: OSCILLATOR SYSTEM DIAGRAM
Primary Oscillator
OSC1 DOZE<2:0>
POSCCLK XT, HS, EC
S2
XTPLL, HSPLL,
S3 ECPLL, FRCPLL
S1/S3
DOZE
FCY(2)
S1 PLL(1)
OSC2 FVCO(1)
POSCMD<1:0>
FP(2)
FRCDIV
FRCCLK ÷2
FRC FRCDIVN
Oscillator S7
FOSC
FRCDIV<2:0>
TUN<5:0> FRCDIV16 Reference Clock Generation
÷ 16 S6
FRC POSCCLK
S0 REFCLKO
÷N
FOSC
LPRC LPRC RPn
S5
Oscillator
BFRC If CF = 1 BFRC ROSEL RODIV<3:0>

S4
Oscillator
Clock Fail Clock Switch Reset
S7 NOSC<2:0> FNOSC<2:0>
WDT, PWRT
FSCM, CTMU
Note 1: See Figure 9-2 for PLL and FVCO details.

2: The term, FP, refers to the clock source for all peripherals, while FCY refers to the clock source for the CPU. Throughout this
document, FCY and FP are used interchangeably, except in the case of Doze mode. FP and FCY will be different when Doze
mode is used with a Doze ratio of 1:2 or lower.

9.1 CPU Clocking System For instruction execution speed or device operating
frequency, FCY, see Equation 9-1.
The dsPIC33EVXXXGM00X/10X family of devices
provides the following six system clock options: EQUATION 9-1: DEVICE OPERATING
• Fast RC (FRC) Oscillator FREQUENCY
• FRC Oscillator with Phase-Locked Loop (PLL) FCY = FOSC/2
• FRC Oscillator with Postscaler
• Primary (XT, HS or EC) Oscillator Figure 9-2 provides the block diagram of the PLL
• Primary Oscillator with PLL module.
• Low-Power RC (LPRC) Oscillator Equation 9-2 provides the relationship between input
frequency (FIN) and output frequency (FOSC).
Equation 9-3 provides the relationship between input
frequency (FIN) and VCO frequency (FSYS).
FIGURE 9-2: PLL BLOCK DIAGRAM
0.8 MHz < FPLLI(1) < 8.0 MHz 120 MHz < FSYS(1) < 340 MHz FOSC < 140 MHz
FIN FPLLI FSYS

÷ N1 FOSC
PFD VCO ÷ N2
PLLPRE<4:0>
÷M PLLPST<1:0>
PLLDIV<8:0>
Note 1: This frequency range must be met at all times.
EQUATION 9-2: FOSC CALCULATION
FOSC = FIN  ( N1 M ) = F  ( (PLLPRE<4:0>(PLLDIV<8:0>

IN
+ 2)
+ 2)  2(PLLPOST<1:0> + 1) )
Where:
N1 = PLLPRE<4:0> + 2
N2 = 2 x (PLLPOST<1:0> + 1)
M = PLLDIV<8:0> + 2
EQUATION 9-3: FVCO CALCULATION
FSYS = FIN  ( N1M ) = F  ( (PLLPRE<4:0>

IN
(PLLDIV<8:0> + 2)
+ 2) )

Table 9-1 provides the Configuration bits which allow

users to choose between the various clock modes.
TABLE 9-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION

Oscillator Mode Oscillator Source POSCMD<1:0> FNOSC<2:0>
Fast RC Oscillator with Divide-by-N (FRCDIVN)(1,2) Internal xx 111
(1)
Fast RC Oscillator with Divide-by-16 (FRCDIV16) Internal xx 110
Low-Power RC Oscillator (LPRC)(1) Internal xx 101
Primary Oscillator (HS) with PLL (HSPLL) Primary 10 011
Primary Oscillator (XT) with PLL (XTPLL) Primary 01 011
(1)
Primary Oscillator (EC) with PLL (ECPLL) Primary 00 011
Primary Oscillator (HS) Primary 10 010
Primary Oscillator (XT) Primary 01 010
Primary Oscillator (EC)(1) Primary 00 010
Fast RC Oscillator (FRC) with Divide-by-N and PLL Internal xx 001
(FRCPLL)(1)
Fast RC Oscillator (FRC)(1) Internal xx 000
Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit.
2: This is the default oscillator mode for an unprogrammed (erased) device.

REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER(1,3)

U-0 R-0 R-0 R-0 U-0 R/W-y R/W-y R/W-y
(2) (2)
— COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0(2)
bit 15 bit 8
R/W-0 R/W-0 R-0 U-0 R/C-0 U-0 U-0 R/W-0

CLKLOCK IOLOCK LOCK — CF — — OSWEN
bit 7 bit 0
Legend: C = Clearable bit y = Value set from Configuration bits on POR


bit 14-12 COSC<2:0>: Current Oscillator Selection bits (read-only)
111 = Fast RC Oscillator (FRC) with Divide-by-N
110 = Fast RC Oscillator (FRC) with Divide-by-16
101 = Low-Power RC Oscillator (LPRC)
100 = Backup FRC Oscillator (BFRC)(4)
011 = Primary Oscillator (XT, HS, EC) with PLL
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator (FRC) Divided by N and PLL
000 = Fast RC Oscillator (FRC)
bit 10-8 NOSC<2:0>: New Oscillator Selection bits(2)
111 = Fast RC Oscillator (FRC) with Divide-by-N
110 = Fast RC Oscillator (FRC) with Divide-by-16
101 = Low-Power RC Oscillator (LPRC)
100 = Reserved(5)
011 = Primary Oscillator (XT, HS, EC) with PLL
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator (FRC) Divided by N and PLL
000 = Fast RC Oscillator (FRC)
bit 7 CLKLOCK: Clock Lock Enable bit
1 = If FCKSM0 = 1, then clock and PLL configurations are locked; if FCKSM0 = 0, then clock and PLL
configurations may be modified
0 = Clock and PLL selections are not locked, configurations may be modified
bit 6 IOLOCK: I/O Lock Enable bit
1 = I/O lock is active
0 = I/O lock is not active
bit 5 LOCK: PLL Lock Status bit (read-only)
1 = Indicates that PLL is in lock or PLL start-up timer is satisfied
0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled
Note 1: Writes to this register require an unlock sequence. Refer to “Oscillator” (DS70580) in the
“dsPIC33/PIC24 Family Reference Manual” (available from the Microchip web site) for details.
2: Direct clock switches between any Primary Oscillator mode with PLL and FRCPLL mode are not permit-
ted. This applies to clock switches in either direction. In these instances, the application must switch to
FRC mode as a transitional clock source between the two PLL modes.
3: This register resets only on a Power-on Reset (POR).
4: COSC<2:0> bits will be set to ‘0b100’ when FRC fails.
5: User cannot write ‘0b100’ to NOSC<2:0>. COSC<2:0> will be set to ‘0b100’ (BFRC) when the FRC fails.

REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER(1,3) (CONTINUED)

bit 3 CF: Clock Fail Detect bit (read/clear by application)
1 = FSCM has detected a clock failure
0 = FSCM has not detected a clock failure
bit 0 OSWEN: Oscillator Switch Enable bit
1 = Requests oscillator switch to selection specified by the NOSC<2:0> bits
0 = Oscillator switch is complete
Note 1: Writes to this register require an unlock sequence. Refer to “Oscillator” (DS70580) in the
“dsPIC33/PIC24 Family Reference Manual” (available from the Microchip web site) for details.
2: Direct clock switches between any Primary Oscillator mode with PLL and FRCPLL mode are not permit-
ted. This applies to clock switches in either direction. In these instances, the application must switch to
FRC mode as a transitional clock source between the two PLL modes.
4: COSC<2:0> bits will be set to ‘0b100’ when FRC fails.
5: User cannot write ‘0b100’ to NOSC<2:0>. COSC<2:0> will be set to ‘0b100’ (BFRC) when the FRC fails.

REGISTER 9-2: CLKDIV: CLOCK DIVISOR REGISTER(2)

(3) (3) (3) (1,4)
ROI DOZE2 DOZE1 DOZE0 DOZEN FRCDIV2 FRCDIV1 FRCDIV0
bit 15 bit 8
R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PLLPOST1 PLLPOST0 — PLLPRE4 PLLPRE3 PLLPRE2 PLLPRE1 PLLPRE0
bit 7 bit 0
Legend:
bit 15 ROI: Recover on Interrupt bit

1 = Interrupts will clear the DOZEN bit
0 = Interrupts have no effect on the DOZEN bit
bit 14-12 DOZE<2:0>: Processor Clock Reduction Select bits(3)
111 = FCY divided by 128
000 = FCY divided by 1 (default)
bit 11 DOZEN: Doze Mode Enable bit(1,4)
1 = DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks
0 = Processor clock and peripheral clock ratio are forced to 1:1
bit 10-8 FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits
111 = FRC divided by 256
001 = FRC divided by 2 (default)
bit 7-6 PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler)
11 = Output divided by 8
10 = Reserved
Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs.
3: DOZE<2:0> bits can only be written to when the DOZEN bit is clear. If DOZEN = 1, any writes to
DOZE<2:0> are ignored.
4: The DOZEN bit cannot be set if DOZE<2:0> = 000. If DOZE<2:0> = 000, any attempt by user software to
set the DOZEN bit is ignored.

REGISTER 9-2: CLKDIV: CLOCK DIVISOR REGISTER(2) (CONTINUED)

bit 4-0 PLLPRE<4:0>: PLL Phase Detector Input Divider Select bits (also denoted as ‘N1’, PLL prescaler)
11111 = Input divided by 33
•
•
•
00001 = Input divided by 3
00000 = Input divided by 2 (default)
Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs.
3: DOZE<2:0> bits can only be written to when the DOZEN bit is clear. If DOZEN = 1, any writes to
DOZE<2:0> are ignored.
4: The DOZEN bit cannot be set if DOZE<2:0> = 000. If DOZE<2:0> = 000, any attempt by user software to
set the DOZEN bit is ignored.

REGISTER 9-3: PLLFBD: PLL FEEDBACK DIVISOR REGISTER(1)

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — PLLDIV8
bit 15 bit 8

PLLDIV<7:0>
bit 7 bit 0
Legend:

bit 8-0 PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier)
111111111 = 513
•
•
•
000110000 = 50 (default)
•
•
•
000000010 = 4
000000001 = 3
000000000 = 2
Note 1: This register is reset only on a Power-on Reset (POR).

REGISTER 9-4: OSCTUN: FRC OSCILLATOR TUNING REGISTER(1)

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — TUN<5:0>
bit 7 bit 0
Legend:

bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits
111111 = Center frequency – 0.048% (7.363 MHz)
•
•
•
011111 = Center frequency + 1.5% (7.48 MHz)
•
•
•
000000 = Center frequency (7.37 MHz nominal)
Note 1: This register is reset only on a Power-on Reset (POR).

REGISTER 9-5: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ROON — ROSSLP ROSEL RODIV3(1) RODIV2(1) RODIV1(1) RODIV0(1)
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 7 bit 0
Legend:
bit 15 ROON: Reference Oscillator Output Enable bit

1 = Reference oscillator output is enabled on the REFCLK pin(2)
0 = Reference oscillator output is disabled
bit 13 ROSSLP: Reference Oscillator Run in Sleep bit
1 = Reference oscillator output continues to run in Sleep mode
0 = Reference oscillator output is disabled in Sleep mode
bit 12 ROSEL: Reference Oscillator Source Select bit
1 = Oscillator crystal is used as the reference clock
0 = System clock is used as the reference clock
bit 11-8 RODIV<3:0>: Reference Oscillator Divider bits(1)
1111 = Reference clock divided by 32,768
1001 = Reference clock divided by 512
0000 = Reference clock
Note 1: The reference oscillator output must be disabled (ROON = 0) before writing to these bits.
2: This pin is remappable. See Section 11.5 “Peripheral Pin Select (PPS)” for more information.

10.0 POWER-SAVING FEATURES 10.1 Clock Frequency and Clock

Switching
of the dsPIC33EVXXXGM00X/10X The dsPIC33EVXXXGM00X/10X family devices allow
family of devices. It is not intended to be a wide range of clock frequencies to be selected under
a comprehensive reference source. To application control. If the system clock configuration is
complement the information in this data not locked, users can choose low-power or high-
sheet, refer to “Watchdog Timer and precision oscillators by simply changing the NOSCx
Power-Saving Modes” (DS70615) in bits (OSCCON<10:8>). For more information on the
the “dsPIC33/PIC24 Family Reference process of changing a system clock during operation,
Manual”, which is available from the as well as limitations to the process, see Section 9.0
Microchip web site (www.microchip.com). “Oscillator Configuration”.
described in this section may not be 10.2 Instruction-Based Power-Saving
available on all devices. Refer to Modes
The dsPIC33EVXXXGM00X/10X family devices have
two special power-saving modes that are entered
through the execution of a special PWRSAV
The dsPIC33EVXXXGM00X/10X devices provide the instruction. Sleep mode stops clock operation and
ability to manage power consumption by selectively halts all code execution. Idle mode halts the CPU
managing clocking to the CPU and the peripherals. and code execution, but allows peripheral modules
In general, a lower clock frequency and a reduction to continue operation. The assembler syntax of the
in the number of peripherals being clocked PWRSAV instruction is shown in Example 10-1.
constitutes lower consumed power. Note: SLEEP_MODE and IDLE_MODE are con-
The dsPIC33EVXXXGM00X/10X family devices can stants defined in the Assembler Include
manage power consumption in the following four file for the selected device.
methods:
Sleep and Idle modes can be exited as a result of an
• Clock Frequency enabled interrupt, WDT time-out or a device Reset. When
• Instruction-Based Sleep and Idle modes the device exits these modes, it is said to “wake-up”.
• Software Controlled Doze mode
• Selective Peripheral Control in Software
Combinations of these methods can be used to
selectively tailor an application’s power consumption
while still maintaining critical application features,
such as timing-sensitive communications.
EXAMPLE 10-1: PWRSAV INSTRUCTION SYNTAX

PWRSAV #SLEEP_MODE ; Put the device into Sleep mode
PWRSAV #IDLE_MODE ; Put the device into Idle mode

10.2.1 SLEEP MODE 10.2.2 IDLE MODE

The following events occur in Sleep mode: The following events occur in Idle mode:
• The system clock source is shut down. If an • The CPU stops executing instructions.
on-chip oscillator is used, it is turned off. • The WDT is automatically cleared.
• The device current consumption is reduced to a • The system clock source remains active. By
minimum, provided that no I/O pin is sourcing default, all peripheral modules continue to operate
current. normally from the system clock source, but can
• The Fail-Safe Clock Monitor does not operate, also be selectively disabled (see Section 10.4
since the system clock source is disabled. “Peripheral Module Disable”).
• The LPRC clock continues to run in Sleep mode if • If the WDT or FSCM is enabled, the LPRC also
the WDT is enabled. remains active.
• The WDT, if enabled, is automatically cleared The device wakes from Idle mode on any of these
before entering Sleep mode. events:
• Some device features or peripherals can continue • Any interrupt that is individually enabled
to operate. This includes items such as the Input
• Any device Reset
Change Notification (ICN) on the I/O ports or
peripherals that use an external clock input. • A WDT time-out
• Any peripheral that requires the system clock On wake-up from Idle mode, the clock is reapplied to
source for its operation is disabled. the CPU and instruction execution will begin (2-4 clock
cycles later), starting with the instruction following the
The device wakes up from Sleep mode on any of these
PWRSAV instruction or the first instruction in the
events:
Interrupt Service Routine (ISR).
• Any interrupt source that is individually enabled
All peripherals also have the option to discontinue
• Any form of device Reset operation when Idle mode is entered to allow for
• A WDT time-out increased power savings. This option is selectable in
On wake-up from Sleep mode, the processor restarts the control register of each peripheral; for example, the
with the same clock source that was active when Sleep TSIDL bit in the Timer1 Control register (T1CON<13>).
mode was entered.
10.2.3 INTERRUPTS COINCIDENT WITH
For optimal power savings, the internal regulator and
POWER SAVE INSTRUCTIONS
the Flash regulator can be configured to go into
Standby mode when Sleep mode is entered by clearing Any interrupt that coincides with the execution of a
the VREGS (RCON<8>) and VREGSF (RCON<11>) PWRSAV instruction is held off until entry into Sleep or
bits (default configuration). Idle mode has completed. The device then wakes up
either from Sleep mode or Idle mode.
If the application requires a faster wake-up time, and
can accept higher current requirements, the VREGS
(RCON<8>) and VREGSF (RCON<11>) bits can be set
to keep the internal regulator and the Flash regulator
active during Sleep mode.

10.3 Doze Mode For example, suppose the device is operating at

20 MIPS and the CAN module has been configured for
The preferred strategies for reducing power consump- 500 kbps, based on this device operating speed. If the
tion are changing clock speed and invoking one of the device is placed in Doze mode, with a clock frequency
power-saving modes. In some circumstances, this may ratio of 1:4, the CAN module continues to communicate
not be practical. For example, it may be necessary for at the required bit rate of 500 kbps, but the CPU now
an application to maintain uninterrupted synchronous starts executing instructions at a frequency of 5 MIPS.
communication, even while it is doing nothing else.
Reducing system clock speed can introduce communi-
10.4 Peripheral Module Disable
cation errors, while using a power-saving mode can
stop communications completely. The Peripheral Module Disable (PMD) registers
Doze mode is a simple and effective alternative method provide a method to disable a peripheral module by
to reduce power consumption while the device is still stopping all clock sources supplied to that module.
executing code. In this mode, the system clock When a peripheral is disabled, using the appropriate
continues to operate from the same source and at the PMDx control bit, the peripheral is in a minimum power
same speed. Peripheral modules continue to be consumption state. The control and status registers
clocked at the same speed, while the CPU clock speed associated with the peripheral are also disabled, so
is reduced. Synchronization between the two clock writes to those registers do not have any effect and
domains is maintained, allowing the peripherals to read values are invalid.
access the SFRs while the CPU executes code at a A peripheral module is enabled only if both the associ-
slower rate. ated bit in the PMDx register is cleared and the peripheral
Doze mode is enabled by setting the DOZEN bit is supported by the specific dsPIC® DSC variant. If the
(CLKDIV<11>). The ratio between peripheral and core peripheral is present in the device, it is enabled in the
clock speed is determined by the DOZE<2:0> bits PMDx register by default.
(CLKDIV<14:12>). There are eight possible configu- Note: If a PMDx bit is set, the corresponding
rations, from 1:1 to 1:128, with 1:1 being the default module is disabled after a delay of one
setting. instruction cycle. Similarly, if a PMDx bit is
Programs can use Doze mode to selectively reduce cleared, the corresponding module is
power consumption in event-driven applications. This enabled after a delay of one instruction
allows clock-sensitive functions, such as synchronous cycle (assuming the module control regis-
communications, to continue without interruption while ters are already configured to enable
the CPU Idles, waiting for something to invoke an inter- module operation).
rupt routine. An automatic return to full-speed CPU
operation on interrupts can be enabled by setting the
ROI bit (CLKDIV<15>). By default, interrupt events
have no effect on Doze mode operation.

REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0
T5MD T4MD T3MD T2MD T1MD — PWMMD —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

I2C1MD U2MD U1MD SPI2MD SPI1MD — C1MD(1) AD1MD
bit 7 bit 0
Legend:
bit 15 T5MD: Timer5 Module Disable bit

1 = Timer5 module is disabled
0 = Timer5 module is enabled
bit 9 PWMMD: PWM Module Disable bit
1 = PWM module is disabled
0 = PWM module is enabled
bit 7 I2C1MD: I2C1 Module Disable bit
1 = I2C1 module is disabled
0 = I2C1 module is enabled
bit 6 U2MD: UART2 Module Disable bit
1 = UART2 module is disabled
0 = UART2 module is enabled
bit 5 U1MD: UART1 Module Disable bit
1 = UART1 module is disabled
0 = UART1 module is enabled
bit 4 SPI2MD: SPI2 Module Disable bit
1 = SPI2 module is disabled
0 = SPI2 module is enabled
bit 3 SPI1MD: SPI1 Module Disable bit
1 = SPI1 module is disabled
0 = SPI1 module is enabled
Note 1: This bit is available on dsPIC33EVXXXGM10X devices only.

REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 (CONTINUED)

bit 1 C1MD: CAN1 Module Disable bit(1)
1 = CAN1 module is disabled
0 = CAN1 module is enabled
bit 0 AD1MD: ADC1 Module Disable bit
1 = ADC1 module is disabled
0 = ADC1 module is enabled
Note 1: This bit is available on dsPIC33EVXXXGM10X devices only.

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — IC4MD IC3MD IC2MD IC1MD
bit 15 bit 8
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — — OC4MD OC3MD OC2MD OC1MD
bit 7 bit 0
Legend:

bit 11-8 IC4MD:IC1MD: Input Capture x (x = 1-4) Module Disable bits
1 = Input Capture x module is disabled
0 = Input Capture x module is enabled
bit 3-0 OC4MD:OC1MD: Output Compare x (x = 1-4) Module Disable bits
1 = Output Compare x module is disabled
0 = Output Compare x module is enabled


U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0
— — — — — CMPMD — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 7 bit 0
Legend:

bit 10 CMPMD: Comparator Module Disable bit
1 = Comparator module is disabled
0 = Comparator module is enabled

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0

— — — — REFOMD CTMUMD — —
bit 7 bit 0
Legend:

bit 3 REFOMD: Reference Clock Module Disable bit
1 = Reference clock module is disabled
0 = Reference clock module is enabled
bit 2 CTMUMD: CTMU Module Disable bit
1 = CTMU module is disabled
0 = CTMU module is enabled


U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — PWM3MD PWM2MD PWM1MD
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 7 bit 0
Legend:

bit 10-8 PWM3MD:PWM1MD: PWMx (x = 1-3) Module Disable bit
1 = PWMx module is disabled
0 = PWMx module is enabled


U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0

— — — DMA0MD(1) — — — —
(1)
DMA1MD
DMA2MD(1)
DMA3MD(1)
bit 7 bit 0
Legend:

bit 4 DMA0MD: DMA0 Module Disable bit(1)
1 = DMA0 module is disabled
0 = DMA0 module is enabled
DMA1MD: DMA1 Module Disable bit(1)
Note 1: This single bit enables and disables all four DMA channels.


U-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0
— — — SENT2MD SENT1MD — — DMTMD
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 7 bit 0
Legend:

bit 12 SENT2MD: SENT2 Module Disable bit
1 = SENT2 module is disabled
0 = SENT2 module is enabled
bit 11 SENT1MD: SENT1 Module Disable bit
1 = SENT1 module is disabled
0 = SENT1 module is enabled
bit 8 DMTMD: Deadman Timer Disable bit
1 = Deadman Timer is disabled
0 = Deadman Timer is enabled

NOTES:

11.0 I/O PORTS the I/O pin. The logic also prevents “loop through”, in
which a port’s digital output can drive the input of a
Note 1: This data sheet summarizes the features peripheral that shares the same pin. Figure 11-1
of the dsPIC33EVXXXGM00X/10X family illustrates how ports are shared with other peripherals
of devices. It is not intended to be a and the associated I/O pin to which they are connected.
comprehensive reference source. To com- When a peripheral is enabled and the peripheral is
plement the information in this data sheet, actively driving an associated pin, the use of the pin as a
refer to “I/O Ports” (DS70000598) in the general purpose output pin is disabled. The I/O pin can
“dsPIC33/PIC24 Family Reference Man- be read, but the output driver for the parallel port bit is
ual”, which is available from the Microchip disabled. If a peripheral is enabled, but the peripheral is
web site (www.microchip.com). not actively driving a pin, that pin can be driven by a port.
2: Some registers and associated bits All port pins have eight registers directly associated
described in this section may not be with their operation as digital I/O. The Data Direction
available on all devices. Refer to register (TRISx) determines whether the pin is an input
Section 4.0 “Memory Organization” in or an output. If the Data Direction register bit is a ‘1’,
this data sheet for device-specific register then the pin is an input. All port pins are defined as
and bit information. inputs after a Reset. Reads from the latch (LATx), read
Many of the device pins are shared among the the latch; writes to the latch, write the latch. Reads from
peripherals and the Parallel I/O ports. All I/O input ports the port (PORTx), read the port pins, while writes to the
feature Schmitt Trigger inputs for improved noise port pins, write the latch.
immunity. All the pins in the device are 5V tolerant pins. Any bit and its associated data and control registers
that are not valid for a particular device are disabled.
11.1 Parallel I/O (PIO) Ports This means that the corresponding LATx and TRISx
registers, and the port pin are read as zeros.
Generally, a Parallel I/O port that shares a pin with a
peripheral is subservient to the peripheral. The When a pin is shared with another peripheral or
peripheral’s output buffer data and control signals are function that is defined as an input only, it is
provided to a pair of multiplexers. The multiplexers nevertheless regarded as a dedicated port, because
select whether the peripheral or the associated port there is no other competing source of output.
has ownership of the output data and control signals of
FIGURE 11-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE

Peripheral Module Output Multiplexers
Peripheral Input Data
Peripheral Module Enable
I/O
Peripheral Output Enable
1
Output Enable
Peripheral Output Data
0
PIO Module 1 Output Data

Read TRISx 0
Data Bus
D Q I/O Pin
WR TRISx
CK
TRISx Latch
D Q
WR LATx +
WR PORTx CK
Data Latch
Read LATx
Input Data
Read PORTx

11.1.1 OPEN-DRAIN CONFIGURATION 11.2.1 I/O PORT WRITE/READ TIMING

In addition to the PORTx, LATx and TRISx registers One instruction cycle is required between a port
for data control, port pins can also be individually direction change or port write operation and a read
configured for either digital or open-drain outputs. This operation of the same port. Typically, this instruction
is controlled by the Open-Drain Control x register would be a NOP, as shown in Example 11-1.
(ODCx) associated with each port. Setting any of the
bits configures the corresponding pin to act as an 11.3 Input Change Notification (ICN)
open-drain output.
The Input Change Notification function (ICN) of the I/O
The open-drain feature allows the generation of
ports allows devices to generate interrupt requests to
outputs other than VDD by using external pull-up
the processor in response to a Change-of-State (COS)
resistors. The maximum open-drain voltage allowed
on selected input pins. This feature can detect input
on any pin is the same as the maximum VIH
Change-of-States, even in Sleep mode, when the
specification for that particular pin.
clocks are disabled. Every I/O port pin can be selected
See Table 30-10 in Section 30.0 “Electrical Charac- (enabled) for generating an interrupt request on a
teristics” for the maximum VIH specification of each Change-of-State.
pin.
Three control registers are associated with the ICN
functionality of each I/O port. The CNENx registers
11.2 Configuring Analog and Digital contain the ICN interrupt enable control bits for each of
Port Pins the input pins. Setting any of these bits enables an ICN
interrupt for the corresponding pins.
The ANSELx registers control the operation of the
analog port pins. The port pins that are to function as Each I/O pin also has a weak pull-up and a weak pull-
analog inputs or outputs must have their corresponding down connected to it. The pull-ups and pull-downs act
ANSELx and TRISx bits set. In order to use port pins as a current source or sink source connected to the
for I/O functionality with digital modules, such as pin, and eliminate the need for external resistors when
timers, UARTs, etc., the corresponding ANSELx bits push button or keypad devices are connected. The
must be cleared. pull-ups and pull-downs are enabled separately using
the CNPUx and the CNPDx registers, which contain
The ANSELx register has a default value of 0xFFFF.
the control bits for each of the pins. Setting any of
Therefore, all pins that share analog functions are
the control bits enables the weak pull-ups and/or
analog (not digital) by default.
pull-downs for the corresponding pins.
Pins with analog functions affected by the ANSELx
registers are listed with a buffer type of analog in the Note: The pull-ups and pull-downs on ICN pins
Pinout I/O Descriptions table (see Table 1-1 in should always be disabled when the port
Section 1.0 “Device Overview”). pin is configured as a digital output.
If the TRISx bit is cleared (output) while the ANSELx bit

is set, the digital output level (VOH or VOL) is converted EXAMPLE 11-1: PORT WRITE/READ
by an analog peripheral, such as the ADC module or EXAMPLE
comparator module. MOV 0xFF00, W0 ; Configure PORTB<15:8>
; as inputs
When the PORTx register is read, all pins configured as
MOV W0, TRISB ; and PORTB<7:0>
analog input channels are read as cleared (a low level).
; as outputs
Pins configured as digital inputs do not convert an NOP ; Delay 1 cycle
analog input. Analog levels on any pin defined as a BTSS PORTB, #13 ; Next Instruction
digital input (including the ANx pins) can cause the
input buffer to consume current that exceeds the
device specifications.

11.4 Slew Rate Selection 11.5.2 AVAILABLE PERIPHERALS

The slew rate selection feature allows the device to have The peripherals managed by the PPS are all digital
control over the slew rate selection on the required I/O only peripherals. These include general serial commu-
pin which supports this feature. For this purpose, for nications (UART and SPI), general purpose timer clock
each I/O port, there are two registers: SR1x and SR0x, inputs, timer related peripherals (input capture and
which configure the selection of the slew rate. The output compare) and Interrupt-on-Change (IOC)
register outputs are directly connected to the associated inputs.
I/O pins, which support the slew rate selection function. In comparison, some digital only peripheral modules are
The SR1x register specifies the MSb and the SR0x never included in the PPS feature, because the
register provides the LSb of the 2-bit field that selects the peripheral’s function requires special I/O circuitry on a
desired slew rate. For example, slew rate selections for specific port and cannot be easily connected to multiple
PORTA are as follows: pins. These modules include I2C and the PWM. A similar
requirement excludes all modules with analog inputs,
EXAMPLE 11-2: SLEW RATE SELECTIONS such as the ADC Converter.
FOR PORTA A key difference between the remappable and non-
SR1Ax, SR0Ax = 00 = Fastest Slew rate remappable peripherals is that the remappable
SR1Ax, SR0Ax = 01 = 4x slower Slew rate peripherals are not associated with a default I/O pin. The
SR1Ax, SR0Ax = 10 = 8x slower Slew rate peripheral must always be assigned to a specific I/O pin
SR1Ax, SR0Ax = 11 = 16x slower Slew rate before it can be used. In contrast, the non-remappable
peripherals are always available on a default pin,
11.5 Peripheral Pin Select (PPS) assuming that the peripheral is active and not conflicting
with another peripheral.
A major challenge in general purpose devices is provid- When a remappable peripheral is active on a given I/O
ing the largest possible set of peripheral features while pin, it takes priority over all the other digital I/O and digital
minimizing the conflict of features on I/O pins. The communication peripherals associated with the pin. Pri-
challenge is even greater on low pin count devices. In ority is given regardless of the type of peripheral that is
an application where more than one peripheral needs mapped. Remappable peripherals never take priority
to be assigned to a single pin, inconvenient work over any analog functions associated with the pin.
arounds in application code, or a complete redesign,
may be the only option. 11.5.3 CONTROLLING PERIPHERAL PIN
The Peripheral Pin Select (PPS) configuration provides SELECT
an alternative to these choices by enabling peripheral The PPS features are controlled through two sets of
set selection and their placement on a wide range of I/O SFRs: one to map the peripheral inputs and the other
pins. By increasing the pinout options available on a par- to map the outputs. Because they are separately con-
ticular device, users can better tailor the device to their trolled, a particular peripheral’s input and output (if the
entire application, rather than trimming the application to peripheral has both) can be placed on any selectable
fit the device. function pin without constraint.
The PPS configuration feature operates over a fixed The association of a peripheral to a peripheral-selectable
subset of digital I/O pins. Users may independently pin is handled in two different ways, depending on
map the input and/or output of most digital peripherals whether an input or output is being mapped.
to any one of these I/O pins. Hardware safeguards are
included that prevent accidental or spurious changes to 11.5.4 INPUT MAPPING
the peripheral mapping after it has been established.
The inputs of the PPS options are mapped on the basis
11.5.1 AVAILABLE PINS of the peripheral. That is, a control register associated
with a peripheral dictates the pin it will be mapped to. The
The number of available pins is dependent on the par- RPINRx registers are used to configure peripheral input
ticular device and its pin count. Pins that support the mapping (see Table 11-1 and Register 11-1 through
PPS feature include the designation, “RPn” or “RPIn”, Register 11-17). Each register contains sets of 8-bit
in their full pin designation, where “n” is the remappable fields, with each set associated with one of the remap-
pin number. “RP” is used to designate pins that support pable peripherals. Programming a given peripheral’s bit
both remappable input and output functions, while field with an appropriate 8-bit value maps the RPn pin
“RPI” indicates pins that support remappable input with the corresponding value to that peripheral. For any
functions only. given device, the valid range of values for any bit field
corresponds to the maximum number of Peripheral Pin
Selects supported by the device.

For example, Figure 11-2 shows the remappable pin 11.5.4.1 Virtual Connections
selection for the U1RX input.
dsPIC33EVXXXGM00X/10X family devices support
virtual (internal) connections to the output of the
FIGURE 11-2: REMAPPABLE INPUT FOR op amp/comparator module (see Figure 25-1 in
U1RX Section 25.0 “Op Amp/Comparator Module”).
U1RXR<6:0> These devices provide six virtual output pins

(RPV0-RPV5) that correspond to the outputs of six
0 peripheral pin output remapper blocks (RP176-RP181).
RP0 The six virtual remapper outputs (RP176-RP181) are
not connected to actual pins. The six virtual pins may
1
be read by any of the input remappers as inputs,
RP1
U1RX Input RPI176-RPI181. These virtual pins can be used to
2 to Peripheral connect the internal peripherals, whose signals are of
RP3 significant use to the other peripherals, but these
output signals are not present on the device pin.
Virtual connections provide a simple way of inter-
peripheral connection without utilizing a physical pin.
n For example, by setting the FLT1R<7:0> bits of the
RPn
RPINR12 register to the value of ‘b0000001’, the
output of the analog comparator, C1OUT, will be
Note: For input only, PPS functionality does not connected to the PWM Fault 1 input, which allows the
have priority over TRISx settings. There- analog comparator to trigger PWM Faults without the
fore, when configuring an RPn pin for input, use of an actual physical pin on the device.
the corresponding bit in the TRISx register
must also be configured for input (set to ‘1’).

TABLE 11-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)

Input Name(1) Function Name Register Configuration Bits
External Interrupt 1 INT1 RPINR0 INT1R<7:0>
External Interrupt 2 INT2 RPINR1 INT2R<7:0>
Timer2 External Clock T2CK RPINR3 T2CKR<7:0>
Input Capture 1 IC1 RPINR7 IC1R<7:0>
Output Compare Fault A OCFA RPINR11 OCFAR<7:0>
PWM Fault 1 FLT1 RPINR12 FLT1R<7:0>
PWM Fault 2 FLT2 RPINR12 FLT2R<7:0>
UART1 Receive U1RX RPINR18 U1RXR<7:0>
UART2 Receive U2RX RPINR19 U2RXR<7:0>
SPI2 Data Input SDI2 RPINR22 SDI2R<7:0>
SPI2 Clock Input SCK2 RPINR22 SCK2R<7:0>
SPI2 Slave Select SS2 RPINR23 SS2R<7:0>
CAN1 Receive C1RX RPINR26 C1RXR<7:0>
PWM Sync Input 1 SYNCI1 RPINR37 SYNCI1R<7:0>
PWM Dead-Time Compensation 1 DTCMP1 RPINR38 DTCMP1R<7:0>
SENT1 Input SENT1R RPINR44 SENT1R<7:0>
SENT2 Input SENT2R RPINR45 SENT2R<7:0>
Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger input buffers.

TABLE 11-2: INPUT PIN SELECTION FOR SELECTABLE INPUT SOURCES

Peripheral Pin Peripheral Pin
Input/ Input/
Select Input Pin Assignment Select Input Pin Assignment
Output Output
Register Value Register Value
000 0000 I VSS 011 0010 I RPI50
000 0001 I CMP1(1) 011 0011 I RPI51
000 0010 I CMP2(1) 011 0100 I RPI52
000 0011 I CMP3(1) 011 0101 I RPI53
(1)
000 0100 I CMP4 011 0110 I/O RP54
000 0101 — — 011 0111 I/O RP55
000 1100 I CMP5(1) 011 1000 I/O RP56
000 1101 — — 011 1001 I/O RP57
000 1110 — — 011 1010 I RPI58
000 1111 — — 011 1011 — —
001 0000 I RPI16 011 1100 I RPI60
001 0001 I RPI17 011 1101 I RPI61
001 0010 I RPI18 011 1110 — —
001 0011 I RPI19 011 1111 I RPI 63
001 0100 I/O RP20 100 0000 — —
001 0101 — — 100 0001 — —
001 0110 — — 100 0010 — —
001 0111 — — 100 0011 — —
001 1000 I RPI24 100 0100 — —
001 1001 I RPI25 100 0101 I/O RP69
001 1010 — — 100 0110 I/O RP70
001 1011 I RPI27 100 0111 — —
001 1100 I RPI28 100 1000 I RPI72
001 1101 — — 100 1001 — —
001 1110 — — 100 1010 — —
001 1111 — — 100 1011 — —
010 0000 I RPI32 100 1110 — —
010 0001 I RPI33 100 1111 — —
010 0010 I RPI34 101 0010 — —
010 0011 I/O RP35 101 0011 — —
010 0100 I/O RP36 101 0100 — —
010 0101 I/O RP37 010 1001 I/O RP41
010 0110 I/O RP38 010 1010 I/O RP42
010 0111 I/O RP39 010 1011 I/O RP43
010 1000 I/O RP40 101 1000 — —
010 1100 I RPI44 101 1001 — —
010 1101 I RPI45 101 1010 — —
010 1110 I RPI46 101 1011 — —
010 1111 I RPI47 101 1100 — —
011 0000 I/O RP48 101 1101 — —
Legend: Shaded rows indicate the PPS Input register values that are unimplemented.
Note 1: These are virtual pins. See Section 11.5.4.1 “Virtual Connections” for more information on selecting
this pin assignment.

TABLE 11-2: INPUT PIN SELECTION FOR SELECTABLE INPUT SOURCES (CONTINUED)
Peripheral Pin Peripheral Pin
Input/ Input/
Select Input Pin Assignment Select Input Pin Assignment
Output Output
Register Value Register Value
011 0001 I/O RP49 101 1110 I RPI94
110 0000 I RPI96 101 1111 I RPI95
110 0001 I/O RP97 111 0011 — —
110 0010 — — 111 0100 — —
110 0011 — — 111 0101 — —
110 0100 — — 111 0110 I/O RP118
110 0101 — — 111 0111 I RPI119
110 0110 — — 111 1000 I/O RP120
110 0111 — — 111 1001 I RPI121
110 1000 — — 111 1010 — —
110 1001 — — 111 1011 — —
110 1010 — — 111 1100 I RPI124
110 1011 — — 111 1101 I/O RP125
101 0101 — — 111 1110 I/O RP126
101 0110 — — 111 1111 I/O RP127
101 0111 — — 10110000 I/O RP176(1)
110 1100 — — 10110001 I/O RP177(1)
110 1101 — — 10110010 I/O RP178(1)
110 1110 — — 10110011 I/O RP179(1)
110 1111 — — 10110100 I/O RP180(1)
111 0010 — — 10110101 I/O RP181(1)
Legend: Shaded rows indicate the PPS Input register values that are unimplemented.
Note 1: These are virtual pins. See Section 11.5.4.1 “Virtual Connections” for more information on selecting
this pin assignment.
11.5.5 OUTPUT MAPPING FIGURE 11-3: MULTIPLEXING REMAPPABLE

In contrast to inputs, the outputs of the PPS options are OUTPUT FOR RPn
mapped on the basis of the pin. In this case, a control
RPnR<5:0>
register associated with a particular pin dictates the
peripheral output to be mapped. The RPORx registers
are used to control output mapping. Like the RPINRx reg- Default
0
isters, each register contains sets of 6-bit fields, with each U1TX Output
set associated with one RPn pin (see Register 11-18 to 1
Register 11-31). The value of the bit field corresponds to SDO2 Output
2 RPn
one of the peripherals and that peripheral’s output is Output Data
mapped to the pin (see Table 11-3 and Figure 11-3).
A null output is associated with the Output register
Reset value of ‘0’. This is done to ensure that remap-
REFCLKO Output 49
pable outputs remain disconnected from all output pins
by default.

11.5.5.1 Mapping Limitations across any or all of the RPn pins is possible. This
includes both many-to-one, and one-to-many map-
The control schema of the peripheral select pins is not
pings of peripheral inputs and outputs to pins. While
limited to a small range of fixed peripheral configura-
such mappings may be technically possible from a con-
tions. There are no mutual or hardware-enforced
figuration point of view, they may not be supportable
lockouts between any of the peripheral mapping SFRs.
from an electrical point of view.
Literally any combination of peripheral mappings
TABLE 11-3: OUTPUT SELECTION FOR REMAPPABLE PINS (RPn)

Function RPnR<5:0> Output Name
Default Port 000000 RPn tied to Default Pin
U1TX 000001 RPn tied to UART1 Transmit
U2TX 000011 RPn tied to UART2 Transmit
SDO2 001000 RPn tied to SPI2 Data Output
SCK2 001001 RPn tied to SPI2 Clock Output
SS2 001010 RPn tied to SPI2 Slave Select
C1TX 001110 RPn tied to CAN1 Transmit
OC1 010000 RPn tied to Output Compare 1 Output
C1OUT 011000 RPn tied to Comparator Output 1
SYNCO1 101101 RPn tied to PWM Primary Time Base Sync Output
REFCLKO 110001 RPn tied to Reference Clock Output
SENT1 111001 RPn tied to SENT Out 1
SENT2 111010 RPn tied to SENT Out 2

11.6 High-Voltage Detect (HVD) 3. Most I/O pins have multiple functions. Referring
to the device pin diagrams in this data sheet, the
dsPIC33EVXXXGM00X/10X devices contain High- priorities of the functions allocated to any pins
Voltage Detection (HVD) which monitors the VCAP are indicated by reading the pin name, from left-
voltage. The HVD is used to monitor the VCAP supply to-right. The left most function name takes
voltage to ensure that an external connection does not precedence over any function to its right in the
raise the value above a safe level (~2.4V). If high core naming convention; for example, AN16/T2CK/
voltage is detected, all I/Os are disabled and put in a tri- T7CK/RC1. This indicates that AN16 is the high-
state condition. The device remains in this I/O tri-state est priority in this example and will supersede all
condition as long as the high-voltage condition is other functions to its right in the list. Those other
present. functions to its right, even if enabled, would not
work as long as any other function to its left was
11.7 I/O Helpful Tips enabled. This rule applies to all of the functions
listed for a given pin.
1. In some cases, certain pins, as defined in
Table 30-10 under “Injection Current”, have 4. Each pin has an internal weak pull-up resistor
internal protection diodes to VDD and VSS. The and pull-down resistor that can be configured
term, “Injection Current”, is also referred to as using the CNPUx and CNPDx registers, respec-
“Clamp Current”. On designated pins with suffi- tively. These resistors eliminate the need for
cient external current-limiting precautions by the external resistors in certain applications. The
user, I/O pin input voltages are allowed to be internal pull-up is up to ~(VDD – 0.8), not VDD.
greater or less than the data sheet absolute This value is still above the minimum VIH of
maximum ratings, with respect to the VSS and CMOS and TTL devices.
VDD supplies. Note that when the user applica- 5. When driving LEDs directly, the I/O pin can
tion forward biases either of the high or low side source or sink more current than what is
internal input clamp diodes that the resulting specified in the VOH/IOH and VOL/IOL DC charac-
current being injected into the device, that is teristic specifications. The respective IOH and
clamped internally by the VDD and VSS power IOL current rating only applies to maintaining the
rails, may affect the ADC accuracy by four to six corresponding output at or above the VOH, and
counts. at or below the VOL levels. However, for LEDs,
2. I/O pins that are shared with any analog input pin unlike digital inputs of an externally connected
(i.e., ANx) are always analog pins by default after device, they are not governed by the same min-
any Reset. Consequently, configuring a pin as an imum VIH/VIL levels. An I/O pin output can safely
analog input pin automatically disables the digital sink or source any current less than that listed in
input pin buffer and any attempt to read the digital the absolute maximum rating section of this data
input level by reading PORTx or LATx will always sheet. For example:
return a ‘0’, regardless of the digital logic level on VOH = 4.4V at IOH = -8 mA and VDD = 5V
the pin. To use a pin as a digital I/O pin on a The maximum output current sourced by any
shared ANx pin, the user application needs to 8 mA I/O pin = 12 mA.
configure the Analog Pin Configuration registers
in the I/O ports module (i.e., ANSELx) by setting LED source current, <12 mA, is technically
the appropriate bit that corresponds to that I/O permitted. For more information, refer to the VOH/
port pin to a ‘0’. IOH specifications in Section 30.0 “Electrical
Characteristics”.
Note: Although it is not possible to use a digital
input pin when its analog function is
enabled, it is possible to use the digital I/O
output function, TRISx = 0x0, while the
analog function is also enabled. However,
this is not recommended, particularly if the
analog input is connected to an external
analog voltage source, which would
create signal contention between the
analog signal and the output pin driver.

6. The PPS pin mapping rules are as follows: • Any number of “input” remappable functions
• Only one “output” function can be active on a can be mapped to the same pin(s) at the
given pin at any time, regardless if it is a same time, including to any pin with a single
dedicated or remappable function (one pin, output from either a dedicated or remappable
one output). “output”.
• It is possible to assign a “remappable output” • The TRISx registers control only the digital
function to multiple pins and externally short I/O output buffer. Any other dedicated or
or tie them together for increased current remappable active “output” will automatically
drive. override the TRISx setting. The TRISx regis-
• If any “dedicated output” function is enabled ter does not control the digital logic “input”
on a pin, it will take precedence over any buffer. Remappable digital “inputs” do not
remappable “output” function. automatically override TRISx settings, which
means that the TRISx bit must be set to input
• If any “dedicated digital” (input or output)
for pins with only remappable input
function is enabled on a pin, any number of
function(s) assigned
“input” remappable functions can be mapped
to the same pin. • All analog pins are enabled by default after
any Reset and the corresponding digital input
• If any “dedicated analog” function(s) are
buffer on the pin is disabled. Only the Analog
enabled on a given pin, “digital input(s)” of
Pin Select registers control the digital input
any kind will all be disabled, although a single
buffer, not the TRISx register. The user must
“digital output”, at the user’s cautionary dis-
disable the analog function on a pin using the
cretion, can be enabled and active as long as
Analog Pin Select registers in order to use
there is no signal contention with an external
any “digital input(s)” on a corresponding pin;
analog input signal. For example, it is
no exceptions.
possible for the ADC to convert the digital
output logic level, or to toggle a digital output
on a comparator or ADC input provided there
is no external analog input, such as for a
built-in self-test.

11.8 Peripheral Pin Select Registers
REGISTER 11-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0

INT1R<7:0>
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 7 bit 0
Legend:
bit 15-8 INT1R<7:0>: Assign External Interrupt 1 (INT1) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
10110101 = Input tied to RPI181
•
•
•
00000001 = Input tied to CMP1
00000000 = Input tied to VSS

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

INT2R<7:0>
bit 7 bit 0
Legend:

bit 7-0 INT2R<7:0>: Assign External Interrupt 2 (INT2) to the Corresponding RPn Pin bits
•
•
•


U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

T2CKR<7:0>
bit 7 bit 0
Legend:

bit 7-0 T2CKR<7:0>: Assign Timer2 External Clock (T2CK) to the Corresponding RPn pin bits
•
•
•


IC2R7 IC2R6 IC2R5 IC2R4 IC2R3 IC2R2 IC2R1 IC2R0
bit 15 bit 8

bit 7 bit 0
Legend:
bit 15-8 IC2R<7:0>: Assign Input Capture 2 (IC2) to the Corresponding RPn Pin bits
•
•
•
•
•
•


bit 15 bit 8

bit 7 bit 0
Legend:
•
•
•
•
•
•


U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

OCFAR<7:0>
bit 7 bit 0
Legend:

bit 7-0 OCFAR<7:0>: Assign Output Compare Fault A (OCFA) to the Corresponding RPn Pin bits
•
•
•

FLT2R7 FLT2R6 FLT2R5 FLT2R4 FLT2R3 FLT2R2 FLT2R1 FLT2R0
bit 15 bit 8

FLT1R7 FLT1R6 FLT1R5 FLT1R4 FLT1R3 FLT1R2 FLT1R1 FLT1R0
bit 7 bit 0
Legend:
bit 15-8 FLT2R<7:0>: Assign PWM Fault 2 (FLT2) to the Corresponding RPn Pin bits
•
•
•
bit 7-0 FLT1R<7:0>: Assign PWM Fault 1 (FLT1) to the Corresponding RPn Pin bits
•
•
•


U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

U1RXR<7:0>
bit 7 bit 0
Legend:

bit 7-0 U1RXR<7:0>: Assign UART1 Receive (U1RX) to the Corresponding RPn Pin bits
•
•
•

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

U2RXR<7:0>
bit 7 bit 0
Legend:

bit 7-0 U2RXR<7:0>: Assign UART2 Receive (U2RX) to the Corresponding RPn Pin bits
•
•
•


SCK2R7 SCK2R6 SCK2R5 SCK2R4 SCK2R3 SCK2R2 SCK2R1 SCK2R0
bit 15 bit 8

SDI2R SDI2R6 SDI2R5 SDI2R4 SDI2R3 SDI2R2 SDI2R1 SDI2R0
bit 7 bit 0
Legend:
bit 15-8 SCK2R<7:0>: Assign SPI2 Clock Input (SCK2) to the Corresponding RPn Pin bits
•
•
•
bit 7-0 SDI2R<7:0>: Assign SPI2 Data Input (SDI2) to the Corresponding RPn Pin bits
•
•
•


U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

SS2R<7:0>
bit 7 bit 0
Legend:

bit 7-0 SS2R<7:0>: Assign SPI2 Slave Select (SS2) to the Corresponding RPn Pin bits
•
•
•

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

C1RXR<7:0>
bit 7 bit 0
Legend:

bit 7-0 C1RXR<7:0>: Assign CAN1 RX Input (C1RX) to the Corresponding RPn Pin bits
•
•
•


SYNCI1R<7:0>
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 7 bit 0
Legend:
bit 15-8 SYNCI1R<7:0>: Assign PWM Synchronization Input 1 to the Corresponding RPn Pin bits
•
•
•

DTCMP1R<7:0>
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 7 bit 0
Legend:
bit 15-8 DTCMP1R<7:0>: Assign PWM Dead-Time Compensation Input 1 to the Corresponding RPn Pin bits
•
•
•


DTCMP3R7 DTCMP3R6 DTCMP3R5 DTCMP3R4 DTCMP3R3 DTCMP3R2 DTCMP3R1 DTCMP3R0
bit 15 bit 8

DTCMP2R7 DTCMP2R6 DTCMP2R5 DTCMP2R4 DTCMP2R3 DTCMP2R2 DTCMP2R1 DTCMP2R0
bit 7 bit 0
Legend:
•
•
•
•
•
•


SENT1R<7:0>
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 7 bit 0
Legend:
bit 15-8 SENT1R<7:0>: Assign SENT Module Input 1 to the Corresponding RPn Pin bits
•
•
•

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

SENT2R<7:0>
bit 7 bit 0
Legend:

bit 7-0 SENT2R<7:0>: Assign SENT Module Input 2 to the Corresponding RPn Pin bits
•
•
•
00000000= Input tied to VSS

REGISTER 11-18: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — RP35R5 RP35R4 RP35R3 RP35R2 RP35R1 RP35R0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:

bit 13-8 RP35R<5:0>: Peripheral Output Function is Assigned to RP35 Output Pin bits
(see Table 11-3 for peripheral function numbers)

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:



U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:



U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:

REGISTER 11-23: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5(1)

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:

Note 1: This register is present in dsPIC33EVXXXGM004/104/006/106 devices only.


U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:

Note 1: This register is present in dsPIC33EVXXXGM004/104/006/106 devices only

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:



U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:

Note 1: This register is present in dsPIC33EVXXXGM004/106 devices only.


U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — RP120R5(1) RP120R4(1) RP120R3(1) RP120R2(1) RP120R1(1) RP120R0(1)
bit 7 bit 0
Legend:

bit 5-0 RP120R<5:0>: Peripheral Output Function is Assigned to RP120 Output Pin bits(1)
Note 1: RP120R<5:0> is present in dsPIC33EVXXXGM006/106 devices only.

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:



U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — RP181R<5:0>
bit 7 bit 0
Legend:


NOTES:

12.0 TIMER1 The Timer1 module can operate in one of the following
modes:
Note 1: This data sheet summarizes the features of • Timer mode
the dsPIC33EVXXXGM00X/10X family of
• Gated Timer mode
devices. It is not intended to be a
comprehensive reference source. To com- • Synchronous Counter mode
plement the information in this data sheet, • Asynchronous Counter mode
refer to “Timers” (DS70362) in the In Timer and Gated Timer modes, the input clock is
“dsPIC33/PIC24 Family Reference Man- derived from the internal instruction cycle clock (FCY).
ual”, which is available from the Microchip In Synchronous and Asynchronous Counter modes,
web site (www.microchip.com). the input clock is derived from the external clock input
2: Some registers and associated bits at the T1CK pin.
described in this section may not be The Timer modes are determined by the following bits:
Section 4.0 “Memory Organization” in • Timer Clock Source Control bit (TCS): T1CON<1>
this data sheet for device-specific register • Timer Synchronization Control bit (TSYNC):
and bit information. T1CON<2>
• Timer Gate Control bit (TGATE): T1CON<6>
The Timer1 module is a 16-bit timer that can operate as
a free-running, interval timer/counter. Timer control bit settings for different operating modes
are given in Table 12-1.
The Timer1 module has the following unique features
over other timers:
TABLE 12-1: TIMER MODE SETTINGS
• Can be Operated in Asynchronous Counter mode
Mode TCS TGATE TSYNC
from an External Clock Source
• The Timer1 External Clock Input (T1CK) can Timer 0 0 x
Optionally be Synchronized to the Internal Device Gated Timer 0 1 x
Clock and the Clock Synchronization is
Synchronous 1 x 1
Performed after the Prescaler
Counter
A block diagram of Timer1 is shown in Figure 12-1. Asynchronous 1 x 0
Counter
FIGURE 12-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM
Gate Falling Edge

1
Sync Detect
Set T1IF Flag
FP(1) Prescaler 10
T1CLK
(/n) TGATE
Reset Data
00 TMR1 Latch
TCKPS<1:0>
0 CLK
T1CK x1
Prescaler Equal
Sync 1 Comparator
(/n) CTMU Edge
Control Logic
TGATE
TSYNC
TCKPS<1:0> TCS
PR1
Note 1: FP is the peripheral clock.
 2013-2016 Microchip Technology Inc. DS70005144D-page 173

12.1 Timer1 Control Register
REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER

R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
TON(1) — TSIDL — — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0

— TGATE TCKPS1 TCKPS0 — TSYNC(1) TCS(1) —
bit 7 bit 0
Legend:
bit 15 TON: Timer1 On bit(1)

1 = Starts 16-bit Timer1
0 = Stops 16-bit Timer1
bit 13 TSIDL: Timer1 Stop in Idle Mode bit
1 = Discontinues module operation when the device enters Idle mode
0 = Continues module operation in Idle mode
bit 6 TGATE: Timer1 Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4 TCKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 2 TSYNC: Timer1 External Clock Input Synchronization Select bit(1)
When TCS = 1:
1 = External clock input is synchronized
0 = External clock input is not synchronized
When TCS = 0:
bit 1 TCS: Timer1 Clock Source Select bit(1)
1 = External clock is from pin, T1CK (on the rising edge)
0 = Internal clock (FP)
Note 1: When Timer1 is enabled in External Synchronous Counter mode (TCS = 1, TSYNC = 1, TON = 1), any
attempts by user software to write to the TMR1 register are ignored.
DS70005144D-page 174  2013-2016 Microchip Technology Inc.

13.0 TIMER2/3 AND TIMER4/5 Individually, all four of the 16-bit timers can function as
synchronous timers or counters. They also offer the
Note 1: This data sheet summarizes the features of features listed previously, except for the event trigger;
the dsPIC33EVXXXGM00X/10X family of this is implemented only with Timer2/3. The operating
devices. It is not intended to be a modes and enabled features are determined by setting
comprehensive reference source. To the appropriate bit(s) in the T2CON, T3CON, T4CON
complement the information in this data and T5CON registers. T2CON and T4CON are shown
sheet, refer to “Timers” (DS70362) in the in generic form in Register 13-1. The T3CON and
“dsPIC33/PIC24 Family Reference T5CON registers are shown in Register 13-2.
Manual”, which is available from the For 32-bit timer/counter operation, Timer2 and Timer4
Microchip web site (www.microchip.com). are the least significant word (lsw). Timer3 and Timer5
2: Some registers and associated bits are the most significant word (msw) of the 32-bit timers.
Note: For 32-bit operation, the T3CON and
T5CON control bits are ignored. Only the
T2CON and T4CON control bits are used
for setup and control. Timer2 and Timer4
clock and gate inputs are utilized for the
These modules are 32-bit timers, which can also be 32-bit timer modules, but an interrupt is
configured as four independent, 16-bit timers with generated with the Timer3 and Timer5
selectable operating modes. interrupt flags.
As a 32-bit timer, Timer2/3 and Timer4/5 operate in the Block diagrams for the Type B and Type C timers are
following three modes: shown in Figure 13-1 and Figure 13-2, respectively.
• Two Independent 16-Bit Timers (e.g., Timer2 and A block diagram for an example 32-bit timer pair
Timer3) with all 16-Bit Operating modes (except (Timer2/3 and Timer4/5) is shown in Figure 13-3.
Asynchronous Counter mode)
Note: Only Timer2, Timer3, Timer4 and Timer5
• Single 32-Bit Timer can trigger a DMA data transfer.
• Single 32-Bit Synchronous Counter
They also support these features:
• Timer Gate Operation
• Selectable Prescaler Settings
• Timer Operation during Idle and Sleep modes
• Interrupt on a 32-Bit Period Register Match
• Time Base for Input Capture and Output Compare
Modules
• ADC1 Event Trigger (Timer2/3 only)

FIGURE 13-1: TYPE B TIMER BLOCK DIAGRAM (x = 2 AND 4)
Gate Falling Edge

1
Sync Detect
Set TxIF Flag
FP(1) Prescaler 10
TxCLK
(/n) TGATE
Reset Data
00 TMRx Latch
TCKPS<1:0>
CLK
TxCK
Prescaler
Sync x1
(/n) Equal
Comparator
TCKPS<1:0> TGATE
TCS
PRx
FIGURE 13-2: TYPE C TIMER BLOCK DIAGRAM (x = 3 AND 5)
Gate Falling Edge

1
Sync Detect
Set TxIF Flag
FP(1) Prescaler 10
TxCLK
(/n) TGATE
Reset Data
00 TMRx Latch
TCKPS<1:0>
CLK
TxCK
Prescaler
Sync x1
(/n) Equal
Comparator
ADC Start of
Conversion
TGATE Trigger(2)
TCKPS<1:0>
TCS
PRx

2: The ADC trigger is available on TMR3 and TMR5 only.

FIGURE 13-3: TYPE B/TYPE C TIMER PAIR BLOCK DIAGRAM (32-BIT TIMER)
Gate Falling Edge

1
Sync Detect
Set TyIF Flag
PRx PRy
0
TGATE
Equal ADC(4)
Comparator
Data
FP(1) Prescaler 10
(/n) CLK
lsw msw Latch
Reset
TCKPS<1:0>
00 TMRx(2) TMRy(3)
TxCK
Prescaler
Sync x1
(/n)
TMRyHLD
TCKPS<1:0> TGATE
TCS
Data Bus<15:0>

2: Timerx is a Type B timer (x = 2 and 4).
3: Timery is a Type C timer (y = 3 and 5).
4: The ADC trigger is available only on the TMR3:TMR2 and TMR5:TMR4 32-bit timer pairs.

13.1 Timer2/3 and Timer4/5 Control

Registers
REGISTER 13-1: TxCON (T2CON AND T4CON) CONTROL REGISTER

R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
TON — TSIDL — — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0

(1)
— TGATE TCKPS1 TCKPS0 T32 — TCS —
bit 7 bit 0
Legend:
bit 15 TON: Timerx On bit

When T32 = 1:
1 = Starts 32-bit Timerx/y
0 = Stops 32-bit Timerx/y
When T32 = 0:
1 = Starts 16-bit Timerx
0 = Stops 16-bit Timerx
bit 13 TSIDL: Timerx Stop in Idle Mode bit
bit 6 TGATE: Timerx Gated Time Accumulation Enable bit
When TCS = 1:
When TCS = 0:
bit 5-4 TCKPS<1:0>: Timerx Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3 T32: 32-Bit Timer Mode Select bit
1 = Timerx and Timery form a single 32-bit timer
0 = Timerx and Timery act as two 16-bit timers
bit 1 TCS: Timerx Clock Source Select bit(1)
1 = External clock is from pin, TxCK (on the rising edge)
Note 1: The TxCK pin is not available on all timers. Refer to the “Pin Diagrams” section for the available pins.

REGISTER 13-2: TyCON (T3CON AND T5CON) CONTROL REGISTER

R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
TON(1) — TSIDL(2) — — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0

— TGATE(1) TCKPS1(1) TCKPS0(1) — — TCS(1,3) —
bit 7 bit 0
Legend:
bit 15 TON: Timery On bit(1)

1 = Starts 16-bit Timery
0 = Stops 16-bit Timery
bit 13 TSIDL: Timery Stop in Idle Mode bit(2)
1 = Discontinues module operation when the device enters an Idle mode
0 = Continues module operation in an Idle mode
bit 6 TGATE: Timery Gated Time Accumulation Enable bit(1)
When TCS = 1:
When TCS = 0:
bit 5-4 TCKPS<1:0>: Timery Input Clock Prescale Select bits(1)
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 1 TCS: Timery Clock Source Select bit(1,3)
1 = External clock is from pin, TyCK (on the rising edge)
Note 1: When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timery operation; all timer
functions are set through TxCON.
2: When 32-bit timer operation is enabled (T32 = 1) in the Timerx Control register (TxCON<3>), the TSIDL
bit must be cleared to operate the 32-bit timer in Idle mode.
3: The TyCK pin is not available on all timers. See the “Pin Diagrams” section for the available pins.

NOTES:

14.0 DEADMAN TIMER (DMT) The primary function of the Deadman Timer (DMT) is to
reset the processor in the event of a software malfunc-
Note 1: This data sheet summarizes the features tion. The DMT, which works on the system clock, is a
of the dsPIC33EVXXXGM00X/10X family free-running instruction fetch timer, which is clocked
of devices. It is not intended to be a whenever an instruction fetch occurs, until a count
comprehensive reference source. To match occurs. Instructions are not fetched when the
complement the information in this processor is in Sleep mode.
data sheet, refer to “Deadman Timer DMT can be enabled in the Configuration fuse or by
(DMT)” (DS70005155) in the “dsPIC33/ software in the DMTCON register by setting the ON bit.
PIC24 Family Reference Manual”, which The DMT consists of a 32-bit counter with a time-out
is available from the Microchip web site count match value, as specified by the two 16-bit
(www.microchip.com). Configuration Fuse registers: FDMTCNTL and
2: Some registers and associated bits FDMTCNTH.
described in this section may not be A DMT is typically used in mission-critical, and safety-
available on all devices. Refer to critical applications, where any single failure of the
Section 4.0 “Memory Organization” in software functionality and sequencing must be
this data sheet for device-specific register detected.
Figure 14-1 shows a block diagram of the Deadman
Timer module.
FIGURE 14-1: DEADMAN TIMER BLOCK DIAGRAM
BAD1
BAD2 Improper Sequence
Flag
DMT Enable(1)
32-Bit Counter (Counter) = DMT Max Count(1) DMT Event
Instruction Fetched Strobe(2)
System Clock
Note 1: DMT Max Count is controlled by the initial value of the FDMTCNTL and FDMTCNTH Configuration registers.
2: DMT window interval is controlled by the value of the FDMTINTVL and FDMTINTVH Configuration registers.

14.1 Deadman Timer Control Registers

REGISTER 14-1: DMTCON: DEADMAN TIMER CONTROL REGISTER
R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
ON(1) — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 7 bit 0
Legend:
bit 15 ON: DMT Module Enable bit(1)

1 = Deadman Timer module is enabled
0 = Deadman Timer module is not enabled
Note 1: This bit has control only when DMTEN = 0 in the FDMT register.
REGISTER 14-2: DMTPRECLR: DEADMAN TIMER PRECLEAR REGISTER

STEP1<7:0>
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 7 bit 0
Legend:
bit 15-8 STEP1<7:0>: DMT Preclear Enable bits

01000000 = Enables the Deadman Timer preclear (Step 1)
All Other
Write Patterns = Sets the BAD1 flag; these bits are cleared when a DMT Reset event occurs.
STEP1<7:0> bits are also cleared if the STEP2<7:0> bits are loaded with the correct
value in the correct sequence.

REGISTER 14-3: DMTCLR: DEADMAN TIMER CLEAR REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

STEP2<7:0>
bit 7 bit 0
Legend:

bit 7-0 STEP2<7:0>: DMT Clear Timer bits
00001000 = Clears STEP1<7:0>, STEP2<7:0> and the Deadman Timer if preceded by the correct
loading of the STEP1<7:0> bits in the correct sequence. The write to these bits may be
verified by reading the DMTCNTL/H register and observing the counter being reset.
All Other
Write Patterns = Sets the BAD2 bit; the value of STEP1<7:0> will remain unchanged and the new
value being written to STEP2<7:0> will be captured. These bits are cleared when a
DMT Reset event occurs.

REGISTER 14-4: DMTSTAT: DEADMAN TIMER STATUS REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
R-0, HC R-0, HC R-0, HC U-0 U-0 U-0 U-0 R-0

BAD1 BAD2 DMTEVENT — — — — WINOPN
bit 7 bit 0


bit 7 BAD1: Deadman Timer Bad STEP1<7:0> Value Detect bit
1 = Incorrect STEP1<7:0> value was detected
0 = Incorrect STEP1<7:0> value was not detected
bit 6 BAD2: Deadman Timer Bad STEP2<7:0> Value Detect bit
1 = Incorrect STEP2<7:0> value was detected
0 = Incorrect STEP2<7:0> value was not detected
bit 5 DMTEVENT: Deadman Timer Event bit
1 = Deadman Timer event was detected (counter expired, or bad STEP1<7:0> or STEP2<7:0> value
was entered prior to counter increment)
0 = Deadman Timer event was not detected
bit 0 WINOPN: Deadman Timer Clear Window bit
1 = Deadman Timer clear window is open
0 = Deadman Timer clear window is not open

REGISTER 14-5: DMTCNTL: DEADMAN TIMER COUNT REGISTER LOW

COUNTER<15:8>
bit 15 bit 8

COUNTER<7:0>
bit 7 bit 0
Legend:
bit 15-0 COUNTER<15:0>: Read Current Contents of Lower DMT Counter bits
REGISTER 14-6: DMTCNTH: DEADMAN TIMER COUNT REGISTER HIGH

COUNTER<31:24>
bit 15 bit 8

COUNTER<23:16>
bit 7 bit 0
Legend:
bit 15-0 COUNTER<31:16>: Read Current Contents of Higher DMT Counter bits

REGISTER 14-7: DMTPSCNTL: DMT POST CONFIGURE COUNT STATUS REGISTER LOW
PSCNT<15:8>
bit 15 bit 8

PSCNT<7:0>
bit 7 bit 0
Legend:
bit 15-0 PSCNT<15:0>: Lower DMT Instruction Count Value Configuration Status bits
This is always the value of the FDMTCNTL Configuration register.
REGISTER 14-8: DMTPSCNTH: DMT POST CONFIGURE COUNT STATUS REGISTER HIGH
PSCNT<31:24>
bit 15 bit 8

PSCNT<23:16>
bit 7 bit 0
Legend:
bit 15-0 PSCNT<31:16>: Higher DMT Instruction Count Value Configuration Status bits
This is always the value of the FDMTCNTH Configuration register.

REGISTER 14-9: DMTPSINTVL: DMT POST CONFIGURE INTERVAL STATUS REGISTER LOW
PSINTV<15:8>
bit 15 bit 8

PSINTV<7:0>
bit 7 bit 0
Legend:
bit 15-0 PSINTV<15:0>: Lower DMT Window Interval Configuration Status bits
This is always the value of the FDMTINTVL Configuration register.
REGISTER 14-10: DMTPSINTVH: DMT POST CONFIGURE INTERVAL STATUS REGISTER HIGH
PSINTV<31:24>
bit 15 bit 8

PSINTV<23:16>
bit 7 bit 0
Legend:
bit 15-0 PSINTV<31:16>: Higher DMT Window Interval Configuration Status bits
This is always the value of the FDMTINTVH Configuration register.

REGISTER 14-11: DMTHOLDREG: DMT HOLD REGISTER(1)

UPRCNT<15:8>
bit 15 bit 8

UPRCNT<7:0>
bit 7 bit 0
Legend:
bit 15-0 UPRCNT<15:0>: Value of the DMTCNTH register when DMTCNTL and DMTCNTH were Last Read bits
Note 1: The DMTHOLDREG register is initialized to ‘0’ on Reset, and is only loaded when the DMTCNTL and
DMTCNTH registers are read.

15.0 INPUT CAPTURE The input capture module is useful in applications

requiring frequency (period) and pulse measurement.
Note 1: This data sheet summarizes the features of The dsPIC33EVXXXGM00X/10X family devices support
the dsPIC33EVXXXGM00X/10X family of 4 input capture channels.
devices. It is not intended to be a Key features of the input capture module include:
comprehensive reference source. To com-
plement the information in this data sheet, • Hardware-Configurable for 32-Bit Operation in All
refer to “Input Capture” (DS70000352) in Modes by Cascading Two Adjacent modules
the “dsPIC33/PIC24 Family Reference • Synchronous and Trigger Modes of Output
Manual”, which is available from the Compare Operation, with up to 31 User-Selectable
Microchip web site (www.microchip.com). Trigger/Sync Sources Available
2: Some registers and associated bits • A 4-Level FIFO Buffer for Capturing and Holding
described in this section may not be Timer Values for Several Events
available on all devices. Refer to • Configurable Interrupt Generation
Section 4.0 “Memory Organization” in • Up to Six Clock Sources Available for Each
this data sheet for device-specific register Module, Driving a Separate Internal 16-Bit Counter
Figure 15-1 shows a block diagram of the Input capture
module.
FIGURE 15-1: INPUT CAPTURE x MODULE BLOCK DIAGRAM
ICM<2:0> CTMU Edge

ICI<1:0>
Control Logic
Prescaler Edge Detect Logic Event and Set ICxIF

Counter and Interrupt
1:1/4/16 Clock Synchronizer Logic
ICx Pin
ICTSEL<2:0>
Increment
16
ICx Clock Clock
ICxTMR 4-Level FIFO Buffer
Sources Select 16
Trigger and Trigger and Reset 16

Sync Sources Sync Logic ICxBUF
SYNCSEL<4:0>
Trigger(1)
ICOV, ICBNE System Bus
Note 1: The trigger/sync source is enabled by default and is set to Timer3 as a source. This timer must be enabled for
proper ICx module operation or the trigger/sync source must be changed to another source option.

15.1 Input Capture Control Registers
REGISTER 15-1: ICxCON1: INPUT CAPTURE x CONTROL REGISTER 1

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0
— — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R-0, HC, HS R-0, HC, HS R/W-0 R/W-0 R/W-0
— ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0
bit 7 bit 0
Legend: HC = Hardware Clearable bit HS = Hardware Settable bit


bit 13 ICSIDL: Input Capture x Stop in Idle Mode Control bit
1 = Input Capture x will halt in CPU Idle mode
0 = Input Capture x will continue to operate in CPU Idle mode
bit 12-10 ICTSEL<2:0>: Input Capture x Timer Select bits
111 = Peripheral clock (FP) is the clock source of the ICx
110 = Reserved
101 = Reserved
100 = T1CLK is the clock source of the ICx (only the synchronous clock is supported)
011 = T5CLK is the clock source of the ICx
bit 6-5 ICI<1:0>: Number of Captures per Interrupt Select bits (this field is not used if ICM<2:0> = 001 or 111)
11 = Interrupt on every fourth capture event
10 = Interrupt on every third capture event
01 = Interrupt on every second capture event
00 = Interrupt on every capture event
bit 4 ICOV: Input Capture x Overflow Status Flag bit (read-only)
1 = Input Capture x buffer overflow has occurred
0 = Input Capture x buffer overflow has not occurred
bit 3 ICBNE: Input Capture x Buffer Not Empty Status bit (read-only)
1 = Input Capture x buffer is not empty, at least one more capture value can be read
0 = Input Capture x buffer is empty
bit 2-0 ICM<2:0>: Input Capture x Mode Select bits
111 = Input Capture x functions as an interrupt pin only in CPU Sleep and Idle modes (rising edge
detect only, all other control bits are not applicable)
110 = Unused (module is disabled)
101 = Capture mode, every 16th rising edge (Prescaler Capture mode)
100 = Capture mode, every 4th rising edge (Prescaler Capture mode)
011 = Capture mode, every rising edge (Simple Capture mode)
010 = Capture mode, every falling edge (Simple Capture mode)
001 = Capture mode, every edge, rising and falling (Edge Detect mode (ICI<1:0>) is not used in this
mode)
000 = Input Capture x module is turned off

REGISTER 15-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — IC32(1)
bit 15 bit 8
R/W-0 R/W-0, HS U-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-1

ICTRIG(2) TRIGSTAT(3) — SYNCSEL4(4) SYNCSEL3(4) SYNCSEL2(4) SYNCSEL1(4) SYNCSEL0(4)
bit 7 bit 0
Legend: HS = Hardware Settable bit


bit 8 IC32: Input Capture x 32-Bit Timer Mode Select bit (Cascade mode)(1)
1 = Odd ICx and even ICx form a single 32-bit input capture module
0 = Cascade module operation is disabled
bit 7 ICTRIG: Input Capture x Trigger Operation Select bit(2)
1 = Input source is used to trigger the input capture timer (Trigger mode)
0 = Input source is used to synchronize the input capture timer to the timer of another module
(Synchronization mode)
bit 6 TRIGSTAT: Timer Trigger Status bit(3)
1 = ICxTMR has been triggered and is running
0 = ICxTMR has not been triggered and is being held clear
Note 1: The IC32 bit in both the odd and even ICx must be set to enable Cascade mode.
2: The input source is selected by the SYNCSEL<4:0> bits of the ICxCON2 register.
3: This bit is set by the selected input source (selected by the SYNCSEL<4:0> bits); it can be read, set and
cleared in software.
4: Do not use the ICx module as its own sync or trigger source.
5: This option should only be selected as a trigger source and not as a synchronization source.
6: When the source ICx timer rolls over, then in the next clock cycle, trigger or synchronization occurs.

REGISTER 15-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2 (CONTINUED)

bit 4-0 SYNCSEL<4:0>: Input Source Select for Synchronization and Trigger Operation bits(4)
11111 = Reserved
11110 = Reserved
11101 = Reserved
11100 = CTMU trigger is the source for the capture timer synchronization
11011 = ADC1 interrupt is the source for the capture timer synchronization(5)
11010 = Analog Comparator 3 is the source for the capture timer synchronization(5)
10101 = Reserved
10100 = Reserved
10011 = Input Capture 4 interrupt is the source for the capture timer synchronization
01111 = GP Timer5 is the source for the capture timer synchronization
01010 = Reserved
01001 = Reserved
01000 = Input Capture 4 is the source for the capture timer synchronization(6)
00100 = Output Compare 4 is the source for the capture timer synchronization
00000 = Reserved
Note 1: The IC32 bit in both the odd and even ICx must be set to enable Cascade mode.
2: The input source is selected by the SYNCSEL<4:0> bits of the ICxCON2 register.
3: This bit is set by the selected input source (selected by the SYNCSEL<4:0> bits); it can be read, set and
cleared in software.
4: Do not use the ICx module as its own sync or trigger source.
5: This option should only be selected as a trigger source and not as a synchronization source.
6: When the source ICx timer rolls over, then in the next clock cycle, trigger or synchronization occurs.

16.0 OUTPUT COMPARE sources for its time base. The module compares the
value of the timer with the value of one or two Compare
Note 1: This data sheet summarizes the features registers, depending on the operating mode selected.
of the dsPIC33EVXXXGM00X/10X family The state of the output pin changes when the timer
of devices. It is not intended to be a value matches the Compare register value. The output
comprehensive reference source. To compare module generates either a single output
complement the information in this data pulse, or a sequence of output pulses, by changing the
sheet, refer to “Output Compare” state of the output pin on the compare match events.
(DS70005157) in the “dsPIC33/PIC24 The output compare module can also generate
Family Reference Manual”, which is interrupts on compare match events and trigger DMA
available from the Microchip web site data transfers.
(www.microchip.com).
Figure 16-1 shows a block diagram of the output
2: Some registers and associated bits compare module.
available on all devices. Refer to Note: For more information on OCxR and
Section 4.0 “Memory Organization” in OCxRS register restrictions, refer to the
this data sheet for device-specific register “Output Compare” (DS70005157)
and bit information. section in the “dsPIC33/PIC24 Family
Reference Manual”.
support up to 4 output compare modules. The output
compare module can select one of eight available clock
FIGURE 16-1: OUTPUT COMPARE x MODULE BLOCK DIAGRAM
OCxCON1
OCxCON2
OCxR
CTMU Edge
Rollover/Reset Control Logic
OCxR Buffer
OCx Pin
Comparator
Increment Match
OCx Clock Clock Event
Sources Select
OCxTMR OCx Output and
Rollover Fault Logic
Reset
Comparator OCFA
Match Event Match
Trigger and Event
Trigger and
Sync Sources Sync Logic
OCxRS Buffer
SYNCSEL<4:0> Rollover/Reset
Trigger(1)
OCx Synchronization/Trigger Event
OCxRS
OCx Interrupt
Reset
Note 1: The trigger/sync source is enabled by default and is set to Timer2 as a source. This timer must be enabled for
proper OCx module operation or the trigger/sync source must be changed to another source option.

16.1 Output Compare Control Registers
REGISTER 16-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0
— — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 — —
bit 15 bit 8
R/W-0 U-0 U-0 R/W-0, HSC R/W-0 R/W-0 R/W-0 R/W-0

ENFLTA — — OCFLTA TRIGMODE OCM2 OCM1 OCM0
bit 7 bit 0
Legend: HSC = Hardware Settable/Clearable bit


bit 13 OCSIDL: Output Compare x Stop in Idle Mode Control bit
1 = Output Compare x halts in CPU Idle mode
0 = Output Compare x continues to operate in CPU Idle mode
bit 12-10 OCTSEL<2:0>: Output Compare x Clock Select bits
111 = Peripheral clock (FP)
110 = Reserved
101 = Reserved
100 = T1CLK is the clock source of the OCx (only the synchronous clock is supported)
011 = T5CLK is the clock source of the OCx
bit 7 ENFLTA: Output Compare x Fault A Input Enable bit
1 = Output Compare Fault A (OCFA) input is enabled
0 = Output Compare Fault A (OCFA) input is disabled
bit 4 OCFLTA: PWM Fault A Condition Status bit
1 = PWM Fault A condition on the OCFA pin has occurred
0 = PWM Fault A condition on the OCFA pin has not occurred
bit 3 TRIGMODE: Trigger Status Mode Select bit
1 = TRIGSTAT (OCxCON2<6>) is cleared when OCxRS = OCxTMR or in software
0 = TRIGSTAT is cleared only by software
Note 1: OCxR and OCxRS are double-buffered in PWM mode only.

REGISTER 16-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 (CONTINUED)

bit 2-0 OCM<2:0>: Output Compare x Mode Select bits
111 = Center-Aligned PWM mode: Output sets high when OCxTMR = OCxR and sets low when
OCxTMR = OCxRS(1)
110 = Edge-Aligned PWM mode: Output sets high when OCxTMR = 0 and sets low when
OCxTMR = OCxR(1)
101 = Double Compare Continuous Pulse mode: Initializes OCx pin low, toggles OCx state continuously
on alternate matches of OCxR and OCxRS
100 = Double Compare Single-Shot mode: Initializes OCx pin low, toggles OCx state on matches of
OCxR and OCxRS for one cycle
011 = Single Compare mode: Compare event with OCxR, continuously toggles OCx pin
010 = Single Compare Single-Shot mode: Initializes OCx pin high, compare event with OCxR, forces
OCx pin low
001 = Single Compare Single-Shot mode: Initializes OCx pin low, compare event with OCxR, forces
OCx pin high
000 = Output compare channel is disabled
Note 1: OCxR and OCxRS are double-buffered in PWM mode only.

REGISTER 16-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2

R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0
FLTMD FLTOUT FLTTRIEN OCINV — — — OC32
bit 15 bit 8
R/W-0 R/W-0, HS R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0

OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
bit 7 bit 0
Legend: HS = Hardware Settable bit

bit 15 FLTMD: Fault Mode Select bit

1 = Fault mode is maintained until the Fault source is removed; the OCFLTA bit is cleared in software
and a new PWM period starts
0 = Fault mode is maintained until the Fault source is removed and a new PWM period starts
bit 14 FLTOUT: Fault Out bit
1 = PWM output is driven high on a Fault
0 = PWM output is driven low on a Fault
bit 13 FLTTRIEN: Fault Output State Select bit
1 = OCx pin is tri-stated on a Fault condition
0 = OCx pin I/O state is defined by the FLTOUT bit on a Fault condition
bit 12 OCINV: Output Compare x Invert bit
1 = OCx output is inverted
0 = OCx output is not inverted
bit 8 OC32: Cascade Two OCx Modules Enable bit (32-bit operation)
1 = Cascade module operation is enabled
0 = Cascade module operation is disabled
bit 7 OCTRIG: Output Compare x Trigger/Sync Select bit
1 = Triggers OCx from the source designated by the SYNCSELx bits
0 = Synchronizes OCx with the source designated by the SYNCSELx bits
bit 6 TRIGSTAT: Timer Trigger Status bit
1 = Timer source has been triggered and is running
0 = Timer source has not been triggered and is being held clear
bit 5 OCTRIS: Output Compare x Output Pin Direction Select bit
1 = Output Compare x is tri-stated
0 = Output Compare x module drives the OCx pin
Note 1: Do not use the OCx module as its own synchronization or trigger source.
2: When the OCy module is turned off, it sends a trigger out signal. If the OCx module uses the OCy module
as a trigger source, the OCy module must be unselected as a trigger source prior to disabling it.

REGISTER 16-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 (CONTINUED)

bit 4-0 SYNCSEL<4:0>: Trigger/Synchronization Source Selection bits
11111 = OCxRS compare event is used for synchronization
11110 = INT2 is the source for compare timer synchronization
11101 = INT1 is the source for compare timer synchronization
11100 = CTMU Trigger is the source for compare timer synchronization
11011 = ADC1 interrupt is the source for compare timer synchronization
11010 = Analog Comparator 3 is the source for compare timer synchronization
10101 = Capture timer is unsynchronized
10011 = Input Capture 4 interrupt is the source for compare timer synchronization
01111 = GP Timer5 is the source for compare timer synchronization
01010 = Compare timer is unsynchronized
00100 = Output Compare 4 is the source for compare timer synchronization(1,2)
Note 1: Do not use the OCx module as its own synchronization or trigger source.
2: When the OCy module is turned off, it sends a trigger out signal. If the OCx module uses the OCy module
as a trigger source, the OCy module must be unselected as a trigger source prior to disabling it.

NOTES:

17.0 HIGH-SPEED PWM MODULE The high-speed PWMx module contains up to three
PWM generators. Each PWM generator provides two
Note 1: This data sheet summarizes the features of PWM outputs: PWMxH and PWMxL. The master time
the dsPIC33EVXXXGM00X/10X family base generator provides a synchronous signal as a
of devices. It is not intended to be a common time base to synchronize the various PWM
comprehensive reference source. To com- outputs. The individual PWM outputs are available on
plement the information in this data sheet, the output pins of the device. The input Fault signals
refer to “High-Speed PWM” (DS70645) in and current-limit signals, when enabled, can monitor
the “dsPIC33/PIC24 Family Reference and protect the system by placing the PWM outputs
Manual”, which is available from the into a known “safe” state.
Microchip web site (www.microchip.com). Each PWMx can generate a trigger to the ADC module
2: Some registers and associated bits to sample the analog signal at a specific instance
described in this section may not be during the PWM period. In addition, the high-speed
available on all devices. Refer to PWMx module also generates a Special Event Trigger
Section 4.0 “Memory Organization” in to the ADC module based on the master time base.
this data sheet for device-specific register The high-speed PWMx module can synchronize itself
and bit information. with an external signal or can act as a synchronizing
The dsPIC33EVXXXGM00X/10X family devices source to any external device. The SYNCI1 input pin,
support a dedicated Pulse-Width Modulation (PWM) that utilizes PPS, can synchronize the high-speed
module with up to 6 outputs. PWMx module with an external signal. The SYNCO1
pin is an output pin that provides a synchronous signal
The high-speed PWMx module consists of the to an external device.
following major features:
Figure 17-1 illustrates an architectural overview of the
• Three PWM Generators high-speed PWMx module and its interconnection with
• Two PWM Outputs per PWM Generator the CPU and other peripherals.
• Individual Period and Duty Cycle for each PWM Pair
• Duty Cycle, Dead Time, Phase Shift and 17.1 PWM Faults
Frequency Resolution of 8.32 ns
The PWMx module incorporates multiple external Fault
• Independent Fault and Current-Limit Inputs for inputs as follows:
Six PWM Outputs
• FLT1 and FLT2, available on 28-pin, 44-pin and
• Redundant Output
64-pin packages, which are remappable using the
• Center-Aligned PWM mode PPS feature
• Output Override Control • FLT3, available on 44-pin and 64-pin packages,
• Chop mode (also known as Gated mode) which is available as a fixed pin
• Special Event Trigger • FLT4-FLT8, available on 64-pin packages, which
• Prescaler for Input Clock are available as fixed pins
• PWMxL and PWMxH Output Pin Swapping • FLT32 is available on a fixed pin on all devices
• Independent PWM Frequency, Duty Cycle and These Faults provide a safe and reliable way to safely
Phase-Shift Changes for each PWM Generator shut down the PWM outputs when the Fault input is
• Dead-Time Compensation asserted.
• Enhanced Leading-Edge Blanking (LEB)
Functionality 17.1.1 PWM FAULTS AT RESET
• Frequency Resolution Enhancement During any Reset event, the PWMx module maintains
• PWM Capture Functionality ownership of the Class B Fault, FLT32. At Reset, this
Fault is enabled in Latched mode to ensure the fail-safe
Note: In Edge-Aligned PWM mode, the duty power-up of the application. The application software
cycle, dead time, phase shift and frequency must clear the PWM Fault before enabling the high-
resolution are 8.32 ns at 60 MIPS. speed motor control PWMx module. To clear the Fault
condition, the FLT32 pin must first be pulled low
externally or the internal pull-down resistor in the
CNPDx register can be enabled.
Note: The Fault mode may be changed using
the FLTMOD<1:0> bits (FCLCONx<1:0>),
regardless of the state of FLT32.

17.1.2 WRITE-PROTECTED REGISTERS To gain write access to these locked registers, the user
application must write two consecutive values (0xABCD
On dsPIC33EVXXXGM00X/10X family devices, write
and 0x4321) to the PWMKEY register to perform the
protection is implemented for the IOCONx and
unlock operation. The write access to the IOCONx or
FCLCONx registers. The write protection feature
FCLCONx registers must be the next SFR access
prevents any inadvertent writes to these registers.
following the unlock process. There can be no other SFR
This protection feature can be controlled by the
accesses during the unlock process and subsequent
PWMLOCK Configuration bit (FDEVOPT<0>). The
write access. To write to both the IOCONx and
default state of the write protection feature is enabled
FCLCONx registers requires two unlock operations.
(PWMLOCK = 1). The write protection feature can be
disabled by configuring PWMLOCK = 0. The correct unlocking sequence is described in
Example 17-1.
EXAMPLE 17-1: PWM1 WRITE-PROTECTED REGISTER UNLOCK SEQUENCE

; FLT32 pin must be pulled low externally in order to clear and disable the fault
; Writing to FCLCON1 register requires unlock sequence
mov #0xabcd, w10 ; Load first unlock key to w10 register

mov #0x4321, w11 ; Load second unlock key to w11 register
mov #0x0000, w0 ; Load desired value of FCLCON1 register in w0
mov w10, PWMKEY ; Write first unlock key to PWMKEY register
mov w11, PWMKEY ; Write second unlock key to PWMKEY register
mov w0, FCLCON1 ; Write desired value to FCLCON1 register
; Set PWM ownership and polarity using the IOCON1 register

; Writing to IOCON1 register requires unlock sequence
mov #0xabcd, w10 ; Load first unlock key to w10 register

mov #0x4321, w11 ; Load second unlock key to w11 register
mov #0xF000, w0 ; Load desired value of IOCON1 register in w0
mov w10, PWMKEY ; Write first unlock key to PWMKEY register
mov w11, PWMKEY ; Write second unlock key to PWMKEY register
mov w0, IOCON1 ; Write desired value to IOCON1 register

FIGURE 17-1: HIGH-SPEED PWMx MODULE ARCHITECTURAL OVERVIEW
SYNCI1
Data Bus
FOSC Master Time Base
SYNCO1
Synchronization Signal
PWM1 Interrupt(1)
PWM1H
PWM
Generator 1
PWM1L
Fault, Current-Limit
and Dead-Time Compensation
PWM2 Interrupt(1) PWM2H

CPU
PWM
Generator 2
PWM2L
Fault, Current-Limit
and Dead-Time Compensation
PWM3 Interrupt(1) PWM3H

PWM
Generator 3
PWM3L
Primary Trigger
Fault, Current-Limit and
Dead-Time Compensation
ADC Module Primary Special FLT1-FLT8, FLT32
Event Trigger
DTCMP1-DTCMP3
Note 1: The PWM interrupts are generated by logically ORing the FLTSTAT, CLSTAT and TRGSTAT status bits for the
given PWM generator. For more information, refer to “High-Speed PWM” (DS70645) in the “dsPIC33/PIC24
Family Reference Manual”.

FIGURE 17-2: HIGH-SPEED PWMx MODULE REGISTER INTERCONNECTION DIAGRAM
FOSC
PTCON, PTCON2 Module Control and Timing
SYNCI1
PWMKEY IOCONx and FCLCONx Unlock Register
SYNCO1
PTPER SEVTCMP Special Event Compare Trigger
Special Event
Comparator Comparator Postscaler
Special Event Trigger
Master Time Base Counter
Clock
PMTMR Prescaler Primary Master Time Base
MDC Master Duty Cycle Register

Synchronization
Master Duty Cycle
PDCx PWM Generator 1
MUX
16-Bit Data Bus
PWM Output Mode

Master Period
Comparator Control Logic
User Override Logic

ADC Trigger Dead-Time Pin PWM1H
Current-Limit Logic Control
Override Logic Logic PWM1L
PTMRx Comparator
Fault Override Logic
PHASEx TRIGx
Interrupt Fault and FLTx

Logic(1) Current-Limit
Logic DTCMP1
FCLCONx
Synchronization
IOCONx ALTDTRx
PWMCONx,
LEBCONx,
AUXCONx
Master Duty Cycle
TRGCONx LEBDLYx
Master Period
DTRx
PWMxH
PWMxL
PWM Generator 2 and PWM Generator 3
FLTx
DTCMPx
Note 1: The PWM interrupts are generated by logically ORing the FLTSTAT, CLSTAT and TRGSTAT status bits for the
given PWM generator. For more information, refer to, “High-Speed PWM” (DS70645) in the “dsPIC33/PIC24
Family Reference Manual”.

17.2 PWM Resources 17.2.1 KEY RESOURCES

Many useful resources are provided on the main • “High-Speed PWM” (DS70645) in the “dsPIC33/
product page on the Microchip web site PIC24 Family Reference Manual”
(www.microchip.com) for the devices listed in this data • Code Samples
sheet. This product page contains the latest updates • Application Notes
and additional information. • Software Libraries
Note: In case the above link is not accessible, • Webinars
enter this URL in your browser: • All Related “dsPIC33/PIC24 Family Reference
http://www.microchip.com/wwwproducts/ Manual” Sections
Devices.aspx?dDocName=en555464 • Development Tools

17.3 PWMx Control Registers

REGISTER 17-1: PTCON: PWMx TIME BASE CONTROL REGISTER
R/W-0 U-0 R/W-0 HS-0, HC R/W-0 R/W-0 R/W-0 R/W-0
PTEN — PTSIDL SESTAT SEIEN EIPU(1) SYNCPOL(1) SYNCOEN(1)
bit 15 bit 8

SYNCEN(1) SYNCSRC2(1) SYNCSRC1(1) SYNCSRC0(1) SEVTPS3(1) SEVTPS2(1) SEVTPS1(1) SEVTPS0(1)
bit 7 bit 0

bit 15 PTEN: PWMx Module Enable bit

1 = PWMx module is enabled
0 = PWMx module is disabled
bit 13 PTSIDL: PWMx Time Base Stop in Idle Mode bit
1 = PWMx time base halts in CPU Idle mode
0 = PWMx time base runs in CPU Idle mode
bit 12 SESTAT: Special Event Interrupt Status bit
1 = Special event interrupt is pending
0 = Special event interrupt is not pending
bit 11 SEIEN: Special Event Interrupt Enable bit
1 = Special event interrupt is enabled
0 = Special event interrupt is disabled
bit 10 EIPU: Enable Immediate Period Updates bit(1)
1 = Active Period register is updated immediately
0 = Active Period register updates occur on PWMx cycle boundaries
bit 9 SYNCPOL: Synchronize Input and Output Polarity bit(1)
1 = SYNCI1/SYNCO1 polarity is inverted (active-low)
0 = SYNCI1/SYNCO1 is active-high
bit 8 SYNCOEN: Primary Time Base Sync Enable bit(1)
1 = SYNCO1 output is enabled
0 = SYNCO1 output is disabled
bit 7 SYNCEN: External Time Base Synchronization Enable bit(1)
1 = External synchronization of primary time base is enabled
0 = External synchronization of primary time base is disabled
Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCI1 feature, the user
application must program the Period register with a value that is slightly larger than the expected period of
the external synchronization input signal.

REGISTER 17-1: PTCON: PWMx TIME BASE CONTROL REGISTER (CONTINUED)

bit 6-4 SYNCSRC<2:0>: Synchronous Source Selection bits(1)
111 = Reserved
•
•
•
100 = Reserved
011 = Reserved
010 = Reserved
001 = Reserved
000 = SYNCI1 input from PPS
bit 3-0 SEVTPS<3:0>: Special Event Trigger Output Postscaler Select bits(1)
1111 = 1:16 postscaler generates a Special Event Trigger on every sixteenth compare match event
•
•
•
0001 = 1:2 postscaler generates a Special Event Trigger on every second compare match event
0000 = 1:1 postscaler generates a Special Event Trigger on every compare match event
Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCI1 feature, the user
application must program the Period register with a value that is slightly larger than the expected period of
the external synchronization input signal.
REGISTER 17-2: PTCON2: PWMx PRIMARY MASTER CLOCK DIVIDER SELECT REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — PCLKDIV<2:0>(1)
bit 7 bit 0
Legend:

bit 2-0 PCLKDIV<2:0>: PWMx Input Clock Prescaler (Divider) Select bits(1)
111 = Reserved
110 = Divide-by-64
101 = Divide-by-32
100 = Divide-by-16
011 = Divide-by-8
010 = Divide-by-4
001 = Divide-by-2
000 = Divide-by-1, maximum PWMx timing resolution (power-on default)
Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.

REGISTER 17-3: PTPER: PWMx PRIMARY MASTER TIME BASE PERIOD REGISTER
PTPER<15:8>
bit 15 bit 8

PTPER<7:0>
bit 7 bit 0
Legend:
bit 15-0 PTPER<15:0>: Primary Master Time Base (PMTMR) Period Value bits
REGISTER 17-4: SEVTCMP: PWMx PRIMARY SPECIAL EVENT COMPARE REGISTER

SEVTCMP<15:8>
bit 15 bit 8

SEVTCMP<7:0>
bit 7 bit 0
Legend:
bit 15-0 SEVTCMP<15:0>: Special Event Compare Count Value bits

REGISTER 17-5: CHOP: PWMx CHOP CLOCK GENERATOR REGISTER

R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
CHPCLKEN — — — — — CHOPCLK9 CHOPCLK8
bit 15 bit 8

CHOPCLK7 CHOPCLK6 CHOPCLK5 CHOPCLK4 CHOPCLK3 CHOPCLK2 CHOPCLK1 CHOPCLK0
bit 7 bit 0
Legend:
bit 15 CHPCLKEN: Enable Chop Clock Generator bit

1 = Chop clock generator is enabled
0 = Chop clock generator is disabled
bit 9-0 CHOPCLK<9:0>: Chop Clock Divider bits
The frequency of the chop clock signal is given by the following expression:
Chop Frequency = (FP/PCLKDIV<2:0>)/(CHOPCLK<9:0> + 1)
REGISTER 17-6: MDC: PWMx MASTER DUTY CYCLE REGISTER

MDC<15:8>
bit 15 bit 8

MDC<7:0>
bit 7 bit 0
Legend:
bit 15-0 MDC<15:0>: PWMx Master Duty Cycle Value bits

REGISTER 17-7: PWMCONx: PWMx CONTROL REGISTER

HS-0, HC HS-0, HC HS-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTSTAT(1) CLSTAT(1) TRGSTAT FLTIEN CLIEN TRGIEN ITB(2) MDCS(2)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0

DTC1 DTC0 DTCP(3) — — CAM(2,4) XPRES(5) IUE(2)
bit 7 bit 0

bit 15 FLTSTAT: Fault Interrupt Status bit(1)

1 = Fault interrupt is pending
0 = Fault interrupt is not pending
This bit is cleared by setting FLTIEN = 0.
bit 14 CLSTAT: Current-Limit Interrupt Status bit(1)
1 = Current-limit interrupt is pending
0 = Current-limit interrupt is not pending
This bit is cleared by setting CLIEN = 0.
bit 13 TRGSTAT: Trigger Interrupt Status bit
1 = Trigger interrupt is pending
0 = Trigger interrupt is not pending
This bit is cleared by setting TRGIEN = 0.
bit 12 FLTIEN: Fault Interrupt Enable bit
1 = Fault interrupt is enabled
0 = Fault interrupt is disabled and the FLTSTAT bit is cleared
bit 11 CLIEN: Current-Limit Interrupt Enable bit
1 = Current-limit interrupt is enabled
0 = Current-limit interrupt is disabled and the CLSTAT bit is cleared
bit 10 TRGIEN: Trigger Interrupt Enable bit
1 = Trigger event generates an interrupt request
0 = Trigger event interrupts are disabled and the TRGSTAT bit is cleared
bit 9 ITB: Independent Time Base Mode bit(2)
1 = PHASEx register provides time base period for this PWM generator
0 = PTPER register provides timing for this PWM generator
bit 8 MDCS: Master Duty Cycle Register Select bit(2)
1 = MDC register provides duty cycle information for this PWM generator
0 = PDCx register provides duty cycle information for this PWM generator
Note 1: Software must clear the interrupt status here and in the corresponding IFSx bit in the interrupt controller.
2: These bits should not be changed after the PWMx is enabled (PTEN = 1).
3: DTC<1:0> = 11 for DTCP to be effective; else, DTCP is ignored.
4: The Independent Time Base (ITB = 1) mode must be enabled to use Center-Aligned mode. If ITB = 0, the
CAM bit is ignored.
5: To operate in External Period Reset mode, the ITB bit must be ‘1’ and the CLMOD bit in the FCLCONx
register must be ‘0’.

REGISTER 17-7: PWMCONx: PWMx CONTROL REGISTER (CONTINUED)

bit 7-6 DTC<1:0>: Dead-Time Control bits
11 = Dead-Time Compensation mode
10 = Dead-time function is disabled
01 = Negative dead time is actively applied for Complementary Output mode
00 = Positive dead time is actively applied for all Output modes
bit 5 DTCP: Dead-Time Compensation Polarity bit(3)
When Set to ‘1’:
If DTCMPx = 0, PWMxL is shortened and PWMxH is lengthened.
If DTCMPx = 1, PWMxH is shortened and PWMxL is lengthened.
When Set to ‘0’:
If DTCMPx = 0, PWMxH is shortened and PWMxL is lengthened.
If DTCMPx = 1, PWMxL is shortened and PWMxH is lengthened.
bit 2 CAM: Center-Aligned Mode Enable bit(2,4)
1 = Center-Aligned mode is enabled
0 = Edge-Aligned mode is enabled
bit 1 XPRES: External PWMx Reset Control bit(5)
1 = Current-limit source resets the time base for this PWM generator if it is in Independent Time Base mode
0 = External pins do not affect PWMx time base
bit 0 IUE: Immediate Update Enable bit(2)
1 = Updates to the active MDC/PDCx/DTRx/ALTDTRx/PHASEx registers are immediate
0 = Updates to the active MDC/PDCx/DTRx/ALTDTRx/PHASEx registers are synchronized to the
PWMx period boundary
Note 1: Software must clear the interrupt status here and in the corresponding IFSx bit in the interrupt controller.
2: These bits should not be changed after the PWMx is enabled (PTEN = 1).
3: DTC<1:0> = 11 for DTCP to be effective; else, DTCP is ignored.
4: The Independent Time Base (ITB = 1) mode must be enabled to use Center-Aligned mode. If ITB = 0, the
CAM bit is ignored.
5: To operate in External Period Reset mode, the ITB bit must be ‘1’ and the CLMOD bit in the FCLCONx
register must be ‘0’.

REGISTER 17-8: PDCx: PWMx GENERATOR DUTY CYCLE REGISTER

PDCx<15:8>
bit 15 bit 8

PDCx<7:0>
bit 7 bit 0
Legend:
bit 15-0 PDCx<15:0>: PWMx Generator Duty Cycle Value bits
REGISTER 17-9: PHASEx: PWMx PRIMARY PHASE-SHIFT REGISTER

PHASEx<15:8>
bit 15 bit 8

PHASEx<7:0>
bit 7 bit 0
Legend:
bit 15-0 PHASEx<15:0>: PWMx Phase-Shift Value or Independent Time Base Period for the PWM Generator bits
Note 1: If ITB (PWMCONx<9>) = 0, the following applies based on the mode of operation:
Complementary, Redundant and Push-Pull Output modes (PMOD<1:0> (IOCONx<11:10>) = 00, 01 or
10), PHASEx<15:0> = Phase-shift value for PWMxH and PWMxL outputs.
2: If ITB (PWMCONx<9>) = 1, the following applies based on the mode of operation:
Complementary, Redundant and Push-Pull Output modes (PMOD<1:0> (IOCONx<11:10>) = 00, 01 or 10),
PHASEx<15:0> = Independent Time Base period value for PWMxH and PWMxL.

REGISTER 17-10: DTRx: PWMx DEAD-TIME REGISTER

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — DTRx<13:8>
bit 15 bit 8

DTRx<7:0>
bit 7 bit 0
Legend:

bit 13-0 DTRx<13:0>: Unsigned 14-Bit Dead-Time Value for PWMx Dead-Time Unit bits
REGISTER 17-11: ALTDTRx: PWMx ALTERNATE DEAD-TIME REGISTER

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — ALTDTRx<13:8>
bit 15 bit 8

ALTDTRx<7:0>
bit 7 bit 0
Legend:

bit 13-0 ALTDTRx<13:0>: Unsigned 14-Bit Alternate Dead-Time Value for PWMx Dead-Time Unit bits

REGISTER 17-12: TRGCONx: PWMx TRIGGER CONTROL REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0 — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — TRGSTRT5(1) TRGSTRT4(1) TRGSTRT3(1) TRGSTRT2(1) TRGSTRT1(1) TRGSTRT0(1)
bit 7 bit 0
Legend:
bit 15-12 TRGDIV<3:0>: Trigger Output Divider bits

1111 = Triggers output for every 16th trigger event
0010 = Triggers output for every 3rd trigger event
0001 = Triggers output for every 2nd trigger event
0000 = Triggers output for every trigger event
bit 5-0 TRGSTRT<5:0>: Trigger Postscaler Start Enable Select bits(1)
111111 = Waits 63 PWM cycles before generating the first trigger event after the module is enabled
•
•
•
000001 = Waits 1 PWM cycle before generating the first trigger event after the module is enabled
Note 1: The secondary PWM generator cannot generate PWMx trigger interrupts.

REGISTER 17-13: IOCONx: PWMx I/O CONTROL REGISTER(2)

PENH PENL POLH POLL PMOD1(1) PMOD0(1) OVRENH OVRENL
bit 15 bit 8

OVRDAT1 OVRDAT0 FLTDAT1 FLTDAT0 CLDAT1 CLDAT0 SWAP OSYNC
bit 7 bit 0
Legend:
bit 15 PENH: PWMxH Output Pin Ownership bit

1 = PWMx module controls the PWMxH pin
0 = GPIO module controls the PWMxH pin
bit 14 PENL: PWMxL Output Pin Ownership bit
1 = PWMx module controls the PWMxL pin
0 = GPIO module controls the PWMxL pin
bit 13 POLH: PWMxH Output Pin Polarity bit
1 = PWMxH pin is active-low
0 = PWMxH pin is active-high
bit 12 POLL: PWMxL Output Pin Polarity bit
1 = PWMxL pin is active-low
0 = PWMxL pin is active-high
bit 11-10 PMOD<1:0>: PWMx I/O Pin Mode bits(1)
11 = Reserved; do not use
10 = PWMx I/O pin pair is in the Push-Pull Output mode
01 = PWMx I/O pin pair is in the Redundant Output mode
00 = PWMx I/O pin pair is in the Complementary Output mode
bit 9 OVRENH: Override Enable for PWMxH Pin bit
1 = OVRDAT1 controls the output on the PWMxH pin
0 = PWMx generator controls the PWMxH pin
bit 8 OVRENL: Override Enable for PWMxL Pin bit
1 = OVRDAT0 controls the output on the PWMxL pin
0 = PWMx generator controls the PWMxL pin
bit 7-6 OVRDAT<1:0>: Data for PWMxH, PWMxL Pins if Override is Enabled bits
If OVERENH = 1, PWMxH is driven to the state specified by OVRDAT1.
If OVERENL = 1, PWMxL is driven to the state specified by OVRDAT0.
bit 5-4 FLTDAT<1:0>: Data for PWMxH and PWMxL Pins if FLTMOD is Enabled bits
If Fault is active, PWMxH is driven to the state specified by FLTDAT1.
If Fault is active, PWMxL is driven to the state specified by FLTDAT0.
bit 3-2 CLDAT<1:0>: Data for PWMxH and PWMxL Pins if CLMOD is Enabled bits
If current limit is active, PWMxH is driven to the state specified by CLDAT1.
If current limit is active, PWMxL is driven to the state specified by CLDAT0.
Note 1: These bits should not be changed after the PWMx module is enabled (PTEN = 1).
2: If the PWMLOCK Configuration bit (FDEVOPT<0>) is a ‘1’, the IOCONx register can only be written after
the unlock sequence has been executed.

REGISTER 17-13: IOCONx: PWMx I/O CONTROL REGISTER(2) (CONTINUED)

bit 1 SWAP: SWAP PWMxH and PWMxL Pins bit
1 = PWMxH output signal is connected to the PWMxL pin; PWMxL output signal is connected to the
PWMxH pin
0 = PWMxH and PWMxL pins are mapped to their respective pins
bit 0 OSYNC: Output Override Synchronization bit
1 = Output overrides through the OVRDAT<1:0> bits are synchronized to the PWMx time base
0 = Output overrides through the OVRDAT<1:0> bits occur on the next CPU clock boundary
Note 1: These bits should not be changed after the PWMx module is enabled (PTEN = 1).
2: If the PWMLOCK Configuration bit (FDEVOPT<0>) is a ‘1’, the IOCONx register can only be written after
REGISTER 17-14: TRIGx: PWMx PRIMARY TRIGGER COMPARE VALUE REGISTER

TRGCMP<15:8>
bit 15 bit 8

TRGCMP<7:0>
bit 7 bit 0
Legend:
bit 15-0 TRGCMP<15:0>: Trigger Control Value bits

When the primary PWMx functions in the local time base, this register contains the compare values
that can trigger the ADC module.

REGISTER 17-15: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER(1)

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— CLSRC4 CLSRC3 CLSRC2 CLSRC1 CLSRC0 CLPOL(2) CLMOD
bit 15 bit 8

FLTSRC4 FLTSRC3 FLTSRC2 FLTSRC1 FLTSRC0 FLTPOL(2) FLTMOD1 FLTMOD0
bit 7 bit 0
Legend:

bit 14-10 CLSRC<4:0>: Current-Limit Control Signal Source Select for PWM Generator x bits
11111 = Fault 32
11110 = Reserved
•
•
•
01100 = Op Amp/Comparator 5
01011 = Comparator 4
00111 = Fault 8
00110 = Fault 7
00101 = Fault 6
00100 = Fault 5
00011 = Fault 4
00010 = Fault 3
00001 = Fault 2
00000 = Fault 1 (default)
bit 9 CLPOL: Current-Limit Polarity for PWM Generator x bit(2)
1 = The selected current-limit source is active-low
0 = The selected current-limit source is active-high
bit 8 CLMOD: Current-Limit Mode Enable for PWM Generator x bit
1 = Current-Limit mode is enabled
0 = Current-Limit mode is disabled
Note 1: If the PWMLOCK Configuration bit (FDEVOPT<0>) is a ‘1’, the FCLCONx register can only be written after
2: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will yield
unpredictable results.

REGISTER 17-15: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER(1) (CONTINUED)

bit 7-3 FLTSRC<4:0>: Fault Control Signal Source Select for PWM Generator x bits
11111 = Fault 32 (default)
11110 = Reserved
•
•
•
01011 = Comparator 4
00111 = Fault 8
00110 = Fault 7
00101 = Fault 6
00100 = Fault 5
00011 = Fault 4
00010 = Fault 3
00001 = Fault 2
00000 = Fault 1
bit 2 FLTPOL: Fault Polarity for PWM Generator x bit(2)
1 = The selected Fault source is active-low
0 = The selected Fault source is active-high
bit 1-0 FLTMOD<1:0>: Fault Mode for PWM Generator x bits
11 = Fault input is disabled
10 = Reserved
01 = The selected Fault source forces the PWMxH, PWMxL pins to FLTDAT<1:0> values (cycle)
00 = The selected Fault source forces the PWMxH, PWMxL pins to FLTDAT<1:0> values (latched condition)
Note 1: If the PWMLOCK Configuration bit (FDEVOPT<0>) is a ‘1’, the FCLCONx register can only be written after
2: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will yield
unpredictable results.

REGISTER 17-16: LEBCONx: PWMx LEADING-EDGE BLANKING CONTROL REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0
PHR PHF PLR PLF FLTLEBEN CLLEBEN — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

(1) (1)
— — BCH BCL BPHH BPHL BPLH BPLL
bit 7 bit 0
Legend:
bit 15 PHR: PWMxH Rising Edge Trigger Enable bit

1 = Rising edge of PWMxH will trigger the Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores the rising edge of PWMxH
bit 14 PHF: PWMxH Falling Edge Trigger Enable bit
1 = Falling edge of PWMxH will trigger the Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores the falling edge of PWMxH
bit 13 PLR: PWMxL Rising Edge Trigger Enable bit
1 = Rising edge of PWMxL will trigger the Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores the rising edge of PWMxL
bit 12 PLF: PWMxL Falling Edge Trigger Enable bit
1 = Falling edge of PWMxL will trigger the Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores the falling edge of PWMxL
bit 11 FLTLEBEN: Fault Input Leading-Edge Blanking Enable bit
1 = Leading-Edge Blanking is applied to the selected Fault input
0 = Leading-Edge Blanking is not applied to the selected Fault input
bit 10 CLLEBEN: Current-Limit Input Leading-Edge Blanking Enable bit
1 = Leading-Edge Blanking is applied to the selected current-limit input
0 = Leading-Edge Blanking is not applied to the selected current-limit input
bit 5 BCH: Blanking in Selected Blanking Signal High Enable bit(1)
1 = State blanking (of current-limit and/or Fault input signals) when selected blanking signal is high
0 = No blanking when the selected blanking signal is high
bit 4 BCL: Blanking in Selected Blanking Signal Low Enable bit(1)
1 = State blanking (of current-limit and/or Fault input signals) when selected blanking signal is low
0 = No blanking when the selected blanking signal is low
bit 3 BPHH: Blanking in PWMxH High Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when the PWMxH output is high
0 = No blanking when the PWMxH output is high
bit 2 BPHL: Blanking in PWMxH Low Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when the PWMxH output is low
0 = No blanking when the PWMxH output is low
bit 1 BPLH: Blanking in PWMxL High Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when the PWMxL output is high
0 = No blanking when the PWMxL output is high
bit 0 BPLL: Blanking in PWMxL Low Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when the PWMxL output is low
0 = No blanking when the PWMxL output is low
Note 1: The blanking signal is selected through the BLANKSEL<3:0> bits in the AUXCONx register.

REGISTER 17-17: LEBDLYx: PWMx LEADING-EDGE BLANKING DELAY REGISTER

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — LEB<11:8>
bit 15 bit 8

LEB<7:0>
bit 7 bit 0
Legend:

bit 11-0 LEB<11:0>: Leading-Edge Blanking Delay for Current-Limit and Fault Inputs bits

REGISTER 17-18: AUXCONx: PWMx AUXILIARY CONTROL REGISTER

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN
bit 7 bit 0
Legend:

bit 11-8 BLANKSEL<3:0>: PWMx State Blank Source Select bits
The selected state blank signal will block the current-limit and/or Fault input signals (if enabled through
the BCH and BCL bits in the LEBCONx register).
1001 = Reserved
•
•
•
0100 = Reserved
0011 = PWM3H is selected as the state blank source
0000 = No state blanking
bit 5-2 CHOPSEL<3:0>: PWMx Chop Clock Source Select bits
The selected signal will enable and disable (Chop) the selected PWMx outputs.
1001 = Reserved
•
•
•
0100 = Reserved
0011 = PWM3H is selected as the chop clock source
0000 = Chop clock generator is selected as the chop clock source
bit 1 CHOPHEN: PWMxH Output Chopping Enable bit
1 = PWMxH chopping function is enabled
0 = PWMxH chopping function is disabled
bit 0 CHOPLEN: PWMxL Output Chopping Enable bit
1 = PWMxL chopping function is enabled
0 = PWMxL chopping function is disabled

NOTES:

18.0 SERIAL PERIPHERAL The SPI1 module uses dedicated pins which allow for a
higher speed when using SPI1. The SPI2 module takes
INTERFACE (SPI)
advantage of the Peripheral Pin Select (PPS) feature to
Note 1: This data sheet summarizes the features allow for greater flexibility in pin configuration of this
of the dsPIC33EVXXXGM00X/10X family module, but results in a lower maximum speed. See
of devices. It is not intended to be a Section 30.0 “Electrical Characteristics” for more
comprehensive reference source. To information.
complement the information in this data The SPIx serial interface consists of the following four
sheet, refer to “Serial Peripheral pins:
Interface (SPI)” (DS70005185) in the
• SDIx: Serial Data Input
“dsPIC33/PIC24 Family Reference Man-
ual”, which is available from the Microchip • SDOx: Serial Data Output
web site (www.microchip.com). • SCKx: Shift Clock Input or Output
2: Some registers and associated bits • SSx/FSYNCx: Active-Low Slave Select or Frame
described in this section may not be Synchronization I/O Pulse
available on all devices. Refer to Note: All of the 4 pins of the SPIx serial interface
Section 4.0 “Memory Organization” in must be configured as digital in the
this data sheet for device-specific register ANSELx registers.
The SPIx module can be configured to operate with
The Serial Peripheral Interface (SPI) module is a two, three or four pins. In 3-pin mode, SSx is not used.
synchronous serial interface, useful for communicating In 2-pin mode, neither SDOx nor SSx is used.
with other peripheral or microcontroller devices. These Figure 18-1 illustrates the block diagram of the SPIx
peripheral devices can be serial EEPROMs, shift reg- module in Standard and Enhanced modes.
isters, display drivers, ADC Converters, etc. The SPI
module is compatible with the Motorola® SPI and SIOP
interfaces.
The dsPIC33EVXXXGM00X/10X device family offers
two SPI modules on a single device, SPI1 and SPI2,
that are functionally identical. Each SPI module
includes an eight-word FIFO buffer and allows DMA
bus connections. When using the SPI module with
DMA, FIFO operation can be disabled.
Note: In this section, the SPI modules are
referred to together as SPIx, or separately
as SPI1 and SPI2. Special Function
Registers follow a similar notation. For
example, SPIxCON refers to the control
register for the SPI1 and SPI2 modules.

FIGURE 18-1: SPIx MODULE BLOCK DIAGRAM
SCKx 1:1 to 1:8 1:1/4/16/64

Secondary Primary FP
Prescaler Prescaler
SSx/FSYNCx
Sync Control Select
Control Clock Edge
SPIxCON1<1:0>
Shift Control
SDOx SPIxCON1<4:2>
Enable
bit 0 Master Clock
SDIx
SPIxSR
Transfer Transfer
8-Level FIFO 8-Level FIFO

Receive Buffer(1) Transmit Buffer(1)
SPIxBUF
Read SPIxBUF Write SPIxBUF
16
Internal Data Bus
Note 1: In Standard mode, the FIFO is only one level deep.

18.1 SPI Helpful Tips 3. FRMEN (SPIxCON2<15>) = 1 and SSEN

(SPIxCON1<7>) = 1 are exclusive and invalid.
1. In Frame mode, if there is a possibility that the In Frame mode, SCKx is continuous and the
master may not be initialized before the slave: Frame Sync pulse is active on the SSx pin,
a) If FRMPOL (SPIxCON2<13>) = 1, use a which indicates the start of a data frame.
pull-down resistor on SSx.
Note: Not all third-party devices support Frame
b) If FRMPOL = 0, use a pull-up resistor on mode timing. For more information, refer
SSx. to the SPI specifications in Section 30.0
Note: This insures that the first frame transmis- “Electrical Characteristics”.
sion after initialization is not shifted or
corrupted. 4. In Master mode only, set the SMP bit
(SPIxCON1<9>) to a ‘1’ for the fastest SPI data
2. In Non-Framed 3-Wire mode (i.e., not using SSx rate possible. The SMP bit can only be set at the
from a master): same time or after the MSTEN bit
a) If CKP (SPIxCON1<6>) = 1, always place a (SPIxCON1<5>) is set.
pull-up resistor on SSx. To avoid invalid slave read data to the master, the
b) If CKP = 0, always place a pull-down user’s master software must ensure enough time for
resistor on SSx. slave software to fill its write buffer before the user
application initiates a master write/read cycle. It is
Note: This will insure that during power-up and
always advisable to preload the SPIxBUF Transmit
initialization, the master/slave will not lose
register in advance of the next master transaction
sync due to an errant SCKx transition that
cycle. SPIxBUF is transferred to the SPIx Shift register
would cause the slave to accumulate data
and is empty once the data transmission begins.
shift errors, for both transmit and receive,
appearing as corrupted data.

18.2 SPI Control Registers
REGISTER 18-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER

R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0
SPIEN — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0
bit 15 bit 8
R/W-0 R/C-0, HS R/W-0 R/W-0 R/W-0 R/W-0 R-0, HS, HC R-0, HS, HC
SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF
bit 7 bit 0

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared C = Clearable bit
bit 15 SPIEN: SPIx Enable bit

1 = Enables the SPIx module and configures SCKx, SDOx, SDIx and SSx as serial port pins
0 = Disables the SPIx module
bit 13 SPISIDL: SPIx Stop in Idle Mode bit
1 = Discontinues the SPIx module operation when the device enters Idle mode
0 = Continues the SPIx module operation in Idle mode
bit 10-8 SPIBEC<2:0>: SPIx Buffer Element Count bits (valid in Enhanced Buffer mode)
Master mode:
Number of SPIx transfers are pending.
Slave mode:
Number of SPIx transfers are unread.
bit 7 SRMPT: SPIx Shift Register (SPIxSR) Empty bit (valid in Enhanced Buffer mode)
1 = The SPIx Shift register is empty and ready to send or receive the data
0 = The SPIx Shift register is not empty
bit 6 SPIROV: SPIx Receive Overflow Flag bit
1 = A new byte/word is completely received and discarded; the user application has not read the
previous data in the SPIxBUF register
0 = Overflow has not occurred
bit 5 SRXMPT: SPIx Receive FIFO Empty bit (valid in Enhanced Buffer mode)
1 = RX FIFO is empty
0 = RX FIFO is not empty
bit 4-2 SISEL<2:0>: SPIx Buffer Interrupt Mode bits (valid in Enhanced Buffer mode)
111 = Interrupt when the SPIx transmit buffer is full (SPITBF bit is set)
110 = Interrupt when the last bit is shifted into SPIxSR, and as a result, the TX FIFO is empty
101 = Interrupt when the last bit is shifted out of SPIxSR and the transmit is complete
100 = Interrupt when one data is shifted into SPIxSR, and as a result, the TX FIFO has one open
memory location
011 = Interrupt when the SPIx receive buffer is full (SPIRBF bit is set)
010 = Interrupt when the SPIx receive buffer is 3/4 or more full
001 = Interrupt when data is available in the SPIx receive buffer (SRMPT bit is set)
000 = Interrupt when the last data in the SPIx receive buffer is read, and as a result, the buffer is
empty (SRXMPT bit is set)

REGISTER 18-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED)

bit 1 SPITBF: SPIx Transmit Buffer Full Status bit
1 = Transmit has not yet started, the SPIxTXB bit is full
0 = Transmit has started, the SPIxTXB bit is empty
Standard Buffer mode:
Automatically set in hardware when the core writes to the SPIxBUF location, loading SPIxTXB.
Automatically cleared in hardware when the SPIx module transfers data from SPIxTXB to SPIxSR.
Enhanced Buffer mode:
Automatically set in the hardware when the CPU writes to the SPIxBUF location, loading the last avail-
able buffer location. Automatically cleared in hardware when a buffer location is available for a CPU
write operation.
bit 0 SPIRBF: SPIx Receive Buffer Full Status bit
1 = Receive is complete, the SPIxRXB bit is full
0 = Receive is incomplete, the SPIxRXB bit is empty
Standard Buffer mode:
Automatically set in the hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically
cleared in hardware when the core reads the SPIxBUF location, reading SPIxRXB.
Enhanced Buffer mode:
Automatically set in hardware when SPIx transfers data from SPIxSR to the buffer, filling the last
unread buffer location. Automatically cleared in hardware when a buffer location is available for a
transfer from SPIxSR.

REGISTER 18-2: SPIxCON1: SPIx CONTROL REGISTER 1

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — DISSCK DISSDO MODE16 SMP CKE(1)
bit 15 bit 8

(2) (3) (3) (3) (3)
SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0(3)
bit 7 bit 0
Legend:

bit 12 DISSCK: Disable SCKx Pin bit (SPI Master modes only)
1 = Internal SPI clock is disabled, pin functions as I/O
0 = Internal SPI clock is enabled
bit 11 DISSDO: Disable SDOx Pin bit
1 = SDOx pin is not used by the module; pin functions as I/O
0 = SDOx pin is controlled by the module
bit 10 MODE16: Word/Byte Communication Select bit
1 = Communication is word-wide (16 bits)
0 = Communication is byte-wide (8 bits)
bit 9 SMP: SPIx Data Input Sample Phase bit
Master mode:
1 = Input data is sampled at the end of data output time
0 = Input data is sampled at the middle of data output time
Slave mode:
SMP must be cleared when SPIx is used in Slave mode.
bit 8 CKE: Clock Edge Select bit(1)
1 = Serial output data changes on transition from active clock state to Idle clock state (refer to bit 6)
0 = Serial output data changes on transition from Idle clock state to active clock state (refer to bit 6)
bit 7 SSEN: Slave Select Enable bit (Slave mode)(2)
1 = SSx pin is used for Slave mode
0 = SSx pin is not used by the module; pin is controlled by port function
bit 6 CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
bit 5 MSTEN: Master Mode Enable bit
1 = Master mode
0 = Slave mode
Note 1: The CKE bit is not used in Framed SPI modes. Program this bit to ‘0’ for Framed SPI modes
(FRMEN = 1).
2: This bit must be cleared when FRMEN = 1.
3: Do not set both primary and secondary prescalers to the value of 1:1.

REGISTER 18-2: SPIxCON1: SPIx CONTROL REGISTER 1 (CONTINUED)

bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode)(3)
111 = Secondary prescale 1:1
•
•
•
bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode)(3)
11 = Primary prescale 1:1
Note 1: The CKE bit is not used in Framed SPI modes. Program this bit to ‘0’ for Framed SPI modes
(FRMEN = 1).
2: This bit must be cleared when FRMEN = 1.
3: Do not set both primary and secondary prescalers to the value of 1:1.

REGISTER 18-3: SPIxCON2: SPIx CONTROL REGISTER 2

R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0
FRMEN SPIFSD FRMPOL — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

— — — — — — FRMDLY SPIBEN
bit 7 bit 0
Legend:
bit 15 FRMEN: Framed SPIx Support bit

1 = Framed SPIx support is enabled (SSx pin is used as the Frame Sync pulse input/output)
0 = Framed SPIx support is disabled
bit 14 SPIFSD: SPIx Frame Sync Pulse Direction Control bit
1 = Frame Sync pulse input (slave)
0 = Frame Sync pulse output (master)
bit 13 FRMPOL: Frame Sync Pulse Polarity bit
1 = Frame Sync pulse is active-high
0 = Frame Sync pulse is active-low
bit 1 FRMDLY: Frame Sync Pulse Edge Select bit
1 = Frame Sync pulse coincides with the first bit clock
0 = Frame Sync pulse precedes the first bit clock
bit 0 SPIBEN: SPIx Enhanced Buffer Enable bit
1 = Enhanced buffer is enabled
0 = Enhanced buffer is disabled (Standard mode)

19.0 INTER-INTEGRATED CIRCUIT Figure 19-1 shows a block diagram of the I2C module.
(I2C)
19.1 I2C Baud Rate Generator
The Baud Rate Generator (BRG) used for I2C mode
operation is used to set the SCL clock frequency for
of devices. It is not intended to be a
100 kHz, 400 kHz and 1 MHz. The BRG reload value is
comprehensive reference source. To
contained in the I2CxBRG register. The BRG will
automatically begin counting on a write to the I2CxTRN
sheet, refer to “Inter-Integrated Circuit™
register.
(I2C™)” (DS70000195) in the “dsPIC33/
PIC24 Family Reference Manual”, which Equation 19-1 and Equation 19-2 provide the BRG
is available from the Microchip web site reload formula and FSCL frequency, respectively.
(www.microchip.com).
2: Some registers and associated bits EQUATION 19-1: BRG FORMULA
available on all devices. Refer to I2CxBRG = (( F 1
SCL
– Delay x FCY
) 2 )–2
this data sheet for device-specific register Where:
and bit information. Delay varies from 110 ns to 130 ns.
The dsPIC33EVXXXGM00X/10X family of devices
contains one Inter-Integrated Circuit (I2C) module, I2C1. EQUATION 19-2: FSCL FREQUENCY
The I2C module provides complete hardware support
for both Slave and Multi-Master modes of the I2C serial FSCL = FCY/((I2CxBRG + 2) * 2)
communication standard, with a 16-bit interface.
The I2C module has the following 2-pin interface:
• The SCLx pin is clock.
• The SDAx pin is data.
The I2C module offers the following key features:
• I2C Interface Supporting Both Master and Slave
modes of Operation
• I2C Slave mode Supports 7 and 10-Bit Addressing
• I2C Master mode Supports 7 and 10-Bit Addressing
• I2C Port allows Bidirectional Transfers between
Master and Slaves
• Serial Clock Synchronization for I2C Port can be
used as a Handshake Mechanism to Suspend
and Resume Serial Transfer (SCLREL control)
• I2C Supports Multi-Master Operation, Detects Bus
Collision and Arbitrates Accordingly
• Support for Address Bit Masking up to Lower 7 Bits
• I2C Slave Enhancements:
- SDAx hold time selection of SMBus (300 ns
or 150 ns)
- Start/Stop bit interrupt enables

FIGURE 19-1: I2Cx BLOCK DIAGRAM (x = 1)
Internal
Data Bus
I2CxRCV
Read
Shift
SCLx/ASCLx Clock
I2CxRSR
LSb
SDAx/ASDAx Address Match

Match Detect Write
I2CxMSK
Write Read
I2CxADD
Read
Start and Stop

Bit Detect
Write
Start, Restart, Stop

Bit Generate I2CxSTAT
Control Logic
Read
Collision Write
Detect
I2CxCON
Acknowledge
Generation Read
Clock
Stretching
Write
I2CxTRN
LSb
Shift Clock Read
Reload
Control
Write
BRG Down Counter I2CxBRG
Read
FCY

19.2 I2C Control Registers
REGISTER 19-1: I2CxCON1: I2Cx CONTROL REGISTER 1

R/W-0 U-0 R/W-0 R/S-1 R/W-0 R/W-0 R/W-0 R/W-0
(1)
I2CEN — I2CSIDL SCLREL STRICT A10M DISSLW SMEN
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC

GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0
Legend: S = Settable bit HC = Hardware Clearable bit

bit 15 I2CEN: I2Cx Enable bit (writable from SW only)

1 = Enables the I2C module and configures the SDAx and SCLx pins as serial port pins
0 = Disables the I2C module and all I2C pins are controlled by port functions
bit 13 I2CSIDL: I2Cx Stop in Idle Mode bit
bit 12 SCLREL: SCLx Release Control bit (I2C Slave mode only)(1)
Module resets and (I2CEN = 0) sets SCLREL = 1.
If STREN = 0:(2)
1 = Releases clock
0 = Forces clock low (clock stretch)
If STREN = 1:
1 = Releases clock
0 = Holds clock low (clock stretch); user may program this bit to ‘0’, clock stretch at the next SCLx low
bit 11 STRICT: Strict I2C Reserved Address Rule Enable bit
1 = Strict reserved addressing is enforced
In Slave mode, the device does not respond to reserved address space and addresses falling in
that category are NACKed.
0 = Reserved addressing would be Acknowledged
In Slave mode, the device will respond to an address falling in the reserved address space. When
there is a match with any of the reserved addresses, the device will generate an ACK.
bit 10 A10M: 10-Bit Slave Address Flag bit
1 = I2CxADD is a 10-bit slave address
0 = I2CxADD is a 7-bit slave address
bit 9 DISSLW: Slew Rate Control Disable bit
1 = Slew rate control is disabled for Standard Speed mode (100 kHz, also disabled for 1 MHz mode)
0 = Slew rate control is enabled for High-Speed mode (400 kHz)
bit 8 SMEN: SMBus Input Levels Enable bit
1 = Enables the input logic so thresholds are compliant with the SMBus specification
0 = Disables the SMBus-specific inputs
Note 1: Automatically cleared to ‘0’ at the beginning of slave transmission; automatically cleared to ‘0’ at the end
of slave reception.
2: Automatically cleared to ‘0’ at the beginning of slave transmission.

REGISTER 19-1: I2CxCON1: I2Cx CONTROL REGISTER 1 (CONTINUED)

bit 7 GCEN: General Call Enable bit (I2C Slave mode only)
1 = Enables interrupt when a general call address is received in I2CxRSR; module is enabled for reception
0 = General call address is disabled.
bit 6 STREN: SCLx Clock Stretch Enable bit
In I2C Slave mode only, used in conjunction with the SCLREL bit.
1 = Enables clock stretching
0 = Disables clock stretching
bit 5 ACKDT: Acknowledge Data bit
In I2C Master mode, during Master Receive mode. The value that will be transmitted when the user
initiates an Acknowledge sequence at the end of a receive.
In I2C Slave mode when AHEN = 1 or DHEN = 1. The value that the slave will transmit when it initiates
an Acknowledge sequence at the end of an address or data reception.
1 = NACK is sent
0 = ACK is sent
bit 4 ACKEN: Acknowledge Sequence Enable bit
In I2C Master mode only; applicable during Master Receive mode.
1 = Initiates Acknowledge sequence on SDAx and SCLx pins, and transmits ACKDT data bit
0 = Acknowledge sequence is Idle
bit 3 RCEN: Receive Enable bit (I2C Master mode only)
1 = Enables Receive mode for I2C, automatically cleared by hardware at the end of 8-bit receive data byte
0 = Receive sequence is not in progress
bit 2 PEN: Stop Condition Enable bit (I2C Master mode only)
1 = Initiates Stop condition on SDAx and SCLx pins
0 = Stop condition is Idle
bit 1 RSEN: Restart Condition Enable bit (I2C Master mode only)
1 = Initiates Restart condition on SDAx and SCLx pins
0 = Restart condition is Idle
bit 0 SEN: Start Condition Enable bit (I2C Master mode only)
1 = Initiates Start condition on SDAx and SCLx pins
0 = Start condition is Idle
Note 1: Automatically cleared to ‘0’ at the beginning of slave transmission; automatically cleared to ‘0’ at the end
of slave reception.
2: Automatically cleared to ‘0’ at the beginning of slave transmission.

REGISTER 19-2: I2CxCON2: I2Cx CONTROL REGISTER 2

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

— PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN
bit 7 bit 0
Legend:

bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C Slave mode only).
1 = Enables interrupt on detection of Stop condition
0 = Stop detection interrupts are disabled
bit 5 SCIE: Start Condition Interrupt Enable bit (I2C Slave mode only)
1 = Enables interrupt on detection of Start or Restart conditions
0 = Start detection interrupts are disabled
bit 4 BOEN: Buffer Overwrite Enable bit (I2C Slave mode only)
1 = The I2CxRCV register bit is updated and an ACK is generated for a received address/data byte,
ignoring the state of the I2COV bit only if the RBF bit = 0
0 = The I2CxRCV register bit is only updated when I2COV is clear
bit 3 SDAHT: SDAx Hold Time Selection bit
1 = Minimum of 300 ns hold time on SDAx after the falling edge of SCLx
0 = Minimum of 100 ns hold time on SDAx after the falling edge of SCLx
bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
If, on the rising edge of SCLx, SDAx is sampled low when the module is outputting a high state, the
BCL bit is set and the bus goes Idle. This Detection mode is only valid during data and ACK transmit
sequences.
1 = Slave bus collision interrupts are enabled
0 = Slave bus collision interrupts are disabled
bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only)
1 = Following the 8th falling edge of SCLx for a matching received address byte; the SCLREL bit
(I2CxCON1<12>) will be cleared and the SCLx will be held low
0 = Address holding is disabled
bit 0 DHEN: Data Hold Enable bit (I2C Slave mode only)
1 = Following the 8th falling edge of SCLx for a received data byte; slave hardware clears the SCLREL
bit (I2CxCON1<12>) and the SCLx is held low
0 = Data holding is disabled

REGISTER 19-3: I2CxSTAT: I2Cx STATUS REGISTER

R-0, HSC R-0, HSC R-0, HSC U-0 U-0 R/C-0, HSC R-0, HSC R-0, HSC
ACKSTAT TRSTAT ACKTIM — — BCL GCSTAT ADD10
bit 15 bit 8
R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC
IWCOL I2COV D_A P S R_W RBF TBF
bit 7 bit 0
Legend: C = Clearable bit HSC = Hardware Settable/Clearable bit

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware Settable bit
bit 15 ACKSTAT: Acknowledge Status bit (updated in all Master and Slave modes)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 14 TRSTAT: Transmit Status bit (when operating as I2C master; applicable to master transmit operation)
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
bit 13 ACKTIM: Acknowledge Time Status bit (valid in I2C Slave mode only)
1 = Indicates I2C bus is in an Acknowledge sequence, set on 8th falling edge of SCLx clock
0 = Not an Acknowledge sequence, cleared on 9th rising edge of SCLx clock
bit 10 BCL: Bus Collision Detect bit (Master/Slave mode; cleared when I2C module is disabled, I2CEN = 0)
1 = A bus collision has been detected during a master or slave transmit operation
0 = Bus collision has not been detected
bit 9 GCSTAT: General Call Status bit (cleared after Stop detection)
1 = General call address was received
0 = General call address was not received
bit 8 ADD10: 10-Bit Address Status bit (cleared after Stop detection)
1 = 10-bit address was matched
0 = 10-bit address was not matched
bit 7 IWCOL: Write Collision Detect bit
1 = An attempt to write to the I2CxTRN register failed because the I2C module is busy; must be cleared
in software
0 = Collision has not occurred
bit 6 I2COV: I2Cx Receive Overflow Flag bit
1 = A byte was received while the I2CxRCV register is still holding the previous byte; I2COV is a “don’t
care” in Transmit mode, must be cleared in software
0 = Overflow has not occurred
bit 5 D_A: Data/Address bit (when operating as I2C slave)
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received or transmitted was an address
bit 4 P: I2Cx Stop bit
Updated when Start, Reset or Stop is detected; cleared when the I2C module is disabled, I2CEN = 0.
1 = Indicates that a Stop bit has been detected last
0 = Indicates that a Stop bit was not detected last

REGISTER 19-3: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)

bit 3 S: I2Cx Start bit
Updated when Start, Reset or Stop is detected; cleared when the I2C module is disabled, I2CEN = 0.
1 = Indicates that a Start (or Repeated Start) bit has been detected last
0 = Indicates that a Start bit was not detected last
bit 2 R_W: Read/Write Information bit (when operating as I2C slave)
1 = Read: Indicates that the data transfer is output from the slave
0 = Write: Indicates that the data transfer is input to the slave
bit 1 RBF: Receive Buffer Full Status bit
1 = Receive is complete, the I2CxRCV bit is full
0 = Receive is not complete, the I2CxRCV bit is empty
bit 0 TBF: Transmit Buffer Full Status bit
1 = Transmit is in progress, I2CxTRN is full (8 bits of data)
0 = Transmit is complete, I2CxTRN is empty
REGISTER 19-4: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — MSK<9:8>
bit 15 bit 8

MSK<7:0>
bit 7 bit 0
Legend:

bit 9-0 MSK<9:0>: I2Cx Mask for Address Bit x Select bits
1 = Enables masking for bit x of the incoming message address; bit match is not required in this position
0 = Disables masking for bit x; bit match is required in this position

NOTES:

20.0 SINGLE-EDGE NIBBLE SENT protocol timing is based on a predetermined time

unit, TTICK. Both the transmitter and receiver must be
TRANSMISSION (SENT) preconfigured for TTICK, which can vary from 3 to 90 s.
Note 1: This data sheet summarizes the features A SENT message frame starts with a Sync pulse. The
of this group of dsPIC33EVXXXGM00X/ purpose of the Sync pulse is to allow the receiver to cal-
10X family devices. It is not intended to culate the data rate of the message encoded by the
be a comprehensive reference source. transmitter. The SENT specification allows messages
For more information on Single-Edge to be validated with up to a 20% variation in TTICK. This
Nibble Transmission, refer to “Single- allows for the transmitter and receiver to run from differ-
Edge Nibble Transmission (SENT) ent clocks that may be inaccurate, and drift with time
Module” (DS70005145) in the “dsPIC33/ and temperature. The data nibbles are 4 bits in length
PIC24 Family Reference Manual”, which and are encoded as the data value + 12 ticks. This
is available from the Microchip web site yields a 0 value of 12 ticks and the maximum value,
(www.microchip.com). 0xF, of 27 ticks.
2: Some registers and associated bits A SENT message consists of the following:
described in this section may not be • A synchronization/calibration period of 56 tick
available on all devices. Refer to times
Section 4.0 “Memory Organization” in • A status nibble of 12-27 tick times
• Up to six data nibbles of 12-27 tick times
• A CRC nibble of 12-27 tick times
• An optional pause pulse period of 12-768 tick
20.1 Module Introduction times
The Single-Edge Nibble Transmission (SENT) module is Figure 20-1 shows a block diagram of the SENTx
based on the SAE J2716, “SENT – Single-Edge Nibble module.
Transmission for Automotive Applications”. The SENT
Figure 20-2 shows the construction of a typical 6-nibble
protocol is a one-way, single wire time modulated serial
data frame, with the numbers representing the minimum
communication, based on successive falling edges. It is
or maximum number of tick times for each section.
intended for use in applications where high-resolution
sensor data needs to be communicated from a sensor to
an Engine Control Unit (ECU).
The SENTx module has the following major features:
• Selectable Transmit or Receive mode
• Synchronous or Asynchronous Transmit modes
• Automatic Data Rate Synchronization
• Optional Automatic Detection of CRC Errors in
Receive mode
• Optional Hardware Calculation of CRC in
Transmit mode
• Support for Optional Pause Pulse Period
• Data Buffering for One Message Frame
• Selectable Data Length for Transmit/Receive
from 3 to 6 Nibbles
• Automatic Detection of Framing Errors

FIGURE 20-1: SENTx MODULE BLOCK DIAGRAM
SENTxCON1 SENTxSTAT
SENTxCON2 SENTxSYNC
SENTxCON3 SENTxDATH/L
SENTx TX
Output SENTx Edge
Driver Control
Nibble Period Tick Period Edge

Detector Generator Timing
SENTx RX
Edge Sync Period Control and
Detect Detector Error Detection
Legend: Receiver Only Transmitter Only Shared
FIGURE 20-2: SENTx PROTOCOL DATA FRAMES
Sync Period Status Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 CRC Pause (optional)
56 12-27 12-27 12-27 12-27 12-27 12-27 12-27 12-27 12-768

20.2 Transmit Mode 20.2.1 TRANSMIT MODE

CONFIGURATION
By default, the SENTx module is configured for transmit
operation. The module can be configured for continuous 20.2.1.1 Initializing the SENTx Module:
asynchronous message frame transmission, or alterna-
tively, for Synchronous mode triggered by software. Perform the following steps to initialize the module:
When enabled, the transmitter will send a Sync followed 1. Write RCVEN (SENTxCON1<11>) = 0 for
by the appropriate number of data nibbles, an optional Transmit mode.
CRC and optional pause pulse. The tick period used by 2. Write TXM (SENTxCON1<10>) = 0 for
the SENTx transmitter is set by writing a value to the Asynchronous Transmit mode or TXM = 1 for
TICKTIME<15:0> (SENTxCON2<15:0>) bits. The tick Synchronous mode.
period calculations are shown in Equation 20-1.
3. Write NIBCNT<2:0> (SENTxCON1<2:0>) for
the desired data frame length.
EQUATION 20-1: TICK PERIOD
4. Write CRCEN (SENTxCON1<8>) for hardware
CALCULATION or software CRC calculation.
TTICK 5. Write PPP (SENTxCON1<7>) for optional
TICKTIME<15:0> = –1 pause pulse.
TCLK
6. If PPP = 1, write TFRAME to SENTxCON3.
An optional pause pulse can be used in Asynchronous 7. Write SENTxCON2 with the appropriate value
mode to provide a fixed message frame time period. for desired tick period.
The frame period used by the SENTx transmitter is set 8. Enable interrupts and set interrupt priority.
by writing a value to the FRAMETIME<15:0> 9. Write initial status and data values to
(SENTxCON3<15:0>) bits. The formulas used to SENTxDATH/L.
calculate the value of frame time are shown in
10. If CRCEN = 0, calculate CRC and write the
Equation 20-2.
value to CRC<3:0> (SENTxDATL<3:0>).
11. Set the SNTEN (SENTxCON1<15>) bit to
EQUATION 20-2: FRAME TIME
enable the module.
CALCULATIONS
User software updates to SENTxDATH/L must be
FRAMETIME<15:0> = TTICK/TFRAME performed after the completion of the CRC and before
the next message frame’s status nibble. The recom-
FRAMETIME<15:0>  122 + 27N mended method is to use the message frame
FRAMETIME<15:0>  848 + 12N completion interrupt to trigger data writes.
Where:
TFRAME = Total time of the message from ms
N = The number of data nibbles in message, 1-6
Note: The module will not produce a pause

period with less than 12 ticks, regard-
less of the FRAMETIME<15:0> value.
FRAMETIME<15:0> values beyond 2047
will have no effect on the length of a data
frame.

20.3 Receive Mode 20.3.1 RECEIVE MODE CONFIGURATION

The module can be configured for receive operation 20.3.1.1 Initializing the SENTx Module:
by setting the RCVEN (SENTxCON1<11>) bit.
The time between each falling edge is compared Perform the following steps to initialize the module:
to SYNCMIN<15:0> (SENTxCON3<15:0>) and 1. Write RCVEN (SENTxCON1<11>) = 1 for
SYNCMAX<15:0> (SENTxCON2<15:0>), and if the Receive mode.
measured time lies between the minimum and maximum 2. Write NIBCNT<2:0> (SENTxCON1<2:0>) for
limits, the module begins to receive data. The validated the desired data frame length.
Sync time is captured in the SENTxSYNC register and 3. Write CRCEN (SENTxCON1<8>) for hardware
the tick time is calculated. Subsequent falling edges are or software CRC validation.
verified to be within the valid data width and the data is
4. Write PPP (SENTxCON1<7>) = 1 if pause pulse
stored in the SENTxDATH/L register. An interrupt event
is present.
is generated at the completion of the message and the
user software should read the SENTx Data register 5. Write SENTxCON2 with the value of SYNCMAXx
before the reception of the next nibble. The equation for (Nominal Sync Period + 20%).
SYNCMIN<15:0> and SYNCMAX<15:0> is shown in 6. Write SENTxCON3 with the value of SYNCMINx
Equation 20-3. (Nominal Sync Period – 20%).
7. Enable interrupts and set interrupt priority.
EQUATION 20-3: SYNCMIN<15:0> AND 8. Set the SNTEN (SENTxCON1<15>) bit to
SYNCMAX<15:0> enable the module.
CALCULATIONS The data should be read from the SENTxDATH/L regis-
ter after the completion of the CRC and before the next
TTICK = TCLK • (TICKTIME<15:0> + 1) message frame’s status nibble. The recommended
method is to use the message frame completion
FRAMETIME<15:0> = TTICK/TFRAME
interrupt trigger.
SyncCount = 8 x FRCV x TTICK
SYNCMIN<15:0> = 0.8 x SyncCount
SYNCMAX<15:0> = 1.2 x SyncCount
FRAMETIME<15:0>  122 + 27N
FRAMETIME<15:0>  848 + 12N
Where:
TFRAME = Total time of the message from ms
N = The number of data nibbles in message, 1-6
FRCV = FCY x prescaler
TCLK = FCY/Prescaler
For TTICK = 3.0 s and FCLK = 4 MHz,

SYNCMIN<15:0> = 76.
Note: To ensure a Sync period can be identified,

the value written to SYNCMIN<15:0>
must be less than the value written to
SYNCMAX<15:0>.

REGISTER 20-1: SENTxCON1: SENTx CONTROL REGISTER 1

R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
SNTEN — SNTSIDL — RCVEN TXM(1) TXPOL(1) CRCEN
bit 15 bit 8
R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0

PPP SPCEN(2) — PS — NIBCNT2 NIBCNT1 NIBCNT0
bit 7 bit 0
Legend:
bit 15 SNTEN: SENTx Enable bit

1 = SENTx is enabled
0 = SENTx is disabled
bit 13 SNTSIDL: SENTx Stop in Idle Mode bit
bit 11 RCVEN: SENTx Receive Enable bit
1 = SENTx operates as a receiver
0 = SENTx operates as a transmitter (sensor)
bit 10 TXM: SENTx Transmit Mode bit(1)
1 = SENTx transmits data frame only when triggered using the SYNCTXEN status bit
0 = SENTx transmits data frames continuously while SNTEN = 1
bit 9 TXPOL: SENTx Transmit Polarity bit(1)
1 = SENTx data output pin is low in the Idle state
0 = SENTx data output pin is high in the Idle state
bit 8 CRCEN: CRC Enable bit
Module in Receive Mode (RCVEN = 1):
1 = SENTx performs CRC verification on received data using the preferred J2716 method
0 = SENTx does not perform CRC verification on received data
Module in Transmit Mode (RCVEN = 1):
1 = SENTx automatically calculates CRC using the preferred J2716 method
0 = SENTx does not calculate CRC
bit 7 PPP: Pause Pulse Present bit
1 = SENTx is configured to transmit/receive SENT messages with pause pulse
0 = SENTx is configured to transmit/receive SENT messages without pause pulse
bit 6 SPCEN: Short PWM Code Enable bit(2)
1 = SPC control from external source is enabled
0 = SPC control from external source is disabled
bit 4 PS: SENTx Module Clock Prescaler (divider) bits
1 = Divide-by-4
0 = Divide-by-1
Note 1: This bit has no function in Receive mode (RCVEN = 1).

2: This bit has no function in Transmit mode (RCVEN = 0).

REGISTER 20-1: SENTxCON1: SENTx CONTROL REGISTER 1 (CONTINUED)

bit 2-0 NIBCNT<2:0>: Nibble Count Control bits
110 = Module transmits/receives 6 data nibbles in a SENT data pocket
Note 1: This bit has no function in Receive mode (RCVEN = 1).

2: This bit has no function in Transmit mode (RCVEN = 0).

REGISTER 20-2: SENTxSTAT: SENTx STATUS REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R/C-0 R-0 R/W-0, HC

PAUSE NIB2 NIB1 NIB0 CRCERR FRMERR RXIDLE SYNCTXEN(1)
bit 7 bit 0
Legend: C = Clearable bit HC = Hardware Clearable bit


bit 7 PAUSE: Pause Period Status bit
1 = The module is transmitting/receiving a pause period
0 = The module is not transmitting/receiving a pause period
bit 6-4 NIB<2:0>: Nibble Status bit
Module in Transmit Mode (RCVEN = 0):
111 = Module is transmitting a CRC nibble
110 = Module is transmitting Data Nibble 6
000 = Module is transmitting a status nibble or pause period, or is not transmitting
111 = Module is receiving a CRC nibble or was receiving this nibble when an error occurred
110 = Module is receiving Data Nibble 6 or was receiving this nibble when an error occurred
000 = Module is receiving a status nibble or waiting for Sync
bit 3 CRCERR: CRC Status bit (Receive mode only)
1 = A CRC error occurred for the 1-6 data nibbles in SENTxDATH/L
0 = A CRC error has not occurred
bit 2 FRMERR: Framing Error Status bit (Receive mode only)
1 = A data nibble was received with less than 12 tick periods or greater than 27 tick periods
0 = Framing error has not occurred
bit 1 RXIDLE: SENTx Receiver Idle Status bit (Receive mode only)
1 = The SENTx data bus has been Idle (high) for a period of SYNCMAX<15:0> or greater
0 = The SENTx data bus is not Idle
Note 1: In Receive mode (RCVEN = 1), the SYNCTXEN bit is read-only.

REGISTER 20-2: SENTxSTAT: SENTx STATUS REGISTER (CONTINUED)

bit 0 SYNCTXEN: SENTx Synchronization Period Status/Transmit Enable bit(1)
1 = A valid synchronization period was detected; the module is receiving nibble data
0 = No synchronization period has been detected; the module is not receiving nibble data
Module in Asynchronous Transmit Mode (RCVEN = 0, TXM = 0):
The bit always reads as ‘1’ when the module is enabled, indicating the module transmits SENTx data
frames continuously. The bit reads ‘0’ when the module is disabled.
Module in Synchronous Transmit Mode (RCVEN = 0, TXM = 1):
1 = The module is transmitting a SENTx data frame
0 = The module is not transmitting a data frame, user software may set SYNCTXEN to start another
data frame transmission
Note 1: In Receive mode (RCVEN = 1), the SYNCTXEN bit is read-only.

REGISTER 20-3: SENTxDATL: SENTx RECEIVE DATA REGISTER LOW(1)

DATA4<3:0> DATA5<3:0>
bit 15 bit 8

DATA6<3:0> CRC<3:0>
bit 7 bit 0
Legend:
bit 15-12 DATA4<3:0>: Data Nibble 4 Data bits

bit 3-0 CRC<3:0>: CRC Nibble Data bits
Note 1: Register bits are read-only in Receive mode (RCVEN = 1). In Transmit mode, the CRC<3:0> bits are
read-only when automatic CRC calculation is enabled (RCVEN = 0, CRCEN = 1).
REGISTER 20-4: SENTxDATH: SENTx RECEIVE DATA REGISTER HIGH(1)

STAT<3:0> DATA1<3:0>
bit 15 bit 8

DATA2<3:0> DATA3<3:0>
bit 7 bit 0
Legend:
bit 15-12 STAT<3:0>: Status Nibble Data bits

Note 1: Register bits are read-only in Receive mode (RCVEN = 1). In Transmit mode, the CRC<3:0> bits are
read-only when automatic CRC calculation is enabled (RCVEN = 0, CRCEN = 1).

NOTES:

21.0 UNIVERSAL ASYNCHRONOUS hardware flow control option with the UxCTS and
UxRTS pins, and also includes an IrDA® encoder and
RECEIVER TRANSMITTER decoder.
(UART)
Note: Hardware flow control using UxRTS and
Note 1: This data sheet summarizes the features UxCTS is not available on all pin count
of the dsPIC33EVXXXGM00X/10X devices. See the “Pin Diagrams” section
family of devices. It is not intended to be a for availability.
complement the information in this data The primary features of the UARTx module are:
sheet, refer to “Universal Asynchro- • Full-Duplex, 8 or 9-Bit Data Transmission through
nous Receiver Transmitter (UART)” the UxTX and UxRX Pins
(DS70000582) in the “dsPIC33/PIC24 • Even, Odd or No Parity Options (for 8-bit data)
Family Reference Manual”, which is
• One or Two Stop Bits
available from the Microchip web site
(www.microchip.com). • Hardware Flow Control Option with UxCTS and
UxRTS Pins
• Fully Integrated Baud Rate Generator with 16-Bit
Prescaler
Section 4.0 “Memory Organization” in • Baud Rates Ranging from 4.375 Mbps to 67 bps at
this data sheet for device-specific register 16x mode at 70 MIPS
and bit information. • Baud Rates Ranging from 17.5 Mbps to 267 bps at
4x mode at 70 MIPS
The dsPIC33EVXXXGM00X/10X family of devices • 4-Deep First-In First-Out (FIFO) Transmit Data
contains two UART modules. Buffer
The Universal Asynchronous Receiver Transmitter • 4-Deep FIFO Receive Data Buffer
(UART) module is one of the serial I/O modules • Parity, Framing and Buffer Overrun Error Detection
available in the dsPIC33EVXXXGM00X/10X device
• Support for 9-Bit mode with Address Detect
family. The UART is a full-duplex, asynchronous
(9th bit = 1)
system that can communicate with peripheral devices,
such as personal computers, LIN/J2602, RS-232 and • Transmit and Receive Interrupts
RS-485 interfaces. The module also supports a • A Separate Interrupt for All UART Error Conditions
FIGURE 21-1: UARTx SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA®
Hardware Flow Control UxRTS/BCLKx

UxCTS
UARTx Receiver UxRX
UARTx Transmitter UxTX

21.1 UART Helpful Tips 2. The first character received on wake-up from
Sleep mode, caused by activity on the UxRX pin
1. In multi-node direct connect UART networks, of the UART module, will be invalid. In Sleep
UART receive inputs react to the complementary mode, peripheral clocks are disabled. By the
logic level defined by the URXINV bit time the oscillator system has restarted and
(UxMODE<4>), which defines the Idle state, the stabilized from Sleep mode, the baud rate bit
default of which is logic high (i.e., URXINV = 0). sampling clock, relative to the incoming UxRX
Because remote devices do not initialize at the bit timing, is no longer synchronized, resulting in
same time, it is likely that one of the devices, the first character being invalid. This is to be
because the RX line is floating, will trigger a Start expected.
bit detection and will cause the first byte received,
after the device has been initialized, to be invalid.
To avoid this situation, the user should use a pull-
up or pull-down resistor on the RX pin, depending
on the value of the URXINV bit.
a) If URXINV = 0, use a pull-up resistor on the
RX pin.
b) If URXINV = 1, use a pull-down resistor on
the RX pin.

21.2 UART Control Registers
REGISTER 21-1: UxMODE: UARTx MODE REGISTER

R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
(1) (2)
UARTEN — USIDL IREN RTSMD — UEN1 UEN0
bit 15 bit 8
R/W-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WAKE LPBACK ABAUD URXINV BRGH PDSEL1 PDSEL0 STSEL
bit 7 bit 0

bit 15 UARTEN: UARTx Enable bit(1)

1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>
0 = UARTx is disabled; all UARTx pins are controlled by PORT latches; UARTx power consumption
is minimal
bit 13 USIDL: UARTx Stop in Idle Mode bit
bit 12 IREN: IrDA® Encoder and Decoder Enable bit(2)
1 = IrDA encoder and decoder are enabled
0 = IrDA encoder and decoder are disabled
bit 11 RTSMD: Mode Selection for UxRTS Pin bit
1 = UxRTS pin is in Simplex mode
0 = UxRTS pin is in Flow Control mode
bit 9-8 UEN<1:0>: UARTx Pin Enable bits
11 = UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin is controlled by PORT latches(3)
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used(4)
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by PORT latches(4)
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins are controlled by
PORT latches
bit 7 WAKE: UARTx Wake-up on Start bit Detect During Sleep Mode Enable bit
1 = UARTx continues to sample the UxRX pin; interrupt is generated on the falling edge, bit is cleared
in hardware on the following rising edge
0 = Wake-up is not enabled
bit 6 LPBACK: UARTx Loopback Mode Select bit
1 = Loopback mode is enabled
0 = Loopback mode is disabled
Note 1: Refer to “Universal Asynchronous Receiver Transmitter (UART)” (DS70000582) in the

“dsPIC33/PIC24 Family Reference Manual” for information on enabling the UART module for receive or
transmit operation.
2: This feature is only available for the 16x BRG mode (BRGH = 0).
3: This feature is only available on 44-pin and 64-pin devices.
4: This feature is only available on 64-pin devices.

REGISTER 21-1: UxMODE: UARTx MODE REGISTER (CONTINUED)

bit 5 ABAUD: Auto-Baud Enable bit
1 = Baud rate measurement on the next character is enabled – requires reception of a Sync field (55h)
before other data; cleared in hardware upon completion
0 = Baud rate measurement is disabled or has completed
bit 4 URXINV: UARTx Receive Polarity Inversion bit
1 = UxRX Idle state is ‘0’
0 = UxRX Idle state is ‘1’
bit 3 BRGH: High Baud Rate Enable bit
1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)
0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode)
bit 2-1 PDSEL<1:0>: Parity and Data Selection bits
11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
bit 0 STSEL: Stop Bit Selection bit
1 = Two Stop bits
0 = One Stop bit
Note 1: Refer to “Universal Asynchronous Receiver Transmitter (UART)” (DS70000582) in the

“dsPIC33/PIC24 Family Reference Manual” for information on enabling the UART module for receive or
transmit operation.
2: This feature is only available for the 16x BRG mode (BRGH = 0).
3: This feature is only available on 44-pin and 64-pin devices.
4: This feature is only available on 64-pin devices.

REGISTER 21-2: UxSTA: UARTx STATUS AND CONTROL REGISTER

R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R/W-0 R-0 R-1
(1)
UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/C-0 R-0

URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA
bit 7 bit 0
Legend: C = Clearable bit HC = Hardware Clearable bit

bit 15,13 UTXISEL<1:0>: UARTx Transmission Interrupt Mode Selection bits

10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result,
the transmit buffer becomes empty
01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
operations are completed
00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at
least one character open in the transmit buffer)
bit 14 UTXINV: UARTx Transmit Polarity Inversion bit
If IREN = 0:
1 = UxTX Idle state is ‘0’
0 = UxTX Idle state is ‘1’
If IREN = 1:
1 = IrDA® encoded UxTX Idle state is ‘1’
0 = IrDA encoded UxTX Idle state is ‘0’
bit 11 UTXBRK: UARTx Transmit Break bit
1 = Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop
bit; cleared by hardware upon completion
0 = Sync Break transmission is disabled or has completed
bit 10 UTXEN: UARTx Transmit Enable bit(1)
1 = Transmit is enabled, UxTX pin is controlled by UARTx
0 = Transmit is disabled, any pending transmission is aborted and the buffer is reset; UxTX pin is
controlled by the PORT
bit 9 UTXBF: UARTx Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written
bit 8 TRMT: Transmit Shift Register (TSR) Empty bit (read-only)
1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit Shift Register is not empty, a transmission is in progress or queued
bit 7-6 URXISEL<1:0>: UARTx Receive Interrupt Mode Selection bits
11 = Interrupt is set on UxRSR transfer, making the receive buffer full (i.e., has 4 data characters)
10 = Interrupt is set on UxRSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters)
0x = Interrupt is set when any character is received and transferred from the UxRSR to the receive
buffer; receive buffer has one or more characters
Note 1: Refer to “Universal Asynchronous Receiver Transmitter (UART)” (DS70000582) in the “dsPIC33/
PIC24 Family Reference Manual” for information on enabling the UART module for transmit operation.

REGISTER 21-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)

bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1 = Address Detect mode is enabled; if 9-bit mode is not selected, this does not take effect
0 = Address Detect mode is disabled
bit 4 RIDLE: Receiver Idle bit (read-only)
1 = Receiver is Idle
0 = Receiver is active
bit 3 PERR: Parity Error Status bit (read-only)
1 = Parity error has been detected for the current character (character at the top of the receive FIFO)
0 = Parity error has not been detected
bit 2 FERR: Framing Error Status bit (read-only)
1 = Framing error has been detected for the current character (character at the top of the receive
FIFO)
0 = Framing error has not been detected
bit 1 OERR: Receive Buffer Overrun Error Status bit (clear/read-only)
1 = Receive buffer has overflowed
0 = Receive buffer has not overflowed; clearing a previously set OERR bit (1  0 transition) resets
the receive buffer and the UxRSR to the empty state
bit 0 URXDA: UARTx Receive Buffer Data Available bit (read-only)
1 = Receive buffer has data, at least one more character can be read
0 = Receive buffer is empty
Note 1: Refer to “Universal Asynchronous Receiver Transmitter (UART)” (DS70000582) in the “dsPIC33/
PIC24 Family Reference Manual” for information on enabling the UART module for transmit operation.

22.0 CONTROLLER AREA The CAN module features are as follows:

NETWORK (CAN) MODULE • Implementation of the CAN Protocol, CAN 1.2,
(dsPIC33EVXXXGM10X CAN 2.0A and CAN 2.0B
• Standard and Extended Data Frames
DEVICES ONLY)
• 0 to 8-Byte Data Length
Note 1: This data sheet summarizes the features of • Programmable Bit Rate, up to 1 Mbit/sec
the dsPIC33EVXXXGM00X/10X family of • Automatic Response to Remote Transmission
devices. It is not intended to be a Requests
• Up to Eight Transmit Buffers with Application
Specified Prioritization and Abort Capability (each
sheet, refer to “Enhanced Controller
buffer can contain up to 8 bytes of data)
Area Network (ECAN™)” (DS70353) in
the “dsPIC33/PIC24 Family Reference • Up to 32 Receive Buffers (each buffer can contain
Manual”, which is available from the up to 8 bytes of data)
Microchip web site (www.microchip.com). • Up to 16 Full (Standard/Extended Identifier)
Acceptance Filters
described in this section may not be • Three Full Acceptance Filter Masks
available on all devices. Refer to • DeviceNet™ Addressing Support
Section 4.0 “Memory Organization” in • Programmable Wake-up Functionality with
this data sheet for device-specific register Integrated Low-Pass Filter
and bit information. • Programmable Loopback Mode Supports
Self-Test Operation
22.1 Overview • Signaling through Interrupt Capabilities for All
CAN Receiver and Transmitter Error States
The Controller Area Network (CAN) module is a serial
• Programmable Clock Source
interface, useful for communicating with other CAN
modules or microcontroller devices. This interface/ • Programmable Link to Input Capture 2 (IC2)
protocol was designed to allow communications within module for Timestamping and Network
noisy environments. The dsPIC33EVXXXGM10X Synchronization
devices contain one CAN module. • Low-Power Sleep and Idle Modes
The CAN module is a communication controller imple- The CAN bus module consists of a protocol engine and
menting the CAN 2.0 A/B protocol, as defined in the message buffering/control. The CAN protocol engine
BOSCH CAN specification. The module supports handles all functions for receiving and transmitting
CAN 1.2, CAN 2.0A, CAN 2.0B Passive and CAN 2.0B messages on the CAN bus. Messages are transmitted
Active versions of the protocol. The module implemen- by first loading the appropriate data registers. Status
tation is a full CAN system. The CAN specification is and errors can be checked by reading the appropriate
not covered within this data sheet. The reader can refer registers. Any message detected on the CAN bus is
to the BOSCH CAN specification for further details. checked for errors, and then matched against filters to
see if it should be received and stored in one of the
Receive registers.
Figure 22-1 shows a block diagram of the CANx
module.

FIGURE 22-1: CANx MODULE BLOCK DIAGRAM
RxF15 Filter
RxF14 Filter
RxF13 Filter
RxF12 Filter
RxF11 Filter
DMA Controller
RxF10 Filter
RxF9 Filter
RxF8 Filter
TRB7 TX/RX Buffer Control Register RxF7 Filter
TRB2 TX/RX Buffer Control Register RxF2 Filter RxM2 Mask

Transmit Byte Message Assembly

Sequencer Buffer
Control
CPU
Configuration Bus
Logic
CAN Protocol
Engine
Interrupts
CxTx CxRx
22.2 Modes of Operation Modes are requested by setting the REQOP<2:0> bits
(CxCTRL1<10:8>). Entry into a mode is Acknowledged
The CANx module can operate in one of several by monitoring the OPMODE<2:0> bits (CxCTRL1<7:5>).
operation modes selected by the user. These modes The module does not change the mode and the
include: OPMODEx bits until a change in mode is acceptable,
• Initialization mode generally during bus Idle time, which is defined as at least
• Disable mode 11 consecutive recessive bits.
• Normal Operation mode
• Listen Only mode
• Listen All Messages mode
• Loopback mode

22.3 CAN Control Registers
REGISTER 22-1: CxCTRL1: CANx CONTROL REGISTER 1

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0
— — CSIDL ABAT CANCKS REQOP2 REQOP1 REQOP0
bit 15 bit 8
R-1 R-0 R-0 U-0 R/W-0 U-0 U-0 R/W-0

OPMODE2 OPMODE1 OPMODE0 — CANCAP — — WIN
bit 7 bit 0
Legend:

bit 13 CSIDL: CANx Stop in Idle Mode bit
bit 12 ABAT: Abort All Pending Transmissions bit
1 = Signals all transmit buffers to abort transmission
0 = Module will clear this bit when all transmissions are aborted
bit 11 CANCKS: CANx Module Clock (FCAN) Source Select bit
1 = FCAN is equal to 2 * FP
0 = FCAN is equal to FP
bit 10-8 REQOP<2:0>: Request Operation Mode bits
111 = Sets Listen All Messages mode
110 = Reserved
101 = Reserved
100 = Sets Configuration mode
011 = Sets Listen Only mode
010 = Sets Loopback mode
001 = Sets Disable mode
000 = Sets Normal Operation mode
bit 7-5 OPMODE<2:0>: Operation Mode bits
111 = Module is in Listen All Messages mode
110 = Reserved
101 = Reserved
100 = Module is in Configuration mode
011 = Module is in Listen Only mode
010 = Module is in Loopback mode
001 = Module is in Disable mode
000 = Module is in Normal Operation mode
bit 3 CANCAP: CANx Message Receive Timer Capture Event Enable bit
1 = Enables input capture based on CAN message receive
0 = Disables CAN capture
bit 0 WIN: SFR Map Window Select bit
1 = Uses filter window
0 = Uses buffer window

REGISTER 22-2: CxCTRL2: CANx CONTROL REGISTER 2

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0

— — — DNCNT<4:0>
bit 7 bit 0
Legend:

bit 4-0 DNCNT<4:0>: DeviceNet™ Filter Bit Number bits
10010-11111 = Invalid selection
10001 = Compare up to Data Byte 3, bit 6 with EID<17>
•
•
•
00001 = Compare up to Data Byte 1, bit 7 with EID<0>
00000 = Do not compare data bytes

REGISTER 22-3: CxVEC: CANx INTERRUPT CODE REGISTER

U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0
— — — FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0
bit 15 bit 8
U-0 R-1 R-0 R-0 R-0 R-0 R-0 R-0

— ICODE6 ICODE5 ICODE4 ICODE3 ICODE2 ICODE1 ICODE0
bit 7 bit 0
Legend:

bit 12-8 FILHIT<4:0>: Filter Hit Number bits
10000-11111 = Reserved
01111 = Filter 15
•
•
•
00001 = Filter 1
00000 = Filter 0
bit 6-0 ICODE<6:0>: Interrupt Flag Code bits
1000101-1111111 = Reserved
1000100 = FIFO almost full interrupt
1000011 = Receiver overflow interrupt
1000010 = Wake-up interrupt
1000001 = Error interrupt
1000000 = No interrupt
•
•
•
0010000-0111111 = Reserved
0001111 = RB15 buffer interrupt
•
•
•
0000111 = TRB7 buffer interrupt
0000000 = TRB0 Buffer interrupt

REGISTER 22-4: CxFCTRL: CANx FIFO CONTROL REGISTER

R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0
DMABS2 DMABS1 DMABS0 — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — FSA5 FSA4 FSA3 FSA2 FSA1 FSA0
bit 7 bit 0
Legend:
bit 15-13 DMABS<2:0>: DMA Buffer Size bits

111 = Reserved
110 = 32 buffers in RAM
bit 5-0 FSA<5:0>: FIFO Area Starts with Buffer bits
11111 = Receive Buffer RB31
11110 = Receive Buffer RB30
•
•
•
00001 = TX/RX Buffer TRB1
00000 = TX/RX Buffer TRB0

REGISTER 22-5: CxFIFO: CANx FIFO STATUS REGISTER

U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0
— — FBP5 FBP4 FBP3 FBP2 FBP1 FBP0
bit 15 bit 8
U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0

— — FNRB5 FNRB4 FNRB3 FNRB2 FNRB1 FNRB0
bit 7 bit 0
Legend:

bit 13-8 FBP<5:0>: FIFO Buffer Pointer bits
011111 = RB31 buffer
•
•
•
000001 = TRB1 buffer
bit 5-0 FNRB<5:0>: FIFO Next Read Buffer Pointer bits
•
•
•

REGISTER 22-6: CxINTF: CANx INTERRUPT FLAG REGISTER

U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0
— — TXBO TXBP RXBP TXWAR RXWAR EWARN
bit 15 bit 8
R/C-0 R/C-0 R/C-0 U-0 R/C-0 R/C-0 R/C-0 R/C-0

IVRIF WAKIF ERRIF — FIFOIF RBOVIF RBIF TBIF
bit 7 bit 0
Legend: C = Writable bit, but only ‘0’ can be written to clear the bit

bit 13 TXBO: Transmitter in Error State Bus Off bit
1 = Transmitter is in Bus Off state
0 = Transmitter is not in Bus Off state
bit 12 TXBP: Transmitter in Error State Bus Passive bit
1 = Transmitter is in Bus Passive state
0 = Transmitter is not in Bus Passive state
bit 11 RXBP: Receiver in Error State Bus Passive bit
1 = Receiver is in Bus Passive state
0 = Receiver is not in Bus Passive state
bit 10 TXWAR: Transmitter in Error State Warning bit
1 = Transmitter is in Error Warning state
0 = Transmitter is not in Error Warning state
bit 9 RXWAR: Receiver in Error State Warning bit
1 = Receiver is in Error Warning state
0 = Receiver is not in Error Warning state
bit 8 EWARN: Transmitter or Receiver in Error State Warning bit
1 = Transmitter or receiver is in Error Warning state
0 = Transmitter or receiver is not in Error Warning state
bit 7 IVRIF: Invalid Message Interrupt Flag bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 6 WAKIF: Bus Wake-up Activity Interrupt Flag bit
bit 5 ERRIF: Error Interrupt Flag bit (multiple sources in CxINTF<13:8> register)
bit 3 FIFOIF: FIFO Almost Full Interrupt Flag bit
bit 2 RBOVIF: RX Buffer Overflow Interrupt Flag bit

REGISTER 22-6: CxINTF: CANx INTERRUPT FLAG REGISTER (CONTINUED)

bit 1 RBIF: RX Buffer Interrupt Flag bit
bit 0 TBIF: TX Buffer Interrupt Flag bit
REGISTER 22-7: CxINTE: CANx INTERRUPT ENABLE REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

IVRIE WAKIE ERRIE — FIFOIE RBOVIE RBIE TBIE
bit 7 bit 0
Legend:

bit 7 IVRIE: Invalid Message Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 6 WAKIE: Bus Wake-up Activity Interrupt Enable bit
bit 5 ERRIE: Error Interrupt Enable bit
bit 3 FIFOIE: FIFO Almost Full Interrupt Enable bit
bit 2 RBOVIE: RX Buffer Overflow Interrupt Enable bit
bit 1 RBIE: RX Buffer Interrupt Enable bit
bit 0 TBIE: TX Buffer Interrupt Enable bit

REGISTER 22-8: CxEC: CANx TRANSMIT/RECEIVE ERROR COUNT REGISTER

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
TERRCNT<7:0>
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

RERRCNT<7:0>
bit 7 bit 0
Legend:
bit 15-8 TERRCNT<7:0>: Transmit Error Count bits

bit 7-0 RERRCNT<7:0>: Receive Error Count bits
REGISTER 22-9: CxCFG1: CANx BAUD RATE CONFIGURATION REGISTER 1

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
bit 7 bit 0
Legend:

bit 7-6 SJW<1:0>: Synchronization Jump Width bits
11 = Length is 4 x TQ
bit 5-0 BRP<5:0>: Baud Rate Prescaler bits
11 1111 = TQ = 2 x 64 x 1/FCAN
•
•
•
00 0010 = TQ = 2 x 3 x 1/FCAN
00 0001 = TQ = 2 x 2 x 1/FCAN
00 0000 = TQ = 2 x 1 x 1/FCAN

REGISTER 22-10: CxCFG2: CANx BAUD RATE CONFIGURATION REGISTER 2

U-0 R/W-x U-0 U-0 U-0 R/W-x R/W-x R/W-x
— WAKFIL — — — SEG2PH2 SEG2PH1 SEG2PH0
bit 15 bit 8

SEG2PHTS SAM SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2 PRSEG1 PRSEG0
bit 7 bit 0
Legend:

bit 14 WAKFIL: Select CAN Bus Line Filter for Wake-up bit
1 = Uses CAN bus line filter for wake-up
0 = CAN bus line filter is not used for wake-up
bit 10-8 SEG2PH<2:0>: Phase Segment 2 bits
•
•
•
bit 7 SEG2PHTS: Phase Segment 2 Time Select bit
1 = Freely programmable
0 = Maximum of SEG1PH<2:0> bits or Information Processing Time (IPT), whichever is greater
bit 6 SAM: Sample of the CAN Bus Line bit
1 = Bus line is sampled three times at the sample point
0 = Bus line is sampled once at the sample point
bit 5-3 SEG1PH<2:0>: Phase Segment 1 bits
•
•
•
bit 2-0 PRSEG<2:0>: Propagation Time Segment bits
•
•
•

REGISTER 22-11: CxFEN1: CANx ACCEPTANCE FILTER ENABLE REGISTER 1

FLTEN<15:8>
bit 15 bit 8

FLTEN<7:0>
bit 7 bit 0
Legend:
bit 15-0 FLTEN<15:0>: Enable Filter n to Accept Messages bits

1 = Enables Filter n
0 = Disables Filter n
REGISTER 22-12: CxBUFPNT1: CANx FILTERS 0-3 BUFFER POINTER REGISTER 1

F3BP3 F3BP2 F3BP1 F3BP0 F2BP3 F2BP2 F2BP1 F2BP0
bit 15 bit 8

bit 7 bit 0
Legend:
bit 15-12 F3BP<3:0>: RX Buffer Mask for Filter 3 bits

1111 = Filter hits received in RX FIFO buffer
1110 = Filter hits received in RX Buffer 14
•
•
•
bit 11-8 F2BP<3:0>: RX Buffer Mask for Filter 2 bits (same values as bits 15-12)


bit 15 bit 8

bit 7 bit 0
Legend:

•
•
•


bit 15 bit 8

bit 7 bit 0
Legend:

•
•
•


bit 15 bit 8

bit 7 bit 0
Legend:

•
•
•

REGISTER 22-16: CxRXFnSID: CANx ACCEPTANCE FILTER n STANDARD IDENTIFIER

REGISTER (n = 0-15)
SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3
bit 15 bit 8
R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x

SID2 SID1 SID0 — EXIDE — EID17 EID16
bit 7 bit 0
Legend:
bit 15-5 SID<10:0>: Standard Identifier bits

1 = Message address bit, SIDx, must be ‘1’ to match filter
0 = Message address bit, SIDx, must be ‘0’ to match filter
bit 3 EXIDE: Extended Identifier Enable bit
If MIDE = 1:
1 = Matches only messages with Extended Identifier addresses
0 = Matches only messages with Standard Identifier addresses
If MIDE = 0:
Ignores EXIDE bit.
bit 1-0 EID<17:16>: Extended Identifier bits
1 = Message address bit, EIDx, must be ‘1’ to match filter
REGISTER 22-17: CxRXFnEID: CANx ACCEPTANCE FILTER n EXTENDED IDENTIFIER

REGISTER (n = 0-15)
EID<15:8>
bit 15 bit 8

EID<7:0>
bit 7 bit 0
Legend:


REGISTER 22-18: CxFMSKSEL1: CANx FILTERS 7-0 MASK SELECTION REGISTER 1

F7MSK1 F7MSK0 F6MSK1 F6MSK0 F5MSK1 F5MSK0 F4MSK1 F4MSK0
bit 15 bit 8

bit 7 bit 0
Legend:
bit 15-14 F7MSK<1:0>: Mask Source for Filter 7 bit

11 = Reserved
10 = Acceptance Mask 2 registers contain the mask
bit 13-12 F6MSK<1:0>: Mask Source for Filter 6 bit (same values as bits 15-14)

REGISTER 22-19: CxFMSKSEL2: CANx FILTERS 15-8 MASK SELECTION REGISTER 2

F15MSK1 F15MSK0 F14MSK1 F14MSK0 F13MSK‘ F13MSK0 F12MSK1 F12MSK0
bit 15 bit 8

bit 7 bit 0
Legend:
bit 15-14 F15MSK<1:0>: Mask Source for Filter 15 bit

11 = Reserved

REGISTER 22-20: CxRXMnSID: CANx ACCEPTANCE FILTER MASK n STANDARD IDENTIFIER

REGISTER (n = 0-2)
SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3
bit 15 bit 8
R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x

SID2 SID1 SID0 — MIDE — EID17 EID16
bit 7 bit 0
Legend:

1 = Includes bit, SIDx, in filter comparison
0 = Bit, SIDx, is a don’t care in filter comparison
bit 3 MIDE: Identifier Receive Mode bit
1 = Matches only message types (standard or extended address) that correspond to the EXIDE bit in
the filter
0 = Matches either standard or extended address message if filters match, i.e., if:
(Filter SID) = (Message SID) or if (Filter SID/EID) = (Message SID/EID)
1 = Includes bit, EIDx, in filter comparison
0 = Bit, EIDx, is a don’t care in filter comparison
REGISTER 22-21: CxRXMnEID: CANx ACCEPTANCE FILTER MASK n EXTENDED IDENTIFIER

REGISTER (n = 0-2)
EID<15:8>
bit 15 bit 8

EID<7:0>
bit 7 bit 0
Legend:

1 = Includes bit, EIDx, in filter comparison
0 = Bit, EIDx, is a don’t care in filter comparison

REGISTER 22-22: CxRXFUL1: CANx RECEIVE BUFFER FULL REGISTER 1

R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0
RXFUL<15:8>
bit 15 bit 8

RXFUL<7:0>
bit 7 bit 0
bit 15-0 RXFUL<15:0>: Receive Buffer n Full bits

1 = Buffer is full (set by module)
0 = Buffer is empty (cleared by user software)
REGISTER 22-23: CxRXFUL2: CANx RECEIVE BUFFER FULL REGISTER 2

RXFUL<31:24>
bit 15 bit 8

RXFUL<23:16>
bit 7 bit 0
bit 15-0 RXFUL<31:16>: Receive Buffer n Full bits

1 = Buffer is full (set by module)
0 = Buffer is empty (cleared by user software)

REGISTER 22-24: CxRXOVF1: CANx RECEIVE BUFFER OVERFLOW REGISTER 1

RXOVF<15:8>
bit 15 bit 8

RXOVF<7:0>
bit 7 bit 0
bit 15-0 RXOVF<15:0>: Receive Buffer n Overflow bits

1 = Module attempted to write to a full buffer (set by module)
0 = No overflow condition (cleared by user software)
REGISTER 22-25: CxRXOVF2: CANx RECEIVE BUFFER OVERFLOW REGISTER 2

RXOVF<31:24>
bit 15 bit 8

RXOVF<23:16>
bit 7 bit 0
bit 15-0 RXOVF<31:16>: Receive Buffer n Overflow bits

1 = Module attempted to write to a full buffer (set by module)
0 = No overflow condition (cleared by user software)

REGISTER 22-26: CxTRmnCON: CANx TX/RX BUFFER mn CONTROL REGISTER

(m = 0,2,4,6; n = 1,3,5,7)
R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
TXENn TXABTn TXLARBn TXERRn TXREQn RTRENn TXnPRI1 TXnPRI0
bit 15 bit 8
R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

TXENm TXABTm(1) TXLARBm(1) TXERRm(1) TXREQm RTRENm TXmPRI1 TXmPRI0
bit 7 bit 0
Legend:
bit 15-8 See Definition for bits 7-0, controls Buffer n.

bit 7 TXENm: TX/RX Buffer Selection bit
1 = Buffer, TRBm, is a transmit buffer
0 = Buffer, TRBm, is a receive buffer
bit 6 TXABTm: Message Aborted bit(1)
1 = Message was aborted
0 = Message completed transmission successfully
bit 5 TXLARBm: Message Lost Arbitration bit(1)
1 = Message lost arbitration while being sent
0 = Message did not lose arbitration while being sent
bit 4 TXERRm: Error Detected During Transmission bit(1)
1 = A bus error occurred while the message was being sent
0 = A bus error did not occur while the message was being sent
bit 3 TXREQm: Message Send Request bit
1 = Requests that a message be sent; the bit automatically clears when the message is successfully
sent
0 = Clearing the bit to ‘0’ while set requests a message abort
bit 2 RTRENm: Auto-Remote Transmit Enable bit
1 = When a remote transmit is received, TXREQ will be set
0 = When a remote transmit is received, TXREQ will be unaffected
bit 1-0 TXmPRI<1:0>: Message Transmission Priority bits
11 = Highest message priority
10 = High intermediate message priority
01 = Low intermediate message priority
00 = Lowest message priority
Note 1: This bit is cleared when TXREQm is set.
Note: The buffers, SID, EID, DLC, Data Field and Receive Status registers, are located in DMA RAM.

22.4 CAN Message Buffers

CAN Message Buffers are part of RAM memory. They
are not CAN Special Function Registers. The user appli-
cation must directly write into the RAM area that is
configured for CAN Message Buffers. The location and
size of the buffer area is defined by the user application.
BUFFER 22-1: CANx MESSAGE BUFFER WORD 0

U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x
— — — SID10 SID9 SID8 SID7 SID6
bit 15 bit 8

SID5 SID4 SID3 SID2 SID1 SID0 SRR IDE
bit 7 bit 0
Legend:

bit 1 SRR: Substitute Remote Request bit
When IDE = 0:
1 = Message will request remote transmission
0 = Normal message
When IDE = 1:
The SRR bit must be set to ‘1’.
bit 0 IDE: Extended Identifier bit
1 = Message will transmit an Extended Identifier
0 = Message will transmit a Standard Identifier

U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x
— — — — EID<17:14>
bit 15 bit 8

EID<13:6>
bit 7 bit 0
Legend:


(

EID5 EID4 EID3 EID2 EID1 EID0 RTR RB1
bit 15 bit 8
U-x U-x U-x R/W-x R/W-x R/W-x R/W-x R/W-x

— — — RB0 DLC3 DLC2 DLC1 DLC0
bit 7 bit 0
Legend:

bit 9 RTR: Remote Transmission Request bit
When IDE = 1:
1 = Message will request remote transmission
0 = Normal message
When IDE = 0:
The RTR bit is ignored.
bit 8 RB1: Reserved Bit 1
User must set this bit to ‘0’ per CAN protocol.
bit 4 RB0: Reserved Bit 0
User must set this bit to ‘0’ per CAN protocol.
bit 3-0 DLC<3:0>: Data Length Code bits

Byte 1<15:8>
bit 15 bit 8

Byte 0<7:0>
bit 7 bit 0
Legend:
bit 15-8 Byte 1<15:8>: CANx Message Byte 1 bits



Byte 3<15:8>
bit 15 bit 8

Byte 2<7:0>
bit 7 bit 0
Legend:


Byte 5<15:8>
bit 15 bit 8

Byte 4<7:0>
bit 7 bit 0
Legend:



Byte 7<15:8>
bit 15 bit 8

Byte 6<7:0>
bit 7 bit 0
Legend:


U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x
— — — FILHIT<4:0>(1)
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 7 bit 0
Legend:

bit 12-8 FILHIT<4:0>: Filter Hit Code bits(1)
Encodes number of filter that resulted in writing this buffer.
Note 1: Only written by module for receive buffers, unused for transmit buffers.

23.0 CHARGE TIME Together with other on-chip analog modules, the
CTMU can be used to precisely measure time,
MEASUREMENT UNIT (CTMU) measure capacitance, measure relative changes in
Note 1: This data sheet summarizes the features capacitance or generate output pulses that are
of the dsPIC33EVXXXGM00X/10X family independent of the system clock.
of devices. It is not intended to be a The CTMU module is ideal for interfacing with
comprehensive reference source. To capacitive-based sensors. The CTMU is controlled
complement the information in this data through three registers: CTMUCON1, CTMUCON2
sheet, refer to “Charge Time Measure- and CTMUICON. CTMUCON1 and CTMUCON2
ment Unit (CTMU)” (DS70661) in the enable the module and control edge source selection,
“dsPIC33/PIC24 Family Reference edge source polarity selection and edge sequencing.
Manual”, which is available on the The CTMUICON register controls the selection and
Microchip web site (www.microchip.com). trim of the current source.
The Charge Time Measurement Unit (CTMU) is a flexible

analog module that provides accurate differential time
measurement between pulse sources, as well as
asynchronous pulse generation. Its key features include:
• Nine Edge Input Trigger Sources
• Polarity Control for Each Edge Source
• Control of Edge Sequence
• Control of Response to Edges
• Time Measurement Resolution Down to 200 ps
• Accurate Current Source Suitable for Capacitive
Measurement
• On-Chip Temperature Measurement using a
Built-in Diode
• Pulse Generation Generates a Pulse using the
C1INB Comparator Input and Outputs the Pulse
onto the CTPLS Remappable Output

FIGURE 23-1: CTMU BLOCK DIAGRAM
CTMUCON1 or CTMUCON2
CTMUICON
CTED1 ITRIM<5:0>
IRNG<1:0>
CTED2
Current Source
FOSC
Edge
OSCI Pin Control
FRC Logic
EDG1STAT CTMU
BFRC Control Analog-to-Digital
EDG2STAT TGEN Trigger
LPRC Current Logic
Control
Timer1
OC1 Pulse
IC1 CTPLS
Generator
CMP1 CTMUI to ADC (1)
CTMUP
CTMU TEMP
CTMU C1IN1-
Temperature
Sensor
CDelay
CMP1
External Capacitor
for Pulse Generation
Current Control Selection TGEN EDG1STAT, EDG2STAT
CTMU TEMP 0 EDG1STAT = EDG2STAT

CTMUI to ADC 0 EDG1STAT  EDG2STAT
CTMUP 1 EDG1STAT  EDG2STAT
No Connect 1 EDG1STAT = EDG2STAT
Note 1: Current source to particular ANx pins is provided only when 10-Bit ADC mode is chosen.

23.1 CTMU Control Registers
REGISTER 23-1: CTMUCON1: CTMU CONTROL REGISTER 1

CTMUEN (2) (1)
— CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 7 bit 0
Legend:
bit 15 CTMUEN: CTMU Enable bit

1 = Module is enabled
0 = Module is disabled
bit 13 CTMUSIDL: CTMU Stop in Idle Mode bit
bit 12 TGEN: Time Generation Enable bit(2)
1 = Edge delay generation is enabled
0 = Edge delay generation is disabled
bit 11 EDGEN: Edge Enable bit
1 = Hardware modules are used to trigger edges (TMRx, CTEDx, etc.)
0 = Software is used to trigger edges (manual set of EDGxSTAT)
bit 10 EDGSEQEN: Edge Sequence Enable bit
1 = Edge 1 event must occur before Edge 2 event can occur
0 = No edge sequence is needed
bit 9 IDISSEN: Analog Current Source Control bit(1)
1 = Analog current source output is grounded
0 = Analog current source output is not grounded
bit 8 CTTRIG: ADC Trigger Control bit
1 = CTMU triggers the ADC start of conversion
0 = CTMU does not trigger the ADC start of conversion
Note 1: The ADC module Sample-and-Hold (S&H) capacitor is not automatically discharged between sample/
conversion cycles. Any software using the ADC as part of a capacitance measurement must discharge the
ADC capacitor before conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this func-
tion. The ADC must be sampling while the IDISSEN bit is active to connect the discharge sink to the
capacitor array.
2: If the TGEN bit is set to ‘1’, then the CMP1 module should be selected as the Edge 2 source in the
EDG2SELx bits field; otherwise, the module will not function.

REGISTER 23-2: CTMUCON2: CTMU CONTROL REGISTER 2

EDG1MOD EDG1POL EDG1SEL3 EDG1SEL2 EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0

EDG2MOD EDG2POL EDG2SEL3 EDG2SEL2 EDG2SEL1 EDG2SEL0 — —
bit 7 bit 0
Legend:
bit 15 EDG1MOD: Edge 1 Edge Sampling Mode Selection bit

1 = Edge 1 is edge-sensitive
0 = Edge 1 is level-sensitive
bit 14 EDG1POL: Edge 1 Polarity Select bit
1 = Edge 1 is programmed for a positive edge response
0 = Edge 1 is programmed for a negative edge response
bit 13-10 EDG1SEL<3:0>: Edge 1 Source Select bits
1111 = FOSC
1110 = OSCI pin
1101 = FRC Oscillator
1100 = BFRC Oscillator
1011 = Internal LPRC Oscillator
1010 = Reserved
1001 = Reserved
1000 = Reserved
0111 = Reserved
0110 = Reserved
0101 = Reserved
0100 = Reserved
0011 = CTED1 pin
0010 = CTED2 pin
0001 = OC1 module
0000 = TMR1 module
bit 9 EDG2STAT: Edge 2 Status bit
Indicates the status of Edge 2 and can be written to control the edge source.
1 = Edge 2 has occurred
0 = Edge 2 has not occurred
bit 8 EDG1STAT: Edge 1 Status bit
Indicates the status of Edge 1 and can be written to control the edge source.
1 = Edge 1 has occurred
0 = Edge 1 has not occurred
bit 7 EDG2MOD: Edge 2 Edge Sampling Mode Selection bit
1 = Edge 2 is edge-sensitive
0 = Edge 2 is level-sensitive
bit 6 EDG2POL: Edge 2 Polarity Select bit
1 = Edge 2 is programmed for a positive edge response
0 = Edge 2 is programmed for a negative edge response

REGISTER 23-2: CTMUCON2: CTMU CONTROL REGISTER 2 (CONTINUED)

bit 5-2 EDG2SEL<3:0>: Edge 2 Source Select bits
1111 = FOSC
1110 = OSCI pin
1100 = BFRC Oscillator
1011 = Internal LPRC Oscillator
1010 = Reserved
1001 = Reserved
1000 = Reserved
0111 = Reserved
0110 = Reserved
0101 = Reserved
0100 = CMP1 module
0011 = CTED2 pin
0010 = CTED1 pin
0001 = OCMP1 module
0000 = IC1 module

REGISTER 23-3: CTMUICON: CTMU CURRENT CONTROL REGISTER(3)

ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1(2) IRNG0(2)
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 7 bit 0
Legend:
bit 15-10 ITRIM<5:0>: Current Source Trim bits

011111 = Maximum positive change from nominal current + 62%
011110 = Maximum positive change from nominal current + 60%
•
•
•
000010 = Minimum positive change from nominal current + 4%
000001 = Minimum positive change from nominal current + 2%
000000 = Nominal current output specified by IRNG<1:0>
111111 = Minimum negative change from nominal current – 2%
111110 = Minimum negative change from nominal current – 4%
•
•
•
100010 = Maximum negative change from nominal current – 60%
100001 = Maximum negative change from nominal current – 62%
bit 9-8 IRNG<1:0>: Current Source Range Select bits(2)
11 = 100  Base Current
10 = 10  Base Current
01 = Base Current Level
00 = 1000  Base Current(1)
Note 1: This current range is not available for use with the internal temperature measurement diode.
2: Refer to the CTMU Current Source Specifications (Table 30-53) in Section 30.0 “Electrical Characteristics”
for the current range selection values.
3: Current sources are not generated when 12-Bit ADC mode is chosen. Current sources are active only
when 10-Bit ADC mode is chosen.

24.0 10-BIT/12-BIT 24.1.2 12-BIT ADC CONFIGURATION

ANALOG-TO-DIGITAL The 12-bit ADC configuration supports all the features
CONVERTER (ADC) listed previously, with the exception of the following:
• In the 12-bit configuration, conversion speeds of
Note 1: This data sheet summarizes the features up to 500 ksps are supported
• There is only one S&H amplifier in the 12-bit
of devices. It is not intended to be a
configuration. Therefore, simultaneous sampling
of multiple channels is not supported.
complement the information in this
data sheet, refer to “Analog-to-Digital The ADC has up to 36 analog inputs. The analog
Converter (ADC)” (DS70621) in the inputs, AN32 through AN63, are multiplexed, thus
“dsPIC33/PIC24 Family Reference providing flexibility in using any of these analog inputs
Manual”, which is available from the in addition to the analog inputs, AN0 through AN31.
Microchip web site (www.microchip.com). Since AN32 through AN63 are multiplexed, do not use
two channels simultaneously, since it may result in
erroneous output from the module. These analog
inputs are shared with op amp inputs and outputs, com-
parator inputs and external voltage references. When
op amp/comparator functionality is enabled, the analog
input that shares that pin is no longer available. The
actual number of analog input pins and op amps
The Analog-to-Digital (ADC) module in the depends on the specific device.
dsPIC33EVXXXGM00X/10X family devices supports A block diagram of the ADC module with connection
up to 36 analog input channels. options is shown in Figure 24-1. Figure 24-2 shows a
The ADC module can be configured by the user as block diagram of the ADC conversion clock period.
either a 10-bit, 4 Sample-and-Hold (S&H) ADC (default
configuration) or a 12-bit, 1 S&H ADC.
Note: The ADC module needs to be disabled
before modifying the AD12B bit.
24.1 Key Features

24.1.1 10-BIT ADC CONFIGURATION
The 10-bit ADC configuration has the following key
features:
• Successive Approximation (SAR) Conversion
• Conversion Speeds of up to 1.1 Msps
• Up to 36 Analog Input Pins
• Connections to Four Internal Op Amps
• Connections to the Charge Time Measurement Unit
(CTMU) and Temperature Measurement Diode
• Simultaneous Sampling of:
- Up to four analog input pins
- Four op amp outputs
• Combinations of Analog Inputs and Op Amp Outputs
• Automatic Channel Scan mode
• Selectable Conversion Trigger Source
• Selectable Buffer Fill modes
• Four Result Alignment Options (signed/unsigned,
fractional/integer)
• Operation during CPU Sleep and Idle Modes

FIGURE 24-1: ADCx MODULE BLOCK DIAGRAM WITH CONNECTION OPTIONS FOR ANx PINS AND OP AMPS
DS70005144E-page 286
This diagram depicts all of the available
ADC connection options to the four S&H 000000
amplifiers, which are designated: CH0,
AN0-AN31 Channel Scan 1
CH1, CH2 and CH3.
OA1-OA3, OA5
The ANx analog pins or op amp outputs are From CTMU
CH0SA<5:0>(1) 0
connected to the CH0-CH3 amplifiers Current Source (CTMUI)
111111
through the multiplexers, controlled by the S&H0 CSCNA
SFR control bits, CH0Sx, CH0Nx, + A
AN32-AN63 CH0Sx
CH123Sx and CH123Nx. 100000 CH0Sx CH0
(AN61-Band Gap Voltage – CH0SB<5:0>(1) B
AN62-CTMU Temp Diode
AN63-Not Connected) 111111 VREFL 0
1 CH0NA(1) A
CH0Nx
(1)
AN0/OA2OUT/RA0 CH0NB B
000 CH0Nx
001
PGEC1/AN4/C1IN1+/RPI34/RB2 ++ S&H1
CMP1
010 + CH123SA<2:0> A
/OA1 011 CH1 CH123Sx
PGED1/AN5/C1IN1-/RP35/RB3 –– – CH123SB<2:0> B
OA1 1xx
PGEC3/AN3/OA1OUT/RPI33/CTED1/RB1 CH123Sx
VREFL 0x
CH123NA<1:0> A
10 CH123Nx
AN9/RPI27/RA11 11 CH123NB<1:0> B
000 CH123Nx
AN1/C2IN1+/RA1
001 S&H2
+ 010 + Alternate Input
CH2 ALTS (MUX A/MUX B)
011
– – Selection
1xx
OA2
CH123Sx
VREFL 0x
10
AN10/RPI28/RA12 11
AVDD AVSS
PGED3/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 CH123Nx
000
ADC1BUF0(2,3)
AN8/C3IN1+/U1RTS/BCLK1/RC2 +
001 S&H3
010 + ADC1BUF1(3)
CH3 VREFH VREFL ADC1BUF2(3)
AN7/C3IN1-/C4IN1-/RC1 – 011 –
OA3 1xx
CH123Sx
AN6/OA3OUT/C4IN1+/RC0
VREFL 0x SAR ADC
10
AN11/C1IN2-/U1CTS/RC11 11
OA5IN+/AN24/C5IN3-/C5IN1+/SDO1/RP20/T1CK/RA4 + CH123Nx ADC1BUFE(3)

ADC1BUFF(3)
OA5IN-/AN27/C5IN1-/RP41/RB9 –
OA5
Note 1: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation.
2: When ADDMAEN (ADxCON4<8>) = 0, ADC1BUF0-ADC1BUFF are used.
3: When ADDMAEN (ADxCON4<8>) = 1 enabling DMA, only ADC1BUF0 is used.
FIGURE 24-2: ADCx CONVERSION CLOCK PERIOD BLOCK DIAGRAM
ADxCON3<15>
ADC Internal
1
RC Clock(2)
TAD
ADxCON3<7:0> 0
ADC Conversion
TP(1) Clock Multiplier
1, 2, 3, 4, 5,..., 256
Note 1: TP = 1/FP.
2: Refer to the ADC electrical specifications in Section 30.0 “Electrical Characteristics” for
the exact RC clock value.

24.2 ADC Helpful Tips 3. When the DMA module is enabled

(ADDMAEN = 1), the ADC module has only
1. The SMPIx control bits in the ADxCON2 registers: 1 ADC result buffer (i.e., ADCxBUF0) per ADC
a) Determine when the ADC interrupt flag is peripheral and the ADC conversion result must
set and an interrupt is generated, if be read, either by the CPU or DMA Controller,
enabled. before the next ADC conversion is complete to
b) When the CSCNA bit in the ADxCON2 reg- avoid overwriting the previous value.
ister is set to ‘1’, this determines when the 4. The DONE bit (ADxCON1<0>) is only cleared at
ADC analog scan channel list, defined in the start of each conversion and is set at the
the ADxCSSL/ADxCSSH registers, starts completion of the conversion, but remains set
over from the beginning. indefinitely, even through the next sample phase
c) When the DMA peripheral is not used until the next conversion begins. If application
(ADDMAEN = 0), this determines when code is monitoring the DONE bit in any kind of
the ADC Result Buffer Pointer to software loop, the user must consider this
ADC1BUF0-ADC1BUFF gets reset back behavior because the CPU code execution is
to the beginning at ADC1BUF0. faster than the ADC. As a result, in Manual
d) When the DMA peripheral is used Sample mode, particularly where the user’s
(ADDMAEN = 1), this determines when the code is setting the SAMP bit (ADxCON1<1>),
DMA Address Pointer is incremented after a the DONE bit should also be cleared by the user
sample/conversion operation. ADC1BUF0 is application just before setting the SAMP bit.
the only ADC buffer used in this mode. The 5. Enabling op amps, comparator inputs and exter-
ADC Result Buffer Pointer to ADC1BUF0- nal voltage references can limit the availability of
ADC1BUFF gets reset back to the beginning analog inputs (ANx pins). For example, when
at ADC1BUF0. The DMA address is Op Amp 2 is enabled, the pins for AN0, AN1 and
incremented after completion of every 32nd AN2 are used by the op amp’s inputs and output.
sample/conversion operation. Conversion This negates the usefulness of Alternate Input
results are stored in the ADC1BUF0 register mode since the MUX A selections use AN0-AN2.
for transfer to RAM using the DMA peripheral. Carefully study the ADC block diagram to
2. When the DMA module is disabled determine the configuration that will best suit
(ADDMAEN = 0), the ADC has 16 result buffers. your application. For configuration examples,
ADC conversion results are stored sequentially refer to “Analog-to-Digital Converter (ADC)”
in ADC1BUF0-ADC1BUFF, regardless of which (DS70621) in the “dsPIC33/PIC24 Family
analog inputs are being used subject to the Reference Manual”.
SMPIx bits and the condition described in 1.c)
above. There is no relationship between the
ANx input being measured and which ADC
buffer (ADC1BUF0-ADC1BUFF) that the
conversion results will be placed in.

24.3 ADC Control Registers
REGISTER 24-1: ADxCON1: ADCx CONTROL REGISTER 1

R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
ADON — ADSIDL ADDMABM — AD12B FORM1 FORM0
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0, HC, HS R/C-0, HC, HS
SSRC2 SSRC1 SSRC0 SSRCG SIMSAM ASAM SAMP DONE(1)
bit 7 bit 0
Legend: C = Clearable bit U = Unimplemented bit, read as ‘0’

R = Readable bit W = Writable bit HS = Hardware Settable bit HC = Hardware Clearable bit
bit 15 ADON: ADCx Operating Mode bit

1 = ADCx module is operating
0 = ADCx is off
bit 13 ADSIDL: ADCx Stop in Idle Mode bit
bit 12 ADDMABM: ADCx DMA Buffer Build Mode bit
1 = DMA buffers are written in the order of conversion; the module provides an address to the DMA
channel that is the same as the address used for the non-DMA stand-alone buffer
0 = DMA buffers are written in Scatter/Gather mode; the module provides a Scatter/Gather mode
address to the DMA channel based on the index of the analog input and the size of the DMA buffer
bit 10 AD12B: ADCx 10-Bit or 12-Bit Operation Mode bit
1 = 12-bit, 1-channel ADC operation
0 = 10-bit, 4-channel ADC operation
bit 9-8 FORM<1:0>: Data Output Format bits
For 10-Bit Operation:
11 = Signed fractional (DOUT = sddd dddd dd00 0000, where s = .NOT.d<9>)
10 = Fractional (DOUT = dddd dddd dd00 0000)
01 = Signed integer (DOUT = ssss sssd dddd dddd, where s = .NOT.d<9>)
00 = Integer (DOUT = 0000 00dd dddd dddd)
For 12-Bit Operation:
11 = Signed fractional (DOUT = sddd dddd dddd 0000, where s = .NOT.d<11>)
10 = Fractional (DOUT = dddd dddd dddd 0000)
01 = Signed integer (DOUT = ssss sddd dddd dddd, where s = .NOT.d<11>)
00 = Integer (DOUT = 0000 dddd dddd dddd)
Note 1: Do not clear the DONE bit in software if auto-sample is enabled (ASAM = 1).

REGISTER 24-1: ADxCON1: ADCx CONTROL REGISTER 1 (CONTINUED)

bit 7-5 SSRC<2:0>: Sample Clock Source Select bits
If SSRCG = 1:
111 = Reserved
110 = Reserved
101 = Reserved
100 = Reserved
011 = Reserved
010 = PWM Generator 3 primary trigger compare ends sampling and starts conversion
If SSRCG = 0:
111 = Internal counter ends sampling and starts conversion (auto-convert)
110 = CTMU ends sampling and starts conversion
101 = Reserved
100 = Timer5 compare ends sampling and starts conversion
011 = PWM primary Special Event Trigger ends sampling and starts conversion
010 = Timer3 compare ends sampling and starts conversion
001 = Active transition on the INT0 pin ends sampling and starts conversion
000 = Clearing the Sample bit (SAMP) ends sampling and starts conversion (Manual mode)
bit 4 SSRCG: Sample Trigger Source Group bit
See SSRC<2:0> for details.
bit 3 SIMSAM: Simultaneous Sample Select bit (only applicable when CHPS<1:0> = 01 or 1x)
In 12-Bit Mode (AD12B = 1), SIMSAM is Unimplemented and is Read as ‘0’:
1 = Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x) or samples CH0 and CH1
simultaneously (when CHPS<1:0> = 01)
0 = Samples multiple channels individually in sequence
bit 2 ASAM: ADCx Sample Auto-Start bit
1 = Sampling begins immediately after last conversion; SAMP bit is auto-set
0 = Sampling begins when SAMP bit is set
bit 1 SAMP: ADCx Sample Enable bit
1 = ADCx Sample-and-Hold amplifiers are sampling
0 = ADCx Sample-and-Hold amplifiers are holding
If ASAM = 0, software can write ‘1’ to begin sampling. Automatically set by hardware if ASAM = 1. If
SSRC<2:0> = 000, software can write ‘0’ to end sampling and start conversion. If SSRC<2:0> 000,
automatically cleared by hardware to end sampling and start conversion.
bit 0 DONE: ADCx Conversion Status bit(1)
1 = ADCx conversion cycle is completed.
0 = ADCx conversion has not started or is in progress
Automatically set by hardware when conversion is complete. Software can write ‘0’ to clear DONE bit
status (software not allowed to write ‘1’). Clearing this bit does NOT affect any operation in progress.
Automatically cleared by hardware at the start of a new conversion.
Note 1: Do not clear the DONE bit in software if auto-sample is enabled (ASAM = 1).


R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0
VCFG2(1) VCFG1(1) VCFG0(1) — — CSCNA CHPS1 CHPS0
bit 15 bit 8
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

BUFS SMPI4 SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS
bit 7 bit 0
Legend:
bit 15-13 VCFG<2:0>: Converter Voltage Reference Configuration bits(1)

Value VREFH VREFL
xxx AVDD AVSS
bit 10 CSCNA: Input Scan Select bit
1 = Scans inputs for CH0+ during Sample MUX A
0 = Does not scan inputs
bit 9-8 CHPS<1:0>: Channel Select bits
In 12-Bit Mode (AD21B = 1), CHPS<1:0> bits are Unimplemented and are Read as ‘0’:
1x = Converts CH0, CH1, CH2 and CH3
01 = Converts CH0 and CH1
00 = Converts CH0
bit 7 BUFS: Buffer Fill Status bit (only valid when BUFM = 1)
1 = ADCx is currently filling the second half of the buffer; the user application should access data in the
first half of the buffer
0 = ADCx is currently filling the first half of the buffer; the user application should access data in the
second half of the buffer
bit 6-2 SMPI<4:0>: Increment Rate bits
When ADDMAEN = 0:
x1111 = Generates interrupt after completion of every 16th sample/conversion operation
x1110 = Generates interrupt after completion of every 15th sample/conversion operation
•
•
•
x0001 = Generates interrupt after completion of every 2nd sample/conversion operation
x0000 = Generates interrupt after completion of every sample/conversion operation
When ADDMAEN = 1:
11111 = Increments the DMA address after completion of every 32nd sample/conversion operation
11110 = Increments the DMA address after completion of every 31st sample/conversion operation
•
•
•
00001 = Increments the DMA address after completion of every 2nd sample/conversion operation
00000 = Increments the DMA address after completion of every sample/conversion operation
Note 1: The ADCx VREFH Input is connected to AVDD and the VREFL input is connected to AVSS.

REGISTER 24-2: ADxCON2: ADCx CONTROL REGISTER 2 (CONTINUED)

bit 1 BUFM: Buffer Fill Mode Select bit
1 = Starts buffer filling the first half of the buffer on the first interrupt and the second half of the buffer
on the next interrupt
0 = Always starts filling the buffer from the Start address
bit 0 ALTS: Alternate Input Sample Mode Select bit
1 = Uses channel input selects for Sample MUX A on the first sample and Sample MUX B on the next sample
0 = Always uses channel input selects for Sample MUX A
Note 1: The ADCx VREFH Input is connected to AVDD and the VREFL input is connected to AVSS.


R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
(1) (1) (1) (1)
ADRC — — SAMC4 SAMC3 SAMC2 SAMC1 SAMC0(1)
bit 15 bit 8

ADCS7(2) ADCS6(2) ADCS5(2) ADCS4(2) ADCS3(2) ADCS2(2) ADCS1(2) ADCS0(2)
bit 7 bit 0
Legend:
bit 15 ADRC: ADCx Conversion Clock Source bit

1 = ADCx internal RC clock
0 = Clock derived from system clock
bit 12-8 SAMC<4:0>: Auto-Sample Time bits(1)
11111 = 31 TAD
•
•
•
00001 = 1 TAD
00000 = 0 TAD
bit 7-0 ADCS<7:0>: ADCx Conversion Clock Select bits(2)
11111111 = TP • (ADCS<7:0> + 1) = TP • 256 = TAD
•
•
•
00000010 = TP • (ADCS<7:0> + 1) = TP • 3 = TAD
00000001 = TP • (ADCS<7:0> + 1) = TP • 2 = TAD
00000000 = TP • (ADCS<7:0> + 1) = TP • 1 = TAD
Note 1: These bits are only used if SSRC<2:0> (ADxCON1<7:5>) = 111 and SSRCG (ADxCON1<4>) = 0.
2: These bits are not used if ADRC (ADxCON3<15>) = 1.


U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — ADDMAEN
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — DMABL2 DMABL1 DMABL0
bit 7 bit 0
Legend:

bit 8 ADDMAEN: ADCx DMA Enable bit
1 = Conversion results are stored in the ADC1BUF0 register for transfer to RAM using DMA
0 = Conversion results are stored in the ADC1BUF0 through ADC1BUFF registers; DMA will not be used
bit 2-0 DMABL<2:0>: Selects Number of DMA Buffer Locations per Analog Input bits
111 = Allocates 128 words of buffer to each analog input
000 = Allocates 1 word of buffer to each analog input

REGISTER 24-5: ADxCHS123: ADCx INPUT CHANNELS 1, 2, 3 SELECT REGISTER

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — CH123SB2 CH123SB1 CH123NB1 CH123NB0 CH123SB0
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — CH123SA2 CH123SA1 CH123NA1 CH123NA0 CH123SA0
bit 7 bit 0
Legend:

bit 12-11 CH123SB<2:1>: Channels 1, 2, 3 Positive Input Select for Sample B bits
1xx = CH1 positive input is AN0 (Op Amp 2), CH2 positive input is AN25 (Op Amp 5), CH3 positive
input is AN6 (Op Amp 3)
011 = CH1 positive input is AN3 (Op Amp 1), CH2 positive input is AN0 (Op Amp 2), CH3 positive input
is AN25 (Op Amp 5)
is AN6 (Op Amp 3)
001 = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5
bit 10-9 CH123NB<1:0>: Channels 1, 2, 3 Negative Input Select for Sample B bits
11 = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11
0x = CH1, CH2, CH3 negative inputs are VREFL
bit 8 CH123SB0: Channels 1, 2, 3 Positive Input Select for Sample B bit
See bits<12:11> for bit selections.
bit 4-3 CH123SA<2:1>: Channels 1, 2, 3 Positive Input Select for Sample A bits
1xx = CH1 positive input is AN0 (Op Amp 2), CH2 positive input is AN25 (Op Amp 5), CH3 positive
input is AN6 (Op Amp 3)
is AN25 (Op Amp 5)
is AN6 (Op Amp 3)
bit 2-1 CH123NA<1:0>: Channels 1, 2, 3 Negative Input Select for Sample A bits
0x = CH1, CH2, CH3 negative inputs are VREFL
bit 0 CH123SA0: Channels 1, 2, 3 Positive Input Select for Sample A bit
See bits<4:3> for bit selections.

REGISTER 24-6: ADxCHS0: ADCx INPUT CHANNEL 0 SELECT REGISTER

CH0NB — CH0SB5(1,3) CH0SB4(1,3) CH0SB3(1,3) CH0SB2(1,3) CH0SB1(1,3) CH0SB0(1,3)
bit 15 bit 8

CH0NA — CH0SA5(1,3) CH0SA4(1,3) CH0SA3(1,3) CH0SA2(1,3) CH0SA1(1,3) CH0SA0(1,3)
bit 7 bit 0
Legend:
bit 15 CH0NB: Channel 0 Negative Input Select for Sample MUX B bit
1 = Channel 0 negative input is AN1(1)
0 = Channel 0 negative input is VREFL
bit 13-8 CH0SB<5:0>: Channel 0 Positive Input Select for Sample MUX B bits(1,3)
111111 = Channel 0 positive input is AN63
111101 = Channel 0 positive input is AN61 (internal band gap voltage)
•
•
•
•
•
•
000000 = Channel 0 positive input is AN0 (Op Amp 2)(2)
bit 7 CH0NA: Channel 0 Negative Input Select for Sample MUX A bit
1 = Channel 0 negative input is AN1(1)
0 = Channel 0 negative input is VREFL
Note 1: AN0 to AN7 are repurposed when comparator and op amp functionality are enabled. See Figure 24-1 to
determine how enabling a particular op amp or comparator affects selection choices for Channels 1, 2 and 3.
2: If the op amp is selected (OPAEN bit (CMxCON<10>) = 1), the OAx input is used; otherwise, the ANx
input is used.
3: See the “Pin Diagrams” section for the available analog channels for each device.

REGISTER 24-6: ADxCHS0: ADCx INPUT CHANNEL 0 SELECT REGISTER (CONTINUED)

bit 5-0 CH0SA<5:0>: Channel 0 Positive Input Select for Sample MUX A bits(1,3)
111111 = Channel 0 positive input is AN63 (Unconnected)
111110 = Channel 0 positive input is AN62 (CTMU temperature diode)
111101 = Channel 0 positive input is AN61 (internal band gap voltage)
•
•
•
•
•
•
000000 = Channel 0 positive input is AN0 (Op Amp 2)(2)
Note 1: AN0 to AN7 are repurposed when comparator and op amp functionality are enabled. See Figure 24-1 to
determine how enabling a particular op amp or comparator affects selection choices for Channels 1, 2 and 3.
2: If the op amp is selected (OPAEN bit (CMxCON<10>) = 1), the OAx input is used; otherwise, the ANx
input is used.
3: See the “Pin Diagrams” section for the available analog channels for each device.

REGISTER 24-7: ADxCSSH: ADCx INPUT SCAN SELECT REGISTER HIGH(2)

(1) (1)
CSS31 CSS30 CSS29 CSS28 CSS27 CSS26 CSS25 CSS24(1)
bit 15 bit 8
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — — CSS19 CSS18 CSS17 CSS16
bit 7 bit 0
Legend:
bit 15 CSS31: ADCx Input Scan Selection bit

1 = Selects ANx for input scan
0 = Skips ANx for input scan
bit 13 CSS29: ADCx Input Scan Selection bits
bit 10 CSS26: ADCx Input Scan Selection bit(1)
1 = Selects OA3/AN6 for input scan
0 = Skips OA3/AN6 for input scan
Note 1: If the op amp is selected (OPAEN bit (CMxCON<10>) = 1), the OAx input is used; otherwise, the ANx
input is used.
2: All bits in this register can be selected by the user application. However, inputs selected for scan without a
corresponding input on the device convert VREFL.

REGISTER 24-7: ADxCSSH: ADCx INPUT SCAN SELECT REGISTER HIGH(2) (CONTINUED)
Note 1: If the op amp is selected (OPAEN bit (CMxCON<10>) = 1), the OAx input is used; otherwise, the ANx
input is used.
2: All bits in this register can be selected by the user application. However, inputs selected for scan without a
corresponding input on the device convert VREFL.

REGISTER 24-8: ADxCSSL: ADCx INPUT SCAN SELECT REGISTER LOW(1,2)

CSS<15:8>
bit 15 bit 8

CSS<7:0>
bit 7 bit 0
Legend:
bit 15-0 CSS<15:0>: ADCx Input Scan Selection bits

Note 1: On devices with less than 16 analog inputs, all bits in this register can be selected by the user application.
However, inputs selected for scan without a corresponding input on the device convert VREFL.
2: CSSx = ANx, where ‘x’ = 0-5.

25.0 OP AMP/COMPARATOR The dsPIC33EVXXXGM00X/10X family devices contain

up to five comparators that can be configured in various
MODULE
ways. CMP1, CMP2, CMP3 and CMP5 also have the
Note 1: This data sheet summarizes the features option to be configured as op amps, with the output
of the dsPIC33EVXXXGM00X/10X family being brought to an external pin for gain/filtering connec-
of devices. It is not intended to be a tions. As shown in Figure 25-1, individual comparator
comprehensive reference source. To options are specified by the comparator module’s
complement the information in this data Special Function Register (SFR) control bits.
sheet, refer to “Op Amp/Comparator” The following options allow users to:
(DS70000357) in the “dsPIC33/PIC24
• Select the Edge for Trigger and Interrupt Generation
Family Reference Manual”, which is avail-
able from the Microchip web site • Configure the Comparator Voltage Reference
(www.microchip.com). • Configure Output Blanking and Masking
2: Some registers and associated bits • Configure as a Comparator or Op Amp
described in this section may not be (CMP1, CMP2, CMP3 and CMP5 only)
available on all devices. Refer to Note: Not all op amp/comparator input/output
Section 4.0 “Memory Organization” in connections are available on all devices.
this data sheet for device-specific register See the “Pin Diagrams” section for
and bit information. available connections.
FIGURE 25-1: OP AMP/COMPARATOR x MODULE BLOCK DIAGRAM
CCH<1:0> (CMxCON<1:0>) Op Amp/Comparator 1, 2, 3, 5

CxIN1- 00
(x = 1, 2, 3, 5)
CxIN2- 01 Op Amp/Comparator
CXIN3- 10
VIN- –
CXIN4- 11 Blanking Digital
CMPx Function Filter CxOUT(1)
VIN+
CxIN1+ 0 + (see Figure 25-2) (see Figure 25-3)
CVREFIN 1 OPAEN (CMxCON<10>)

–
Op Amp x OAxOUT
+
OAx
(to ADC)
CREF (CMxCON<4>)
CCH<1:0> (CM4CON<1:0>) Comparator 4
OA1/AN3/C4IN2- 01
OA2/AN0/C4IN3- 10
OA3/AN6/C4IN4- 11
C4IN1- 00
VIN- – Blanking Digital C4OUT(1)
CMP4 Function Filter
VIN+ (see Figure 25-3) Trigger
C4IN1+ 0 + (see Figure 25-2) Output
CVREFIN 1
CREF (CMxCON<4>)
Note 1: The CxOUT pin is not a dedicated output pin on the device. This must be mapped to a physical pin using
Peripheral Pin Select (PPS). Refer to Section 11.0 “I/O Ports” for more information.

Figure 25-2, shows the user-programmable blanking
function block diagram.
FIGURE 25-2: USER-PROGRAMMABLE BLANKING FUNCTION BLOCK DIAGRAM

SELSRCA<3:0>
(CMxMSKSRC<3:0>)
Comparator Output To Digital

Filter
MUX A
MAI Blanking
Blanking “AND-OR” Function Logic
Signals MAI
MBI ANDI
AND
SELSRCB<3:0> MCI
(CMxMSKSRC<7:4>)
MAI HLMS
(CMxMSKCON<15>)
MUX B
MBI MBI Mask

Blanking OR
Signals
MCI
SELSRCC<3:0>
(CMxMSKSRC<11:8>)
CMxMSKCON
MUX C
Blanking MCI
Signals
Figure 25-3, shows the digital filter interconnect block

diagram.
FIGURE 25-3: DIGITAL FILTER INTERCONNECT BLOCK DIAGRAM
TX Timer Match(1,2) 1xx

SYNCO1(3) 010
FP(4) 000
(4)
FOSC 001
CFDIV
CFSEL<2:0> CFLTREN
(CMxFLTR<6:4>) (CMxFLTR<3>)
From Blanking Logic Digital Filter 1

CxOUT
0
Note 1: See the Type C Timer Block Diagram (Figure 13-2).

2: See the Type B Timer Block Diagram (Figure 13-1).
3: See the PWMx Module Register Interconnect Diagram (Figure 17-2).
4: See the Oscillator System Diagram (Figure 9-1).

25.1 Op Amp/Comparator Control

Registers
REGISTER 25-1: CMSTAT: OP AMP/COMPARATOR STATUS REGISTER
R/W-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0
PSIDL — — C5EVT(1) C4EVT(1) C3EVT(1) C2EVT(1) C1EVT(1)
bit 15 bit 8
U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0

— — — C5OUT(2) C4OUT(2) C3OUT(2) C2OUT(2) C1OUT(2)
bit 7 bit 0
Legend:
bit 15 PSIDL: Op Amp/Comparator Stop in Idle Mode bit

1 = Discontinues operation of all op amps/comparators when device enters Idle mode
0 = Continues operation of all op amps/comparators in Idle mode
bit 12-8 C5EVT:C1EVT: Op Amp/Comparator 1-5 Event Status bits(1)
1 = Op amp/comparator event occurred
0 = Op amp/comparator event did not occur
bit 4-0 C5OUT:C1OUT: Op Amp/Comparator 1-5 Output Status bits(2)
When CPOL = 0:
1 = VIN+ > VIN-
0 = VIN+ < VIN-
When CPOL = 1:
1 = VIN+ < VIN-
0 = VIN+ > VIN-
Note 1: Reflects the value of the of the CEVT bit in the respective Op Amp/Comparator Control register,
CMxCON<9>.
2: Reflects the value of the COUT bit in the respective Op Amp/Comparator Control register, CMxCON<8>.

REGISTER 25-2: CMxCON: COMPARATOR x CONTROL REGISTER (x = 1, 2, 3 OR 5)

R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R-0
CON COE CPOL — — OPAEN(2) CEVT COUT
bit 15 bit 8
R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0

EVPOL1(3) EVPOL0(3) — CREF(1) — — CCH1(1) CCH0(1)
bit 7 bit 0
Legend:
bit 15 CON: Op Amp/Comparator x Enable bit

1 = Op Amp/Comparator x is enabled
0 = Op Amp/Comparator x is disabled
bit 14 COE: Comparator x Output Enable bit
1 = Comparator output is present on the CxOUT pin
0 = Comparator output is internal only
bit 13 CPOL: Comparator x Output Polarity Select bit
1 = Comparator output is inverted
0 = Comparator output is not inverted
bit 10 OPAEN: Op Amp x Enable bit(2)
1 = Op Amp x is enabled
0 = Op Amp x is disabled
bit 9 CEVT: Comparator x Event bit
1 = Comparator event, according to EVPOL<1:0> settings, occurred; disables future triggers and
interrupts until the bit is cleared
0 = Comparator event did not occur
bit 8 COUT: Comparator x Output bit
When CPOL = 0 (non-inverted polarity):
1 = VIN+ > VIN-
0 = VIN+ < VIN-
When CPOL = 1 (inverted polarity):
1 = VIN+ < VIN-
0 = VIN+ > VIN-
Note 1: Inputs that are selected and not available will be tied to VSS. See the “Pin Diagrams” section for available
inputs for each package.
2: The op amp and the comparator can be used simultaneously in these devices. The OPAEN bit only
enables the op amp while the comparator is still functional.
3: After configuring the comparator, either for a high-to-low or low-to-high COUT transition
(EVPOL<1:0> (CMxCON<7:6>) = 10 or 01), the Comparator x Event bit, CEVT (CMxCON<9>), and the
Comparator Interrupt Flag, CMPIF (IFS1<2>), must be cleared before enabling the Comparator Interrupt
Enable bit, CMPIE (IEC1<2>).

REGISTER 25-2: CMxCON: COMPARATOR x CONTROL REGISTER (x = 1, 2, 3 OR 5) (CONTINUED)

bit 7-6 EVPOL<1:0>: Trigger/Event/Interrupt Polarity Select bits(3)
11 = Trigger/event/interrupt generated on any change of the comparator output (while CEVT = 0)
10 = Trigger/event/interrupt generated only on high-to-low transition of the polarity selected comparator
output (while CEVT = 0)
If CPOL = 1 (inverted polarity):
Low-to-high transition of the comparator output.
If CPOL = 0 (non-inverted polarity):
High-to-low transition of the comparator output.
01 = Trigger/event/interrupt generated only on low-to-high transition of the polarity selected comparator
00 = Trigger/event/interrupt generation is disabled
bit 4 CREF: Comparator x Reference Select bit (VIN+ input)(1)
1 = VIN+ input connects to the internal CVREFIN voltage
0 = VIN+ input connects to the CxIN1+ pin
bit 1-0 CCH<1:0>: Op Amp/Comparator x Channel Select bits(1)
11 = Inverting input of op amp/comparator connects to the CxIN4- pin
2: The op amp and the comparator can be used simultaneously in these devices. The OPAEN bit only
enables the op amp while the comparator is still functional.
(EVPOL<1:0> (CMxCON<7:6>) = 10 or 01), the Comparator x Event bit, CEVT (CMxCON<9>), and the
Comparator Interrupt Flag, CMPIF (IFS1<2>), must be cleared before enabling the Comparator Interrupt
Enable bit, CMPIE (IEC1<2>).

REGISTER 25-3: CM4CON: COMPARATOR 4 CONTROL REGISTER

R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R-0
CON COE CPOL — — — CEVT COUT
bit 15 bit 8
R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0

EVPOL1(2) EVPOL0(2) — CREF(1) — — CCH1(1) CCH0(1)
bit 7 bit 0
Legend:
bit 15 CON: Op Amp/Comparator 4 Enable bit

1 = Comparator is enabled
0 = Comparator is disabled
bit 14 COE: Comparator 4 Output Enable bit
1 = Comparator output is present on the C4OUT pin
0 = Comparator output is internal only
bit 13 CPOL: Comparator 4 Output Polarity Select bit
1 = Comparator output is inverted
0 = Comparator output is not inverted
bit 9 CEVT: Comparator 4 Event bit
1 = Comparator event, according to EVPOL<1:0> settings, occurred; disables future triggers and
interrupts until the bit is cleared
0 = Comparator event did not occur
bit 8 COUT: Comparator 4 Output bit
When CPOL = 0 (non-inverted polarity):
1 = VIN+ > VIN-
0 = VIN+ < VIN-
When CPOL = 1 (inverted polarity):
1 = VIN+ < VIN-
0 = VIN+ > VIN-
(EVPOL<1:0> (CMxCON<7:6>) = 10 or 01), the comparator Event bit, CEVT (CMxCON<9>), and the
Comparator Combined Interrupt Flag, CMPIF (IFS1<2>), must be cleared before enabling the Comparator
Interrupt Enable bit, CMPIE (IEC1<2>).

REGISTER 25-3: CM4CON: COMPARATOR 4 CONTROL REGISTER (CONTINUED)

bit 7-6 EVPOL<1:0>: Trigger/Event/Interrupt Polarity Select bits(2)
11 = Trigger/event/interrupt generated on any change of the comparator output (while CEVT = 0)
10 = Trigger/event/interrupt generated only on high-to-low transition of the polarity selected comparator
01 = Trigger/event/interrupt generated only on low-to-high transition of the polarity selected comparator
00 = Trigger/event/interrupt generation is disabled
bit 4 CREF: Comparator 4 Reference Select bit (VIN+ input)(1)
1 = VIN+ input connects to the internal CVREFIN voltage
0 = VIN+ input connects to the C4IN1+ pin
bit 1-0 CCH<1:0>: Comparator 4 Channel Select bits(1)
11 = VIN- input of comparator connects to the C4IN4- pin
(EVPOL<1:0> (CMxCON<7:6>) = 10 or 01), the comparator Event bit, CEVT (CMxCON<9>), and the
Comparator Combined Interrupt Flag, CMPIF (IFS1<2>), must be cleared before enabling the Comparator
Interrupt Enable bit, CMPIE (IEC1<2>).

REGISTER 25-4: CMxMSKSRC: COMPARATOR x MASK SOURCE SELECT

CONTROL REGISTER
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 RW-0
— — — — SELSRCC3 SELSRCC2 SELSRCC1 SELSRCC0
bit 15 bit 8

SELSRCB3 SELSRCB2 SELSRCB1 SELSRCB0 SELSRCA3 SELSRCA2 SELSRCA1 SELSRCA0
bit 7 bit 0
Legend:

bit 11-8 SELSRCC<3:0>: Mask C Input Select bits
1111 = FLT4
1110 = FLT2
1101 = Reserved
1100 = Reserved
1011 = Reserved
1010 = Reserved
1001 = Reserved
1000 = Reserved
0111 = Reserved
0110 = Reserved
0101 = PWM3H
0100 = PWM3L
0011 = PWM2H
0010 = PWM2L
0001 = PWM1H
0000 = PWM1L
bit 7-4 SELSRCB<3:0>: Mask B Input Select bits
1111 = FLT4
1110 = FLT2
1101 = Reserved
1100 = Reserved
1011 = Reserved
1010 = Reserved
1001 = Reserved
1000 = Reserved
0111 = Reserved
0110 = Reserved
0101 = PWM3H
0100 = PWM3L
0011 = PWM2H
0010 = PWM2L
0001 = PWM1H
0000 = PWM1L

REGISTER 25-4: CMxMSKSRC: COMPARATOR x MASK SOURCE SELECT

CONTROL REGISTER (CONTINUED)
bit 3-0 SELSRCA<3:0>: Mask A Input Select bits
1111 = FLT4
1110 = FLT2
1101 = Reserved
1100 = Reserved
1011 = Reserved
1010 = Reserved
1001 = Reserved
1000 = Reserved
0111 = Reserved
0110 = Reserved
0101 = PWM3H
0100 = PWM3L
0011 = PWM2H
0010 = PWM2L
0001 = PWM1H
0000 = PWM1L

REGISTER 25-5: CMxMSKCON: COMPARATOR x MASK GATING CONTROL

REGISTER
HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN
bit 15 bit 8

NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN
bit 7 bit 0
Legend:
bit 15 HLMS: High or Low-Level Masking Select bit

1 = The masking (blanking) function will prevent any asserted (‘0’) comparator signal from propagating
0 = The masking (blanking) function will prevent any asserted (‘1’) comparator signal from propagating
bit 13 OCEN: OR Gate C Input Enable bit
1 = MCI is connected to OR gate
0 = MCI is not connected to OR gate
bit 12 OCNEN: OR Gate C Input Inverted Enable bit
1 = Inverted MCI is connected to OR gate
0 = Inverted MCI is not connected to OR gate
bit 11 OBEN: OR Gate B Input Enable bit
1 = MBI is connected to OR gate
0 = MBI is not connected to OR gate
bit 10 OBNEN: OR Gate B Input Inverted Enable bit
1 = Inverted MBI is connected to OR gate
0 = Inverted MBI is not connected to OR gate
bit 9 OAEN: OR Gate A Input Enable bit
1 = MAI is connected to OR gate
0 = MAI is not connected to OR gate
bit 8 OANEN: OR Gate A Input Inverted Enable bit
1 = Inverted MAI is connected to OR gate
0 = Inverted MAI is not connected to OR gate
bit 7 NAGS: AND Gate Output Inverted Enable bit
1 = Inverted ANDI is connected to OR gate
0 = Inverted ANDI is not connected to OR gate
bit 6 PAGS: AND Gate Output Enable bit
1 = ANDI is connected to OR gate
0 = ANDI is not connected to OR gate
bit 5 ACEN: AND Gate C Input Enable bit
1 = MCI is connected to AND gate
0 = MCI is not connected to AND gate
bit 4 ACNEN: AND Gate C Input Inverted Enable bit
1 = Inverted MCI is connected to AND gate
0 = Inverted MCI is not connected to AND gate

REGISTER 25-5: CMxMSKCON: COMPARATOR x MASK GATING CONTROL

REGISTER (CONTINUED)
bit 3 ABEN: AND Gate B Input Enable bit
1 = MBI is connected to AND gate
0 = MBI is not connected to AND gate
bit 2 ABNEN: AND Gate B Input Inverted Enable bit
1 = Inverted MBI is connected to AND gate
0 = Inverted MBI is not connected to AND gate
bit 1 AAEN: AND Gate A Input Enable bit
1 = MAI is connected to AND gate
0 = MAI is not connected to AND gate
bit 0 AANEN: AND Gate A Input Inverted Enable bit
1 = Inverted MAI is connected to AND gate
0 = Inverted MAI is not connected to AND gate

REGISTER 25-6: CMxFLTR: COMPARATOR x FILTER CONTROL REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

— CFSEL2 CFSEL1 CFSEL0 CFLTREN CFDIV2 CFDIV1 CFDIV0
bit 7 bit 0
Legend:

bit 6-4 CFSEL<2:0>: Comparator x Filter Input Clock Select bits
111 = T5CLK(1)
110 = T4CLK(2)
101 = T3CLK(1)
100 = T2CLK(2)
011 = Reserved
010 = SYNCO1(3)
001 = FOSC(4)
000 = FP(4)
bit 3 CFLTREN: Comparator x Filter Enable bit
1 = Digital filter is enabled
0 = Digital filter is disabled
bit 2-0 CFDIV<2:0>: Comparator x Filter Clock Divide Select bits
111 = Clock divide 1:128
Note 1: See the Type C Timer Block Diagram (Figure 13-2).

2: See the Type B Timer Block Diagram (Figure 13-1).
3: See the High-Speed PWMx Module Register Interconnection Diagram (Figure 17-2).
4: See the Oscillator System Diagram (Figure 9-1).

26.0 COMPARATOR VOLTAGE 26.1 Configuring the Comparator

REFERENCE Voltage Reference
Note 1: This data sheet summarizes the features The comparator voltage reference module is controlled
of the dsPIC33EVXXXGM00X/10X family through the CVRxCON registers (Register 26-1 and
of devices. It is not intended to be a Register 26-2). The comparator voltage reference
comprehensive reference source. To provides a range of output voltages with 128 distinct
complement the information in this data levels. The comparator reference supply voltage can
sheet, refer to “Op Amp/Comparator” come from either VDD and VSS, or the external CVREF+
(DS70000357) in the “dsPIC33/PIC24 and AVSS pins. The voltage source is selected by the
Family Reference Manual”, which is avail- CVRSS bit (CVRxCON<11>). The settling time of the
able from the Microchip web site comparator voltage reference must be considered
(www.microchip.com). when changing the CVREF output.


FIGURE 26-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
VREFSEL
(CVR1CON<10>)
CVRSS = 1
CVREF+ (CVR1CON<11>)
CVRSRC 1
CVR1CON<6:0>
AVDD
CVRSS = 0 CVREFIN
CVR6
CVR5
CVR4
CVR3
CVR2
CVR1
CVR0
(CVR1CON<11>)
0
CVREN
(CVR1CON<15>)
R
128-to-1 MUX
R
128 Steps
CVREF1O
R CVROE
(CVR1CON<14>)
R
VREFSEL
R (CVR2CON<10>)
AVSS
1
CVRSS = 1
CVREF+ (CVR2CON<11>) CVRSRC
CVR2CON<6:0>
AVDD
CVRSS = 0
CVR6
CVR5
CVR4
CVR3
CVR2
CVR1
CVR0
(CVR2CON<11>)
CVREN
(CVR2CON<15>)
R
R
128-to-1 MUX
R
128 Steps
CVREF2O
R CVROE
(CVR2CON<14>)
R
R
AVSS
Note 1: CVREF2O and CVROE (CVR2CON<14>) is not available on the 28-pin devices.

26.2 Comparator Voltage Reference Registers
REGISTER 26-1: CVR1CON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER 1

R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0
CVREN CVROE — — CVRSS VREFSEL — —
bit 15 bit 8

— CVR6 CVR5 CVR4 CVR3 CVR2 CVR1 CVR0
bit 7 bit 0
Legend:
bit 15 CVREN: Comparator Voltage Reference Enable bit

1 = Comparator voltage reference circuit is powered on
0 = Comparator voltage reference circuit is powered down
bit 14 CVROE: Comparator Voltage Reference Output Enable (CVREF1O Pin) bit
1 = Voltage level is output on the CVREF1O pin
0 = Voltage level is disconnected from the CVREF1O pin
bit 11 CVRSS: Comparator Voltage Reference Source Selection bit
1 = Comparator reference source, CVRSRC = CVREF+ – AVSS
0 = Comparator reference source, CVRSRC = AVDD – AVSS
bit 10 VREFSEL: Voltage Reference Select bit
1 = CVREFIN = CVREF+
0 = CVREFIN is generated by the resistor network
bit 6-0 CVR<6:0>: Comparator Voltage Reference Value Selection bits
1111111 = 127/128 x VREF input voltage
•
•
•
0000000 = 0.0 volts

REGISTER 26-2: CVR2CON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER 2

R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0
CVREN CVROE(1) — — CVRSS VREFSEL — —
bit 15 bit 8

— CVR6 CVR5 CVR4 CVR3 CVR2 CVR1 CVR0
bit 7 bit 0
Legend:
bit 15 CVREN: Comparator Voltage Reference Enable bit

1 = Comparator voltage reference circuit is powered on
0 = Comparator voltage reference circuit is powered down
bit 14 CVROE: Comparator Voltage Reference Output Enable (CVREF2O Pin) bit(1)
1 = Voltage level is output on the CVREF2O pin
0 = Voltage level is disconnected from the CVREF2O pin
bit 11 CVRSS: Comparator Voltage Reference Source Selection bit
1 = Comparator reference source, CVRSRC = CVREF+ – AVSS
0 = Comparator reference source, CVRSRC = AVDD – AVSS
bit 10 VREFSEL: Voltage Reference Select bit
1 = Comparator Reference Source 2 (CVR2) provides inverting input voltage when VREFSEL
(CVR1CON<10>) = 0
0 = Comparator Reference Source 1 (CVR1) provides inverting input voltage when VREFSEL
(CVR1CON<10>) = 0
bit 6-0 CVR<6:0>: Comparator Voltage Reference Value Selection bits
1111111 = 127/128 x VREF input voltage
•
•
•
0000000 = 0.0 volts
Note 1: CVROE (CVR2CON<14>) is not available on the 28-pin devices.

27.0 SPECIAL FEATURES 27.1 Configuration Bits

Note: This data sheet summarizes the features of In dsPIC33EVXXXGM00X/10X family devices, the
the dsPIC33EVXXXGM00X/10X family of Configuration bytes are implemented as volatile
devices. It is not intended to be a memory. This means that configuration data must be
comprehensive reference source. To programmed each time the device is powered up.
complement the information in this data Configuration data is stored at the top of the on-chip
sheet, refer to the related section of the program memory space, known as the Flash Configu-
“dsPIC33/PIC24 Family Reference Manual”, ration bytes. Their specific locations are shown in
which is available from the Microchip Table 27-1. The configuration data is automatically
web site (www.microchip.com). loaded from the Flash Configuration bytes to the proper
Configuration Shadow registers during device Resets.
Note: Configuration data is reloaded on all types
include several features intended to maximize
of device Resets.
application flexibility and reliability, and minimize cost
through elimination of external components. These When creating applications for these devices, users
are: should always specifically allocate the location of the
• Flexible Configuration Flash Configuration bytes for configuration data in their
code for the compiler. This is to ensure that program
• Watchdog Timer (WDT)
code is not stored in this address when the code is
• Code Protection and CodeGuard™ Security compiled.
• In-Circuit Serial Programming™ (ICSP™)
The upper 2 bytes of all Flash Configuration
• In-Circuit Emulation Words in program memory should always be
‘1111 1111 1111 1111’. This makes them appear to
be NOP instructions in the remote event that their
locations are ever executed by accident. Since Config-
uration bits are not implemented in the corresponding
locations, writing ‘1’s to these locations has no effect on
device operation.
Note: Performing a page erase operation on the
last page of program memory clears the
Flash Configuration bytes, enabling code
protection as a result. Therefore, users
should avoid performing page erase
operations on the last page of program
memory.
The Configuration Flash bytes map is shown in
Table 27-1.

DS70005144E-page 318
TABLE 27-1: CONFIGURATION WORD REGISTER MAP
Device
Memory Bits
File Name Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Size 23-16
(Kbytes)
FSEC 005780 32
00AB80 64
— AIVTDIS — — — CSS2 CSS1 CSS0 CWRP GSS1 GSS0 GWRP — BSEN BSS1 BSS0 BWRP
015780 128
02AB80 256
FBSLIM 005790 32
00AB90 64
— — — — BSLIM<12:0>
015790 128
02AB90 256
Reserved 005794 32
00AB94 64
— Reserved(1) — — — — — — — — — — — — — — —
015794 128
02AB94 256
FOSCSEL 005798 32
00AB98 64
— — — — — — — — — IESO — — — — FNOSC2 FNOSC1 FNOSC0
015798 128
02AB98 256
FOSC 00579C 32
00AB9C 64
— — — — — — — — PLLKEN FCKSM1 FCKSM0 IOL1WAY — — OSCIOFNC POSCMD1 POSCMD0
01579C 128
02AB9C 256
FWDT 0057A0 32
00ABA0 64
— — — — — — — WDTWIN1 WDTWIN0 WINDIS FWDTEN1 FWDTEN0 WDTPRE WDTPS3 WDTPS2 WDTPS1 WDTPS0
0157A0 128
02ABA0 256
FPOR 0057A4 32
00ABA4 64
— — — — — — — — — — — — — — — — BOREN
0157A4 128
02ABA4 256
FICD 0057A8 32
00ABA8 64
— — — — — — — — — Reserved(2) — — — — — ICS1 ICS0
0157A8 128
02ABA8 256
Legend: — = unimplemented, read as ‘1’.
Note 1: This bit is reserved and must be programmed as ‘0’.
2: This bit is reserved and must be programmed as ‘1’.
TABLE 27-1: CONFIGURATION WORD REGISTER MAP (CONTINUED)

Device
Memory Bits
File Name Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Size 23-16
(Kbytes)
FDMTINTVL 0057AC 32
00ABAC 64
— DMTIVT<15:0>
0157AC 128
02ABAC 256
FDMTINTVH 0057B0 32
00ABB0 64
— DMTIVT<31:16>
0157B0 128
02ABB0 256
FDMTCNTL 0057B4 32
00ABB4 64
— DMTCNT<15:0>
0157B4 128
02ABB4 256
FDMTCNTH 0057B8 32
00AB8 64
— DMTCNT<31:16>
0157B8 128
02ABB8 256
FDMT 0057BC 32
00ABBC 64
— — — — — — — — — — — — — — — — DMTEN
0157BC 128
02ABBC 256
FDEVOPT 0057C0 32
00ABC0 64
— — — — — — — — — — — — — ALTI2C1 Reserved(2) — PWMLOCK
0157C0 128
02ABC0 256
FALTREG 0057C4 32
00ABC4 64
— — — — — — — — — — CTXT2<2:0> — CTXT1<2:0>
0157C4 128
DS70005144E-page 319
02ABC4 256
Legend: — = unimplemented, read as ‘1’.
Note 1: This bit is reserved and must be programmed as ‘0’.
2: This bit is reserved and must be programmed as ‘1’.
TABLE 27-2: dsPIC33EVXXXGM00X/10X CONFIGURATION BITS DESCRIPTION

Bit Field Register Description
BWRP FSEC Boot Segment Write-Protect bit
1 = User program memory is not write-protected
0 = User program memory is write-protected
BSS<1:0> FSEC Boot Segment Code Flash Protection Level bits
11 = No protection (other than BWRP write protection)
10 = Standard security
0x = High security
BSEN FSEC Boot Segment Control bit
1 = No Boot Segment
0 = Boot Segment size is determined by BSLIM<12:0>
GWRP FSEC General Segment Write-Protect bit
1 = User program memory is not write-protected
0 = User program memory is write-protected
GSS<1:0> FSEC General Segment Code Flash Protection Level bits
11 = No protection (other than GWRP write protection)
0x = High security
CWRP FSEC Configuration Segment Write-Protect bit
1 = Configuration Segment is not write-protected
0 = Configuration Segment is write-protected
CSS<2:0> FSEC Configuration Segment Code Flash Protection Level bits
111 = No protection (other than CWRP write protection)
10x = Enhanced security
0xx = High security
AIVTDIS FSEC Alternate Interrupt Vector Table Disable bit
1 = Disables AIVT
0 = Enables AIVT
BSLIM<12:0> FBSLIM Boot Segment Code Flash Page Address Limit bits
Contains the page address of the first active General Segment page. The
value to be programmed is the inverted page address, such that
programming additional ‘0’s can only increase the Boot Segment size.
For example, 0x1FFD = 2 pages or 1024 instruction words.
FNOSC<2:0> FOSCSEL Initial Oscillator Source Selection bits
111 = Internal Fast RC (FRC) Oscillator with Postscaler
110 = Internal Fast RC (FRC) Oscillator with Divide-by-16
101 = LPRC Oscillator
100 = Reserved
011 = Primary (XT, HS, EC) Oscillator with PLL
010 = Primary (XT, HS, EC) Oscillator
001 = Internal Fast RC (FRC) Oscillator with PLL
IESO FOSCSEL Two-Speed Oscillator Start-up Enable bit
1 = Starts up device with FRC, then automatically switches to the
user-selected oscillator source when ready
0 = Starts up device with user-selected oscillator source
POSCMD<1:0> FOSC Primary Oscillator Mode Select bits
11 = Primary Oscillator is disabled
10 = HS Crystal Oscillator mode
01 = XT Crystal Oscillator mode
00 = EC (External Clock) mode

TABLE 27-2: dsPIC33EVXXXGM00X/10X CONFIGURATION BITS DESCRIPTION (CONTINUED)

OSCIOFNC FOSC OSC2 Pin Function bit (except in XT and HS modes)
1 = OSC2 is the clock output
0 = OSC2 is the general purpose digital I/O pin
IOL1WAY FOSC Peripheral Pin Select Configuration bit
1 = Allows only one reconfiguration
0 = Allows multiple reconfigurations
FCKSM<1:0> FOSC Clock Switching Mode bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
PLLKEN FOSC PLL Lock Wait Enable bit
1 = Clock switches to the PLL source; will wait until the PLL lock signal is valid
0 = Clock switch will not wait for PLL lock
WDTPS<3:0> FWDT Watchdog Timer Postscaler bits
1111 = 1:32,768
1110 = 1:16,384
•
•
•
0001 = 1:2
0000 = 1:1
WDTPRE FWDT Watchdog Timer Prescaler bit
1 = 1:128
0 = 1:32
FWDTEN<1:0> FWDT Watchdog Timer Enable bits
11 = WDT is enabled in hardware
10 = WDT is controlled through the SWDTEN bit
01 = WDT is enabled only while device is active and disabled in Sleep; the
SWDTEN bit is disabled
00 = WDT and the SWDTEN bit are disabled
WINDIS FWDT Watchdog Timer Window Enable bit
1 = Watchdog Timer is in Non-Window mode
0 = Watchdog Timer is in Window mode
WDTWIN<1:0> FWDT Watchdog Timer Window Select bits
11 = WDT window is 25% of WDT period
10 = WDT window is 37.5% of WDT period
BOREN FPOR Brown-out Reset (BOR) Detection Enable bit
1 = BOR is enabled
0 = BOR is disabled
ICS<1:0> FICD ICD Communication Channel Select bits
11 = Communicates on PGEC1 and PGED1
00 = Reserved, do not use
DMTIVT<15:0> FDMTINTVL Lower 16 Bits of 32-Bit Field that Configures the DMT Window Interval bits
DMTIVT<31:16> FDMTINTVH Upper 16 Bits of 32-Bit Field that Configures the DMT Window Interval bits
DMTCNT<15:0> FDMTCNTL Lower 16 Bits of 32-Bit Field that Configures the DMT Instruction Count
Time-out Value bits

TABLE 27-2: dsPIC33EVXXXGM00X/10X CONFIGURATION BITS DESCRIPTION (CONTINUED)

DMTCNT<31:16> FDMCNTH Upper 16 Bits of 32-Bit Field that Configures the DMT Instruction Count
Time-out Value bits
DMTEN FDMT Deadman Timer Enable bit
1 = Deadman Timer is enabled and cannot be disabled by software
0 = Deadman Timer is disabled and can be enabled by software
PWMLOCK FDEVOPT PWM Lock Enable bit
1 = Certain PWM registers may only be written after a key sequence
0 = PWM registers may be written without a key sequence
ALTI2C1 FDEVOPT Alternate I2C Pins for I2C1 bit
1 = I2C1 is mapped to the SDA1/SCL1 pins
0 = I2C1 is mapped to the ASDA1/ASCL1 pins
CTXT1<2:0> FALTREG Specifies the Alternate Working Register Set 1 Association with
Interrupt Priority Level (IPL) bits
111 = Not assigned
110 = Alternate Register Set 1 is assigned to IPL Level 6
000 = Not assigned
CTXT2<2:0> FALTREG Specifies the Alternate Working Register Set 2 Association with
Interrupt Priority Level (IPL) bits
111 = Not assigned
000 = Not assigned

REGISTER 27-1: DEVID: DEVICE ID REGISTER

R R R R R R R R
DEVID<23:16>(1)
bit 23 bit 16
R R R R R R R R
DEVID<15:8>(1)
bit 15 bit 8
R R R R R R R R
DEVID<7:0>(1)
bit 7 bit 0
Legend: R = Read-Only bit U = Unimplemented bit
bit 23-0 DEVID<23:0>: Device Identifier bits(1)
Note 1: Refer to “dsPIC33EVXXXGM00X/10X Families Flash Programming Specification” (DS70005137) for the
list of Device ID values.
REGISTER 27-2: DEVREV: DEVICE REVISION REGISTER

R R R R R R R R
DEVREV<23:16>(1)
bit 23 bit 16
R R R R R R R R
DEVREV<15:8>(1)
bit 15 bit 8
R R R R R R R R
DEVREV<7:0>(1)
bit 7 bit 0
Legend: R = Read-only bit U = Unimplemented bit
bit 23-0 DEVREV<23:0>: Device Revision bits(1)
Note 1: Refer to “dsPIC33EVXXXGM00X/10X Families Flash Programming Specification” (DS70005137) for the
list of device revision values.

27.2 User OTP Memory 27.4 Brown-out Reset (BOR)

Locations, 800F80h-800FFEh, are a One-Time- The Brown-out Reset (BOR) module is based on an
Programmable (OTP) memory area. The user OTP internal voltage reference circuit that monitors the reg-
words can be used for storing product information, such ulated supply voltage, VCAP. The main purpose of the
as serial numbers, system manufacturing dates, manu- BOR module is to generate a device Reset when a
facturing lot numbers and other application-specific brown-out condition occurs. Brown-out conditions are
information. generally caused by glitches on the AC mains (for
example, missing portions of the AC cycle waveform
27.3 On-Chip Voltage Regulator due to bad power transmission lines or voltage sags
due to excessive current draw when a large inductive
All of the dsPIC33EVXXXGM00X/10X family devices load is turned on).
power their core digital logic at a nominal 1.8V. This can
A BOR generates a Reset pulse, which resets the
create a conflict for designs that are required to operate at
device. The BOR selects the clock source based on the
a higher typical voltage, such as 5.0V. To simplify system
device Configuration bit values (FNOSC<2:0> and
design, all devices in the dsPIC33EVXXXGM00X/10X
POSCMD<1:0>).
family incorporate an on-chip regulator that allows the
device to run its core logic from VDD. If an oscillator mode is selected, the BOR activates the
Oscillator Start-up Timer (OST). The system clock is
The regulator provides power to the core from the other
held until OST expires. If the PLL is used, the clock is
VDD pins. A low-ESR (less than 1 Ohm) capacitor (such
held until the LOCK bit (OSCCON<5>) is ‘1’.
as tantalum or ceramic) must be connected to the VCAP
pin (see Figure 27-1). This helps to maintain the stability Concurrently, the Power-up Timer (PWRT) Time-out
of the regulator. The recommended value for the filter (TPWRT) is applied before the internal Reset is released.
capacitor is provided in Table 30-5, located in If TPWRT = 0 and a crystal oscillator is being used, then a
Section 30.0 “Electrical Characteristics”. nominal delay of TFSCM is applied. The total delay in this
case is TFSCM. Refer to Parameter SY35 in Table 30-22
Note: It is important for the low-ESR capacitor to of Section 30.0 “Electrical Characteristics” for specific
be placed as close as possible to the VCAP TFSCM values.
pin.
The BOR status bit (RCON<1>) is set to indicate that a
BOR has occurred. The BOR circuit continues to oper-
FIGURE 27-1: CONNECTIONS FOR THE ate while in Sleep or Idle mode and resets the device
ON-CHIP VOLTAGE should VDD fall below the BOR threshold voltage.
REGULATOR(1,2,3)
5.0V
dsPIC33EV
VDD
AVDD
VCAP
CEFC
VSS
AVSS
Note 1: These are typical operating voltages.

Refer to Table 30-4 located in
Section 30.1 “DC Characteristics” for
the full operating ranges of VDD and VCAP.
2: It is important for the low-ESR capacitor to
be placed as close as possible to the
VCAP pin.
3: Typical VCAP pin voltage = 1.8V when
VDD ≥ VDDMIN.

27.5 Watchdog Timer (WDT) 27.5.2 SLEEP AND IDLE MODES

For dsPIC33EVXXXGM00X/10X family devices, the If the WDT is enabled, it continues to run during Sleep or
WDT is driven by the LPRC oscillator. When the WDT Idle modes. When the WDT time-out occurs, the device
is enabled, the clock source is also enabled. wakes the device and code execution continues from
where the PWRSAV instruction was executed. The corre-
27.5.1 PRESCALER/POSTSCALER sponding SLEEP or IDLE bit (RCON<3:2>) needs to be
cleared in software after the device wakes up.
The nominal WDT clock source from LPRC is 32 kHz.
This feeds a prescaler that can be configured for either 27.5.3 ENABLING WDT
5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The
prescaler is set by the WDTPRE Configuration bit. With a The WDT is enabled or disabled by the FWDTEN<1:0>
32 kHz input, the prescaler yields a WDT Time-out Period Configuration bits in the FWDT Configuration register.
(TWDT), as shown in Parameter SY12 in Table 30-22. When the FWDTEN<1:0> Configuration bits are set,
the WDT is always enabled.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods. The WDT can be optionally controlled in software
The postscaler is controlled by the WDTPOST<3:0> when the FWDTENx Configuration bits have been
Configuration bits (FWDT<3:0>), which allow the programmed to ‘00’. The WDT is enabled in software
selection of 16 settings, from 1:1 to 1:32,768. Using the by setting the SWDTEN control bit (RCON<5>). The
prescaler and postscaler, time-out periods ranging SWDTEN control bit is cleared on any device Reset.
from 1 ms to 131 seconds can be achieved. The software WDT option allows the user application
to enable the WDT for critical code segments and
The WDT, prescaler and postscaler are reset: disable the WDT during non-critical segments for
• On any device Reset maximum power savings.
• On the completion of a clock switch, whether The WDT flag bit, WDTO (RCON<4>), is not automatically
invoked by software (i.e., setting the OSWEN bit cleared following a WDT time-out. To detect subsequent
after changing the NOSCx bits) or by hardware WDT events, the flag must be cleared in software.
(i.e., Fail-Safe Clock Monitor)
• When a PWRSAV instruction is executed 27.5.4 WDT WINDOW
(i.e., Sleep or Idle mode is entered) The Watchdog Timer has an optional Windowed mode
• When the device exits Sleep or Idle mode to enabled by programming the WINDIS bit in the WDT
resume normal operation Configuration register (FWDT<7>). In the Windowed
• By a CLRWDT instruction during normal execution mode (WINDIS = 0), the WDT should be cleared based
on the settings in the programmable Watchdog Timer
Note: The CLRWDT and PWRSAV instructions
Window (WDTWIN<1:0>) select bits.
clear the prescaler and postscaler counts
when executed.
FIGURE 27-2: WDT BLOCK DIAGRAM
All Device Resets

Transition to New Clock Source
Exit Sleep or Idle Mode
PWRSAV Instruction
CLRWDT Instruction Watchdog Timer
Sleep/Idle
WDTPRE WDTPOST<3:0>
SWDTEN WDT
FWDTEN<1:0> Wake-up
1
RS RS
Prescaler Postscaler
LPRC Clock (Divide-by-N1) (Divide-by-N2) WDT
0 Reset
WINDIS
WDT Window Select
WDTWIN<1:0>
CLRWDT Instruction

27.6 In-Circuit Serial Programming Any of the following three pairs of debugging clock/data
pins can be used:
The dsPIC33EVXXXGM00X/10X family devices can be
serially programmed while in the end application circuit. • PGEC1 and PGED1
This is done with two lines for clock and data, and three • PGEC2 and PGED2
other lines for power, ground and the programming • PGEC3 and PGED3
sequence. Serial programming allows customers to To use the in-circuit debugger function of the device,
manufacture boards with unprogrammed devices and the design must implement ICSP connections to
then program the device just before shipping the MCLR, VDD, VSS and the PGECx/PGEDx pin pair. In
product. Serial programming also allows the most recent addition, when the feature is enabled, some of the
firmware or a custom firmware to be programmed. resources are not available for general use. These
Refer to “dsPIC33EVXXXGM00X/10X Families Flash resources include the first 80 bytes of data RAM and
Programming Specification” (DS70005137) for details two I/O pins (PGECx and PGEDx).
about In-Circuit Serial Programming™ (ICSP™).
Any of the following three pairs of programming clock/ 27.8 Code Protection and
data pins can be used: CodeGuard™ Security
• PGEC1 and PGED1
The dsPIC33EVXXXGM00X/10X family devices offer
• PGEC2 and PGED2
Intermediate CodeGuard Security that supports
• PGEC3 and PGED3 General Segment (GS) security, Boot Segment (BS)
security and Configuration Segment (CS) security. This
27.7 In-Circuit Debugger feature helps protect individual Intellectual Properties.
When MPLAB® ICD 3 or REAL ICE™ is selected as a Note: Refer to “CodeGuard™ Intermediate
debugger, the in-circuit debugging functionality is Security” (DS70005182) in the “dsPIC33/
enabled. This function allows simple debugging functions PIC24 Family Reference Manual” for
when used with MPLAB X IDE. Debugging functionality further information on usage, configuration
is controlled through the PGECx (Emulation/Debug and operation of CodeGuard Security.
Clock) and PGEDx (Emulation/Debug Data) pin
functions.

28.0 INSTRUCTION SET SUMMARY Most bit-oriented instructions (including simple rotate/
shift instructions) have two operands:
Note: This data sheet summarizes the features of • The W register (with or without an address
the dsPIC33EVXXXGM00X/10X family of modifier) or file register (specified by the value of
devices. It is not intended to be a ‘Ws’ or ‘f’)
• The bit in the W register or file register (specified
by a literal value or indirectly by the contents of
sheet, refer to the related section of the
register ‘Wb’)
“dsPIC33/PIC24 Family Reference Manual”,
which is available from the Microchip The literal instructions that involve data movement can
web site (www.microchip.com). use some of the following operands:
• A literal value to be loaded into a W register or file
The dsPIC33EV instruction set is almost identical to
register (specified by ‘k’)
that of the dsPIC30F and dsPIC33F.
• The W register or file register where the literal
Most instructions are a single program memory word value is to be loaded (specified by ‘Wb’ or ‘f’)
(24 bits). Only three instructions require two program
memory locations. However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
Each single-word instruction is a 24-bit word, divided
into an 8-bit opcode, which specifies the instruction • The first source operand, which is a register ‘Wb’
type and one or more operands, which further specify without any address modifier
the operation of the instruction. • The second source operand, which is a literal
value
The instruction set is highly orthogonal and is grouped
into following five basic categories: • The destination of the result (only if not the same
as the first source operand), which is typically a
• Word or byte-oriented operations register ‘Wd’ with or without an address modifier
• Bit-oriented operations
The MAC class of DSP instructions can use some of the
• Literal operations following operands:
• DSP operations
• The accumulator (A or B) to be used (required
• Control operations operand)
Table 28-1 lists the general symbols used in describing • The W registers to be used as the two operands
the instructions. • The X and Y address space prefetch operations
The dsPIC33E instruction set summary in Table 28-2 • The X and Y address space prefetch destinations
lists all the instructions, along with the Status Flags • The accumulator write-back destination
affected by each instruction.
The other DSP instructions do not involve any
Most word or byte-oriented W register instructions multiplication and can include:
(including barrel shift instructions) have the following
three operands: • The accumulator to be used (required)
• The source or destination operand (designated as
• The first source operand, which is typically a
Wso or Wdo, respectively) with or without an
register ‘Wb’ without any address modifier
address modifier
• The second source operand, which is typically a
• The amount of shift specified by a W register ‘Wn’
register ‘Ws’ with or without an address modifier
or a literal value
• The destination of the result, which is typically a
register ‘Wd’ with or without an address modifier The control instructions can use some of the following
operands:
However, word or byte-oriented file register instructions
have two operands: • A program memory address
• The mode of the Table Read and Table Write
• The file register specified by the value ‘f’
instructions
• The destination, which could be either the file
register ‘f’ or the W0 register, which is denoted as
‘WREG’

Most instructions are a single word. Certain double-word these cases, the execution takes multiple instruction
instructions are designed to provide all the required cycles with the additional instruction cycle(s) executed
information in these 48 bits. In the second word, the as a NOP. Certain instructions that involve skipping over
8 MSbs are ‘0’s. If this second word is executed as an the subsequent instruction require either two or three
instruction (by itself), it executes as a NOP. cycles if the skip is performed, depending on whether
The double-word instructions execute in two instruction the instruction being skipped is a single-word or two-
cycles. word instruction. Moreover, double-word moves require
two cycles.
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true, or the Note: For more details on the instruction set, refer
Program Counter is changed as a result of the to the “16-bit MCU and DSC Programmer’s
instruction, or a PSV or Table Read is performed. In Reference Manual” (DS70157).
TABLE 28-1: SYMBOLS USED IN OPCODE DESCRIPTIONS

Field Description
#text Means literal defined by “text”

(text) Means “content of text”
[text] Means “the location addressed by text”
{} Optional field or operation
a  {b, c, d} a is selected from the set of values b, c, d
<n:m> Register bit field
.b Byte mode selection
.d Double-Word mode selection
.S Shadow register select
.w Word mode selection (default)
Acc One of two accumulators {A, B}
AWB Accumulator Write-Back Destination Address register {W13, [W13]+ = 2}
bit4 4-bit bit selection field (used in word-addressed instructions) {0...15}
C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Expr Absolute address, label or expression (resolved by the linker)
f File register address {0x0000...0x1FFF}
lit1 1-bit unsigned literal {0,1}
lit4 4-bit unsigned literal {0...15}
lit10 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode
lit23 23-bit unsigned literal {0...8388608}; LSb must be ‘0’
None Field does not require an entry, can be blank
OA, OB, SA, SB DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate
PC Program Counter
Slit10 10-bit signed literal {-512...511}
Wb Base W register {W0...W15}
Wd Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo Destination W register 
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn Dividend, Divisor Working register pair (Direct Addressing)

TABLE 28-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)

Field Description
Wm*Wm Multiplicand and Multiplier Working register pair for Square instructions 
{W4 * W4,W5 * W5,W6 * W6,W7 * W7}
Wm*Wn Multiplicand and Multiplier Working register pair for DSP instructions 
{W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7}
Wn One of 16 Working registers {W0...W15}
Wnd One of 16 Destination Working registers {W0...W15}
Wns One of 16 Source Working registers {W0...W15}
WREG W0 (Working register used in file register instructions)
Ws Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso Source W register 
{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
Wx X Data Space Prefetch Address register for DSP instructions
 {[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2,
[W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2,
[W9 + W12], none}
Wxd X Data Space Prefetch Destination register for DSP instructions {W4...W7}
Wy Y Data Space Prefetch Address register for DSP instructions
 {[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2,
[W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2,
[W11 + W12], none}
Wyd Y Data Space Prefetch Destination register for DSP instructions {W4...W7}

TABLE 28-2: INSTRUCTION SET OVERVIEW

Base
Assembly # of # of Status Flags
Instr Assembly Syntax Description
Mnemonic Words Cycles Affected
#
1 ADD ADD Acc Add Accumulators 1 1 OA,OB,SA,

SB
ADD f f = f + WREG 1 1 C,DC,N,OV,Z
ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z
ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z
ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z
ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z
ADD Wso,#Slit4,Acc 16-bit Signed Add to Accumulator 1 1 OA,OB,SA,
SB
2 ADDC ADDC f f = f + WREG + (C) 1 1 C,DC,N,OV,Z
ADDC f,WREG WREG = f + WREG + (C) 1 1 C,DC,N,OV,Z
ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C,DC,N,OV,Z
ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C,DC,N,OV,Z
ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C,DC,N,OV,Z
3 AND AND f f = f .AND. WREG 1 1 N,Z
AND f,WREG WREG = f .AND. WREG 1 1 N,Z
AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N,Z
AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N,Z
AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N,Z
4 ASR ASR f f = Arithmetic Right Shift f 1 1 C,N,OV,Z
ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C,N,OV,Z
ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C,N,OV,Z
ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N,Z
ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N,Z
5 BCLR BCLR f,#bit4 Bit Clear f 1 1 None
BCLR Ws,#bit4 Bit Clear Ws 1 1 None
6 BRA BRA C,Expr Branch if Carry 1 1 (4) None
BRA GE,Expr Branch if greater than or equal 1 1 (4) None
BRA GEU,Expr Branch if unsigned greater than or equal 1 1 (4) None
BRA GT,Expr Branch if greater than 1 1 (4) None
BRA GTU,Expr Branch if unsigned greater than 1 1 (4) None
BRA LE,Expr Branch if less than or equal 1 1 (4) None
BRA LEU,Expr Branch if unsigned less than or equal 1 1 (4) None
BRA LT,Expr Branch if less than 1 1 (4) None
BRA LTU,Expr Branch if unsigned less than 1 1 (4) None
BRA N,Expr Branch if Negative 1 1 (4) None
BRA NC,Expr Branch if Not Carry 1 1 (4) None
BRA NN,Expr Branch if Not Negative 1 1 (4) None
BRA NOV,Expr Branch if Not Overflow 1 1 (4) None
BRA NZ,Expr Branch if Not Zero 1 1 (4) None
BRA OA,Expr Branch if Accumulator A overflow 1 1 (4) None
BRA OB,Expr Branch if Accumulator B overflow 1 1 (4) None
BRA OV,Expr Branch if Overflow 1 1 (4) None
BRA SA,Expr Branch if Accumulator A saturated 1 1 (4) None
BRA SB,Expr Branch if Accumulator B saturated 1 1 (4) None
BRA Expr Branch Unconditionally 1 4 None
BRA Z,Expr Branch if Zero 1 1 (4) None
BRA Wn Computed Branch 1 4 None
7 BSET BSET f,#bit4 Bit Set f 1 1 None
BSET Ws,#bit4 Bit Set Ws 1 1 None
Note: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.

TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Base
#
8 BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None

BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None
9 BTG BTG f,#bit4 Bit Toggle f 1 1 None
BTG Ws,#bit4 Bit Toggle Ws 1 1 None
10 BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 None
(2 or 3)
BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 None
(2 or 3)
11 BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None
(2 or 3)
BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None
(2 or 3)
12 BTST BTST f,#bit4 Bit Test f 1 1 Z
BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C
BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z
BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C
BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z
13 BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z
BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C
BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z
14 CALL CALL lit23 Call subroutine 2 4 SFA
CALL Wn Call indirect subroutine 1 4 SFA
CALL.L Wn Call indirect subroutine (long address) 1 4 SFA
15 CLR CLR f f = 0x0000 1 1 None
CLR WREG WREG = 0x0000 1 1 None
CLR Ws Ws = 0x0000 1 1 None
CLR Acc,Wx,Wxd,Wy,Wyd,AWB Clear Accumulator 1 1 OA,OB,SA,
SB
16 CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO,Sleep
17 COM COM f f=f 1 1 N,Z
COM f,WREG WREG = f 1 1 N,Z
COM Ws,Wd Wd = Ws 1 1 N,Z
18 CP CP f Compare f with WREG 1 1 C,DC,N,OV,Z
CP Wb,#lit8 Compare Wb with lit8 1 1 C,DC,N,OV,Z
CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C,DC,N,OV,Z
19 CP0 CP0 f Compare f with 0x0000 1 1 C,DC,N,OV,Z
CP0 Ws Compare Ws with 0x0000 1 1 C,DC,N,OV,Z
20 CPB CPB f Compare f with WREG, with Borrow 1 1 C,DC,N,OV,Z
CPB Wb,#lit8 Compare Wb with lit8, with Borrow 1 1 C,DC,N,OV,Z
CPB Wb,Ws Compare Wb with Ws, with Borrow 1 1 C,DC,N,OV,Z
(Wb – Ws – C)
21 CPSEQ CPSEQ Wb,Wn Compare Wb with Wn, skip if = 1 1 None
(2 or 3)
CPBEQ CPBEQ Wb,Wn,Expr Compare Wb with Wn, branch if = 1 1 (5) None
22 CPSGT CPSGT Wb,Wn Compare Wb with Wn, skip if > 1 1 None
(2 or 3)
CPBGT CPBGT Wb,Wn,Expr Compare Wb with Wn, branch if > 1 1 (5) None
23 CPSLT CPSLT Wb,Wn Compare Wb with Wn, skip if < 1 1 None
(2 or 3)
CPBLT CPBLT Wb,Wn,Expr Compare Wb with Wn, branch if < 1 1 (5) None
24 CPSNE CPSNE Wb,Wn Compare Wb with Wn, skip if  1 1 None
(2 or 3)
CPBNE CPBNE Wb,Wn,Expr Compare Wb with Wn, branch if  1 1 (5) None


Base
#
25 CTXTSWP CTXTSWP #lit3 Switch CPU register context to context 1 2 None

defined by lit3
CTXTSWP Wn Switch CPU register context to context 1 2 None
defined by Wn
26 DAW DAW Wn Wn = decimal adjust Wn 1 1 C
27 DEC DEC f f=f–1 1 1 C,DC,N,OV,Z
DEC f,WREG WREG = f – 1 1 1 C,DC,N,OV,Z
DEC Ws,Wd Wd = Ws – 1 1 1 C,DC,N,OV,Z
28 DEC2 DEC2 f f=f–2 1 1 C,DC,N,OV,Z
DEC2 f,WREG WREG = f – 2 1 1 C,DC,N,OV,Z
DEC2 Ws,Wd Wd = Ws – 2 1 1 C,DC,N,OV,Z
29 DISI DISI #lit14 Disable Interrupts for k instruction cycles 1 1 None
30 DIV DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C,OV
DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C,OV
DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C,OV
DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N,Z,C,OV
31 DIVF DIVF Wm,Wn Signed 16/16-bit Fractional Divide 1 18 N,Z,C,OV
32 DO DO #lit15,Expr Do code to PC + Expr, lit15 + 1 times 2 2 None
DO Wn,Expr Do code to PC + Expr, (Wn) + 1 times 2 2 None
33 ED ED Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance (no accumulate) 1 1 OA,OB,OAB,
SA,SB,SAB
34 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance 1 1 OA,OB,OAB,
SA,SB,SAB
35 EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None
36 FBCL FBCL Ws,Wnd Find Bit Change from Left (MSb) Side 1 1 C
37 FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C
38 FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C
39 GOTO GOTO Expr Go to address 2 4 None
GOTO Wn Go to indirect 1 4 None
GOTO.L Wn Go to indirect (long address) 1 4 None
40 INC INC f f=f+1 1 1 C,DC,N,OV,Z
INC f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z
INC Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z
41 INC2 INC2 f f=f+2 1 1 C,DC,N,OV,Z
INC2 f,WREG WREG = f + 2 1 1 C,DC,N,OV,Z
INC2 Ws,Wd Wd = Ws + 2 1 1 C,DC,N,OV,Z
42 IOR IOR f f = f .IOR. WREG 1 1 N,Z
IOR f,WREG WREG = f .IOR. WREG 1 1 N,Z
IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N,Z
IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N,Z
IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N,Z
43 LAC LAC Wso,#Slit4,Acc Load Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
44 LNK LNK #lit14 Link Frame Pointer 1 1 SFA
45 LSR LSR f f = Logical Right Shift f 1 1 C,N,OV,Z
LSR f,WREG WREG = Logical Right Shift f 1 1 C,N,OV,Z
LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C,N,OV,Z
LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N,Z
LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N,Z


Base
#
46 MAC MAC Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,AWB Multiply and Accumulate 1 1 OA,OB,OAB,

SA,SB,SAB
MAC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square and Accumulate 1 1 OA,OB,OAB,
SA,SB,SAB
47 MOV MOV f,Wn Move f to Wn 1 1 None
MOV f Move f to f 1 1 None
MOV f,WREG Move f to WREG 1 1 None
MOV #lit16,Wn Move 16-bit literal to Wn 1 1 None
MOV.b #lit8,Wn Move 8-bit literal to Wn 1 1 None
MOV Wn,f Move Wn to f 1 1 None
MOV Wso,Wdo Move Ws to Wd 1 1 None
MOV WREG,f Move WREG to f 1 1 None
MOV.D Wns,Wd Move Double from W(ns):W(ns + 1) to Wd 1 2 None
MOV.D Ws,Wnd Move Double from Ws to W(nd + 1):W(nd) 1 2 None
48 MOVPAG MOVPAG #lit10,DSRPAG Move 10-bit literal to DSRPAG 1 1 None
MOVPAG #lit9,DSWPAG Move 9-bit literal to DSWPAG 1 1 None
MOVPAG #lit8,TBLPAG Move 8-bit literal to TBLPAG 1 1 None
MOVPAGW Ws, DSRPAG Move Ws<9:0> to DSRPAG 1 1 None
MOVPAGW Ws, DSWPAG Move Ws<8:0> to DSWPAG 1 1 None
MOVPAGW Ws, TBLPAG Move Ws<7:0> to TBLPAG 1 1 None
49 MOVSAC MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB Prefetch and store accumulator 1 1 None
50 MPY MPY Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square Wm to Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
51 MPY.N MPY.N Wm*Wn,Acc,Wx,Wxd,Wy,Wyd -(Multiply Wm by Wn) to Accumulator 1 1 None
52 MSC MSC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd,AWB Multiply and Subtract from Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB


Base
#
53 MUL MUL.SS Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * 1 1 None

signed(Ws)
MUL.SS Wb,Ws,Acc Accumulator = signed(Wb) * signed(Ws) 1 1 None
MUL.SU Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * 1 1 None
unsigned(Ws)
MUL.SU Wb,Ws,Acc Accumulator = signed(Wb) * 1 1 None
unsigned(Ws)
MUL.SU Wb,#lit5,Acc Accumulator = signed(Wb) * unsigned(lit5) 1 1 None
MUL.US Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * 1 1 None
signed(Ws)
MUL.US Wb,Ws,Acc Accumulator = unsigned(Wb) * 1 1 None
signed(Ws)
MUL.UU Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * 1 1 None
unsigned(Ws)
MUL.UU Wb,#lit5,Acc Accumulator = unsigned(Wb) * 1 1 None
unsigned(lit5)
MUL.UU Wb,Ws,Acc Accumulator = unsigned(Wb) * 1 1 None
unsigned(Ws)
MULW.SS Wb,Ws,Wnd Wnd = signed(Wb) * signed(Ws) 1 1 None
MULW.SU Wb,Ws,Wnd Wnd = signed(Wb) * unsigned(Ws) 1 1 None
MULW.US Wb,Ws,Wnd Wnd = unsigned(Wb) * signed(Ws) 1 1 None
MULW.UU Wb,Ws,Wnd Wnd = unsigned(Wb) * unsigned(Ws) 1 1 None
MUL.SU Wb,#lit5,Wnd {Wnd + 1, Wnd} = signed(Wb) * 1 1 None
unsigned(lit5)
MUL.SU Wb,#lit5,Wnd Wnd = signed(Wb) * unsigned(lit5) 1 1 None
MUL.UU Wb,#lit5,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * 1 1 None
unsigned(lit5)
MUL.UU Wb,#lit5,Wnd Wnd = unsigned(Wb) * unsigned(lit5) 1 1 None
MUL f W3:W2 = f * WREG 1 1 None
54 NEG NEG Acc Negate Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
NEG f f=f+1 1 1 C,DC,N,OV,Z
NEG f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z
NEG Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z
55 NOP NOP No Operation 1 1 None
NOPR No Operation 1 1 None
56 POP POP f Pop f from Top-of-Stack (TOS) 1 1 None
POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None
POP.D Wnd Pop from Top-of-Stack (TOS) to 1 2 None
W(nd):W(nd + 1)
POP.S Pop Shadow Registers 1 1 All
57 PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None
PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None
PUSH.D Wns Push W(ns):W(ns + 1) to Top-of-Stack 1 2 None
(TOS)
PUSH.S Push Shadow Registers 1 1 None
58 PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO,Sleep
59 RCALL RCALL Expr Relative Call 1 4 SFA
RCALL Wn Computed Call 1 4 SFA
60 REPEAT REPEAT #lit15 Repeat Next Instruction lit15 + 1 times 1 1 None
REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None
61 RESET RESET Software device Reset 1 1 None
62 RETFIE RETFIE Return from interrupt 1 6 (5) SFA


Base
#
63 RETLW RETLW #lit10,Wn Return with literal in Wn 1 6 (5) SFA

64 RETURN RETURN Return from Subroutine 1 6 (5) SFA
65 RLC RLC f f = Rotate Left through Carry f 1 1 C,N,Z
RLC f,WREG WREG = Rotate Left through Carry f 1 1 C,N,Z
RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C,N,Z
66 RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N,Z
RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N,Z
RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N,Z
67 RRC RRC f f = Rotate Right through Carry f 1 1 C,N,Z
RRC f,WREG WREG = Rotate Right through Carry f 1 1 C,N,Z
RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C,N,Z
68 RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N,Z
RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z
RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z
69 SAC SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None
SAC.R Acc,#Slit4,Wdo Store Rounded Accumulator 1 1 None
70 SE SE Ws,Wnd Wnd = sign-extended Ws 1 1 C,N,Z
71 SETM SETM f f = 0xFFFF 1 1 None
SETM WREG WREG = 0xFFFF 1 1 None
SETM Ws Ws = 0xFFFF 1 1 None
72 SFTAC SFTAC Acc,Wn Arithmetic Shift Accumulator by (Wn) 1 1 OA,OB,OAB,
SA,SB,SAB
SFTAC Acc,#Slit6 Arithmetic Shift Accumulator by Slit6 1 1 OA,OB,OAB,
SA,SB,SAB
73 SL SL f f = Left Shift f 1 1 C,N,OV,Z
SL f,WREG WREG = Left Shift f 1 1 C,N,OV,Z
SL Ws,Wd Wd = Left Shift Ws 1 1 C,N,OV,Z
SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N,Z
SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N,Z
74 SUB SUB Acc Subtract Accumulators 1 1 OA,OB,OAB,
SA,SB,SAB
SUB f f = f – WREG 1 1 C,DC,N,OV,Z
SUB f,WREG WREG = f – WREG 1 1 C,DC,N,OV,Z
SUB #lit10,Wn Wn = Wn – lit10 1 1 C,DC,N,OV,Z
SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C,DC,N,OV,Z
SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C,DC,N,OV,Z
75 SUBB SUBB f f = f – WREG – (C) 1 1 C,DC,N,OV,Z
SUBB f,WREG WREG = f – WREG – (C) 1 1 C,DC,N,OV,Z
SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C,DC,N,OV,Z
SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C,DC,N,OV,Z
SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C,DC,N,OV,Z
76 SUBR SUBR f f = WREG – f 1 1 C,DC,N,OV,Z
SUBR f,WREG WREG = WREG – f 1 1 C,DC,N,OV,Z
SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C,DC,N,OV,Z
SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 C,DC,N,OV,Z
77 SUBBR SUBBR f f = WREG – f – (C) 1 1 C,DC,N,OV,Z
SUBBR f,WREG WREG = WREG – f – (C) 1 1 C,DC,N,OV,Z
SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C,DC,N,OV,Z
SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 C,DC,N,OV,Z


Base
#
78 SWAP SWAP.b Wn Wn = nibble swap Wn 1 1 None

SWAP Wn Wn = byte swap Wn 1 1 None
79 TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 5 None
80 TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 5 None
81 TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None
82 TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None
83 ULNK ULNK Unlink Frame Pointer 1 1 SFA
84 XOR XOR f f = f .XOR. WREG 1 1 N,Z
XOR f,WREG WREG = f .XOR. WREG 1 1 N,Z
XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N,Z
XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N,Z
XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N,Z
85 ZE ZE Ws,Wnd Wnd = Zero-extend Ws 1 1 C,Z,N

29.0 DEVELOPMENT SUPPORT 29.1 MPLAB X Integrated Development

Environment Software
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user
of software and hardware development tools: interface for Microchip and third-party software, and
• Integrated Development Environment hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
- MPLAB® X IDE Software
MPLAB X IDE is an entirely new IDE with a host of free
• Compilers/Assemblers/Linkers software components and plug-ins for high-
- MPLAB XC Compiler performance application development and debugging.
- MPASMTM Assembler Moving between tools and upgrading from software
- MPLINKTM Object Linker/ simulators to hardware debugging and programming
MPLIBTM Object Librarian tools is simple with the seamless user interface.
- MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs,
Various Device Families a configurable watch window and a feature-rich editor
• Simulators that includes code completion and context menus,
- MPLAB X SIM Software Simulator MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
• Emulators
multiple projects with simultaneous debugging, MPLAB
- MPLAB REAL ICE™ In-Circuit Emulator X IDE is also suitable for the needs of experienced
• In-Circuit Debuggers/Programmers users.
- MPLAB ICD 3 Feature-Rich Editor:
- PICkit™ 3
• Color syntax highlighting
• Device Programmers
• Smart code completion makes suggestions and
- MPLAB PM3 Device Programmer provides hints as you type
• Low-Cost Demonstration/Development Boards, • Automatic code formatting based on user-defined
Evaluation Kits and Starter Kits rules
• Third-party development tools • Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
• Multiple projects
• Multiple tools
• Multiple configurations
• Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker

29.2 MPLAB XC Compilers 29.4 MPLINK Object Linker/

The MPLAB XC Compilers are complete ANSI C
MPLIB Object Librarian
compilers for all of Microchip’s 8, 16, and 32-bit MCU The MPLINK Object Linker combines relocatable
and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link
integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using
ease of use. MPLAB XC Compilers run on Windows, directives from a linker script.
Linux or MAC OS X.
The MPLIB Object Librarian manages the creation and
For easy source level debugging, the compilers provide modification of library files of precompiled code. When
debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only
IDE. the modules that contain that routine will be linked in
The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be
devices and commands, with no time or memory used efficiently in many different applications.
restrictions, and offer sufficient code optimization for The object linker/library features include:
most applications.
• Efficient linking of single libraries instead of many
MPLAB XC Compilers include an assembler, linker and smaller files
utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping
files that can then be archived or linked with other relo- related modules together
catable object files and archives to create an execut-
• Flexible creation of libraries with easy module
able file. MPLAB XC Compiler uses the assembler to
listing, replacement, deletion and extraction
produce its object file. Notable features of the assem-
bler include:
29.5 MPLAB Assembler, Linker and
• Support for the entire device instruction set
Librarian for Various Device
• Support for fixed-point and floating-point data
Families
• Command-line interface
• Rich directive set MPLAB Assembler produces relocatable machine
• Flexible macro language code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
• MPLAB X IDE compatibility
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
29.3 MPASM Assembler then be archived or linked with other relocatable object
The MPASM Assembler is a full-featured, universal files and archives to create an executable file. Notable
macro assembler for PIC10/12/16/18 MCUs. features of the assembler include:
The MPASM Assembler generates relocatable object • Support for the entire device instruction set
files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data
files, MAP files to detail memory usage and symbol • Command-line interface
reference, absolute LST files that contain source lines • Rich directive set
and generated machine code, and COFF files for • Flexible macro language
debugging.
• MPLAB X IDE compatibility
The MPASM Assembler features include:
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process

29.6 MPLAB X SIM Software Simulator 29.8 MPLAB ICD 3 In-Circuit Debugger
The MPLAB X SIM Software Simulator allows code
System
development in a PC-hosted environment by simulat- The MPLAB ICD 3 In-Circuit Debugger System is
ing the PIC MCUs and dsPIC DSCs on an instruction Microchip’s most cost-effective, high-speed hardware
level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash DSC and
examined or modified and stimuli can be applied from MCU devices. It debugs and programs PIC Flash
a comprehensive stimulus controller. Registers can be microcontrollers and dsPIC DSCs with the powerful,
logged to files for further run-time analysis. The trace yet easy-to-use graphical user interface of the MPLAB
buffer and logic analyzer display extend the power of IDE.
the simulator to record and track program execution,
The MPLAB ICD 3 In-Circuit Debugger probe is
actions on I/O, most peripherals and internal registers.
connected to the design engineer’s PC using a high-
The MPLAB X SIM Software Simulator fully supports speed USB 2.0 interface and is connected to the target
symbolic debugging using the MPLAB XC Compilers, with a connector compatible with the MPLAB ICD 2 or
and the MPASM and MPLAB Assemblers. The soft- MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
ware simulator offers the flexibility to develop and supports all MPLAB ICD 2 headers.
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software 29.9 PICkit 3 In-Circuit Debugger/
development tool.
Programmer
29.7 MPLAB REAL ICE In-Circuit The MPLAB PICkit 3 allows debugging and program-
Emulator System ming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
The MPLAB REAL ICE In-Circuit Emulator System is interface of the MPLAB IDE. The MPLAB PICkit 3 is
Microchip’s next generation high-speed emulator for connected to the design engineer’s PC using a full-
Microchip Flash DSC and MCU devices. It debugs and speed USB interface and can be connected to the tar-
programs all 8, 16 and 32-bit MCU, and DSC devices get via a Microchip debug (RJ-11) connector (compati-
with the easy-to-use, powerful graphical user interface of ble with MPLAB ICD 3 and MPLAB REAL ICE). The
the MPLAB X IDE. connector uses two device I/O pins and the Reset line
The emulator is connected to the design engineer’s to implement in-circuit debugging and In-Circuit Serial
PC using a high-speed USB 2.0 interface and is Programming™ (ICSP™).
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11) 29.10 MPLAB PM3 Device Programmer
or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection The MPLAB PM3 Device Programmer is a universal,
(CAT5). CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
The emulator is field upgradable through future firmware maximum reliability. It features a large LCD display
downloads in MPLAB X IDE. MPLAB REAL ICE offers (128 x 64) for menus and error messages, and a mod-
significant advantages over competitive emulators ular, detachable socket assembly to support various
including full-speed emulation, run-time variable package types. The ICSP cable assembly is included
watches, trace analysis, complex breakpoints, logic as a standard item. In Stand-Alone mode, the MPLAB
probes, a ruggedized probe interface and long (up to PM3 Device Programmer can read, verify and program
three meters) interconnection cables. PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.

29.11 Demonstration/Development 29.12 Third-Party Development Tools

Boards, Evaluation Kits, and Microchip also offers a great collection of tools from
Starter Kits third-party vendors. These tools are carefully selected
A wide variety of demonstration, development and to offer good value and unique functionality.
evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers
DSCs allows quick application development on fully from companies, such as SoftLog and CCS
functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel
areas for adding custom circuitry and provide applica- and Trace Systems
tion firmware and source code for examination and • Protocol Analyzers from companies, such as
modification. Saleae and Total Phase
The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as
temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex
interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies,
EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika®
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and demonstra-
tion software for analog filter design, KEELOQ® security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.

30.0 ELECTRICAL CHARACTERISTICS

This section provides an overview of dsPIC33EVXXXGM00X/10X family electrical characteristics. Additional
information will be provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the dsPIC33EVXXXGM00X/10X family are listed below. Exposure to these maximum
rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any
other conditions above the parameters indicated in the operation listings of this specification is not implied.
Absolute Maximum Ratings(1)

Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +160°C
Voltage on VDD with respect to VSS .......................................................................................................... -0.3V to +6.0V
Voltage on VCAP with respect to VSS ........................................................................................................ 1.62V to 1.98V
Maximum current out of VSS pin ...........................................................................................................................350 mA
Maximum current into VDD pin(2) ...........................................................................................................................350 mA
Maximum current sunk by any I/O pin.....................................................................................................................20 mA
Maximum current sourced by I/O pin ......................................................................................................................18 mA
Maximum current sourced/sunk by all ports(2) ......................................................................................................200 mA
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 30-2).

30.1 DC Characteristics
TABLE 30-1: OPERATING MIPS vs. VOLTAGE

VDD Range Temperature Range Maximum MIPS
Characteristic
(in Volts) (in °C) dsPIC33EVXXXGM00X/10X Family
(1,2)
I-Temp 4.5V to 5.5V -40°C to +85°C 70
E-Temp 4.5V to 5.5V(1,2) -40°C to +125°C 60
Note 1: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules: ADC, op amp/comparator and
comparator voltage reference will have degraded performance. Device functionality is tested but not
characterized. Refer to Parameter BO10 in Table 30-12 for the minimum and maximum BOR values.
2: When BOR is enabled, the device will work from 4.7V to 5.5V.
Note 1: Customer operating voltage range is specified as: 4.5V to 5.5V.
TABLE 30-2: THERMAL OPERATING CONDITIONS

Rating Symbol Min. Typ. Max. Unit
Industrial Temperature Devices:
Operating Junction Temperature Range TJ -40 — +125 °C
Operating Ambient Temperature Range TA -40 — +85 °C
Extended Temperature Devices:
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD –  IOH) PD PINT + PI/O W
I/O Pin Power Dissipation:
I/O =  ({VDD – VOH} x IOH) +  (VOL x IOL)
Maximum Allowed Power Dissipation PDMAX (TJ – TA)/JA W
TABLE 30-3: THERMAL PACKAGING CHARACTERISTICS

Characteristic Symbol Typ. Max. Unit Notes
Package Thermal Resistance, 64-Pin QFN, 9x9x0.9 mm JA 28.0 — °C/W 1
Package Thermal Resistance, 64-Pin TQFP, 10x10x1 mm JA 48.3 — °C/W 1
Package Thermal Resistance, 44-Pin QFN, 8x8 mm JA 29.0 — °C/W 1
Package Thermal Resistance, 44-Pin TQFP, 10x10x1 mm JA 49.8 — °C/W 1
Package Thermal Resistance, 28-Pin QFN-S, 6x6x0.9 mm JA 30.0 — °C/W 1
Package Thermal Resistance, 28-Pin SOIC, 7.50 mm JA 69.7 — °C/W 1
Package Thermal Resistance, 28-Pin SSOP, 5.30 mm JA 71.0 — °C/W 1
Package Thermal Resistance, 28-Pin SPDIP, 300 mil JA 60.0 — °C/W 1
Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.

TABLE 30-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS

Standard Operating Conditions (see Note 3): 4.5V to 5.5V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
Param
Symbol Characteristic Min. Typ.(1) Max. Units Conditions
No.
Operating Voltage
DC10 VDD Supply Voltage(3) VBOR — 5.5 V
(2)
DC12 VDR RAM Data Retention Voltage 1.8 — — V
DC16 VPOR VDD Start Voltage — — VSS V
to Ensure Internal
Power-on Reset Signal
DC17 SVDD VDD Rise Rate 1.0 — — V/ms 0V-5.0V in 5 ms
to Ensure Internal
DC18 VCORE VDD Core 1.62 1.8 1.98 V Voltage is dependent on
Internal Regulator Voltage load, temperature and
VDD
Note 1: Data in “Typ.” column is at 5.0V, +25°C unless otherwise stated.
2: This is the limit to which VDD may be lowered without losing RAM data.
3: VDD voltage must remain at VSS for a minimum of 200 s to ensure POR.
TABLE 30-5: FILTER CAPACITOR (CEFC) SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated):
Param
Symbol Characteristics Min. Typ. Max. Units Comments
No.
CEFC External Filter Capacitor 4.7 10 — F Capacitor must have a low
Value(1) series resistance (< 1)
Note 1: Typical VCAP Voltage = 1.8 volts when VDD  VDDMIN.

TABLE 30-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD)

Standard Operating Conditions: 4.5V to 5.5V
DC CHARACTERISTICS
Param. Typ.(2) Max. Units Conditions

Operating Current (IDD) (1)
DC20d 4.5 5.5 mA -40°C

DC20a 4.65 5.6 mA +25°C
5.0V 10 MIPS
DC20b 4.85 6.0 mA +85°C
DC20c 5.6 7.2 mA +125°C
DC22d 8.6 10.6 mA -40°C
DC22a 8.8 10.8 mA +25°C
5.0V 20 MIPS
DC22b 9.1 11.1 mA +85°C
DC22c 9.8 12.6 mA +125°C
DC23d 16.8 18.5 mA -40°C
DC23a 17.2 19.0 mA +25°C
5.0V 40 MIPS
DC23b 17.55 19.2 mA +85°C
DC23c 18.3 21.0 mA +125°C
DC24d 25.15 28.0 mA -40°C
DC24a 25.5 28.0 mA +25°C
5.0V 60 MIPS
DC24b 25.5 28.0 mA +85°C
DC24c 25.55 28.5 mA +125°C
DC25d 29.0 31.0 mA -40°C
DC25a 28.5 31.0 mA +25°C 5.0V 70 MIPS
DC25b 28.3 31.0 mA +85°C
Note 1: IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact
on the current consumption. The test conditions for all IDD measurements are as follows:
• Oscillator is configured in EC mode and external clock is active, OSC1 is driven with external square
wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as outputs and driving low
• MCLR = VDD, WDT and FSCM are disabled
• CPU, SRAM, program memory and data memory are operational
• No peripheral modules are operating or being clocked (defined PMDx bits are all ones)
• CPU executing
while(1)
{
NOP();
}
2: Data in “Typ.” column is at 5.0V, +25°C unless otherwise stated.

TABLE 30-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)

DC CHARACTERISTICS
Parameter
Typ.(2) Max. Units Conditions
No.
Idle Current (IIDLE)(1)
DC40d 1.25 2 mA -40°C
DC40a 1.25 2 mA +25°C
5.0V 10 MIPS
DC40b 1.5 2.6 mA +85°C
DC40c 1.5 2.6 mA +125°C
DC42d 2.3 3 mA -40°C
DC42a 2.3 3 mA +25°C
5.0V 20 MIPS
DC42b 2.6 3.45 mA +85°C
DC42c 2.6 3.85 mA +125°C
DC44d 6.9 8 mA -40°C
DC44a 6.9 8 mA +25°C 5.0V 70 MIPS
DC44b 7.25 8.6 mA +85°C
Note 1: Base Idle current (IIDLE) is measured as follows:
• CPU core is off, oscillator is configured in EC mode and external clock is active, OSC1 is driven with
external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• The NVMSIDL bit (NVMCON<12>) = 1 (i.e., Flash regulator is set to standby while the device is in
Idle mode)
• The VREGSF bit (RCON<11>) = 0 (i.e., Flash regulator is set to standby while the device is in
Sleep mode)

TABLE 30-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)

DC CHARACTERISTICS
Parameter
Typ.(2) Max. Units Conditions
No.
Power-Down Current (IPD) – dsPIC33EVXXXGM00X/10X(1)
DC60d 9.25 30 A -40°C
DC60a 15.75 35 A +25°C
5.0V Base Power-Down Current
DC60b 67.75 250 A +85°C
DC60c 270 750 A +125°C
DC61d 1 7 A -40°C
DC61a 1.25 8 A +25°C
5.0V Watchdog Timer Current: IWDT(3)
DC61b 3.5 12 A +85°C
DC61c 5 15 A +125°C
Note 1: IPD (Sleep) current is measured as follows:
• CPU core is off, oscillator is configured in EC mode and external clock is active, OSC1 is driven with
external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• All peripheral modules are disabled (PMDx bits are all ones)
• The VREGS bit (RCON<8>) = 0 (i.e., core regulator is set to standby while the device is in Sleep mode)
• The VREGSF bit (RCON<11>) = 0 (i.e., Flash regulator is set to standby while the device is in
Sleep mode)
3: The  current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.

TABLE 30-9: DC CHARACTERISTICS: DOZE CURRENT (IDOZE)

DC CHARACTERISTICS
Doze
Parameter No. Typ.(2) Max. Units Conditions
Ratio
Doze Current (IDOZE)(1)
DC73a 16.0 18.25 1:2 mA
-40°C 5.0V 70 MIPS
DC73g 7.1 8.0 1:128 mA
DC70a 16.25 18.5 1:2 mA
+25°C 5.0V 70 MIPS
DC70g 7.3 8.2 1:128 mA
DC71a 17.0 19.0 1:2 mA
+85°C 5.0V 70 MIPS
DC71g 7.5 8.9 1:128 mA
DC72a 17.75 19.95 1:2 mA
+125°C 5.0V 60 MIPS
DC72g 8.25 9.32 1:128 mA
Note 1: IDOZE is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact
on the current consumption. The test conditions for all IDOZE measurements are as follows:
• Oscillator is configured in EC mode and external clock is active, OSC1 is driven with external square
wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• CPU, SRAM, program memory and data memory are operational
• CPU executing
while(1)
{
NOP();
}

TABLE 30-10: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS

DC CHARACTERISTICS
Param
No.
VIL Input Low Voltage
DI10 I/O Pins VSS — 0.2 VDD V
VIH Input High Voltage
DI20 I/O Pins 0.75 VDD — 5.5 V
DI30 ICNPU Change Notification Pull-up 200 375 600 A VDD = 5.0V, VPIN = VSS
Current
DI31 ICNPD Change Notification 175 400 625 A VDD = 5.0V, VPIN = VDD
Pull-Down Current(7)
IIL Input Leakage Current(2,3)
DI50 I/O Pins -100 — 100 nA VSS  VPIN  VDD,
pin at high-impedance
DI55 MCLR -700 — 700 nA VSS VPIN VDD
DI56 OSC1 -200 — 200 nA VSS VPIN VDD,
XT and HS modes
DI60a IICL Input Low Injection Current 0 — -5(4,6) All pins except VDD, VSS,
AVDD, AVSS, MCLR,
VCAP and RB7
DI60b IICH Input High Injection Current 0 — +5(5,6) mA All pins except VDD, VSS,
AVDD, AVSS, MCLR,
VCAP, RB7 and all 5V
tolerant pins(5)
DI60c IICT Total Input Injection Current -20(7) — +20(7) Absolute instantaneous
(sum of all I/O and control sum of all ± input
pins) injection currents from all
I/O pins
( | IICL |+ | IICH | )  IICT
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current can be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: VIL source < (VSS – 0.3). Characterized but not tested.
5: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.
6: Non-zero injection currents can affect the ADC results by approximately 4-6 counts.
7: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted,
provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.

TABLE 30-11: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS

DC CHARACTERISTICS
Param. Symbol Characteristic Min.(1) Typ. Max. Units Conditions

DO16 VOL Output Low Voltage
4x Sink Driver Pins(2) — — 0.4 V IOL = 8.8 mA, VDD = 5.0V
DO10 VOL Output Low Voltage
DO26 VOH Output High Voltage
4x Sink Driver Pins(2) VDD – 0.6 — — V IOH = -8.3 mA, VDD = 5.0V
DO20 VOH Output High Voltage
8x Sink Driver Pins VDD – 0.6 — — V IOH = -12.3 mA, VDD = 5.0V
Note 1: Parameters are characterized, but not tested.
2: Includes all I/O pins that are not 8x sink driver pins (see below).
3: Includes pins, such as RA3, RA4 and RB<15:10> for 28-pin devices, RA3, RA4, RA9 and RB<15:10> for
44-pin devices and RA4, RA7, RA9, RB<15:10> and RC15 for 64-pin devices.
TABLE 30-12: ELECTRICAL CHARACTERISTICS: BOR

DC CHARACTERISTICS
Param
Symbol Characteristic Min.(1) Typ. Max. Units Conditions
No.
BO10 VBOR BOR Event on VDD Transition 4.15 4.285 4.4 V VDD (see Note 2, Note 3
High-to-Low and Note 4)
Note 1: Parameters are for design guidance only and are not tested in manufacturing.
2: The VBOR specification is relative to the VDD.
3: The device is functional at VBORMIN < VDD < VDDMIN. Analog modules: ADC, op amp/comparator and
comparator voltage reference will have degraded performance. Device functionality is tested but not
characterized.
4: The start-up VDD must rise above 4.6V.

TABLE 30-13: DC CHARACTERISTICS: PROGRAM MEMORY

DC CHARACTERISTICS
Param
No.
Program Flash Memory
D130 EP Cell Endurance 10,000 — — E/W -40C to +125C
D131 VPR VDD for Read 4.5 — 5.5 V
D132b VPEW VDD for Self-Timed Write 4.5 — 5.5 V
D134 TRETD Characteristic Retention 20 — — Year Provided no other specifications
are violated, -40C to +125C
D135 IDDP Supply Current During — 10 — mA
Programming
D136a TRW Row Write Cycle Time 0.657 — 0.691 ms TRW = 4965 FRC cycles,
TA = +85°C (see Note 2)
D136b TRW Row Write Cycle Time 0.651 — 0.698 ms TRW = 4965 FRC cycles,
D137a TPE Page Erase Time 19.44 — 20.44 ms TPE = 146893 FRC cycles,
D137b TPE Page Erase Time 19.24 — 20.65 ms TPE = 146893 FRC cycles,
D138a TWW Word Write Cycle Time 45.78 — 48.15 µs TWW = 346 FRC cycles,
D138b TWW Word Write Cycle Time 45.33 — 48.64 µs TWW = 346 FRC cycles,
2: Other conditions: FRC = 7.3728 MHz, TUN<5:0> = b'011111 (for Min), TUN<5:0> = b'100000 (for Max).
This parameter depends on the FRC accuracy (see Table 30-20) and the value of the FRC Oscillator
Tuning register.
TABLE 30-14: ELECTRICAL CHARACTERISTICS: INTERNAL BAND GAP REFERENCE VOLTAGE

DC CHARACTERISTICS
Param
Symbol Characteristic Min. Typ. Max. Units Conditions
No.
DVR10 VBG Internal Band Gap Reference 1.14 1.2 1.26 V
Voltage

30.2 AC Characteristics and Timing

Parameters
This section defines the dsPIC33EVXXXGM00X/10X family AC characteristics and timing parameters.
TABLE 30-15: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC

AC CHARACTERISTICS
Operating voltage VDD range as described in Section 30.1 “DC
Characteristics”.
FIGURE 30-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for All Pins except OSC2 Load Condition 2 – for OSC2
VDD/2
RL Pin CL
VSS
CL
Pin RL = 464
CL = 50 pF for all pins except OSC2
VSS 15 pF for OSC2 output
TABLE 30-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS

Param
No.
DO50 COSCO OSC2 Pin — — 15 pF In XT and HS modes, when
external clock is used to drive
OSC1
DO56 CIO All I/O Pins and OSC2 — — 50 pF EC mode
DO58 CB SCLx, SDAx — — 400 pF In I2C mode

FIGURE 30-2: EXTERNAL CLOCK TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
OS20
OS30 OS30 OS31 OS31
OS25
CLKO
OS41 OS40
TABLE 30-17: EXTERNAL CLOCK TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
Sym Characteristic Min. Typ.(1) Max. Units Conditions
No.
OS10 FIN External CLKI Frequency DC — 40 MHz EC
(External clocks allowed only
in EC and ECPLL modes)
Oscillator Crystal Frequency 3.5 — 10 MHz XT
10 — 25 MHz HS
OS20 TOSC TOSC = 1/FOSC 12.5 — DC ns TA = +125°C
OS25 TCY Instruction Cycle Time(2) 25 — DC ns TA = +125°C
OS30 TosL, External Clock in (OSC1) 0.375 x TOSC — 0.625 x TOSC ns EC
TosH High or Low Time
OS31 TosR, External Clock in (OSC1) — — 20 ns EC
TosF Rise or Fall Time
OS40 TckR CLKO Rise Time(3) — 5.2 — ns
OS41 TckF CLKO Fall Time(3) — 5.2 — ns
OS42 GM External Oscillator — 12 — mA/V HS, VDD = 5.0V,
Transconductance(4) TA = +25°C
— 6 — mA/V XT, VDD = 5.0V,
TA = +25°C
2: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type, under standard operating conditions,
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at
“Minimum” values with an external clock applied to the OSC1 pin. When an external clock input is used,
the “Maximum” cycle time limit is “DC” (no clock) for all devices.
3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.
4: This parameter is characterized but not tested in manufacturing.

TABLE 30-18: PLL CLOCK TIMING SPECIFICATIONS

AC CHARACTERISTICS
Param
No.
OS50 FPLLI PLL Voltage Controlled 0.8 — 8.0 MHz ECPLL, XTPLL modes
Oscillator (VCO) Input
Frequency Range
OS51 FSYS On-Chip VCO System 120 — 340 MHz
Frequency
OS52 TLOCK PLL Start-up Time (Lock Time) 0.9 1.5 3.1 ms
OS53 DCLK CLKO Stability (Jitter)(2) -3 0.5 3 %
Note 1: Data in “Typ.” column is at 5.0V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: This jitter specification is based on clock cycle-by-clock cycle measurements. To get the effective jitter for
individual time bases or communication clocks used by the application, use the following formula:
D CLK
Effective Jitter = -------------------------------------------------------------------------------------------
F OSC
---------------------------------------------------------------------------------------
Time Base or Communication Clock
For example, if FOSC = 120 MHz and the SPI bit rate = 10 MHz, the effective jitter is as follows:
D CLK D CLK D CLK
Effective Jitter = -------------- = -------------- = --------------
120 12 3.464
---------
10
TABLE 30-19: INTERNAL FRC ACCURACY

Standard Operating Conditions: 4.5V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial
Param
Characteristic Min. Typ. Max. Units Conditions
No.
Internal FRC Accuracy @ FRC Frequency = 7.37 MHz(1)
F20a FRC -1 0.5 +1 % -40°C  TA +85°C VDD = 4.5-5.5V
F20b FRC -2 1 +2 % -40°C  TA  +125°C VDD = 4.5-5.5V
Note 1: Frequency calibrated at +25°C and 5.0V. TUN<5:0> bits can be used to compensate for temperature drift.
TABLE 30-20: INTERNAL LPRC ACCURACY

AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial
Param
Characteristic Min. Typ. Max. Units Conditions
No.
LPRC @ 32.768 kHz(1)
F21a LPRC -15 5 +15 % -40°C  TA  +85°C VDD = 4.5-5.5V
F21b LPRC -30 10 +30 % -40°C  TA  +125°C VDD = 4.5-5.5V
Note 1: Change of LPRC frequency as VDD changes.

FIGURE 30-3: I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin Old Value New Value

(Output)
DO31
DO32
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-21: I/O TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
No.
DO31 TIOR Port Output Rise Time — 5 10 ns
DO32 TIOF Port Output Fall Time — 5 10 ns
DI35 TINP INTx Pin High or Low Time (input) 20 — — ns
DI40 TRBP CNx High or Low Time (input) 2 — — TCY
FIGURE 30-4: BOR AND MASTER CLEAR RESET TIMING CHARACTERISTICS
MCLR
TMCLR
(SY20)
BOR
TBOR Various Delays (depending on configuration)

(SY30)
Reset Sequence
CPU Starts Fetching Code

FIGURE 30-5: POWER-ON RESET TIMING CHARACTERISTICS
Power-up Timer – Clock Sources = (FRC, FRCDIVN, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
VDD
VPOR
Power-up Sequence
SY00 SY11
(TPU) (TPWRT)
(Notes 1,2)
Power-up Timer – Clock Sources = (HS, HSPLL, XT and XTPLL)

VDD
VPOR
Power-up Sequence
SY00 Greater of
(TPU) SY10 (TOST)
(Notes 1,2) or
SY11 (TPWRT)
Note 1: The power-up period will be extended if the power-up sequence completes before the device exits from
BOR (VDD < VBOR).
2: The power-up period includes internal voltage regulator stabilization delay.

TABLE 30-22: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions
No.
SY00 TPU Power-up Period — 400 600 µs
SY10 TOST Oscillator Start-up — 1024 TOS — — TOSC = OSC1 period
Time C
SY11 TPWRT Power-up Timer — 1 — ms Using LPRC parameters indicated in
Period F21a/F21b (see Table 30-20)
SY12 TWDT Watchdog Timer 0.8 — 1.2 ms WDTPRE = 0, WDTPS<3:0> = 0000,
Time-out Period using LPRC tolerances indicated in
F21a/F21b (see Table 30-20) at
+85°C
3.2 — 4.8 ms WDTPRE = 1, WDTPS<3:0> = 0000,
using LPRC tolerances indicated in
F21a/F21b (see Table 30-20) at
+85°C
SY13 TIOZ I/O High-Impedance 0.68 0.72 1.2 µs
from MCLR Low or
Watchdog Timer
Reset
SY20 TMCLR MCLR Pulse Width 2 — — µs
(low)
SY30 TBOR BOR Pulse Width 1 — — ms
(low)
SY35 TFSCM Fail-Safe Clock — 500 900 µs -40°C to +85°C
Monitor Delay
SY36 TVREG Voltage Regulator — — 30 µs
Standby-to-Active
mode Transition Time
SY37 TOSCDFRC FRC Oscillator 46 48 54 µs
Start-up Delay
SY38 TOSCDLPRC LPRC Oscillator — — 70 µs
Start-up Delay
Note 1: These parameters are characterized but not tested in manufacturing.

FIGURE 30-6: TIMER1-TIMER5 EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx10 Tx11
Tx15 Tx20
OS60
TMRx
TABLE 30-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)

AC CHARACTERISTICS
Param
Symbol Characteristic(2) Min. Typ. Max. Units Conditions
No.
TA10 TTXH T1CK High Synchronous Greater of: — — ns Must also meet
Time mode 20 or Parameter TA15,
(TCY + 20)/N N = Prescaler
Value (1, 8, 64,
256)
Asynchronous 35 — — ns
mode
TA11 TTXL T1CK Low Synchronous Greater of: — — ns Must also meet
Time mode 20 or Parameter TA15,
(TCY + 20)/N N = Prescaler
Value (1, 8, 64,
256)
Asynchronous 10 — — ns
mode
TA15 TTXP T1CK Input Synchronous Greater of: — — ns N = Prescaler
Period mode 40 or Value
(2 TCY + 40)/N (1, 8, 64, 256)
OS60 Ft1 T1CK Oscillator Input DC — 50 kHz
Frequency Range (oscillator
enabled by setting TCS
(T1CON<1>) bit)
TA20 TCKEXTMRL Delay from External T1CK 0.75 TCY + 40 — 1.75 TCY + 40 ns
Clock Edge to Timer
Increment
Note 1: Timer1 is a Type A.
2: These parameters are characterized but not tested in manufacturing.

TABLE 30-24: TIMER2 AND TIMER4 (TYPE B TIMER) EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
No.
TB10 TTXH TxCK High Synchronous Greater of: — — ns Must also meet
Time mode 20 or Parameter TB15,
(TCY + 20)/N N = Prescaler Value
(1, 8, 64, 256)
TB11 TTXL TxCK Low Synchronous Greater of: — — ns Must also meet
Time mode 20 or Parameter TB15,
(TCY + 20)/N N = Prescaler Value
(1, 8, 64, 256)
TB15 TTXP TxCK Input Synchronous Greater of: — — ns N = Prescaler Value
Period mode 40 or (1, 8, 64, 256)
(2 TCY + 40)/N
TB20 TCKEXT- Delay from External TxCK 0.75 TCY + 40 — 1.75 TCY + 40 ns
MRL Clock Edge to Timer
Increment
TABLE 30-25: TIMER3 AND TIMER5 (TYPE C TIMER) EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
No.
TC10 TTXH TxCK High Synchronous TCY + 20 — — ns Must also meet
Time Parameter TC15
TC11 TTXL TxCK Low Synchronous TCY + 20 — — ns Must also meet
Time Parameter TC15
TC15 TTXP TxCK Input Synchronous, 2 TCY + 40 — — ns N = Prescaler Value
Period with Prescaler (1, 8, 64, 256)
TC20 TCKEXT- Delay from External TxCK 0.75 TCY + 40 — 1.75 TCY + 40 ns
MRL Clock Edge to Timer
Increment

FIGURE 30-7: INPUT CAPTURE x (ICx) TIMING CHARACTERISTICS
ICx
IC10 IC11
IC15
Note 1: Refer to Figure 30-1 for load conditions.
TABLE 30-26: INPUT CAPTURE x (ICx) TIMING REQUIREMENTS

AC CHARACTERISTICS
Param.
Symbol Characteristics(1) Min. Max. Units Conditions
No.
IC10 TCCL ICx Input Low Time Greater of: — ns Must also meet
12.5 + 25 or Parameter IC15
(0.5 TCY/N) + 25
IC11 TCCH ICx Input High Time Greater of: — ns Must also meet
N = Prescaler
12.5 + 25 or Parameter IC15
Value (1, 4, 16)
(0.5 TCY/N) + 25
IC15 TCCP ICx Input Period Greater of: — ns
25 + 50 or
(1 TCY/N) + 50

FIGURE 30-8: OUTPUT COMPARE x (OCx) TIMING CHARACTERISTICS
OCx
(Output Compare
or PWM Mode)
OC11 OC10
TABLE 30-27: OUTPUT COMPARE x (OCx) TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
No.
OC10 TCCF OCx Output Fall Time — — — ns See Parameter DO32
OC11 TCCR OCx Output Rise Time — — — ns See Parameter DO31
FIGURE 30-9: OCx/PWMx MODULE TIMING CHARACTERISTICS
OC20
OCFA
OC15
OCx
TABLE 30-28: OCx/PWMx MODE TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
No.
OC15 TFD Fault Input to PWMx I/O — — TCY + 20 ns
Change
OC20 TFLT Fault Input Pulse Width TCY + 20 — — ns

FIGURE 30-10: HIGH-SPEED PWMx MODULE FAULT TIMING CHARACTERISTICS
MP30
Fault Input
(active-low)
MP20
PWMx
FIGURE 30-11: HIGH-SPEED PWMx MODULE TIMING CHARACTERISTICS
MP11 MP10
PWMx
TABLE 30-29: HIGH-SPEED PWMx MODULE TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
No.
MP10 TFPWM PWMx Output Fall Time — — — ns See Parameter DO32
MP11 TRPWM PWMx Output Rise Time — — — ns See Parameter DO31
MP20 TFD Fault Input  to PWMx — — 15 ns
I/O Change
MP30 TFH Fault Input Pulse Width 15 — — ns

TABLE 30-30: SPI2 MAXIMUM DATA/CLOCK RATE SUMMARY

AC CHARACTERISTICS
Master Master Slave
Maximum
Transmit Only Transmit/Receive Transmit/Receive CKE CKP SMP
Data Rate
(Half-Duplex) (Full-Duplex) (Full-Duplex)
15 MHz Table 30-31 — — 0,1 0,1 0,1
9 MHz — Table 30-32 — 1 0,1 1
9 MHz — Table 30-33 — 0 0,1 1
15 MHz — — Table 30-34 1 0 0
11 MHz — — Table 30-35 1 1 0
15 MHz — — Table 30-36 0 1 0
11 MHz — — Table 30-37 0 0 0
FIGURE 30-12: SPI2 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 0) TIMING
CHARACTERISTICS
SCK2
(CKP = 0)
SP10 SP21 SP20
SCK2
(CKP = 1)
SP35 SP20 SP21
SDO2 MSb Bit 14 - - - - - -1 LSb
SP30, SP31 SP30, SP31

FIGURE 30-13: SPI2 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 1) TIMING
CHARACTERISTICS
SP36
SCK2
(CKP = 0)
SP10 SP21 SP20
SCK2
(CKP = 1)
SP35 SP20 SP21
SDO2 MSb Bit 14 - - - - - -1 LSb
SP30, SP31
TABLE 30-31: SPI2 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS
AC CHARACTERISTICS
Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions
SP10 FscP Maximum SCK2 Frequency — — 15 MHz See Note 3
SP20 TscF SCK2 Output Fall Time — — — ns See Parameter DO32
and Note 4
SP21 TscR SCK2 Output Rise Time — — — ns See Parameter DO31
and Note 4
SP30 TdoF SDO2 Data Output Fall Time — — — ns See Parameter DO32
and Note 4
SP31 TdoR SDO2 Data Output Rise Time — — — ns See Parameter DO31
and Note 4
SP35 TscH2doV, SDO2 Data Output Valid after — 6 20 ns
TscL2doV SCK2 Edge
SP36 TdiV2scH, SDO2 Data Output Setup to 30 — — ns
TdiV2scL First SCK2 Edge
3: The minimum clock period for SCK2 is 66.7 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPI2 pins.

FIGURE 30-14: SPI2 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING
CHARACTERISTICS
SP36
SCK2
(CKP = 0)
SP10 SP21 SP20
SCK2
(CKP = 1)
SP35 SP20 SP21
SDO2 MSb Bit 14 - - - - - -1 LSb
SP40 SP30, SP31
SDI2 MSb In Bit 14 - - - -1 LSb In

SP41
TABLE 30-32: SPI2 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1)

TIMING REQUIREMENTS
AC CHARACTERISTICS
and Note 4
and Note 4
and Note 4
SP31 TdoR SDO2 Data Output Rise — — — ns See Parameter DO31
Time and Note 4
TscL2doV SCK2 Edge
SP36 TdoV2sc, SDO2 Data Output Setup to 30 — — ns
TdoV2scL First SCK2 Edge
SP40 TdiV2scH, Setup Time of SDI2 Data 30 — — ns
TdiV2scL Input to SCK2 Edge
SP41 TscH2diL, Hold Time of SDI2 Data Input 30 — — ns
TscL2diL to SCK2 Edge
3: The minimum clock period for SCK2 is 111 ns. The clock generated in Master mode must not violate this
specification.

FIGURE 30-15: SPI2 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING
CHARACTERISTICS
SCK2
(CKP = 0)
SP10 SP21 SP20
SCK2
(CKP = 1)
SP35 SP36 SP20 SP21
SDO2 MSb Bit 14 - - - - - -1 LSb
SP30, SP31 SP30, SP31
SP40 SP41

TIMING REQUIREMENTS
AC CHARACTERISTICS

SP10 FscP Maximum SCK2 Frequency — — 9 MHz -40ºC to +125ºC and
see Note 3
and Note 4
and Note 4
and Note 4
Time and Note 4
TscL2doV SCK2 Edge
SP36 TdoV2scH, SDO2 Data Output Setup to 30 — — ns
3: The minimum clock period for SCK2 is 111 ns. The clock generated in Master mode must not violate this
specification.

FIGURE 30-16: SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING
CHARACTERISTICS
SP60
SS2
SP50 SP52
SCK2
(CKP = 0)
SP70 SP73 SP72
SCK2
(CKP = 1) SP36
SP35 SP72 SP73
SDO2 MSb Bit 14 - - - - - -1 LSb
SP30, SP31 SP51

SP41
SP40

TABLE 30-34: SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0)

TIMING REQUIREMENTS
AC CHARACTERISTICS
SP70 FscP Maximum SCK2 Input Frequency — — 15 MHz See Note 3
SP72 TscF SCK2 Input Fall Time — — — ns See Parameter DO32
and Note 4
SP73 TscR SCK2 Input Rise Time — — — ns See Parameter DO31
and Note 4
and Note 4
and Note 4
TscL2doV SCK2 Edge
SP40 TdiV2scH, Setup Time of SDI2 Data Input 30 — — ns
TdiV2scL to SCK2 Edge
SP50 TssL2scH, SS2  to SCK2  or SCK2  120 — — ns
TssL2scL Input
SP51 TssH2doZ SS2  to SDO2 Output 10 — 50 ns See Note 4
High-Impedance
SP52 TscH2ssH SS2 after SCK2 Edge 1.5 TCY + 40 — — ns See Note 4
TscL2ssH
SP60 TssL2doV SDO2 Data Output Valid after — — 50 ns
SS2 Edge
3: The minimum clock period for SCK2 is 66.7 ns. Therefore, the SCK2 clock generated by the master must
not violate this specification.

CHARACTERISTICS
SP60
SS2
SP50 SP52
SCK2
(CKP = 0)
SP70 SP73 SP72
SCK2
(CKP = 1) SP36
SP35 SP72 SP73
SDO2 MSb Bit 14 - - - - - -1 LSb
SP30, SP31 SP51

SP41
SP40


TIMING REQUIREMENTS
AC CHARACTERISTICS
and Note 4
and Note 4
and Note 4
and Note 4
TscL2doV SCK2 Edge
TssL2scL Input
High-Impedance
TscL2ssH
SS2 Edge
3: The minimum clock period for SCK2 is 91 ns. Therefore, the SCK2 clock generated by the master must

CHARACTERISTICS
SS2
SP50 SP52
SCK2
(CKP = 0)
SP70 SP73 SP72
SCK2
(CKP = 1)
SP72 SP73
SP35 SP36
SDO2 MSb Bit 14 - - - - - -1 LSb
SP30, SP31 SP51
SP41
SP40


TIMING REQUIREMENTS
AC CHARACTERISTICS
and Note 4
and Note 4
and Note 4
and Note 4
TscL2doV SCK2 Edge
TssL2scL Input
High-Impedance
TscL2ssH
3: The minimum clock period for SCK2 is 66.7 ns. Therefore, the SCK2 clock generated by the master must

CHARACTERISTICS
SS2
SP50 SP52
SCK2
(CKP = 0)
SP70 SP73 SP72
SCK2
(CKP = 1)
SP72 SP73
SP35 SP36
SDO2 MSb Bit 14 - - - - - -1 LSb
SP30, SP31 SP51

SP41
SP40


TIMING REQUIREMENTS
AC CHARACTERISTICS
and Note 4
and Note 4
and Note 4
and Note 4
TscL2doV SCK2 Edge
TssL2scL Input
High-Impedance
TscL2ssH

TABLE 30-38: SPI1 MAXIMUM DATA/CLOCK RATE SUMMARY

AC CHARACTERISTICS
Master Master Slave
Maximum
Transmit Only Transmit/Receive Transmit/Receive CKE CKP SMP
Data Rate
(Half-Duplex) (Full-Duplex) (Full-Duplex)
25 MHz Table 30-39 — — 0,1 0,1 0,1
25 MHz — Table 30-40 — 1 0,1 1
25 MHz — Table 30-41 — 0 0,1 1
25 MHz — — Table 30-42 1 0 0
25 MHz — — Table 30-43 1 1 0
25 MHz — — Table 30-44 0 1 0
25 MHz — — Table 30-45 0 0 0
FIGURE 30-20: SPI1 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 0)

TIMING CHARACTERISTICS
SCK1
(CKP = 0)
SP10 SP21 SP20
SCK1
(CKP = 1)
SP35 SP20 SP21
SDO1 MSb Bit 14 - - - - - -1 LSb
SP30, SP31 SP30, SP31

FIGURE 30-21: SPI1 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 1)

SP36
SCK1
(CKP = 0)
SP10 SP21 SP20
SCK1
(CKP = 1)
SP35 SP20 SP21
SDO1 MSb Bit 14 - - - - - -1 LSb
SP30, SP31
TABLE 30-39: SPI1 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS
AC CHARACTERISTICS
and Note 4
and Note 4
and Note 4
and Note 4
TscL2doV SCK1 Edge
SP36 TdiV2scH, SDO1 Data Output Setup to 20 — — ns
TdiV2scL First SCK1 Edge
3: The minimum clock period for SCK1 is 40 ns. Therefore, the clock generated in Master mode must not

FIGURE 30-22: SPI1 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1)

SP36
SCK1
(CKP = 0)
SP10 SP21 SP20
SCK1
(CKP = 1)
SP35 SP20 SP21
SDO1 MSb Bit 14 - - - - - -1 LSb
SP40 SP30, SP31

SP41
TABLE 30-40: SPI1 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING
REQUIREMENTS
AC CHARACTERISTICS
and Note 4
and Note 4
and Note 4
Time and Note 4
TscL2doV SCK1 Edge
SP36 TdoV2sc, SDO1 Data Output Setup to 20 — — ns

FIGURE 30-23: SPI1 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1)

SCK1
(CKP = 0)
SP10 SP21 SP20
SCK1
(CKP = 1)
SP35 SP36 SP20 SP21
SDO1 MSb Bit 14 - - - - - -1 LSb
SP30, SP31 SP30, SP31
SD1 MSb In Bit 14 - - - -1 LSb In
SP40 SP41


TIMING REQUIREMENTS
AC CHARACTERISTICS
SP10 FscP Maximum SCK1 Frequency — — 25 MHz -40°C to +125°C and
see Note 3
and Note 4
and Note 4
and Note 4
Time and Note 4
TscL2doV SCK1 Edge

FIGURE 30-24: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0)

SP60
SS1
SP50 SP52
SCK1
(CKP = 0)
SP70 SP73 SP72
SCK1
(CKP = 1) SP36
SP35 SP72 SP73
SDO1 MSb Bit 14 - - - - - -1 LSb
SP30, SP31 SP51

SP41
SP40


TIMING REQUIREMENTS
AC CHARACTERISTICS
and Note 4
and Note 4
and Note 4
and Note 4
TscL2doV SCK1 Edge
SP40 TdiV2scH, Setup Time of SDIx Data Input 20 — — ns
TssL2scL Input
High-Impedance
TscL2ssH
SS1 Edge


SP60
SS1
SP50 SP52
SCK1
(CKP = 0)
SP70 SP73 SP72
SCK1
(CKP = 1) SP36
SP35 SP72 SP73
SDO1 MSb Bit 14 - - - - - -1 LSb
SP30, SP31 SP51

SP41
SP40


TIMING REQUIREMENTS
AC CHARACTERISTICS
and Note 4
and Note 4
and Note 4
and Note 4
TscL2doV SCK1 Edge
TssL2scL Input
High-Impedance
SP52 TscH2ssH, SS1 after SCK1 Edge 1.5 TCY + 40 — — ns See Note 4
TscL2ssH
SS1 Edge


SS1
SP50 SP52
SCK1
(CKP = 0)
SP70 SP73 SP72
SCK1
(CKP = 1)
SP72 SP73
SP35 SP36
SDO1 MSb Bit 14 - - - - - -1 LSb
SP30, SP31 SP51

SP41
SP40


TIMING REQUIREMENTS
AC CHARACTERISTICS
and Note 4
and Note 4
and Note 4
and Note 4
TscL2doV SCK1 Edge
TssL2scL Input
High-Impedance
TscL2ssH


SS1
SP50 SP52
SCK1
(CKP = 0)
SP70 SP73 SP72
SCK1
(CKP = 1)
SP72 SP73
SP35 SP36
SDO1 MSb Bit 14 - - - - - -1 LSb
SP30, SP31 SP51
SP41
SP40


TIMING REQUIREMENTS
AC CHARACTERISTICS
and Note 4
and Note 4
and Note 4
and Note 4
TscL2doV SCK1 Edge
TssL2scL Input
High-Impedance
TscL2ssH

FIGURE 30-28: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx
IM31 IM34
IM30 IM33
SDAx
Start Stop
Condition Condition
FIGURE 30-29: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20 IM11 IM21

IM10
SCLx
IM26
IM11
IM10 IM25 IM33
SDAx
In
IM40 IM40 IM45
SDAx
Out

TABLE 30-46: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)

AC CHARACTERISTICS
Param
Symbol Characteristic(4) Min.(1) Max. Units Conditions
No.
IM10 TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 2) — s
400 kHz mode TCY/2 (BRG + 2) — s
1 MHz mode(2) TCY/2 (BRG + 2) — s
IM11 THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 2) — s
400 kHz mode TCY/2 (BRG + 2) — s
IM20 TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be
Fall Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF
1 MHz mode (2) — 100 ns
IM21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be
Rise Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF
1 MHz mode (2)
— 300 ns
IM25 TSU:DAT Data Input 100 kHz mode 250 — ns
Setup Time 400 kHz mode 100 — ns
1 MHz mode(2) 40 — ns
IM26 THD:DAT Data Input 100 kHz mode 0 — s
Hold Time 400 kHz mode 0 0.9 s
1 MHz mode(2) 0.2 — s
IM30 TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 2) — s Only relevant for
Setup Time 400 kHz mode TCY/2 (BRG + 2) — s Repeated Start
1 MHz mode (2)
TCY/2 (BRG + 2) — s condition
IM31 THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 2) — s After this period, the
Hold Time 400 kHz mode TCY/2 (BRG +2) — s first clock pulse is
1 MHz mode (2)
TCY/2 (BRG + 2) — s generated
IM33 TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 2) — s
Setup Time 400 kHz mode TCY/2 (BRG + 2) — s
IM34 THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 2) — s
Hold Time 400 kHz mode TCY/2 (BRG + 2) — s
IM40 TAA:SCL Output Valid 100 kHz mode — 3500 ns
From Clock 400 kHz mode — 1000 ns
1 MHz mode(2) — 400 ns
IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s Time the bus must be
400 kHz mode 1.3 — s free before a new
1 MHz mode (2) 0.5 — s transmission can start
IM50 CB Bus Capacitive Loading — 400 pF
IM51 TPGD Pulse Gobbler Delay 65 390 ns See Note 3
Note 1: BRG is the value of the I2C Baud Rate Generator. Refer to “Inter-Integrated Circuit™ (I2C™)”
(DS70000195) in the “dsPIC33/PIC24 Family Reference Manual”. Please see the Microchip web site for
the latest “dsPIC33/PIC24 Family Reference Manual” sections.
2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
3: Typical value for this parameter is 130 ns.

FIGURE 30-30: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
IS31 IS34
IS30 IS33
SDAx
Start Stop
Condition Condition
FIGURE 30-31: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20 IS11 IS21

IS10
SCLx
IS26
IS30 IS25
IS31 IS33
SDAx
In
IS40 IS40 IS45
SDAx
Out

TABLE 30-47: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)

AC CHARACTERISTICS
Param.
Symbol Characteristic(3) Min. Max. Units Conditions
No.
IS10 TLO:SCL Clock Low Time 100 kHz mode 4.7 — s
400 kHz mode 1.3 — s
1 MHz mode(1) 0.5 — s
IS11 THI:SCL Clock High Time 100 kHz mode 4.0 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 0.6 — s Device must operate at a
minimum of 10 MHz
1 MHz mode(1) 0.5 — s
IS20 TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be from
Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF
1 MHz mode (1) — 100 ns
IS21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be from
Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF
1 MHz mode(1) — 300 ns
IS25 TSU:DAT Data Input 100 kHz mode 250 — ns
Setup Time 400 kHz mode 100 — ns
1 MHz mode(1) 100 — ns
IS26 THD:DAT Data Input 100 kHz mode 0 — s
Hold Time 400 kHz mode 0 0.9 s
1 MHz mode(1) 0 0.3 s
IS30 TSU:STA Start Condition 100 kHz mode 4.7 — s Only relevant for Repeated
Setup Time 400 kHz mode 0.6 — s Start condition
1 MHz mode (1) 0.25 — s
IS31 THD:STA Start Condition 100 kHz mode 4.0 — s After this period, the first
Hold Time 400 kHz mode 0.6 — s clock pulse is generated
1 MHz mode(1) 0.25 — s
IS33 TSU:STO Stop Condition 100 kHz mode 4.7 — s
Setup Time 400 kHz mode 0.6 — s
1 MHz mode(1) 0.6 — s
IS34 THD:STO Stop Condition 100 kHz mode 4 — s
Hold Time 400 kHz mode 0.6 — s
1 MHz mode(1) 0.25 s
IS40 TAA:SCL Output Valid 100 kHz mode 0 3500 ns
From Clock 400 kHz mode 0 1000 ns
1 MHz mode (1) 0 350 ns
IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free
400 kHz mode 1.3 — s before a new transmission
1 MHz mode(1) 0.5 — s can start
IS50 CB Bus Capacitive Loading — 400 pF
IS51 TPGD Pulse Gobbler Delay 65 390 ns See Note 2
Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
2: The typical value for this parameter is 130 ns.

FIGURE 30-32: CANx MODULE I/O TIMING CHARACTERISTICS
CxTX Pin Old Value New Value

(output)
CA10, CA11
CxRX Pin
(input)
CA20
TABLE 30-48: CANx MODULE I/O TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
No.
CA10 TIOF Port Output Fall Time — — — ns See Parameter DO32
CA11 TIOR Port Output Rise Time — — — ns See Parameter DO31
CA20 TCWF Pulse Width to Trigger 120 — — ns
CAN Wake-up Filter
2: Data in “Typ.” column is at 5.0V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
FIGURE 30-33: UARTx MODULE I/O TIMING CHARACTERISTICS
UA20
UxRX MSb In Bits 6-1 LSb In

UxTX
UA10
TABLE 30-49: UARTx MODULE I/O TIMING REQUIREMENTS

AC CHARACTERISTICS (unless otherwise stated)
Operating temperature -40°C  TA  +125°C
Param
No.
UA10 TUABAUD UARTx Baud Time 66.67 — — ns
UA11 FBAUD UARTx Baud Frequency — — 15 Mbps
UA20 TCWF Start Bit Pulse Width to Trigger 500 — — ns
UARTx Wake-up
2: Data in “Typ.” column is at 5.0V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.

TABLE 30-50: OP AMP/COMPARATOR x SPECIFICATIONS

DC CHARACTERISTICS
Param
No.
Comparator AC Characteristics
CM10 TRESP Response Time — 19 80 ns V+ input step of 100 mV,
V- input held at VDD/2
CM11 TMC2OV Comparator Mode — — 10 µs
Change to Output Valid
Comparator DC Characteristics
CM30 VOFFSET Comparator Offset -80 ±60 80 mV
Voltage
CM31 VHYST Input Hysteresis Voltage — 30 — mV
CM32 TRISE/ Comparator Output — 20 — ns 1 pF load capacitance
TFALL Rise/Fall Time on input
CM33 VGAIN Open-Loop Voltage Gain — 90 — db
CM34 VICM Input Common-Mode AVSS — AVDD V
Voltage
Op Amp AC Characteristics
CM20 SR Slew Rate — 9 — V/µs 10 pF load
CM21 PM Phase Margin — 35 — °C G = 100V/V, 10 pF load
CM22 GM Gain Margin — 20 — db G = 100V/V, 10 pF load
CM23 GBW Gain Bandwidth — 10 — MHz 10 pF load
Op Amp DC Characteristics
CM40 VCMR Common-Mode Input AVSS — AVDD V
Voltage Range
CM41 CMRR Common-Mode — 45 — db VCM = AVDD/2
Rejection Ratio
CM42 VOFFSET Op Amp Offset Voltage -50 ±6 50 mV
CM43 VGAIN Open-Loop Voltage Gain — 90 — db
CM44 IOS Input Offset Current — — — — See pad leakage
currents in Table 30-10
CM45 IB Input Bias Current — — — — See pad leakage
currents in Table 30-10
CM46 IOUT Output Current — — 420 µA With minimum value of
RFEEDBACK (CM48)
CM48 RFEEDBACK Feedback Resistance 8 — — k Note 2
Value
CM49a VOUT Output Voltage AVSS + 0.075 — AVDD – 0.075 V IOUT = 420 µA

2: Resistances can vary by ±10% between op amps.
3: Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality
is tested, but not characterized. Analog modules: ADC, op amp/comparator and comparator voltage
reference, will have degraded performance. Refer to Parameter BO10 in Table 30-12 for the minimum and
maximum BOR values.

TABLE 30-51: OP AMP/COMPARATOR x VOLTAGE REFERENCE SETTLING TIME SPECIFICATIONS

AC CHARACTERISTICS
Param. Symbol Characteristic Min. Typ. Max. Units Conditions
VRD310 TSET Settling Time — 1 10 s See Note 1
Note 1: Settling time measured while CVRSS = 1 and the CVR<6:0> bits transition from ‘0000000’ to ‘1111111’.
maximum BOR values.
TABLE 30-52: OP AMP/COMPARATOR x VOLTAGE REFERENCE SPECIFICATIONS

DC CHARACTERISTICS
Param
Symbol Characteristics Min. Typ. Max. Units Conditions
No.
VRD311 CVRAA Absolute Accuracy of — ±25 — mV AVDD = CVRSRC = 5.0V
Internal DAC Input to
Comparators
VRD312 CVRAA1 Absolute Accuracy of — — +35/-65 mV AVDD = CVRSRC = 5.0V
CVREFxO Pins
VRD313 CVRSRC Input Reference Voltage 0 — AVDD + 0.3 V
VRD314 CVROUT Buffer Output Resistance — 1.5k — 
VRD315 CVCL Permissible Capacitive — — 25 pF
Load (CVREFxO pins)
VRD316 IOCVR Permissible Current — — 1 mA
Output (CVREFxO pins)
VRD317 ION Current Consumed when — — 500 µA AVDD = 5.0V
Module is Enabled
VRD318 IOFF Current Consumed when — — 1 nA AVDD = 5.0V
Module is Disabled
Note 1: Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality
maximum BOR values.

TABLE 30-53: CTMU CURRENT SOURCE SPECIFICATIONS

DC CHARACTERISTICS
Param
No.
CTMU Current Source
CTMUI1 IOUT1 Base Range — 550 — nA CTMUICON<9:8> = 01
CTMUI2 IOUT2 10x Range — 5.5 — µA CTMUICON<9:8> = 10
CTMUI3 IOUT3 100x Range — 55 — µA CTMUICON<9:8> = 11
CTMUI4 IOUT4 1000x Range — 550 — µA CTMUICON<9:8> = 00
CTMUFV1 VF Temperature Diode Forward — 0.525 — V TA = +25°C,
Voltage(1,2) CTMUICON<9:8> = 01
— 0.585 — V TA = +25°C,
CTMUICON<9:8> = 10
— 0.645 — V TA = +25°C,
CTMUICON<9:8> = 11
CTMUFV2 VFVR Temperature Diode Rate of — -1.92 — mV/°C CTMUICON<9.8> = 01
Change(1,2) — -1.74 — mV/°C CTMUICON<9:8> = 10
— -1.56 — mV/°C CTMUICON<9:8> = 11
Note 1: Nominal value at center point of current trim range (CTMUICON<15:10> = 000000).
2: Parameters are characterized but not tested in manufacturing. Measurements are taken with the following
conditions:
• VREF = AVDD = 5.0V
• ADC configured for 10-bit mode
• ADC configured for conversion speed of 500 ksps
• All PMDx bits are cleared (PMDx = 0)
• CPU executing
while(1)
{
NOP();
}
• Device operating from the FRC with no PLL

TABLE 30-54: ADC MODULE SPECIFICATIONS

AC CHARACTERISTICS
Param
No.
Device Supply
AD01 AVDD Module VDD Supply Greater of: — Lesser of: V
VDD – 0.3 VDD + 0.3
or VBOR or 5.5
AD02 AVSS Module VSS Supply VSS – 0.3 — VSS + 0.3 V
Reference Inputs
AD05 VREFH Reference Voltage High 4.5 — 5.5 V VREFH = AVDD,
VREFL = AVSS = 0
AD06 VREFL Reference Voltage Low AVSS — AVDD – VBORMIN V See Note 1
AD06a 0 — 0 V VREFH = AVDD,
VREFL = AVSS = 0
AD07 VREF Absolute Reference 4.5 — 5.5 V VREF = VREFH – VREFL
Voltage
AD08 IREF Current Drain — — 10 A ADC off
— — 600 A ADC on
AD09 IAD Operating Current — 5 — mA ADC operating in 10-bit
mode (see Note 1)
— 2 — mA ADC operating in 12-bit
mode (see Note 1)
Analog Input
AD12 VINH Input Voltage Range VINH VINL — VREFH V This voltage reflects
Sample-and-Hold
Channels 0, 1, 2 and 3
(CH0-CH3), positive input
AD13 VINL Input Voltage Range VINL VREFL — AVSS + 1V V This voltage reflects
Sample-and-Hold
Channels 0, 1, 2 and 3
(CH0-CH3), negative input
AD17 RIN Recommended — — 200  Impedance to achieve
Impedance of Analog maximum performance of
Voltage Source ADC
is tested, but is not characterized. Analog modules: ADC, op amp/comparator and comparator voltage
maximum BOR values.

TABLE 30-55: ADC MODULE SPECIFICATIONS (12-BIT MODE)

AC CHARACTERISTICS
Param
No.
ADC Accuracy (12-Bit Mode)
AD20a Nr Resolution 12 data bits bits
AD21a INL Integral Nonlinearity -2 — +2 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5.5V
AD22a DNL Differential Nonlinearity -1 — <1 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5.5V
AD23a GERR Gain Error -10 4 10 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5.5V
AD24a EOFF Offset Error -10 1.75 10 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5.5V
AD25a — Monotonicity(2) — — — — Guaranteed
Dynamic Performance (12-Bit Mode)
AD30a THD Total Harmonic Distortion — — -75 dB
AD31a SINAD Signal to Noise and 68.5 69.5 — dB
Distortion
AD32a SFDR Spurious Free Dynamic 80 — — dB
Range
AD33a FNYQ Input Signal Bandwidth — — 250 kHz
AD34a ENOB Effective Number of Bits 11.09 11.3 — bits
maximum BOR values.
2: The conversion result never decreases with an increase in the input voltage.


AC CHARACTERISTICS
Param
No.
AD20b Nr Resolution 10 data bits bits
AD21b INL Integral Nonlinearity -1.5 — +1.5 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5.5V
AD22b DNL Differential Nonlinearity 1 — <1 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5.5V
AD23b GERR Gain Error 1 3 6 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5.5V
AD24b EOFF Offset Error 1 2 4 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5.5V
AD25b — Monotonicity(2) — — — — Guaranteed
Dynamic Performance (10-Bit Mode)
AD30b THD Total Harmonic Distortion — — -64 dB
AD31b SINAD Signal to Noise and 57 58.5 — dB
Distortion
AD32b SFDR Spurious Free Dynamic 72 — — dB
Range
AD33b FNYQ Input Signal Bandwidth — — 550 kHz
AD34b ENOB Effective Number of Bits 9.16 9.4 — bits
maximum BOR values.
2: The conversion result never decreases with an increase in the input voltage.

FIGURE 30-34: ADC CONVERSION (12-BIT MODE) TIMING CHARACTERISTICS

(ASAM = 0, SSRC<2:0> = 000, SSRCG = 0)
AD50
ADCLK
Instruction Set SAMP Clear SAMP

Execution
SAMP
AD61
AD60
TSAMP AD55
DONE
AD1IF
1 2 3 4 5 6 7 8 9
1 – Software sets ADxCON1. SAMP to start sampling. 5 – Convert bit 11.

2 – Sampling starts after discharge period. TSAMP is described in 6 – Convert bit 10.
“Analog-to-Digital Converter (ADC)” (DS70621) of the
“dsPIC33/PIC24 Family Reference Manual”. 7 – Convert bit 1.
3 – Software clears ADxCON1. SAMP to start conversion. 8 – Convert bit 0.
4 – Sampling ends, conversion sequence starts. 9 – One TAD for end of conversion.

TABLE 30-57: ADC CONVERSION (12-BIT MODE) TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
No.
Clock Parameters
AD50 TAD ADC Clock Period 117.6 — — ns
AD51 tRC ADC Internal RC Oscillator Period — 250 — ns
Conversion Rate
AD55 tCONV Conversion Time — 14 — TAD
AD56 FCNV Throughput Rate — — 500 ksps
AD57a TSAMP Sample Time when Sampling Any 3 — — TAD
ANx Input
AD57b TSAMP Sample Time when Sampling the 3 — — TAD
Op Amp Outputs
Timing Parameters
AD60 tPCS Conversion Start from Sample 2 — 3 TAD Auto-convert trigger is
Trigger(1) not selected
AD61 tPSS Sample Start from Setting 2 — 3 TAD
Sample (SAMP) bit(1)
AD62 tCSS Conversion Completion to — 0.5 — TAD
Sample Start (ASAM = 1)(1)
AD63 tDPU Time to Stabilize Analog Stage — — 20 s See Note 3
from ADC Off to ADC On(1)
Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz may affect linearity
performance, especially at elevated temperatures.
maximum BOR values.
3: The parameter, tDPU, is the time required for the ADC module to stabilize at the appropriate level when the
module is turned on (ADON (ADxCON1<15>) = 1). During this time, the ADC result is indeterminate.

FIGURE 30-35: ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS

(CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000, SSRCG = 0)
AD50
ADCLK
Instruction Set SAMP Clear SAMP

Execution
SAMP
AD61
AD60
TSAMP AD55 AD55
DONE
AD1IF
1 2 3 4 5 6 7 8 5 6 7 8
1 – Software sets ADxCON1. SAMP to start sampling. 5 – Convert bit 9.

2 – Sampling starts after discharge period. TSAMP is described in 6 – Convert bit 8.
“Analog-to-Digital Converter (ADC)” (DS70621) of the
“dsPIC33/PIC24 Family Reference Manual”. 7 – Convert bit 0.
3 – Software clears ADxCON1. SAMP to start conversion. 8 – One TAD for end of conversion.
4 – Sampling ends, conversion sequence starts.
FIGURE 30-36: ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01,
SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SSRCG = 0, SAMC<4:0> = 00010)
AD50
ADCLK
Instruction Set ADON

Execution
AD62
SAMP
TSAMP AD55 AD55 TSAMP AD55
AD1IF
DONE
1 2 3 4 5 6 7 3 4 5 6 8
1 – Software sets ADxCON1. ADON to start ADC operation. 5 – Convert bit 0.
2 – Sampling starts after discharge period. TSAMP is described in 6 – One TAD for end of conversion.
“Analog-to-Digital Converter (ADC)” (DS70621)
of the “dsPIC33/PIC24 Family Reference Manual”. 7 – Begin conversion of next channel.
3 – Convert bit 9.
8 – Sample for time specified by SAMC<4:0>.
4 – Convert bit 8.

TABLE 30-58: ADC CONVERSION (10-BIT MODE) TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
No.
Clock Parameters
AD50 TAD ADC Clock Period 75 — — ns
AD51 tRC ADC Internal RC Oscillator Period — 250 — ns
Conversion Rate
AD55 tCONV Conversion Time — 12 — TAD
AD56 FCNV Throughput Rate — — 1.1 Msps Using simultaneous
sampling
AD57a TSAMP Sample Time When Sampling Any 2 — — TAD
ANx Input
AD57b TSAMP Sample Time When Sampling the 4 — — TAD
Op Amp Outputs
Timing Parameters
AD60 tPCS Conversion Start from Sample 2 — 3 TAD Auto-convert trigger is
Trigger(2) not selected
AD61 tPSS Sample Start from Setting 2 — 3 TAD
Sample (SAMP) bit(2)
AD62 tCSS Conversion Completion to — 0.5 — TAD
Sample Start (ASAM = 1)(2)
AD63 tDPU Time to Stabilize Analog Stage — — 20 s See Note 3
from ADC Off to ADC On(2)
maximum BOR values.
2: Because the sample caps will eventually lose charge, clock rates below 10 kHz may affect linearity
performance, especially at elevated temperatures.
3: The parameter, tDPU, is the time required for the ADC module to stabilize at the appropriate level when the
module is turned on (ADON (ADxCON1<15>) = 1). During this time, the ADC result is indeterminate.
TABLE 30-59: DMA MODULE TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
Characteristic Min. Typ.(1) Max. Units Conditions
No.
DM1 DMA Byte/Word Transfer Latency 1 TCY(2) — — ns
2: Because DMA transfers use the CPU data bus, this time is dependent on other functions on the bus.

NOTES:

31.0 HIGH-TEMPERATURE ELECTRICAL CHARACTERISTICS

This section provides an overview of the dsPIC33EVXXXGM00X/10X family electrical characteristics for devices
operating in an ambient temperature range of -40°C to +150°C.
The specifications between -40°C to +150°C are identical to those shown in Section 30.0 “Electrical Characteristics”
for operation between -40°C to +125°C, with the exception of the parameters listed in this section.
Parameters in this section begin with an H, which denotes High temperature. For example, Parameter DC10 in
Section 30.0 “Electrical Characteristics” is the Industrial and Extended temperature equivalent of HDC10.
Absolute maximum ratings for the dsPIC33EVXXXGM00X/10X family high-temperature devices are listed below.
Exposure to these maximum rating conditions for extended periods can affect device reliability. Functional operation of
the device at these, or any other conditions above the parameters indicated in the operation listings of this specification,
is not implied.
Absolute Maximum Ratings(1)

Ambient temperature under bias(2) .........................................................................................................-40°C to +150°C
Storage temperature .............................................................................................................................. -65°C to +160°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +6.0V
Maximum current out of VSS pin ...........................................................................................................................350 mA
Maximum current into VDD pin(3) ...........................................................................................................................350 mA
Maximum junction temperature............................................................................................................................. +155°C
Maximum current sunk by any I/O pin.....................................................................................................................20 mA
Maximum current sourced by I/O pin ......................................................................................................................18 mA
Maximum current sunk by all ports combined ......................................................................................................200 mA
Maximum current sourced by all ports combined(3) ..............................................................................................200 mA
Note 1: Stresses above those listed under “Absolute Maximum Ratings” can cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions
above those indicated in the operation listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods can affect device reliability.
2: AEC-Q100 reliability testing for devices intended to operate at +150°C is 1,000 hours. Any design in which
the total operating time from +125°C to +150°C will be greater than 1,000 hours is not warranted without
prior written approval from Microchip Technology Inc.
3: Maximum allowable current is a function of device maximum power dissipation (see Table 31-2).

31.1 High-Temperature DC Characteristics
TABLE 31-1: OPERATING MIPS vs. VOLTAGE
VDD Range Temperature Range Max MIPS

Characteristic
(in Volts) (in °C) dsPIC33EVXXXGM00X/10X Family
(1,2)
HDC5 4.5V to 5.5V -40°C to +150°C 40
Note 1: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules, such as the ADC, op amp/comparator
and comparator voltage reference, will have degraded performance. Device functionality is tested but is
not characterized. Refer to Parameter BO10 in Table 30-12 for the minimum and maximum BOR values.
2: When BOR is enabled, the device will work from 4.7V to 5.5V.
TABLE 31-2: THERMAL OPERATING CONDITIONS

Rating Symbol Min Typ Max Unit
High-Temperature Devices
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD –  IOH) PD PINT + PI/O W
I/O Pin Power Dissipation:
I/O =  ({VDD – VOH} x IOH) +  (VOL x IOL)
Maximum Allowed Power Dissipation PDMAX (TJ – TA)/JA W
TABLE 31-3: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS

DC CHARACTERISTICS (unless otherwise stated)
Operating temperature -40°C  TA  +150°C for High Temperature
Param
No.
Operating Voltage
HDC10 VDD Supply Voltage(3) VBOR — 5.5 V
HDC12 VDR RAM Data Retention 1.8 — — V
Voltage(2)
HDC16 VPOR VDD Start Voltage — — VSS V
to Ensure Internal
HDC17 SVDD VDD Rise Rate 1.0 — — V/ms 0V-5.0V in 5 ms
to Ensure Internal
HDC18 VCORE VDD Core 1.62 1.8 1.98 V Voltage is dependent on
Internal Regulator Voltage load, temperature and VDD
2: This is the limit to which VDD may be lowered without losing RAM data.
3: VDD voltage must remain at VSS for a minimum of 200 s to ensure POR.

TABLE 31-4: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)

DC CHARACTERISTICS
Parameter
Typical Max Units Conditions
No.
Power-Down Current (IPD)
HDC60e 1300 2500 A +150°C 5V Base Power-Down Current
HDC61c 10 50 A +150°C 5V Watchdog Timer Current: IWDT
TABLE 31-5: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)

DC CHARACTERISTICS
Parameter
No.
HDC40e 2.6 5.0 mA +150°C 5V 10 MIPS
HDC42e 3.6 7.0 mA +150°C 5V 20 MIPS
TABLE 31-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD)

DC CHARACTERISTICS
Parameter
No.
HDC20e 5.9 8.0 mA +150°C 5V 10 MIPS
HDC22e 10.3 15.0 mA +150°C 5V 20 MIPS
HDC23e 19.0 25.0 mA +150°C 5V 40 MIPS
TABLE 31-7: DC CHARACTERISTICS: DOZE CURRENT (IDOZE)

DC CHARACTERISTICS
Parameter
Typical Max Doze Ratio Units Conditions
No.
HDC73a 18.5 22.0 1:2 mA
+150°C 5V 40 MIPS
HDC73g 8.35 12.0 1:128 mA

TABLE 31-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS

Param
No.
VIL Input Low Voltage
DI10 Any I/O Pins VSS — 0.2 VDD V
VIH Input High Voltage
DI20 I/O Pins 0.75 VDD — 5.5 V
DI30 ICNPU Change Notification Pull-up 200 375 600 A VDD = 5.0V, VPIN = VSS
Current
DI31 ICNPD Change Notification 175 400 625 A VDD = 5.0V, VPIN = VDD
Pull-Down Current(7)
IIL Input Leakage Current(2,3)
DI50 I/O Pins -200 — 200 nA VSS  VPIN  VDD,
pin at high-impedance
DI55 MCLR -1.5 — 1.5 A VSS VPIN VDD
DI56 OSC1 -300 — 300 nA VSS VPIN VDD,
XT and HS modes
DI60a IICL Input Low Injection Current 0 — -5(4,6) mA All pins except VDD, VSS,
AVDD, AVSS, MCLR, VCAP
and RB7
DI60b IICH Input High Injection Current 0 — +5(5,6) mA All pins except VDD, VSS,
AVDD, AVSS, MCLR,
VCAP, RB7 and all 5V
tolerant pins(5)
DI60c IICT Total Input Injection Current -20(7) — +20(7) mA Absolute instantaneous
(sum of all I/O and control sum of all ± input injection
pins) currents from all I/O pins
( | IICL | + | IICH | )  IICT
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current can be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: VIL source < (VSS – 0.3). Characterized but not tested.
5: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.
6: Non-zero injection currents can affect the ADC results by approximately 4-6 counts.
7: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted,
provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.

TABLE 31-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS

DC CHARACTERISTICS
Param
No.
HDO16 VOL Output Low Voltage
HDO10 VOL Output Low Voltage
HDO26 VOH Output High Voltage
4x Sink Driver Pins(2) VDD – 0.6 — — V IOH = -8.3 mA, VDD = 5.0V
HDO20 VOH Output High Voltage
8x Sink Driver Pins VDD – 0.6 — — V IOH = -12.3 mA, VDD = 5.0V
Note 1: Parameters are characterized but not tested.
2: Includes all I/O pins that are not 8x sink driver pins (see below).
3: Includes the pins, such as RA3, RA4 and RB<15:10> for 28-pin devices, RA3, RA4, RA9 and RB<15:10>
for 44-pin devices, and RA4, RA7, RA9, RB<15:10> and RC15 for 64-pin devices.
TABLE 31-10: ELECTRICAL CHARACTERISTICS: BOR

DC CHARACTERISTICS
Param
No.
HBO10 VBOR BOR Event on VDD 4.15 4.285 4.4 V VDD (see Note 2, Note 3 and Note 4)
Transition High-to-Low
Note 1: Parameters are for design guidance only and are not tested in manufacturing.
2: The VBOR specification is relative to the VDD.
3: The device is functional at VBORMIN < VDD < VDDMIN. Analog modules: ADC, op amp/comparator and
comparator voltage reference will have degraded performance. Device functionality is tested but is not
characterized.
4: The start-up VDD must rise above 4.6V.
TABLE 31-11: DC CHARACTERISTICS: PROGRAM MEMORY

DC CHARACTERISTICS
Param
No.
Program Flash Memory
HD130 EP Cell Endurance 10,000 — — E/W -40°C to +150°C(2)
HD134 TRETD Characteristic Retention 20 — — Year 1000 E/W cycles or less and no
other specifications are violated
Note 1: These parameters are assured by design, but are not characterized or tested in manufacturing.
2: Programming of the Flash memory is allowed up to +150°C.

31.2 AC Characteristics and Timing Parameters in this section begin with an H, which denotes
Parameters High temperature. For example, Parameter OS53 in
Section 30.2 “AC Characteristics and Timing
The information contained in this section defines the Parameters” is the Industrial and Extended temperature
dsPIC33EVXXXGM00X/10X family AC characteristics equivalent of HOS53.
and timing parameters for high-temperature devices.
However, all AC timing specifications in this section are
the same as those in Section 30.2 “AC Characteristics
and Timing Parameters”, with the exception of the
parameters listed in this section.
TABLE 31-12: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC

AC CHARACTERISTICS Operating temperature -40°C  TA  +150°C
Operating voltage VDD range as described in Table 31-1.
FIGURE 31-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

Load Condition 1 – for All Pins except OSC2 Load Condition 2 – for OSC2
VDD/2
RL Pin CL
VSS
CL
Pin RL = 464
CL = 50 pF for all pins except OSC2
VSS 15 pF for OSC2 output

TABLE 31-13: PLL CLOCK TIMING SPECIFICATIONS

Param
No.
HOS50 FPLLI PLL Voltage Controlled 0.8 — 8.0 MHz ECPLL, XTPLL modes
Oscillator (VCO) Input
Frequency Range
HOS51 FSYS On-Chip VCO System 120 — 340 MHz
Frequency
HOS52 TLOCK PLL Start-up Time (Lock Time) 0.9 1.5 3.1 ms
HOS53 DCLK CLKO Stability (Jitter)(2) -3 0.5 3 %
Note 1: Data in “Typ.” column is at 5.0V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: This jitter specification is based on clock cycle-by-clock cycle measurements. To get the effective jitter for
individual time bases or communication clocks used by the application, use the following formula:
D CLK
Effective Jitter = -------------------------------------------------------------------------------------------
F OSC
---------------------------------------------------------------------------------------
Time Base or Communication Clock
For example, if FOSC = 120 MHz and the SPI bit rate = 10 MHz, the effective jitter is as follows:
D CLK D CLK D CLK
Effective Jitter = -------------- = -------------- = --------------
120 12 3.464
---------
10
TABLE 31-14: INTERNAL FRC ACCURACY

AC CHARACTERISTICS
Param
Characteristic Min Typ Max Units Conditions
No.
Internal FRC Accuracy @ FRC Frequency = 7.3728 MHz
HF20C FRC -3 1 +3 % -40°C  TA +150°C VDD = 4.5V to 5.5V
TABLE 31-15: INTERNAL LPRC ACCURACY

AC CHARACTERISTICS
Param
Characteristic Min Typ Max Units Conditions
No.
LPRC @ 32.768 kHz(1,2)
HF21C LPRC -30 10 +30 % -40°C  TA +150°C VDD = 4.5V to 5.5V
Note 1: Change of LPRC frequency as VDD changes.
2: LPRC accuracy impacts the Watchdog Timer Time-out Period (TWDT1). See Section 27.5 “Watchdog
Timer (WDT)” for more information.

TABLE 31-16: CTMU CURRENT SOURCE SPECIFICATIONS

Param No. Symbol Characteristic(1) Min. Typ. Max. Units Conditions

CTMU Current Source
HCTMUl1 lOUT1 Base Range — 550 — nA CTMUICON<9.8> = 01
HCTMUl2 lOUT2 10x Range — 5.5 — A CTMUICON<9.8> = 10
HCTMUl3 lOUT3 100x Range — 55 — A CTMUICON<9.8> = 11
HCTMUl0 lOUT4 1000x Range — 550 — A CTMUICON<9.8> = 00
HCTMUFV1 VF Temperature Diode — 0.525 — V TA = +25°C,
Forward Voltage(2) CTMUICON<9.8> = 01
— 0.585 — V TA = +25°C,
CTMUICON<9.8> = 10
— 0.645 — V TA = +25°C,
CTMUICON<9.8> = 11
Note 1: Normal value at center point of current trim range (CTMUICON<15:10> = 000000).
2: Parameters are characterized but not tested in manufacturing. Measurements are taken with the following
conditions:
• VREF = AVDD = 5.0V
• ADC module configured for 10-bit mode
• ADC module configured for conversion speed of 500 ksps
• All PMDx bits are cleared (PMDx = 0)
• CPU executing
while(1)
{
NOP();
}
• Device operating from the FRC with no PLL

TABLE 31-17: OP AMP/COMPARATOR x SPECIFICATIONS

Param
No.
Comparator DC Characteristics
HCM30 VOFFSET Comparator Offset Voltage -80 ±60 80 mV
HCM31 VHYST Input Hysteresis Voltage — 30 — mV
HCM34 VICM Input Common-Mode Voltage AVSS — AVDD V
(2)
Op Amp DC Characteristics
HCM40 VCMR Common-Mode Input AVSS — AVDD V
Voltage Range
HCM42 VOFFSET Op Amp Offset Voltage -50 ±6 50 mV
2: Resistances can vary by ±10% between op amps.
reference, will have degraded performance. Refer to Parameter HBO10 in Table 31-10 for the minimum
and maximum BOR values.

Param
No.
HAD20a Nr Resolution 12 data bits bits
HAD21a INL Integral Nonlinearity -2 — +2 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5.5V
HAD22a DNL Differential Nonlinearity -1 — <1 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5.5V
HAD23a GERR Gain Error -10 4 10 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5.5V
HAD24a EOFF Offset Error -10 1.75 10 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5.5V
maximum BOR values.


Param
No.
HAD20b Nr Resolution 10 data bits bits
HAD21b INL Integral Nonlinearity -1.5 — +1.5 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5.5V
HAD22b DNL Differential Nonlinearity 1 — <1 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5.5V
HAD23b GERR Gain Error 1 3 6 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5.5V
HAD24b EOFF Offset Error 1 2 4 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5.5V
reference, will have degraded performance. Refer to Parameter HBO10 in Table 31-10 for the minimum
and maximum BOR values.

32.0 CHARACTERISTICS FOR INDUSTRIAL/EXTENDED TEMPERATURE

DEVICES (-40°C TO +125°C)
32.1 IDD
FIGURE 32-1: TYPICAL/MAXIMUM IDD vs. FOSC (EC MODE, 10 MHz TO 70 MHz, 5.5V MAX)
35.0
30.0
25.0
-40C Max
-40C Typ
20.0
IDD (mA)
25C Max
25C Typ
15.0 85C Max
85C Typ
10.0 125C Max
125C Typ
5.0
0.0
5 15 25 35 45 55 65 75
Frequency (MIPS)
FIGURE 32-2: TYPICAL IDD vs. VDD (EC MODE, 10 MIPS)

5.6
5.4
5.2
5
IDD (mA)
-40C
25C
4.8
85C
125C
4.6
4.4
4.2
4.4 4.6 4.8 5 5.2 5.4 5.6
VDD (V)


9.8
9.6
9.4
9.2
IDD (mA)
-40C
9
25C
85C
8.8
125C
8.6
8.4
8.2
4.4 4.6 4.8 5 5.2 5.4 5.6
VDD (V)

18.3
18.1
17.9
17.7
17.5
IDD (mA)
-40C
17.3
25C
17.1 85C
125C
16.9
16.7
16.5
16.3
4.4 4.6 4.8 5 5.2 5.4 5.6
VDD (V)


26
25.8
25.6
25.4
25.2
IDD (mA)
-40C
25
25C
24.8 85C
125C
24.6
24.4
24.2
24
4.4 4.6 4.8 5 5.2 5.4 5.6
VDD (V)

29.2
29
28.8
28.6
IDD (mA)
-40C
28.4 25C
85C
28.2
28
27.8
4.4 4.6 4.8 5 5.2 5.4 5.6
VDD (V)

32.2 IIDLE
FIGURE 32-7: TYPICAL/MAXIMUM IIDLE vs. FOSC (EC MODE 10 MHz TO 70 MHz, 5.5V MAX)
6
Max -40C
5 Typ -40C
Max 25C
IIDLE (mA)
4 Typ 25C
Max 85C
3
Typ 85C
Max 125C
2
Typ 125C
0
5 15 25 35 45 55 65 75
Frequency (MIPS)
FIGURE 32-8: TYPICAL IIDLE vs. VDD (EC MODE, 10 MIPS)

1.8
1.7
1.6
IIDLE (mA)
-40C
1.5
25C
85C
1.4 125C
1.3
1.2
4.4 4.6 4.8 5 5.2 5.4 5.6
VDD (V)


2.9
2.8
2.7
2.6
IIDLE (mA)
-40C
2.5
25C
85C
2.4 125C
2.3
2.2
2.1
4.4 4.6 4.8 5 5.2 5.4 5.6
VDD (V)

4.8
4.7
4.6
4.5
IIDLE (mA)
-40C
4.4
25C
85C
4.3
125C
4.2
4.1
4
4.4 4.6 4.8 5 5.2 5.4 5.6
VDD (V)


6.7
6.6
6.5
6.4
IIDLE (mA)
6.3
-40C
25C
6.2
85C
125C
6.1
5.9
5.8
4.4 4.6 4.8 5 5.2 5.4 5.6
VDD (V)

7.1
7.05
7
IIDLE (mA)
6.95 -40C
25C
85C
6.9
6.85
6.8
4.4 4.6 4.8 5 5.2 5.4 5.6
VDD (V)

32.3 IDOZE
FIGURE 32-13: TYPICAL IDOZE vs. VDD (DOZE 1:2, 70 MIPS)
17.8
17.4
17
IDOZE (mA)
-40C
25C
16.6 85C
125C
16.2
15.8
4.4 4.6 4.8 5 5.2 5.4 5.6
VDD (V)
FIGURE 32-14: TYPICAL/MAXIMUM IDOZE vs. TEMPERATURE (DOZE 1:2, 70 MIPS)
20
19
18
IDOZE (mA)
5.5V Max (1:2)
5.5V Typ (1:2)

17
16
15
-50 0 50 100 150
Temperature (C)

8.2
7.8
IDOZE (mA)
-40C
7.6
25C
85C
7.4 125C
7.2
7
4.4 4.6 4.8 5 5.2 5.4 5.6
VDD (V)
9.5
8.5
IDOZE (mA)
5.5V Max
(1:128)
8 5.5V Typ
(1:128)
7.5
7
-50 0 50 100 150
Temperature (C)

32.4 IPD
FIGURE 32-17: TYPICAL IPD vs. VDD
250
200
150
IPD (uA)
-40C
25C
100 85C
125C
50
0
4.4 4.6 4.8 5 5.2 5.4 5.6
VDD(V)
FIGURE 32-18: TYPICAL/MAXIMUM IPD vs. TEMPERATURE

1600
1400
1200
1000
IPD (uA)
800 5.5V Max

5.5V Typ
600
400
200
0
-50 0 50 100 150
Temperature (C)

FIGURE 32-19: TYPICAL/MAXIMUM IWDT vs. TEMPERATURE
12
10
8
IPD (uA)
6 5.5V Max
5.5V Typ
0
-50 0 50 100 150
Temperature (C)
32.5 FRC
FIGURE 32-20: TYPICAL FRC ACCURACY vs. VDD
0.4
0.2
0
FRC Accuracy (%)
-40C
-0.2
25C
85C
-0.4 125C
-0.6
-0.8
4.4 4.6 4.8 5 5.2 5.4 5.6
VDD (V)

FIGURE 32-21: TYPICAL FRC FRC

Typical ACCURACY vs. TEMPERATURE
Accuracy (5.5V VDD)
V/S Temperature
0.4
0.2
FRC Accuracy (%)
-0.2
-0.4
-0.6
-0.8
-50 0 50 100 150
Temperature (C)
32.6 LPRC
FIGURE 32-22: TYPICAL LPRC ACCURACY vs. VDD
2
LPRC Accuracy (%)
-40C
1
25C
85C
0 125C
-1
-2
4.4 4.6 4.8 5 5.2 5.4 5.6
VDD (V)

FIGURE 32-23: TYPICAL LPRC ACCURACY vs. TEMPERATURE (5.5V VDD)
2
LPRC Accuracy (%)
-1
-2
-3
-50 0 50 100 150
Temperature (C)
32.7 Leakage Current

FIGURE 32-24: TYPICAL IIL vs. TEMPERATURE (MCLR)
600
400
Leakage Current (nA)
VPIN = 5.5V
200
VPIN = 0V
-200
-400
-600
-50 0 50 100 150
Temperature (C)

FIGURE 32-25: TYPICAL IIL vs. TEMPERATURE (OSC1)
25
20
15
10
5 VPIN = 5.5V
-5
VPIN = 0V
-10
-15
-20
-25
-50 0 50 100 150
Temperature (C)
FIGURE 32-26: TYPICAL IIL vs. TEMPERATURE (GENERAL PURPOSE I/Os)
20
15
10
5
VPIN = 5.5V
-5
VPIN = 0V
-10
-15
-50 0 50 100 150
Temperature (C)

32.8 Pull-up and Pull-Down Current

FIGURE 32-27: TYPICAL PULL-UP CURRENT (VPIN = VSS) vs. TEMPERATURE
-300
-350
Pull-up Current (uA)
-400
-450
-500
-50 0 50 100 150
Temperature (C)
FIGURE 32-28: TYPICAL PULL-DOWN CURRENT (VPIN = 5.5V) vs. TEMPERATURE

550
500
Pull-down Current (uA)
450
400
350
300
250
-50 0 50 100 150
Temperature (C)

32.9 Voltage Input Low (VIL) – Voltage Input High (VIH)

FIGURE 32-29: TYPICAL VIH/VIL vs. TEMPERATURE (GENERAL PURPOSE I/Os)
5
4.5
4 Ensured Logic High

Voltage (V)
3.5
Indeterminate Logic
3
2.5
Ensured Logic Low

2
1.5
-50 0 50 100 150
Temperature (C)
32.10 Voltage Output Low (VOL) – Voltage Output High (VOH)

FIGURE 32-30: TYPICAL VOH 8x DRIVER PINS vs. IOH (GENERAL PURPOSE I/Os,
TEMPERATURES AS NOTED)
5
4.9
-40C
VOH (V)
4.8 25C
85C
125C
4.7
4.6
7.5 8.5 9.5 10.5 11.5 12.5 13.5
IOH (mA)

4.8
4.75
4.7
4.65
-40C
VOH (V)
4.6
25C
4.55 85C
125C
4.5
4.45
4.4
4.35
7.5 8.5 9.5 10.5 11.5 12.5 13.5
IOH (mA)
FIGURE 32-32: TYPICAL VOL 8x DRIVER PINS vs. IOL (GENERAL PURPOSE I/Os,
200
180
160
VOL (mV)
-40C
140 25C
85C
125C
120
100
80
7.5 8.5 9.5 10.5 11.5 12.5
IOL (mA)

350
300
250
VOL (mV)
-40C
25C
85C
200
125C
150
100
7.5 8 8.5 9 9.5 10 10.5 11 11.5 12 12.5
IOL (mA)
32.11 VREG
FIGURE 32-34: TYPICAL REGULATOR VOLTAGE vs. TEMPERATURE
1.87
1.865
1.86
VREG Voltage (V)
1.855
1.85
1.845
1.84
-50 0 50 100 150
Temperature (C)

32.12 VBOR
FIGURE 32-35: TYPICAL BOR TRIP RANGE vs. TEMPERATURE
4.29
4.285
4.28
BOR Trip Voltage (V)
4.275
4.27
4.265
4.26
4.255
4.25
-50 0 50 100 150
Temperature (C)
32.13 RAM Retention

FIGURE 32-36: TYPICAL RAM RETENTION VOLTAGE vs. TEMPERATURE
1.716
1.714
1.712
RAM Retention Voltage (V)
1.71
1.708
1.706
1.704
1.702
1.7
-50 0 50 100 150
Temperature (C)

32.14 Comparator Op Amp Offset

FIGURE 32-37: TYPICAL COMPARATOR OFFSET vs. VCM
-15
-20
-25
-30
-35
VOFFSET (mV)
-40C
-40
25C
85C
-45
125C
-50
-55
-60
-65
0 1 2 3 4 5 6
VCM (V)
FIGURE 32-38: TYPICAL OP AMP OFFSET vs. VCM OP AMP OFFSET

Typical OPAMP Offset V/S VCM
0
-1
-2
VOFFSET (mV)
-3
-40C
25C
-4 85C
125C
-5
-6
-7
0 1 2 3 4 5 6
VCM (V)

32.15 CTMU Current vs. Temperature

FIGURE 32-39: TYPICAL CTMU CURRENT (IRNG) vs. TEMPERATURE
100
0
CTMU Range Current (uA)
-100 Base Range
-200 10X Base Current
100X Base Range

-300
1000X Base Range

-400
-500
-600
-50 0 50 100 150
Temperature (C)
32.16 CTMU Temperature Forward Diode

FIGURE 32-40: TYPICAL CTMU TEMPERATURE DIODE FORWARD VOLTAGE vs. TEMPERATURE
900
800
700
Forward Voltage (mV)
Base Range
600
10x Range
100x Range
500
400
300
-50 0 50 100 150
Temperature (C)

32.17 ADC DNL

FIGURE 32-41: TYPICAL DNL (VDD = 5.5V, -40°C)
0.3
0.25
0.2
0.15
0.1
DNL (LSBs)
0.05
-0.05
-0.1
-0.15
-0.2
0 500 1000 1500 2000 2500 3000 3500 4000
Codes
FIGURE 32-42: TYPICAL DNL (VDD = 5.5V, +25°C)
0.4
0.3
0.2
DNL (LSBs)
0.1
-0.1
-0.2
-0.3
0 500 1000 1500 2000 2500 3000 3500 4000
Codes

0.4
0.3
0.2
DNL (LSBs)
0.1
-0.1
-0.2
-0.3
0 500 1000 1500 2000 2500 3000 3500 4000
Codes
0.5
0.4
0.3
0.2
DNL (LSBs)
0.1
-0.1
-0.2
-0.3
0 500 1000 1500 2000 2500 3000 3500 4000
Codes

32.18 ADC INL

FIGURE 32-45: TYPICAL INL (VDD = 5.5V, -40°C)
0.5
0.4
0.3
0.2
INL (LSBs)
0.1
-0.1
-0.2
-0.3
-0.4
0 500 1000 1500 2000 2500 3000 3500 4000
Codes
FIGURE 32-46: TYPICAL INL (VDD = 5.5V, +25°C)
0.5
0.4
0.3
0.2
INL (LSBs)
0.1
-0.1
-0.2
-0.3
-0.4
0 500 1000 1500 2000 2500 3000 3500 4000
Codes

0.5
0.4
0.3
0.2
0.1
INL (LSBs)
-0.1
-0.2
-0.3
-0.4
-0.5
0 500 1000 1500 2000 2500 3000 3500 4000
Codes
0.4
0.3
0.2
0.1
INL (LSBs)
-0.1
-0.2
-0.3
-0.4
0 500 1000 1500 2000 2500 3000 3500 4000
Codes

32.19 ADC Gain Offset Error

FIGURE 32-49: TYPICAL ADC GAIN ERROR vs. TEMPERATURE
6.8
6.6
6.4
Gain Error (LSBs)
6.2
5.8
5.6
5.4
5.2
5
-50 0 50 100 150
Temperature
FIGURE 32-50: TYPICAL ADC OFFSET ERROR vs. TEMPERATURE
3.35
3.3
3.25
Offset Error (LSBs)
3.2
3.15
3.1
3.05
2.95
-50 0 50 100 150
Temperature

NOTES:

33.0 CHARACTERISTICS FOR HIGH-TEMPERATURE DEVICES (+150°C)

33.1 IDD
FIGURE 33-1: TYPICAL/MAXIMUM IDD vs. FOSC (EC MODE 10 MHz TO 40 MHz, 5.5V MAX)
25.0
20.0
15.0
IDD (mA)
150C Max
150C Typ
10.0
5.0
0.0
5 10 15 20 25 30 35 40 45
Frequency (MIPS)
7.2
6.7
IDD (mA)
6.2
150C
5.7
5.2
4.4 4.6 4.8 5 5.2 5.4 5.6
VDD (V)

11.7
11.4
11.1
IDD (mA)
150C
10.8
10.5
10.2
4.4 4.6 4.8 5 5.2 5.4 5.6
VDD (V)
20.4
20.1
19.8
19.5
IDD (mA)
19.2 150C
18.9
18.6
18.3
4.4 4.6 4.8 5 5.2 5.4 5.6
VDD (V)

33.2 IIDLE
FIGURE 33-5: TYPICAL/MAXIMUM IIDLE vs. FOSC (EC MODE 10 MHz TO 40 MHz, 5.5V MAX)
7.0
6.0
5.0
IIDLE (mA)
4.0
Max 150C
3.0 Typ 150C
2.0
1.0
0.0
5 10 15 20 25 30 35 40 45
Frequency (MIPS)
2.6
2.4
2.2
2
IIDLE (mA)
1.8 150C
1.6
1.4
1.2
4.4 4.6 4.8 5 5.2 5.4 5.6
VDD (V)

3.7
3.5
3.3
3.1
IIDLE (mA)
2.9
150C
2.7
2.5
2.3
2.1
4.4 4.6 4.8 5 5.2 5.4 5.6
VDD (V)
5.6
5.4
5.2
5
IIDLE (mA)
4.8
150C
4.6
4.4
4.2
4
4.4 4.6 4.8 5 5.2 5.4 5.6
VDD (V)

33.3 IDOZE
18.8
18.3
17.8
IDOZE (mA)
17.3
150C
16.8
16.3
15.8
4.4 4.6 4.8 5 5.2 5.4 5.6
VDD (V)

Typical/Maximum IDoze V/S Temperature (DOZE<2:0>=001; 70 MIPS)
20
19
5.5V
Max
18 (1:2)
IDOZE (mA)
5.5V Typ
(1:2)
17
16
15
-50 0 50 100 150
Temperature (C)


9
8.6
IDOZE (mA)
8.2
150C
7.8
7.4
7
4.4 4.6 4.8 5 5.2 5.4 5.6
VDD (V)

9.5
8.5
IDOZE (mA)
5.5V Max
(1:128)
8 5.5V Typ
(1:128)
7.5
7
-50 0 50 100 150
Temperature (C)

33.4 IPD
FIGURE 33-13: TYPICAL IPD vs. VDD
1500
1300
1100
IPD (uA)
150C
900
700
500
4.4 4.6 4.8 5 5.2 5.4 5.6
VDD (V)
FIGURE 33-14: TYPICAL/MAXIMUM IPD vs. TEMPERATURE

Typical/Maximum IPD V/S Temperature
1600
1400
1200
1000
IPD (uA)
800
5.5V Max
5.5V Typ
600
400
200
0
-50 0 50 100 150
Temperature (C)

FIGURE 33-15: TYPICAL/MAXIMUM IWDT vs. TEMPERATURE
12
10
8
IPD (uA)
6
5.5V Max
5.5V Typ
4
0
-50 0 50 100 150
Temperature (C)
33.5 FRC
FIGURE 33-16: TYPICAL FRC ACCURACY vs. VDD
0.4
0.2
FRC Accuracy (%)
0
150C
-0.2
-0.4
4.4 4.6 4.8 5 5.2 5.4 5.6
VDD (V)

FIGURE 33-17: TYPICAL FRC ACCURACY vs. TEMPERATURE (5.5V VDD)

Typical FRC Accuracy V/S Temperature
0.4
0.2
FRC Accuracy (%)
-0.2
-0.4
-0.6
-0.8
-50 0 50 100 150
Temperature (C)
33.6 LPRC
FIGURE 33-18: TYPICAL LPRC ACCURACY vs. VDD
-0.5
LPRC Accuracy (%)
-1
150C
-1.5
-2
-2.5
4.4 4.6 4.8 5 5.2 5.4 5.6
VDD (V)

FIGURE 33-19: TYPICAL LPRC ACCURACY vs. TEMPERATURE (5.5V VDD)
1
LPRC Accuracy (%)
-1
-2
-3
-50 0 50 100 150
Temperature (C)
33.7 Leakage Current

FIGURE 33-20: TYPICAL IIL vs. TEMPERATURE (MCLR)
Typical IIL V/S Temperature (MCLR)
600
400
200 VPIN = 5.5V
-200 VPIN = 0V
-400
-600
-50 0 50 100 150
Temperature (C)

FIGURE 33-21: TYPICAL IIL vs. TEMPERATURE (OSC1)
25
20
15
10
5 VPIN = 5.5V
-5
VPIN = 0V
-10
-15
-20
-25
-50 0 50 100 150
Temperature (C)
FIGURE 33-22: TYPICAL IIL vs. TEMPERATURE (GENERAL PURPOSE I/Os)

Typical IIL V/S Temperature (General Purpose I/Os)
20
15
10
5
VPIN = 5.5V
-5
VPIN = 0V
-10
-15
-50 0 50 100 150
Temperature (C)

33.8 Pull-up/Pull-Down Current

FIGURE 33-23: TYPICAL PULL-DOWN CURRENT (VPIN = 5.5V) vs. TEMPERATURE
-300
-350
Pull-up Current (uA)
-400
-450
-500
-50 0 50 100 150
Temperature (C)
FIGURE 33-24: TYPICAL PULL-DOWN CURRENT

yp ( (VPIN =
) 5.5V)
/ vs.pTEMPERATURE
550
500
450
Pull-down Current (uA)
400
350
300
250
-50 0 50 100 150
Temperature (C)

33.9 Voltage Input High (VIH) – Voltage Input Low (VIL)

FIGURE 33-25: TYPICAL VIH/VIL vs. TEMPERATURE
Typical (GENERAL PURPOSE I/Os)
VIH/VIL V/S Temperature
5
4.5
4 Ensured Logic High

Voltage (V)
3.5
Indeterminate Logic
3
2.5
Ensured Logic Low

2
1.5
-50 0 50 100 150
Temperature (C)

33.10 Voltage Output Low (VOL) – Voltage Output High (VOH)

4.85
4.8
VOH (V)
4.75
150C
4.7
4.65
7.5 8.5 9.5 10.5 11.5 12.5 13.5
IOH (mA)

4.7
4.65
4.6
4.55
VOH (V)
150C
4.5
4.45
4.4
4.35
7.5 8.5 9.5 10.5 11.5 12.5 13.5
IOH (mA)
220
200
180
VOL (mV)
160
150C
140
120
100
7.5 8 8.5 9 9.5 10 10.5 11 11.5 12 12.5
IOL (mA)

400
350
VOL (mV)
300
150C
250
200
7.5 8 8.5 9 9.5 10 10.5 11 11.5 12 12.5
IOL (mA)
33.11 VREG
FIGURE 33-30: TYPICAL REGULATOR VOLTAGE vs. TEMPERATURE
1.87
1.865
1.86
VREG Voltage (V)
1.855
1.85
1.845
1.84
-50 0 50 100 150
Temperature (C)

33.12 VBOR
FIGURE 33-31: TYPICAL BOR TRIP RANGE vs. TEMPERATURE
4.29
4.285
4.28
BOR Trip Voltage (V)
4.275
4.27
4.265
4.26
4.255
4.25
-50 0 50 100 150
Temperature (C)
33.13 RAM Retention

FIGURE 33-32: TYPICAL RAM RETENTION VOLTAGE vs. TEMPERATURE
1.716
1.714
1.712
RAM Retention Voltage (V)
1.71
1.708
1.706
1.704
1.702
1.7
-50 0 50 100 150
Temperature (C)

33.14 Comparator Op Amp Offset

FIGURE 33-33: TYPICAL COMPARATOR OFFSET vs. VCM
-15
-25
-35
VOFFSET (mV)
-45
150C
-55
-65
-75
0 1 2 3 4 5 6
VCM (V)
FIGURE 33-34: TYPICAL OP AMP OFFSET vs. VCM

Typical OPAMP Offset V/S VCM
0
-2
-4
VOFFSET (mV)
-6
150C
-8
-10
-12
0 1 2 3 4 5 6
VCM (V)

33.15 CTMU Current V/S Temperature

FIGURE 33-35: TYPICAL CTMU CURRENT (IRNG) vs. TEMPERATURE
100
0
CTMU Range Current (uA)
-100 Base Range
10X Base
-200
Current
100X Base
-300 Range
1000X Base
-400 Range
-500
-600
-50 0 50 100 150
Temperature (C)
33.16 CTMU Temperature Forward Diode (V)

FIGURE 33-36: TYPICAL CTMU TEMPERATURE DIODE FORWARD VOLTAGE vs. TEMPERATURE
900
800
Forward Voltage (mV)
700
600
Base Range
10x Range
100x Range
500
400
300
-50 0 50 100 150
Temperature (C)

33.17 ADC DNL

0.4
0.3
0.2
DNL (LSBs)
0.1
-0.1
-0.2
-0.3
0 500 1000 1500 2000 2500 3000 3500 4000
Codes
33.18 ADC INL

0.4
0.3
0.2
0.1
INL (LSBs)
-0.1
-0.2
-0.3
-0.4
0 500 1000 1500 2000 2500 3000 3500 4000
Codes

33.19 ADC Gain Offset Error

FIGURE 33-39: TYPICAL ADC GAIN ERROR vs. TEMPERATURE
Typical ADC Gain Error V/S Temperature
7
6.8
6.6
6.4
Gain Error (LSBs)
6.2
5.8
5.6
5.4
5.2
5
-50 0 50 100 150
Temperature
FIGURE 33-40: TYPICAL ADC OFFSET ERROR vs. TEMPERATURE

Typical ADC Offset Error V/S Temperature
3.35
3.3
3.25
Offset Error (LSBs)
3.2
3.15
3.1
3.05
2.95
-50 0 50 100 150
Temperature

NOTES:

34.0 PACKAGING INFORMATION
34.1 Package Marking Information
28-Lead SPDIP (.300”) Example
XXXXXXXXXXXXXXXXX dsPIC33EV256GM002
XXXXXXXXXXXXXXXXX
YYWWNNN 1610017
28-Lead SOIC (.300”) Example
XXXXXXXXXXXXXXXXXXXX dsPIC33EV256GM002
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
YYWWNNN 1610017
28-Lead SSOP Example
XXXXXXXXXXXX dsPIC33EV256
XXXXXXXXXXXX GM002
YYWWNNN 1610017
28-Lead QFN-S (6x6x0.9 mm) Example
XXXXXXXX 33EV256
XXXXXXXX GM002
YYWWNNN 1610017
Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

34.1 Package Marking Information (Continued)
44-Lead TQFP (10x10x1 mm) Example
XXXXXXXXXX dsPIC33EV
XXXXXXXXXX 256GM004
XXXXXXXXXX
1610017
YYWWNNN
44-Lead QFN (8x8 mm) Example
PIN 1 PIN 1
XXXXXXXXXX 256GM004
XXXXXXXXXX
YYWWNNN 1610017
64-Lead TQFP (10x10x1 mm) Example
XXXXXXXXXX 256GM006
XXXXXXXXXX 1610017
YYWWNNN
64-Lead QFN (9x9x0.9 mm) Example
XXXXXXXXXXX dsPIC33EV
XXXXXXXXXXX 256GM006
XXXXXXXXXXX
YYWWNNN 1610017

34.2 Package Details

The following sections give the technical details of the packages.
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Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging



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44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP]
D A
D1 B
NOTE 2
(DATUM A)
(DATUM B)
E1 E
NOTE 1 A A
2X
N
0.20 H A B
2X 1 2 3
0.20 H A B 4X 11 TIPS
TOP VIEW
0.20 C A B
A A2
C
SEATING PLANE
0.10 C A1
SIDE VIEW
1 2 3
NOTE 1
44 X b
e 0.20 C A B
BOTTOM VIEW
Microchip Technology Drawing C04-076C Sheet 1 of 2

44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP]
L θ
(L1)
SECTION A-A
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Leads N 44
Lead Pitch e 0.80 BSC
Overall Height A - - 1.20
Standoff A1 0.05 - 0.15
Molded Package Thickness A2 0.95 1.00 1.05
Overall Width E 12.00 BSC
Molded Package Width E1 10.00 BSC
Overall Length D 12.00 BSC
Molded Package Length D1 10.00 BSC
Lead Width b 0.30 0.37 0.45
Lead Thickness c 0.09 - 0.20
Lead Length L 0.45 0.60 0.75
Footprint L1 1.00 REF
Foot Angle θ 0° 3.5° 7°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Exact shape of each corner is optional.
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.


44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN or VQFN]
D A B
N
NOTE 1
1
2
E
(DATUM B)
(DATUM A)
2X
0.20 C
2X
0.20 C TOP VIEW
0.10 C A1
C
SEATING A
PLANE 44X
A3 0.08 C
SIDE VIEW
L
0.10 C A B
D2
0.10 C A B
E2
K
2
1
NOTE 1 N
44X b
e 0.07 C A B
0.05 C
BOTTOM VIEW
Microchip Technology Drawing C04-103D Sheet 1 of 2

Units MILLIMETERS
Number of Pins N 44
Pitch e 0.65 BSC
Overall Height A 0.80 0.90 1.00
Standoff A1 0.00 0.02 0.05
Terminal Thickness A3 0.20 REF
Exposed Pad Width E2 6.25 6.45 6.60
Exposed Pad Length D2 6.25 6.45 6.60
Terminal Width b 0.20 0.30 0.35
Terminal Length L 0.30 0.40 0.50
Terminal-to-Exposed-Pad K 0.20 - -
Notes:
2. Package is saw singulated
Microchip Technology Drawing C04-103D Sheet 2 of 2

C1
X2
EV
44
G2
1
2
ØV
EV
C2 Y2
G1
Y1
E SILK SCREEN
X1
RECOMMENDED LAND PATTERN

Units MILLIMETERS
Contact Pitch E 0.65 BSC
Optional Center Pad Width X2 6.60
Optional Center Pad Length Y2 6.60
Contact Pad Spacing C1 8.00
Contact Pad Width (X44) X1 0.35
Contact Pad Length (X44) Y1 0.85
Contact Pad to Contact Pad (X40) G1 0.30
Contact Pad to Center Pad (X44) G2 0.28
Thermal Via Diameter V 0.33
Thermal Via Pitch EV 1.20
Notes:
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing No. C04-2103C

64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
D
D1
D1/2
D
NOTE 2
E1/2
A B
E1 E
A A
SEE DETAIL 1
N
4X N/4 TIPS
0.20 C A-B D 1 3
2
4X
NOTE 1
0.20 H A-B D
TOP VIEW
A2
A
C 0.05
SEATING
PLANE
A1
64 X b
0.08 C 0.08 C A-B D
e
SIDE VIEW

E
L T
(L1) X=A—B OR D
SECTION A-A X
e/2
DETAIL 1
Units MILLIMETERS
Number of Leads N 64
Lead Pitch e 0.50 BSC
Overall Height A - - 1.20
Molded Package Thickness A2 0.95 1.00 1.05
Standoff A1 0.05 - 0.15
Foot Length L 0.45 0.60 0.75
Footprint L1 1.00 REF
Foot Angle I 0° 3.5° 7°
Molded Package Width E1 10.00 BSC
Molded Package Length D1 10.00 BSC
Lead Thickness c 0.09 - 0.20
Lead Width b 0.17 0.22 0.27
Mold Draft Angle Top D 11° 12° 13°
Notes: Mold Draft Angle Bottom E 11° 12° 13°
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.

C1
C2
Y1
X1
Units MILLIMETERS
Distance Between Pads G 0.20
Notes:
Microchip Technology Drawing C04-2085B Sheet 1 of 1

64-Lead Very Thin Plastic Quad Flat, No Lead Package (MR) – 9x9x0.9 mm Body [VQFN]
With 7.15 x 7.15 Exposed Pad [Also called QFN]
9.00 A B
NOTE 1
N
1
2
9.00
(DATUM B)
(DATUM A)
2X
0.25 C
2X
0.25 C
TOP VIEW
A1
C 0.10 C
SEATING A
PLANE 64X
(A3) 0.08 C
SIDE VIEW
0.10 C A B
D2
0.10 C A B
E2
NOTE 1 K
2
1
L 64X b
e
2 0.10 C A B
e 0.05 C
BOTTOM VIEW
Microchip Technology Drawing C04-149D [MR] Sheet 1 of 2

Units MILLIMETERS
Number of Pins N 64
Pitch e 0.50 BSC
Overall Height A 0.80 0.90 1.00
Standoff A1 0.00 0.02 0.05
Contact Thickness A3 0.20 REF
Exposed Pad Width E2 7.05 7.15 7.25
Exposed Pad Length D2 7.05 7.15 7.25
Contact Width b 0.18 0.25 0.30
Contact Length L 0.30 0.40 0.50
Contact-to-Exposed Pad K 0.20 - -
Notes:
2. Package is saw singulated
Microchip Technology Drawing C04-149D [MR] Sheet 2 of 2

C1
Y1
EV
20
G1
1
2
ØV
Y2
C2 G2
EV
Y1
X1
E
SILK SCREEN 2
Units MILLIMETERS
Optional Center Pad Width X2 7.25
Optional Center Pad Length Y2 7.25
Contact Pad to Center Pad (X64) G1 0.40
Spacing Between Contact Pads (X60) G2 0.20
Thermal Via Diameter V 0.33
Thermal Via Pitch EV 1.20
Notes:
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-149C [MR]

NOTES:

APPENDIX A: REVISION HISTORY Revision C (November 2014)

This revision incorporates the following updates:
Revision A (December 2013)
• Sections:
This is the initial version of this document. - Added note in Section 5.2 “RTSP
Operation”
Revision B (June 2014) - Updated “Section 5.4 “Error Correcting
Code (ECC)”
- Deleted 44-Terminal Very Thin Leadless
• Sections: Array Package (TL) - 6x6x0.9 mm Body With
- Added Section 31.0 “High-Temperature Exposed Pad (VTLA).
Electrical Characteristics” • Registers
- Updated the “Power Management”section, - Updated Register 7-6
the “Input/Output” section, Section 3.3
• Figures:
“Data Space Addressing”, Section 4.2
“Data Address Space”, Section 4.3.2 - Updated Figure 4-1, Figure 4-3, Figure 4-4
“Extended X Data Space”, Section 4.6.1 • Tables:
“Bit-Reversed Addressing Implementa- - Updated Table 27-2, Table 31-13, Table 31-14,
tion”, Section 7.4.1 “INTCON1 through Table 31-15
INTCON4”, Section 11.7 “I/O Helpful Tips” - Added Table 31-16, Table 31-17
- Updated note in Section 17.0 “High-Speed
PWM Module”, Section 18.0 “Serial Revision D (April 2015)
Peripheral Interface (SPI)”, Section 27.8
“Code Protection and CodeGuard™ This revision incorporates the following updates:
Security” • Sections:
- Updated title of Section 20.0 “Single-Edge - Updated the Clock Management, Timers/
Nibble Transmission (SENT)” Output Compare/Input Capture, Communica-
- Updated Section 34.0 “Packaging Informa- tion Interfaces and Input/Output sections at
tion”. Deleted e3, Pb-free and Industrial (I) the beginning of the data sheet
temperature range indication throughout the (Page 1 and Page 2).
section, and updated the packaging dia- - Updated all pin diagrams at the beginning of
grams the data sheet (Page 4 through Page 9).
- Updated the “Product Identification System” - Added Section 11.6 “High-Voltage Detect
section (HVD)”
• Registers: - Updated Section 13.0 “Timer2/3 and
- Updated Register 3-2, Register 7-2, Timer4/5”
Register 7-6, Register 9-2, Register 11-3, - Corrects all Buffer heading numbers in
Register 14-1, Register 14-3, Register 14-11, Section 22.4 “CAN Message Buffers”
Register 15-1, Register 22-4
• Registers
• Figures:
- Updated Register 3-2, Register 25-2,
- Added Figure 4-6, Figure 4-8, Figure 4-14, Register 26-2
Figure 4-15, Figure 14-1, Figure 16-1,
• Figures
Figure 17-2, Figure 23-1, Figure 24-1
- Updated Figure 26-1, Figure 30-5, Figure 30-32
• Tables:
• Tables
- Updated Table 1, Table 27-1, Table 27-2,
Table 30-6, Table 30-7, Table 30-8, - Updated Table 1, Table 4-25, Table 30-10,
Table 30-9, Table 30-10, Table 30-11, Table 30-22, Table 30-53 and Table 31-8
Table 30-12, Table 30-38, Table 30-50, • Changes to text and formatting were incorporated
Table 30-53 and added Table 31-11, throughout the document
• Changes to text and formatting were incorporated
throughout the document

Revision E (September 2016)

• Sections:
- Added new Section 32.0 “Characteristics for
Industrial/Extended Temperature Devices (-40°C
to +125°C)” and Section 33.0 “Characteristics
for High-Temperature Devices (+150°C)”.
- Updated the Qualification and Class B
Support section.
- Updated Section 27.6 “In-Circuit Serial
Programming”.
- Updated Section 34.0 “Packaging Informa-
tion” with the addition of the 28-Lead SSOP
package information and new packaging
diagram revisions.
- Updated the “Product Identification
System” section with the addition of the
28-Lead SSOP package.
• Figures:
- Updated Figure 4-6.
• Registers:
- Updated Register 25-2, Register 25-3,
Register 27-1 and Register 27-2.
• Tables:
- Updated Table 30-7, Table 30-9, Table 30-39,
Table 30-40, Table 30-41, Table 30-42,
Table 30-43, Table 30-44 and Table 30-45.

INDEX
A Timer1 External Clock Requirements ....................... 357
Timer2 and Timer4 (Type B) External Clock
Absolute Maximum Ratings .............................................. 341
AC Characteristics ............................................................ 351 Requirements ................................................... 358
10-Bit ADC Conversion Requirements ..................... 401 Timer3 and Timer5 (Type C) External Clock
Requirements ................................................... 358
12-Bit ADC Conversion Requirements ..................... 399
12Cx Bus Data Requirements (Master Mode) .......... 388 UARTx I/O Requirements......................................... 391
ADC Module.............................................................. 395 ADC
10-Bit Configuration.................................................. 285
ADC Module (10-Bit Mode)....................................... 397
ADC Module (12-Bit Mode)....................................... 396 12-Bit Configuration.................................................. 285
CANx I/O Requirements ........................................... 391 Control Registers...................................................... 289
Helpful Tips............................................................... 288
Capacitive Loading Requirements on
Output Pins ....................................................... 351 Key Features ............................................................ 285
DMA Module Requirements...................................... 401 Alternate Interrupt Vector Table (AIVT) .............................. 95
Analog-to-Digital Converter. See ADC.
External Clock Requirements ................................... 352
High Temperature ..................................................... 408 Assemblers
ADC Module (10-Bit Mode)............................... 412 MPASM Assembler .................................................. 338
MPLAB Assembler, Linker, Librarian........................ 338
ADC Module (12-Bit Mode)............................... 411
Internal FRC Accuracy...................................... 409 B
Internal LPRC Accuracy ................................... 409
Bit-Reversed Addressing
PLL Clock ......................................................... 409
Example...................................................................... 78
High-Speed PWMx Requirements ............................ 361
Implementation ........................................................... 77
I/O Requirements...................................................... 354
Sequence Table (16-Entry) ........................................ 78
I2Cx Bus Data Requirements (Slave Mode) ............. 390
Block Diagrams
Input Capture x (ICx) Requirements ......................... 359
16-Bit Timer1 Module ............................................... 173
Internal FRC Accuracy.............................................. 353
Accessing Program Memory with
Internal LPRC Accuracy............................................ 353
Table Instructions ............................................... 81
Load Conditions ................................................ 351, 408
ADCx Conversion Clock Period................................ 287
OCx/PWMx Mode Requirements.............................. 360
ADCx with Connection Options for ANx Pins
Op Amp/Comparator x Voltage Reference
and Op Amps ................................................... 286
Settling Time ..................................................... 393
Addressing for Table Registers .................................. 83
Output Compare x (OCx) Requirements................... 360
Arbiter Architecture..................................................... 73
PLL Clock.................................................................. 353
CALL Stack Frame ..................................................... 74
Reset, Watchdog Timer, Oscillator Start-up Timer
CANx Module ........................................................... 254
and Power-up Timer Requirements .................. 356
Comparator Voltage Reference Module ................... 314
SPI1 Master Mode (Full-Duplex, CKE = 0,
Connections for On-Chip Voltage Regulator ............ 324
CKP = x, SMP = 1) Requirements .................... 378
CPU Core ................................................................... 22
CTMU Module .......................................................... 280
CKP = x, SMP = 1) ........................................... 376
Data Access from Program Space Address
SPI1 Master Mode (Half-Duplex,
Generation.......................................................... 80
Transmit Only) Requirements ........................... 375
Deadman Timer Module ........................................... 181
SPI1 Slave Mode (Full-Duplex, CKE = 0,
Digital Filter Interconnect .......................................... 302
CKP = 0, SMP = 0) Requirements .................... 386
DMA Controller ......................................................... 111
dsPIC33EVXXXGM00X/10X Family........................... 13
EDS Read Address Generation.................................. 68
EDS Write Address Generation.................................. 69
High-Speed PWMx Architectural Overview .............. 201
High-Speed PWMx Register Interconnection ........... 202
I2Cx Module ............................................................. 230
Input Capture x Module ............................................ 189
MCLR Pin Connections .............................................. 18
Multiplexing Remappable Output for RPn ................ 149
Op Amp/Comparator x Module................................. 301
Oscillator Circuit Placement ....................................... 19
Transmit Only) Requirements ........................... 363
Oscillator System...................................................... 123
Output Compare x Module ....................................... 193
Paged Data Memory Space ....................................... 70
Peripheral to DMA Controller.................................... 109
PLL Module .............................................................. 124
Recommended Minimum Connection ........................ 18
Remappable Input for U1RX .................................... 146
Reset System ............................................................. 92

SENTx Module .......................................................... 238 D

Shared I/O Port Structure ......................................... 143
Data Address Space........................................................... 36
SPIx Module.............................................................. 222
Alignment.................................................................... 36
Type B Timer (Timer2 and Timer4)........................... 176
Memory Map for 256-Kbyte Devices .......................... 39
Type B/Type C Timer Pair (32-Bit Timer).................. 177
Memory Map for 32-Kbyte Devices ............................ 37
Type C Timer (Timer3 and Timer5) .......................... 176
Memory Map for 64/128-Kbyte Devices ..................... 38
UARTx Module.......................................................... 247
Near Data Space ........................................................ 36
User-Programmable Blanking Function .................... 302
SFR Space ................................................................. 36
Watchdog Timer (WDT) ............................................ 325
Width .......................................................................... 36
Brown-out Reset (BOR) .................................................... 324
Data Space
C Extended X ................................................................. 72
Memory Arbitration, Bus Master Priority ..................... 73
C Compilers
Paged Memory Scheme ............................................. 68
MPLAB XC ................................................................ 338
DC Characteristics............................................................ 342
CAN
Brown-out Reset (BOR)............................................ 349
CAN Module
CTMU Current Source .............................................. 394
Control Registers ...................................................... 255
Doze Current (IDOZE) ................................................ 347
Message Buffers ....................................................... 275
Filter Capacitor (CEFC) Specifications ...................... 343
Word 0 .............................................................. 275
High Temperature..................................................... 404
Word 1 .............................................................. 275
Brown-out Reset (BOR).................................... 407
Word 2 .............................................................. 276
CTMU Current Source...................................... 410
Word 3 .............................................................. 276
I/O Pin Input Specifications .............................. 406
Word 4 .............................................................. 277
I/O Pin Output Specifications............................ 407
Word 5 .............................................................. 277
Idle Current (IIDLE) ............................................ 405
Word 6 .............................................................. 278
Op Amp/ Comparator x..................................... 411
Word 7 .............................................................. 278
Operating Current (IDD) .................................... 405
Modes of Operation .................................................. 254
Operating MIPS vs. Voltage ............................. 404
Overview ................................................................... 253
Power-Down Current (IPD)................................ 405
Characteristics for High-Temperature
Program Memory.............................................. 407
Devices (+150°C)...................................................... 439
Temperature and Voltage Specifications.......... 404
Characteristics for Industrial/Extended Temperature
Doze Current (IDOZE)........................................ 405
Devices (-40°C to +125°C)........................................ 413
I/O Pin Input Specifications....................................... 348
Charge Time Measurement Unit (CTMU) ......................... 279
I/O Pin Output Specifications.................................... 349
Charge Time Measurement Unit. See CTMU.
Idle Current (IIDLE) .................................................... 345
Code Examples
Internal Band Gap Reference Voltage...................... 350
Port Write/Read ........................................................ 144
Op Amp/Comparator x Specifications....................... 392
PORTA Slew Selections ........................................... 145
Op Amp/Comparator x Voltage Reference
PWM1 Write-Protected Register
Specifications ................................................... 393
Unlock Sequence.............................................. 200
Operating Current (IDD) ............................................ 344
PWRSAV Instruction Syntax ..................................... 133
Operating MIPS vs. Voltage ..................................... 342
Code Protection ........................................................ 317, 326
Power-Down Current (IPD)........................................ 346
CodeGuard Security.................................................. 317, 326
Program Memory ...................................................... 350
Comparator Voltage Reference
Temperature and Voltage Specifications.................. 343
Configuring................................................................ 313
Thermal Operating Conditions.................................. 342
Deadman Timer (DMT)..................................................... 181
Configuration Bits.............................................................. 317
Description ................................................................ 320
Deadman Timer. See DMT.
Controller Area Network (CAN)......................................... 253
Development Support ....................................................... 337
Controller Area Network. See CAN.
Direct Memory Access. See DMA.
CPU..................................................................................... 21
DMA Controller
Addressing Modes ...................................................... 21
Channel to Peripheral Associations.......................... 110
Arithmetic Logic Unit (ALU)......................................... 30
Control Registers ........................................................ 25
Supported Peripherals .............................................. 109
Data Space Addressing .............................................. 21
DMAC Registers
DSP Engine ................................................................ 30
DMAxCNT................................................................. 111
Instruction Set ............................................................. 21
DMAxCON ................................................................ 111
Programmer’s Model................................................... 23
DMAxPAD................................................................. 111
CTMU
DMAxREQ ................................................................ 111
DMAxSTAH/L ........................................................... 111
Customer Change Notification Service ............................. 493
DMAxSTBH/L ........................................................... 111
Customer Notification Service........................................... 493
DMT
Customer Support ............................................................. 493
Doze Mode ....................................................................... 135

E Instruction Addressing Modes ............................................ 74

Electrical Characteristics................................................... 341 File Register Instructions ............................................ 74
AC ..................................................................... 351, 408 Fundamental Modes Supported ................................. 75
MAC Instructions ........................................................ 75
Equations
BRG Formula ............................................................ 229 MCU Instructions ........................................................ 74
Device Operating Frequency .................................... 124 Move and Accumulator Instructions ........................... 75
Other Instructions ....................................................... 75
FOSC Calculation....................................................... 124
Frame Time Calculations .......................................... 239 Instruction Set
FSCL Frequency ........................................................ 229 Overview................................................................... 330
Summary .................................................................. 327
FVCO Calculation....................................................... 124
SYNCMIN and SYNCMAX Calculations ................... 240 Symbols Used in Opcode ......................................... 328
Tick Period Calculation ............................................. 239 Interfacing Program and Data Memory Spaces.................. 79
Inter-Integrated Circuit (I2C) ............................................. 229
Errata .................................................................................. 11
Baud Rate Generator ............................................... 229
F Control Registers...................................................... 231
Flash Program Memory ...................................................... 83 Inter-Integrated Circuit. See I2C.
Control Registers ........................................................ 85 Internal LPRC Oscillator
Error Correcting Code (ECC)...................................... 85 Use with WDT........................................................... 325
Operations .................................................................. 84 Internet Address ............................................................... 493
Resources................................................................... 85 Interrupt Controller
RTSP Operation.......................................................... 84 Control and Status Registers.................................... 100
Table Instructions........................................................ 83 IECx.................................................................. 100
Flexible Configuration ....................................................... 317 IFSx .................................................................. 100
INTCON1.......................................................... 100
G INTCON2.......................................................... 100
Getting Started with 16-Bit DSCs........................................ 17 INTCON3.......................................................... 100
Connection Requirements .......................................... 17 INTCON4.......................................................... 100
CPU Logic Filter Capacitor Connection (VCAP) .......... 18 INTTREG.......................................................... 100
Decoupling Capacitors................................................ 17 IPCx.................................................................. 100
External Oscillator Pins............................................... 19 Reset Sequence ....................................................... 100
ICSP Pins.................................................................... 19 Interrupt Vector Table (IVT) ................................................ 95
Master Clear (MCLR) Pin............................................ 18 Details......................................................................... 98
Oscillator Value Conditions on Device Start-up .......... 19
M
Unused I/Os ................................................................ 19
Memory Maps
H EDS ............................................................................ 72
High Temperature Memory Organization ......................................................... 31
Thermal Operating Conditions .................................. 404 Microchip Internet Web Site.............................................. 493
High-Speed PWM ............................................................. 199 Modulo Addressing ............................................................. 76
Control Registers ...................................................... 204 Applicability................................................................. 77
Faults ........................................................................ 199 Operation Example..................................................... 76
Resources................................................................. 203 Start and End Address ............................................... 76
High-Temperature Electrical Characteristics..................... 403 W Address Register Selection.................................... 76
Absolute Maximum Ratings ...................................... 403 MPLAB PM3 Device Programmer .................................... 339
MPLAB REAL ICE In-Circuit Emulator System ................ 339
I MPLAB X Integrated Development
I/O Ports ............................................................................ 143 Environment Software .............................................. 337
Configuring Analog/Digital Port Pins......................... 144 MPLINK Object Linker/MPLIB Object Librarian ................ 338
Helpful Tips ............................................................... 151
High-Voltage Detect (HVD)....................................... 151
O
Open-Drain Configuration ......................................... 144 Op Amp/Comparator......................................................... 301
Parallel I/O (PIO)....................................................... 143 Control Registers...................................................... 303
Peripheral Pin Select (PPS)...................................... 145 Oscillator Configuration .................................................... 123
Slew Rate Selection.................................................. 145 Bit Values for Clock Selection .................................. 125
Write/Read Timing .................................................... 144 CPU Clocking System .............................................. 124
In-Circuit Debugger ........................................................... 326 Output Compare ............................................................... 193
MPLAB ICD 3............................................................ 339 Control Registers...................................................... 194
PICkit 3 Programmer ................................................ 339
P
In-Circuit Emulation........................................................... 317
In-Circuit Serial Programming (ICSP) ....................... 317, 326 Packaging ......................................................................... 461
Input Capture .................................................................... 189 Details....................................................................... 463
Control Registers ...................................................... 190 Marking............................................................. 461, 462
Input Change Notification (ICN) ........................................ 144 Peripheral Module Disable (PMD) .................................... 135

Peripheral Pin Select (PPS) PPS Output for dsPIC33EVXXXGM002/102

Control Registers ...................................................... 153 Devices............................................................... 50
Input Sources, Maps Input to Function ..................... 147 PPS Output for dsPIC33EVXXXGM004/104
Output Selection for Remappable Pins ..................... 150 Devices............................................................... 50
Pinout I/O Descriptions (table) ............................................ 14 PPS Output for dsPIC33EVXXXGM006/106
Power-Saving Features..................................................... 133 Devices............................................................... 51
Clock Frequency and Switching................................ 133 PWM ........................................................................... 60
Instruction-Based Modes .......................................... 133 PWM Generator 1....................................................... 60
Idle .................................................................... 134 PWM Generator 2....................................................... 61
Sleep................................................................. 134 PWM Generator 3....................................................... 61
Interrupts Coincident with Power Save Reference Clock ......................................................... 53
Instructions........................................................ 134 SENT1 Receiver ......................................................... 49
Program Address Space ..................................................... 31 SENT2 Receiver ......................................................... 49
Construction ................................................................ 79 SPI1 and SPI2 ............................................................ 45
Data Access from Program Memory Using System Control ........................................................... 53
Table Instructions................................................ 81 Timers......................................................................... 43
Memory Map for dsPIC33EV128GM00X/10X UART1 and UART2 .................................................... 45
Devices ............................................................... 33 Registers
Memory Map for dsPIC33EV256GM00X/10X ADxCHS0 (ADCx Input Channel 0 Select) ............... 296
Devices ............................................................... 34 ADxCHS123 (ADCx Input
Memory Map for dsPIC33EV32GM00X/10X Channels 1, 2, 3 Select) ................................... 295
Devices ............................................................... 31 ADxCON1 (ADCx Control 1)..................................... 289
Memory Map for dsPIC33EV64GM00X/10X ADxCON2 (ADCx Control 2)..................................... 291
Devices ............................................................... 32 ADxCON3 (ADCx Control 3)..................................... 293
Table Read Instructions ADxCON4 (ADCx Control 4)..................................... 294
TBLRDH.............................................................. 81 ADxCSSH (ADCx Input Scan Select High)............... 298
TBLRDL .............................................................. 81 ADxCSSL (ADCx Input Scan Select Low) ................ 300
Program Memory ALTDTRx (PWMx Alternate Dead-Time).................. 211
Interrupt/Trap Vectors ................................................. 35 AUXCONx (PWMx Auxiliary Control) ....................... 219
Organization................................................................ 35 CHOP (PWMx Chop Clock Generator)..................... 207
Reset Vector ............................................................... 35 CLKDIV (Clock Divisor) ............................................ 128
Programmer’s Model CM4CON (Comparator 4 Control) ............................ 306
Register Descriptions .................................................. 23 CMSTAT (Op Amp/Comparator Status) ................... 303
CMxCON (Comparator x Control,
R x = 1, 2, 3 or 5) ................................................. 304
Referenced Sources ........................................................... 12 CMxFLTR (Comparator x Filter Control)................... 312
Register Maps CMxMSKCON (Comparator x Mask
ADC1 .......................................................................... 46 Gating Control) ................................................. 310
CAN1 (WIN (C1CTRL) = 0 or 1) ................................. 47 CMxMSKSRC (Comparator x Mask Source
CAN1 (WIN (C1CTRL) = 0)......................................... 47 Select Control).................................................. 308
CAN1 (WIN (C1CTRL) = 1)......................................... 48 CORCON (Core Control) .................................... 27, 102
Configuration Words ................................................. 318 CTMUCON1 (CTMU Control 1) ................................ 281
CPU Core.................................................................... 41 CTMUCON2 (CTMU Control 2) ................................ 282
CTMU.......................................................................... 46 CTMUICON (CTMU Current Control) ....................... 284
DMAC ......................................................................... 59 CTXTSTAT (CPU W Register Context Status)........... 29
DMT ............................................................................ 52 CVR1CON (Comparator Voltage Reference
I2C1 ............................................................................ 44 Control 1).......................................................... 315
Input Capture 1 through Input Capture 4 .................... 44 CVR2CON (Comparator Voltage Reference
Interrupt Controller ...................................................... 55 Control 2).......................................................... 316
NVM ............................................................................ 53 CxBUFPNT1 (CANx Filters 0-3
Op Amp/Comparator ................................................... 58 Buffer Pointer 1) ............................................... 264
Output Compare ......................................................... 57 CxBUFPNT2 (CANx Filters 4-7
Peripheral Input Remap .............................................. 52 Buffer Pointer 2) ............................................... 265
PMD ............................................................................ 54 CxBUFPNT3 (CANx Filters 8-11
PORTA for dsPIC33EVXXXGMX02 Devices.............. 63 Buffer Pointer 3) ............................................... 266
PORTA for dsPIC33EVXXXGMX04 Devices.............. 62 CxBUFPNT4 (CANx Filters 12-15
PORTA for dsPIC33EVXXXGMX06 Devices.............. 62 Buffer Pointer 4) ............................................... 267
PORTB for dsPIC33EVXXXGMX02 Devices.............. 64 CxCFG1 (CANx Baud Rate Configuration 1)............ 262
PORTB for dsPIC33EVXXXGMX04 Devices.............. 64 CxCFG2 (CANx Baud Rate Configuration 2)............ 263
PORTB for dsPIC33EVXXXGMX06 Devices.............. 63 CxCTRL1 (CANx Control 1)...................................... 255
PORTC for dsPIC33EVXXXGMX04 Devices ............. 65 CxCTRL2 (CANx Control 2)...................................... 256
PORTC for dsPIC33EVXXXGMX06 Devices ............. 65 CxEC (CANx Transmit/Receive Error Count) ........... 262
PORTD for dsPIC33EVXXXGMX06 Devices ............. 66 CxFCTRL (CANx FIFO Control) ............................... 258
PORTE for dsPIC33EVXXXGMX06 Devices.............. 66 CxFEN1 (CANx Acceptance Filter Enable 1) ........... 264
PORTF for dsPIC33EVXXXGMX06 Devices .............. 67 CxFIFO (CANx FIFO Status) .................................... 259
PORTG for dsPIC33EVXXXGMX06 Devices ............. 67

CxFMSKSEL1 (CANx Filters 7-0 Mask I2CxMSK (I2Cx Slave Mode Address Mask)............ 235
Selection 1) ....................................................... 269 I2CxSTAT (I2Cx Status) ........................................... 234
CxFMSKSEL2 (CANx Filters 15-8 Mask ICxCON1 (Input Capture x Control 1)....................... 190
Selection 2) ....................................................... 270 ICxCON2 (Input Capture x Control 2)....................... 191
CxINTE (CANx Interrupt Enable) .............................. 261 INTCON1 (Interrupt Control 1) ................................. 103
CxINTF (CANx Interrupt Flag) .................................. 260 INTCON2 (Interrupt Control 2) ................................. 105
CxRXFnEID (CANx Acceptance Filter n INTCON3 (Interrupt Control 3) ................................. 106
Extended Identifier)........................................... 268 INTCON4 (Interrupt Control 4) ................................. 107
CxRXFnSID (CANx Acceptance Filter n INTTREG (Interrupt Control and Status) .................. 108
Standard Identifier) ........................................... 268 IOCONx (PWMx I/O Control).................................... 213
CxRXFUL1 (CANx Receive Buffer Full 1)................. 272 LEBCONx (PWMx Leading-Edge Blanking
CxRXFUL2 (CANx Receive Buffer Full 2)................. 272 Control)............................................................. 217
CxRXMnEID (CANx Acceptance Filter Mask n LEBDLYx (PWMx Leading-Edge Blanking
Extended Identifier)........................................... 271 Delay) ............................................................... 218
CxRXMnSID (CANx Acceptance Filter Mask n MDC (PWMx Master Duty Cycle) ............................. 207
Standard Identifier) ........................................... 271 NVMADR (NVM Lower Address)................................ 88
CxRXOVF1 (CANx Receive Buffer NVMADRU (NVM Upper Address) ............................. 88
Overflow 1) ....................................................... 273 NVMCON (NVM Control)............................................ 86
CxRXOVF2 (CANx Receive Buffer NVMKEY (NVM Key).................................................. 89
Overflow 2) ....................................................... 273 NVMSRCADRH (NVM Data Memory
CxTRmnCON (CANx TX/RX Buffer mn Control) ...... 274 Upper Address) .................................................. 90
CxVEC (CANx Interrupt Code) ................................. 257 NVMSRCADRL (NVM Data Memory
DEVID (Device ID) .................................................... 323 Lower Address) .................................................. 90
DEVREV (Device Revision) ...................................... 323 OCxCON1 (Output Compare x Control 1) ................ 194
DMALCA (DMA Last Channel Active Status) ........... 120 OCxCON2 (Output Compare x Control 2) ................ 196
DMAPPS (DMA Ping-Pong Status) .......................... 121 OSCCON (Oscillator Control)................................... 126
DMAPWC (DMA Peripheral Write OSCTUN (FRC Oscillator Tuning)............................ 131
Collision Status) ................................................ 118 PDCx (PWMx Generator Duty Cycle)....................... 210
DMARQC (DMA Request Collision Status) .............. 119 PHASEx (PWMx Primary Phase-Shift)..................... 210
DMAxCNT (DMA Channel x Transfer Count) ........... 116 PLLFBD (PLL Feedback Divisor) ............................. 130
DMAxCON (DMA Channel x Control) ....................... 112 PMD1 (Peripheral Module Disable Control 1) .......... 136
DMAxPAD (DMA Channel x PMD2 (Peripheral Module Disable Control 2) .......... 137
Peripheral Address) .......................................... 116 PMD3 (Peripheral Module Disable Control 3) .......... 138
DMAxREQ (DMA Channel x IRQ Select) ................. 113 PMD4 (Peripheral Module Disable Control 4) .......... 138
DMAxSTAH (DMA Channel x PMD6 (Peripheral Module Disable Control 6) .......... 139
Start Address A, High) ...................................... 114 PMD7 (Peripheral Module Disable Control 7) .......... 140
DMAxSTAL (DMA Channel x PMD8 (Peripheral Module Disable Control 8) .......... 141
Start Address A, Low) ....................................... 114 PTCON (PWMx Time Base Control) ........................ 204
DMAxSTBH (DMA Channel x PTCON2 (PWMx Primary Master Clock
Start Address B, High) ...................................... 115 Divider Select) .................................................. 205
DMAxSTBL (DMA Channel x PTPER (PWMx Primary Master Time Base
Start Address B, Low) ....................................... 115 Period) .............................................................. 206
DMTCLR (Deadman Timer Clear) ............................ 183 PWMCONx (PWMx Control) .................................... 208
DMTCNTH (Deadman Timer Count High) ................ 185 RCON (Reset Control)................................................ 93
DMTCNTL (Deadman Timer Count Low) ................. 185 REFOCON (Reference Oscillator Control) ............... 132
DMTCON (Deadman Timer Control) ........................ 182 RPINR0 (Peripheral Pin Select Input 0) ................... 153
DMTHOLDREG (DMT Hold)..................................... 188 RPINR1 (Peripheral Pin Select Input 1) ................... 153
DMTPRECLR (Deadman Timer Preclear) ................ 182 RPINR11 (Peripheral Pin Select Input 11) ............... 157
DMTPSCNTH (DMT Post Configure Count RPINR12 (Peripheral Pin Select Input 12) ............... 158
Status High) ...................................................... 186 RPINR18 (Peripheral Pin Select Input 18) ............... 159
DMTPSCNTL (DMT Post Configure Count RPINR19 (Peripheral Pin Select Input 19) ............... 159
Status Low) ....................................................... 186 RPINR22 (Peripheral Pin Select Input 22) ............... 160
DMTPSINTVH (DMT Post Configure Interval RPINR23 (Peripheral Pin Select Input 23) ............... 161
Status High) ...................................................... 187 RPINR26 (Peripheral Pin Select Input 26) ............... 161
DMTPSINTVL (DMT Post Configure Interval RPINR3 (Peripheral Pin Select Input 3) ................... 154
Status Low) ....................................................... 187 RPINR37 (Peripheral Pin Select Input 37) ............... 162
DMTSTAT (Deadman Timer Status)......................... 184 RPINR38 (Peripheral Pin Select Input 38) ............... 162
DSADRH (DMA Most Recent RAM RPINR39 (Peripheral Pin Select Input 39) ............... 163
High Address) ................................................... 117 RPINR44 (Peripheral Pin Select Input 44) ............... 164
DSADRL (DMA Most Recent RAM RPINR45 (Peripheral Pin Select Input 45) ............... 164
Low Address) .................................................... 117 RPINR7 (Peripheral Pin Select Input 7) ................... 155
DTRx (PWMx Dead-Time) ........................................ 211 RPINR8 (Peripheral Pin Select Input 8) ................... 156
FCLCONx (PWMx Fault Current-Limit Control) ........ 215 RPOR0 (Peripheral Pin Select Output 0) ................. 165
I2CxCON1 (I2Cx Control 1) ...................................... 231 RPOR1 (Peripheral Pin Select Output 1) ................. 165
I2CxCON2 (I2Cx Control 2) ...................................... 233 RPOR10 (Peripheral Pin Select Output 10) ............. 170

RPOR11 (Peripheral Pin Select Output 11) .............. 170 T

RPOR12 (Peripheral Pin Select Output 12) .............. 171
Temperature and Voltage Specifications
RPOR13 (Peripheral Pin Select Output 13) .............. 171
AC............................................................................. 351
RPOR2 (Peripheral Pin Select Output 2) .................. 166
High Temperature
AC..................................................................... 408
Thermal Packaging Characteristics .................................. 342
Third-Party Development Tools ........................................ 340
Timer1............................................................................... 173
Control Register........................................................ 174
Timer2/3 and Timer4/5 ..................................................... 175
SENTxCON1 (SENTx Control 1) .............................. 241
Timing Diagrams
SENTxDATH (SENTx Receive Data High) ............... 245
10-Bit ADC Conversion (CHPS<1:0> = 01,
SENTxDATL (SENTx Receive Data Low) ................ 245
SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000,
SENTxSTAT (SENTx Status) ................................... 243
SSRCG = 0) ..................................................... 400
SEVTCMP (PWMx Primary Special Event
10-Bit ADC Conversion (CHPS<1:0> = 01,
Compare) .......................................................... 206
SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111,
SPIxCON1 (SPIx Control 1) ...................................... 226
SSRCG = 0, SAMC<4:0> = 00010).................. 400
SPIxCON2 (SPIx Control 2) ...................................... 228
12-Bit ADC Conversion (ASAM = 0, SSRC<2:0> = 000,
SPIxSTAT (SPIx Status and Control) ....................... 224
SSRCG = 0) ..................................................... 398
SR (CPU STATUS) ............................................. 25, 101
BOR and Master Clear Reset ................................... 354
T1CON (Timer1 Control)........................................... 174
CANx I/O .................................................................. 391
TRGCONx (PWMx Trigger Control).......................... 212
External Clock........................................................... 352
TRIGx (PWMx Primary Trigger Compare Value) ...... 214
High-Speed PWMx Characteristics .......................... 361
TxCON (Timer2 and Timer4 Control)........................ 178
High-Speed PWMx Fault .......................................... 361
TyCON (Timer3 and Timer5 Control)........................ 179
I/O Characteristics .................................................... 354
UxMODE (UARTx Mode) .......................................... 249
I2Cx Bus Data (Master Mode) .................................. 387
UxSTA (UARTx Status and Control) ......................... 251
I2Cx Bus Data (Slave Mode) .................................... 389
Resets ................................................................................. 91
I2Cx Bus Start/Stop Bits (Master Mode)................... 387
Brown-out Reset (BOR) .............................................. 91
I2Cx Bus Start/Stop Bits (Slave Mode)..................... 389
Configuration Mismatch Reset (CM) ........................... 91
Input Capture x (ICx) ................................................ 359
Illegal Condition Reset (IOPUWR) .............................. 91
OCx/PWMx Characteristics ...................................... 360
Illegal Address Mode .......................................... 91
Output Compare x (OCx) Characteristics ................. 360
Illegal Opcode ..................................................... 91
Power-on Reset Characteristics ............................... 355
Security ............................................................... 91
Uninitialized W Register...................................... 91
CKP = x, SMP = 1) ........................................... 377
Master Clear Pin Reset (MCLR) ................................. 91
Master Reset Signal (SYSRST) .................................. 91
CKP = x, SMP = 1) ........................................... 376
Power-on Reset (POR) ............................................... 91
RESET Instruction (SWR)........................................... 91 Transmit Only, CKE = 0)................................... 374
Trap Conflict Reset (TRAPR)...................................... 91
Watchdog Timer Time-out Reset (WDTO).................. 91
Transmit Only, CKE = 1)................................... 375
Revision History ................................................................ 485
S CKP = 0, SMP = 0) ........................................... 385
SENTx Protocol Data Frames........................................... 238
CKP = 1, SMP = 0) ........................................... 383
Serial Peripheral Interface (SPI) ....................................... 221
Serial Peripheral Interface. See SPI.
CKP = 0, SMP = 0) ........................................... 379
Single-Edge Nibble Transmission (SENT) ........................ 237
Receive Mode ........................................................... 240
CKP = 1, SMP = 0) ........................................... 381
Transmit Mode .......................................................... 239
Single-Edge Nibble Transmission for
CKP = x, SMP = 1) ........................................... 365
Automotive Applications............................................ 237
Single-Edge Nibble Transmission. See SENT.
CKP = x, SMP = 1) ........................................... 364
Software Simulator
MPLAB X SIM ........................................................... 339
Software Stack Pointer (SSP) ............................................. 74
Special Features of the CPU............................................. 317
SPI
CKP = 0, SMP = 0) ........................................... 372
Helpful Tips ............................................................... 223
CKP = 1, SMP = 0) ........................................... 370

SPI2 Slave Mode (Full-Duplex, CKE = 1, V

CKP = 0, SMP = 0) ........................................... 366
Voltage Regulator (On-Chip) ............................................ 324
CKP = 1, SMP = 0) ........................................... 368 W
Timer1-Timer5 External Clock .................................. 357 Watchdog Timer (WDT)............................................ 317, 325
UARTx I/O................................................................. 391 Programming Considerations ................................... 325
U WWW Address ................................................................. 493
WWW, On-Line Support ..................................................... 11
UART
Helpful Tips ............................................................... 248
Universal Asynchronous Receiver
Transmitter (UART)................................................... 247
Universal Asynchronous Receiver Transmitter. See UART.
User OTP Memory ............................................................ 324

NOTES:

THE MICROCHIP WEB SITE CUSTOMER SUPPORT

Microchip provides online support via our WWW site at Users of Microchip products can receive assistance
www.microchip.com. This web site is used as a means through several channels:
to make files and information easily available to • Distributor or Representative
customers. Accessible by using your favorite Internet
• Local Sales Office
browser, the web site contains the following
information: • Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design Customers should contact their distributor,
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documents, latest software releases and archived support. Local sales offices are also available to help
software customers. A listing of sales offices and locations is
• General Technical Support – Frequently Asked included in the back of this document.
Questions (FAQ), technical support requests, Technical support is available through the web site
online discussion groups, Microchip consultant at: http://microchip.com/support
program member listing
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ordering guides, latest Microchip press releases,
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CUSTOMER CHANGE NOTIFICATION

SERVICE
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To register, access the Microchip web site at
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“Customer Change Notification” and follow the
registration instructions.

NOTES:

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
dsPIC 33 EV XXX GM0 0X T PT - XXX Example:
dsPIC33EV256GM006-I/PT:
Microchip Trademark dsPIC33, Enhanced Voltage,
256-Kbyte Program Memory, 64-Pin,
Architecture
Industrial Temperature, TQFP Package.
Core Family
Program Memory Size (Kbytes)
Product Group
Pin Count
Tape and Reel Flag (if applicable)
Package
Pattern
Architecture: 33 = 16-Bit Digital Signal Controller
Family: EV = Enhanced Voltage
Product Group: GM = General Purpose plus Motor Control Family
Pin Count: 02 = 28-Pin

04 = 44-Pin
06 = 64-Pin
Temperature Range I = -40°C to +85°C (Industrial)
E = -40°C to +125°C (Extended)
H = -40°C to +150°C (High)
Package: MM = Plastic Quad Flat, No Lead Package – (28-pin) 6x6x0.9 mm body (QFN-S)
SO = Plastic Small Outline – (28-pin) 7.50 mm body (SOIC)
SS = Plastic Shrink Small Outline – (28-pin) 5.30 mm body (SSOP)
SP = Skinny Plastic Dual In-Line – (28-pin) 300 mil body (SPDIP)
ML = Plastic Quad Flat, No Lead Package – (44-pin) 8x8 mm body (QFN)
MR = Plastic Quad Flat, No Lead Package – (64-pin) 9x9x0.9 mm body (QFN)
PT = Plastic Thin Quad Flatpack – (44-pin) 10x10x1 mm body (TQFP)
PT = Plastic Thin Quad Flatpack – (64-pin) 10x10x1 mm body (TQFP)

NOTES:

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, AnyRate,
and may be superseded by updates. It is your responsibility to
dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,
ensure that your application meets with your specifications. KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST,
MICROCHIP MAKES NO REPRESENTATIONS OR MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo,
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O
IMPLIED, WRITTEN OR ORAL, STATUTORY OR are registered trademarks of Microchip Technology
OTHERWISE, RELATED TO THE INFORMATION, Incorporated in the U.S.A. and other countries.
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR ClockWorks, The Embedded Control Solutions Company,
FITNESS FOR PURPOSE. Microchip disclaims all liability ETHERSYNCH, Hyper Speed Control, HyperLight Load,
arising from this information and its use. Use of Microchip IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are
devices in life support and/or safety applications is entirely at registered trademarks of Microchip Technology Incorporated
the buyer’s risk, and the buyer agrees to defend, indemnify and in the U.S.A.
hold harmless Microchip from any and all damages, claims, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut,
suits, or expenses resulting from such use. No licenses are BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
conveyed, implicitly or otherwise, under any Microchip dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,
intellectual property rights unless otherwise stated. EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip
Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker,
Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and Silicon Storage Technology is a registered trademark of
Tempe, Arizona; Gresham, Oregon and design centers in California Microchip Technology Inc. in other countries.
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping GestIC is a registered trademarks of Microchip Technology
devices, Serial EEPROMs, microperipherals, nonvolatile memory and Germany II GmbH & Co. KG, a subsidiary of Microchip
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified. Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
QUALITY MANAGEMENT SYSTEM © 2013-2016, Microchip Technology Incorporated, Printed in
CERTIFIED BY DNV the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0975-5
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06/23/16

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dsPIC33EV128GM106-I/MR dsPIC33EV256GM106-I/PT dsPIC33EV256GM104-I/ML dsPIC33EV256GM102-I/SP
dsPIC33EV64GM102-I/MM dsPIC33EV256GM104-I/PT dsPIC33EV64GM102-I/SP dsPIC33EV128GM104-I/ML
dsPIC33EV64GM106-I/MR dsPIC33EV128GM102-I/SO dsPIC33EV64GM102-I/SO dsPIC33EV256GM106-I/MR
dsPIC33EV128GM102-I/SP dsPIC33EV64GM104-I/PT dsPIC33EV256GM102-I/SO dsPIC33EV64GM106-I/PT
dsPIC33EV128GM102-I/MM dsPIC33EV128GM104-I/PT dsPIC33EV64GM104-I/ML dsPIC33EV256GM102-I/MM
dsPIC33EV128GM106-E/PT dsPIC33EV256GM106-E/PT dsPIC33EV256GM002-E/MM dsPIC33EV256GM002-I/MM
dsPIC33EV128GM006-E/MR dsPIC33EV64GM004-I/ML dsPIC33EV64GM002-I/SO dsPIC33EV32GM002-E/SP
dsPIC33EV32GM002-E/SO dsPIC33EV32GM102-I/SO dsPIC33EV32GM104-E/ML dsPIC33EV32GM006-E/MR
dsPIC33EV32GM004-E/PT dsPIC33EV32GM002-E/MM dsPIC33EV32GM104-I/PT dsPIC33EV32GM102-I/SP
dsPIC33EV32GM106-I/MR dsPIC33EV32GM002-I/MM dsPIC33EV128GM006-I/MR dsPIC33EV64GM002-E/SP
dsPIC33EV128GM102-E/SO dsPIC33EV256GM004-E/PT dsPIC33EV64GM004-E/ML dsPIC33EV32GM002-I/SO
dsPIC33EV32GM004-I/ML dsPIC33EV32GM106-E/MR dsPIC33EV64GM006-E/MR dsPIC33EV128GM006-E/PT
dsPIC33EV32GM102-E/SP dsPIC33EV128GM004-I/PT dsPIC33EV256GM102-E/MM dsPIC33EV64GM006-E/PT
dsPIC33EV32GM102-E/SO dsPIC33EV32GM102-E/MM dsPIC33EV32GM104-E/PT dsPIC33EV32GM006-I/PT
dsPIC33EV256GM006-E/PT dsPIC33EV128GM004-E/ML dsPIC33EV64GM002-I/SP dsPIC33EV128GM002-E/SP
dsPIC33EV256GM002-E/SO dsPIC33EV256GM102-E/SP dsPIC33EV64GM002-I/MM dsPIC33EV64GM106-E/PT
dsPIC33EV256GM104-E/ML dsPIC33EV256GM106-E/MR dsPIC33EV128GM004-I/ML dsPIC33EV128GM106-I/PT
dsPIC33EV256GM002-I/SO dsPIC33EV256GM002-E/SP dsPIC33EV32GM106-E/PT dsPIC33EV256GM006-E/MR
dsPIC33EV64GM004-I/PT dsPIC33EV64GM002-E/MM dsPIC33EV64GM104-E/PT dsPIC33EV256GM004-I/ML
dsPIC33EV128GM106-E/MR dsPIC33EV128GM002-I/MM dsPIC33EV64GM102-E/SO dsPIC33EV128GM104-E/ML
dsPIC33EV128GM002-I/SO dsPIC33EV32GM002-I/SP dsPIC33EV128GM006-I/PT dsPIC33EV128GM002-I/SP
dsPIC33EV128GM002-E/MM dsPIC33EV64GM106-E/MR dsPIC33EV256GM004-I/PT dsPIC33EV256GM102-E/SO
dsPIC33EV128GM104-E/PT dsPIC33EV64GM006-I/PT dsPIC33EV64GM102-E/MM dsPIC33EV64GM104-E/ML
dsPIC33EV64GM002-E/SO dsPIC33EV64GM006-I/MR dsPIC33EV128GM102T-I/SO dsPIC33EV32GM104T-I/ML
dsPIC33EV128GM104T-I/ML dsPIC33EV256GM106T-I/MR dsPIC33EV128GM104T-I/PT dsPIC33EV32GM104T-I/PT

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dsPIC33EVXXXGM00X/10X FAMILY

16-Bit, 5V Digital Signal Controllers with

Clock Management Advanced Analog Features

 2013-2016 Microchip Technology Inc. DS70005144E-page 1

Timers/Output Compare/Input Capture Input/Output

DS70005144E-page 2  2013-2016 Microchip Technology Inc.

TABLE 1: dsPIC33EVXXXGM00X/10X FAMILY DEVICES

General Purpose I/O (GPIO)

4 5 2 4 4 3x2 2 2 1 2 1 36 4/5 1 Intermediate Y 53 3 64 TQFP, QFN

DS70005144E-page 4  2013-2016 Microchip Technology Inc.

Pin Diagrams (Continued)

 2013-2016 Microchip Technology Inc. DS70005144E-page 5

Pin Diagrams (Continued)

DS70005144E-page 6  2013-2016 Microchip Technology Inc.

Pin Diagrams (Continued)

 2013-2016 Microchip Technology Inc. DS70005144E-page 7

Pin Diagrams (Continued)

DS70005144E-page 8  2013-2016 Microchip Technology Inc.

Pin Diagrams (Continued)

 2013-2016 Microchip Technology Inc. DS70005144E-page 9

DS70005144E-page 10  2013-2016 Microchip Technology Inc.

TO OUR VALUED CUSTOMERS

Most Current Data Sheet

Customer Notification System

 2013-2016 Microchip Technology Inc. DS70005144E-page 11

DS70005144E-page 12  2013-2016 Microchip Technology Inc.

1.0 DEVICE OVERVIEW This document contains device-specific information for

FIGURE 1-1: dsPIC33EVXXXGM00X/10X FAMILY BLOCK DIAGRAM

Input Output PORTG

Note 1: This feature or peripheral is only available on dsPIC33EVXXXGM10X devices.

 2013-2016 Microchip Technology Inc. DS70005144E-page 13

TABLE 1-1: PINOUT I/O DESCRIPTIONS

DS70005144E-page 14  2013-2016 Microchip Technology Inc.

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

 2013-2016 Microchip Technology Inc. DS70005144E-page 15

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

DS70005144E-page 16  2013-2016 Microchip Technology Inc.

2.0 GUIDELINES FOR GETTING 2.2 Decoupling Capacitors

Note: The AVDD and AVSS pins must be

 2013-2016 Microchip Technology Inc. DS70005144E-page 17

Ceramic Ceramic transitions must not be adversely affected. Therefore,

F CNV FIGURE 2-2: EXAMPLE OF MCLR PIN

2.2.1 TANK CAPACITORS JP

DS70005144E-page 18  2013-2016 Microchip Technology Inc.

2.5 ICSP Pins FIGURE 2-3: SUGGESTED PLACEMENT

 2013-2016 Microchip Technology Inc. DS70005144E-page 19

DS70005144E-page 20  2013-2016 Microchip Technology Inc.

3.0 CPU 3.2 Instruction Set

 2013-2016 Microchip Technology Inc. DS70005144E-page 21

FIGURE 3-1: dsPIC33EVXXXGM00X/10X FAMILY CPU BLOCK DIAGRAM

Control Signals Instruction

Power, Reset Ports

DS70005144E-page 22  2013-2016 Microchip Technology Inc.

3.5 Programmer’s Model In addition to the registers contained in the programmer’s

TABLE 3-1: PROGRAMMER’S MODEL REGISTER DESCRIPTIONS

 2013-2016 Microchip Technology Inc. DS70005144E-page 23

FIGURE 3-2: PROGRAMMER’S MODEL

AD39 AD31 AD15 AD0

DS70005144E-page 24  2013-2016 Microchip Technology Inc.